1 //===- AMDGPUBaseInfo.h - Top level definitions for AMDGPU ------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #ifndef LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
10 #define LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
11 
12 #include "SIDefines.h"
13 #include "llvm/IR/CallingConv.h"
14 #include "llvm/Support/Alignment.h"
15 
16 struct amd_kernel_code_t;
17 
18 namespace llvm {
19 
20 struct Align;
21 class Argument;
22 class Function;
23 class GCNSubtarget;
24 class GlobalValue;
25 class MCRegisterClass;
26 class MCRegisterInfo;
27 class MCSubtargetInfo;
28 class StringRef;
29 class Triple;
30 
31 namespace amdhsa {
32 struct kernel_descriptor_t;
33 }
34 
35 namespace AMDGPU {
36 
37 struct IsaVersion;
38 
39 /// \returns HSA OS ABI Version identification.
40 Optional<uint8_t> getHsaAbiVersion(const MCSubtargetInfo *STI);
41 /// \returns True if HSA OS ABI Version identification is 2,
42 /// false otherwise.
43 bool isHsaAbiVersion2(const MCSubtargetInfo *STI);
44 /// \returns True if HSA OS ABI Version identification is 3,
45 /// false otherwise.
46 bool isHsaAbiVersion3(const MCSubtargetInfo *STI);
47 /// \returns True if HSA OS ABI Version identification is 4,
48 /// false otherwise.
49 bool isHsaAbiVersion4(const MCSubtargetInfo *STI);
50 /// \returns True if HSA OS ABI Version identification is 5,
51 /// false otherwise.
52 bool isHsaAbiVersion5(const MCSubtargetInfo *STI);
53 /// \returns True if HSA OS ABI Version identification is 3 and above,
54 /// false otherwise.
55 bool isHsaAbiVersion3AndAbove(const MCSubtargetInfo *STI);
56 
57 /// \returns The offset of the hostcall pointer argument from implicitarg_ptr
58 unsigned getHostcallImplicitArgPosition();
59 
60 /// \returns Code object version.
61 unsigned getAmdhsaCodeObjectVersion();
62 
63 struct GcnBufferFormatInfo {
64   unsigned Format;
65   unsigned BitsPerComp;
66   unsigned NumComponents;
67   unsigned NumFormat;
68   unsigned DataFormat;
69 };
70 
71 struct MAIInstInfo {
72   uint16_t Opcode;
73   bool is_dgemm;
74   bool is_gfx940_xdl;
75 };
76 
77 #define GET_MIMGBaseOpcode_DECL
78 #define GET_MIMGDim_DECL
79 #define GET_MIMGEncoding_DECL
80 #define GET_MIMGLZMapping_DECL
81 #define GET_MIMGMIPMapping_DECL
82 #define GET_MIMGBiASMapping_DECL
83 #define GET_MAIInstInfoTable_DECL
84 #include "AMDGPUGenSearchableTables.inc"
85 
86 namespace IsaInfo {
87 
88 enum {
89   // The closed Vulkan driver sets 96, which limits the wave count to 8 but
90   // doesn't spill SGPRs as much as when 80 is set.
91   FIXED_NUM_SGPRS_FOR_INIT_BUG = 96,
92   TRAP_NUM_SGPRS = 16
93 };
94 
95 enum class TargetIDSetting {
96   Unsupported,
97   Any,
98   Off,
99   On
100 };
101 
102 class AMDGPUTargetID {
103 private:
104   const MCSubtargetInfo &STI;
105   TargetIDSetting XnackSetting;
106   TargetIDSetting SramEccSetting;
107 
108 public:
109   explicit AMDGPUTargetID(const MCSubtargetInfo &STI);
110   ~AMDGPUTargetID() = default;
111 
112   /// \return True if the current xnack setting is not "Unsupported".
113   bool isXnackSupported() const {
114     return XnackSetting != TargetIDSetting::Unsupported;
115   }
116 
117   /// \returns True if the current xnack setting is "On" or "Any".
118   bool isXnackOnOrAny() const {
119     return XnackSetting == TargetIDSetting::On ||
120         XnackSetting == TargetIDSetting::Any;
121   }
122 
123   /// \returns True if current xnack setting is "On" or "Off",
124   /// false otherwise.
125   bool isXnackOnOrOff() const {
126     return getXnackSetting() == TargetIDSetting::On ||
127         getXnackSetting() == TargetIDSetting::Off;
128   }
129 
130   /// \returns The current xnack TargetIDSetting, possible options are
131   /// "Unsupported", "Any", "Off", and "On".
132   TargetIDSetting getXnackSetting() const {
133     return XnackSetting;
134   }
135 
136   /// Sets xnack setting to \p NewXnackSetting.
137   void setXnackSetting(TargetIDSetting NewXnackSetting) {
138     XnackSetting = NewXnackSetting;
139   }
140 
141   /// \return True if the current sramecc setting is not "Unsupported".
142   bool isSramEccSupported() const {
143     return SramEccSetting != TargetIDSetting::Unsupported;
144   }
145 
146   /// \returns True if the current sramecc setting is "On" or "Any".
147   bool isSramEccOnOrAny() const {
148   return SramEccSetting == TargetIDSetting::On ||
149       SramEccSetting == TargetIDSetting::Any;
150   }
151 
152   /// \returns True if current sramecc setting is "On" or "Off",
153   /// false otherwise.
154   bool isSramEccOnOrOff() const {
155     return getSramEccSetting() == TargetIDSetting::On ||
156         getSramEccSetting() == TargetIDSetting::Off;
157   }
158 
159   /// \returns The current sramecc TargetIDSetting, possible options are
160   /// "Unsupported", "Any", "Off", and "On".
161   TargetIDSetting getSramEccSetting() const {
162     return SramEccSetting;
163   }
164 
165   /// Sets sramecc setting to \p NewSramEccSetting.
166   void setSramEccSetting(TargetIDSetting NewSramEccSetting) {
167     SramEccSetting = NewSramEccSetting;
168   }
169 
170   void setTargetIDFromFeaturesString(StringRef FS);
171   void setTargetIDFromTargetIDStream(StringRef TargetID);
172 
173   /// \returns String representation of an object.
174   std::string toString() const;
175 };
176 
177 /// \returns Wavefront size for given subtarget \p STI.
178 unsigned getWavefrontSize(const MCSubtargetInfo *STI);
179 
180 /// \returns Local memory size in bytes for given subtarget \p STI.
181 unsigned getLocalMemorySize(const MCSubtargetInfo *STI);
182 
183 /// \returns Number of execution units per compute unit for given subtarget \p
184 /// STI.
185 unsigned getEUsPerCU(const MCSubtargetInfo *STI);
186 
187 /// \returns Maximum number of work groups per compute unit for given subtarget
188 /// \p STI and limited by given \p FlatWorkGroupSize.
189 unsigned getMaxWorkGroupsPerCU(const MCSubtargetInfo *STI,
190                                unsigned FlatWorkGroupSize);
191 
192 /// \returns Minimum number of waves per execution unit for given subtarget \p
193 /// STI.
194 unsigned getMinWavesPerEU(const MCSubtargetInfo *STI);
195 
196 /// \returns Maximum number of waves per execution unit for given subtarget \p
197 /// STI without any kind of limitation.
198 unsigned getMaxWavesPerEU(const MCSubtargetInfo *STI);
199 
200 /// \returns Number of waves per execution unit required to support the given \p
201 /// FlatWorkGroupSize.
202 unsigned getWavesPerEUForWorkGroup(const MCSubtargetInfo *STI,
203                                    unsigned FlatWorkGroupSize);
204 
205 /// \returns Minimum flat work group size for given subtarget \p STI.
206 unsigned getMinFlatWorkGroupSize(const MCSubtargetInfo *STI);
207 
208 /// \returns Maximum flat work group size for given subtarget \p STI.
209 unsigned getMaxFlatWorkGroupSize(const MCSubtargetInfo *STI);
210 
211 /// \returns Number of waves per work group for given subtarget \p STI and
212 /// \p FlatWorkGroupSize.
213 unsigned getWavesPerWorkGroup(const MCSubtargetInfo *STI,
214                               unsigned FlatWorkGroupSize);
215 
216 /// \returns SGPR allocation granularity for given subtarget \p STI.
217 unsigned getSGPRAllocGranule(const MCSubtargetInfo *STI);
218 
219 /// \returns SGPR encoding granularity for given subtarget \p STI.
220 unsigned getSGPREncodingGranule(const MCSubtargetInfo *STI);
221 
222 /// \returns Total number of SGPRs for given subtarget \p STI.
223 unsigned getTotalNumSGPRs(const MCSubtargetInfo *STI);
224 
225 /// \returns Addressable number of SGPRs for given subtarget \p STI.
226 unsigned getAddressableNumSGPRs(const MCSubtargetInfo *STI);
227 
228 /// \returns Minimum number of SGPRs that meets the given number of waves per
229 /// execution unit requirement for given subtarget \p STI.
230 unsigned getMinNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU);
231 
232 /// \returns Maximum number of SGPRs that meets the given number of waves per
233 /// execution unit requirement for given subtarget \p STI.
234 unsigned getMaxNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU,
235                         bool Addressable);
236 
237 /// \returns Number of extra SGPRs implicitly required by given subtarget \p
238 /// STI when the given special registers are used.
239 unsigned getNumExtraSGPRs(const MCSubtargetInfo *STI, bool VCCUsed,
240                           bool FlatScrUsed, bool XNACKUsed);
241 
242 /// \returns Number of extra SGPRs implicitly required by given subtarget \p
243 /// STI when the given special registers are used. XNACK is inferred from
244 /// \p STI.
245 unsigned getNumExtraSGPRs(const MCSubtargetInfo *STI, bool VCCUsed,
246                           bool FlatScrUsed);
247 
248 /// \returns Number of SGPR blocks needed for given subtarget \p STI when
249 /// \p NumSGPRs are used. \p NumSGPRs should already include any special
250 /// register counts.
251 unsigned getNumSGPRBlocks(const MCSubtargetInfo *STI, unsigned NumSGPRs);
252 
253 /// \returns VGPR allocation granularity for given subtarget \p STI.
254 ///
255 /// For subtargets which support it, \p EnableWavefrontSize32 should match
256 /// the ENABLE_WAVEFRONT_SIZE32 kernel descriptor field.
257 unsigned getVGPRAllocGranule(const MCSubtargetInfo *STI,
258                              Optional<bool> EnableWavefrontSize32 = None);
259 
260 /// \returns VGPR encoding granularity for given subtarget \p STI.
261 ///
262 /// For subtargets which support it, \p EnableWavefrontSize32 should match
263 /// the ENABLE_WAVEFRONT_SIZE32 kernel descriptor field.
264 unsigned getVGPREncodingGranule(const MCSubtargetInfo *STI,
265                                 Optional<bool> EnableWavefrontSize32 = None);
266 
267 /// \returns Total number of VGPRs for given subtarget \p STI.
268 unsigned getTotalNumVGPRs(const MCSubtargetInfo *STI);
269 
270 /// \returns Addressable number of VGPRs for given subtarget \p STI.
271 unsigned getAddressableNumVGPRs(const MCSubtargetInfo *STI);
272 
273 /// \returns Minimum number of VGPRs that meets given number of waves per
274 /// execution unit requirement for given subtarget \p STI.
275 unsigned getMinNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU);
276 
277 /// \returns Maximum number of VGPRs that meets given number of waves per
278 /// execution unit requirement for given subtarget \p STI.
279 unsigned getMaxNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU);
280 
281 /// \returns Number of VGPR blocks needed for given subtarget \p STI when
282 /// \p NumVGPRs are used.
283 ///
284 /// For subtargets which support it, \p EnableWavefrontSize32 should match the
285 /// ENABLE_WAVEFRONT_SIZE32 kernel descriptor field.
286 unsigned getNumVGPRBlocks(const MCSubtargetInfo *STI, unsigned NumSGPRs,
287                           Optional<bool> EnableWavefrontSize32 = None);
288 
289 } // end namespace IsaInfo
290 
291 LLVM_READONLY
292 int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx);
293 
294 LLVM_READONLY
295 int getSOPPWithRelaxation(uint16_t Opcode);
296 
297 struct MIMGBaseOpcodeInfo {
298   MIMGBaseOpcode BaseOpcode;
299   bool Store;
300   bool Atomic;
301   bool AtomicX2;
302   bool Sampler;
303   bool Gather4;
304 
305   uint8_t NumExtraArgs;
306   bool Gradients;
307   bool G16;
308   bool Coordinates;
309   bool LodOrClampOrMip;
310   bool HasD16;
311   bool MSAA;
312   bool BVH;
313 };
314 
315 LLVM_READONLY
316 const MIMGBaseOpcodeInfo *getMIMGBaseOpcode(unsigned Opc);
317 
318 LLVM_READONLY
319 const MIMGBaseOpcodeInfo *getMIMGBaseOpcodeInfo(unsigned BaseOpcode);
320 
321 struct MIMGDimInfo {
322   MIMGDim Dim;
323   uint8_t NumCoords;
324   uint8_t NumGradients;
325   bool MSAA;
326   bool DA;
327   uint8_t Encoding;
328   const char *AsmSuffix;
329 };
330 
331 LLVM_READONLY
332 const MIMGDimInfo *getMIMGDimInfo(unsigned DimEnum);
333 
334 LLVM_READONLY
335 const MIMGDimInfo *getMIMGDimInfoByEncoding(uint8_t DimEnc);
336 
337 LLVM_READONLY
338 const MIMGDimInfo *getMIMGDimInfoByAsmSuffix(StringRef AsmSuffix);
339 
340 struct MIMGLZMappingInfo {
341   MIMGBaseOpcode L;
342   MIMGBaseOpcode LZ;
343 };
344 
345 struct MIMGMIPMappingInfo {
346   MIMGBaseOpcode MIP;
347   MIMGBaseOpcode NONMIP;
348 };
349 
350 struct MIMGBiasMappingInfo {
351   MIMGBaseOpcode Bias;
352   MIMGBaseOpcode NoBias;
353 };
354 
355 struct MIMGOffsetMappingInfo {
356   MIMGBaseOpcode Offset;
357   MIMGBaseOpcode NoOffset;
358 };
359 
360 struct MIMGG16MappingInfo {
361   MIMGBaseOpcode G;
362   MIMGBaseOpcode G16;
363 };
364 
365 LLVM_READONLY
366 const MIMGLZMappingInfo *getMIMGLZMappingInfo(unsigned L);
367 
368 LLVM_READONLY
369 const MIMGMIPMappingInfo *getMIMGMIPMappingInfo(unsigned MIP);
370 
371 LLVM_READONLY
372 const MIMGBiasMappingInfo *getMIMGBiasMappingInfo(unsigned Bias);
373 
374 LLVM_READONLY
375 const MIMGOffsetMappingInfo *getMIMGOffsetMappingInfo(unsigned Offset);
376 
377 LLVM_READONLY
378 const MIMGG16MappingInfo *getMIMGG16MappingInfo(unsigned G);
379 
380 LLVM_READONLY
381 int getMIMGOpcode(unsigned BaseOpcode, unsigned MIMGEncoding,
382                   unsigned VDataDwords, unsigned VAddrDwords);
383 
384 LLVM_READONLY
385 int getMaskedMIMGOp(unsigned Opc, unsigned NewChannels);
386 
387 LLVM_READONLY
388 unsigned getAddrSizeMIMGOp(const MIMGBaseOpcodeInfo *BaseOpcode,
389                            const MIMGDimInfo *Dim, bool IsA16,
390                            bool IsG16Supported);
391 
392 struct MIMGInfo {
393   uint16_t Opcode;
394   uint16_t BaseOpcode;
395   uint8_t MIMGEncoding;
396   uint8_t VDataDwords;
397   uint8_t VAddrDwords;
398 };
399 
400 LLVM_READONLY
401 const MIMGInfo *getMIMGInfo(unsigned Opc);
402 
403 LLVM_READONLY
404 int getMTBUFBaseOpcode(unsigned Opc);
405 
406 LLVM_READONLY
407 int getMTBUFOpcode(unsigned BaseOpc, unsigned Elements);
408 
409 LLVM_READONLY
410 int getMTBUFElements(unsigned Opc);
411 
412 LLVM_READONLY
413 bool getMTBUFHasVAddr(unsigned Opc);
414 
415 LLVM_READONLY
416 bool getMTBUFHasSrsrc(unsigned Opc);
417 
418 LLVM_READONLY
419 bool getMTBUFHasSoffset(unsigned Opc);
420 
421 LLVM_READONLY
422 int getMUBUFBaseOpcode(unsigned Opc);
423 
424 LLVM_READONLY
425 int getMUBUFOpcode(unsigned BaseOpc, unsigned Elements);
426 
427 LLVM_READONLY
428 int getMUBUFElements(unsigned Opc);
429 
430 LLVM_READONLY
431 bool getMUBUFHasVAddr(unsigned Opc);
432 
433 LLVM_READONLY
434 bool getMUBUFHasSrsrc(unsigned Opc);
435 
436 LLVM_READONLY
437 bool getMUBUFHasSoffset(unsigned Opc);
438 
439 LLVM_READONLY
440 bool getMUBUFIsBufferInv(unsigned Opc);
441 
442 LLVM_READONLY
443 bool getSMEMIsBuffer(unsigned Opc);
444 
445 LLVM_READONLY
446 bool getVOP1IsSingle(unsigned Opc);
447 
448 LLVM_READONLY
449 bool getVOP2IsSingle(unsigned Opc);
450 
451 LLVM_READONLY
452 bool getVOP3IsSingle(unsigned Opc);
453 
454 /// Returns true if MAI operation is a double precision GEMM.
455 LLVM_READONLY
456 bool getMAIIsDGEMM(unsigned Opc);
457 
458 LLVM_READONLY
459 bool getMAIIsGFX940XDL(unsigned Opc);
460 
461 LLVM_READONLY
462 const GcnBufferFormatInfo *getGcnBufferFormatInfo(uint8_t BitsPerComp,
463                                                   uint8_t NumComponents,
464                                                   uint8_t NumFormat,
465                                                   const MCSubtargetInfo &STI);
466 LLVM_READONLY
467 const GcnBufferFormatInfo *getGcnBufferFormatInfo(uint8_t Format,
468                                                   const MCSubtargetInfo &STI);
469 
470 LLVM_READONLY
471 int getMCOpcode(uint16_t Opcode, unsigned Gen);
472 
473 void initDefaultAMDKernelCodeT(amd_kernel_code_t &Header,
474                                const MCSubtargetInfo *STI);
475 
476 amdhsa::kernel_descriptor_t getDefaultAmdhsaKernelDescriptor(
477     const MCSubtargetInfo *STI);
478 
479 bool isGroupSegment(const GlobalValue *GV);
480 bool isGlobalSegment(const GlobalValue *GV);
481 bool isReadOnlySegment(const GlobalValue *GV);
482 
483 /// \returns True if constants should be emitted to .text section for given
484 /// target triple \p TT, false otherwise.
485 bool shouldEmitConstantsToTextSection(const Triple &TT);
486 
487 /// \returns Integer value requested using \p F's \p Name attribute.
488 ///
489 /// \returns \p Default if attribute is not present.
490 ///
491 /// \returns \p Default and emits error if requested value cannot be converted
492 /// to integer.
493 int getIntegerAttribute(const Function &F, StringRef Name, int Default);
494 
495 /// \returns A pair of integer values requested using \p F's \p Name attribute
496 /// in "first[,second]" format ("second" is optional unless \p OnlyFirstRequired
497 /// is false).
498 ///
499 /// \returns \p Default if attribute is not present.
500 ///
501 /// \returns \p Default and emits error if one of the requested values cannot be
502 /// converted to integer, or \p OnlyFirstRequired is false and "second" value is
503 /// not present.
504 std::pair<int, int> getIntegerPairAttribute(const Function &F,
505                                             StringRef Name,
506                                             std::pair<int, int> Default,
507                                             bool OnlyFirstRequired = false);
508 
509 /// Represents the counter values to wait for in an s_waitcnt instruction.
510 ///
511 /// Large values (including the maximum possible integer) can be used to
512 /// represent "don't care" waits.
513 struct Waitcnt {
514   unsigned VmCnt = ~0u;
515   unsigned ExpCnt = ~0u;
516   unsigned LgkmCnt = ~0u;
517   unsigned VsCnt = ~0u;
518 
519   Waitcnt() = default;
520   Waitcnt(unsigned VmCnt, unsigned ExpCnt, unsigned LgkmCnt, unsigned VsCnt)
521       : VmCnt(VmCnt), ExpCnt(ExpCnt), LgkmCnt(LgkmCnt), VsCnt(VsCnt) {}
522 
523   static Waitcnt allZero(bool HasVscnt) {
524     return Waitcnt(0, 0, 0, HasVscnt ? 0 : ~0u);
525   }
526   static Waitcnt allZeroExceptVsCnt() { return Waitcnt(0, 0, 0, ~0u); }
527 
528   bool hasWait() const {
529     return VmCnt != ~0u || ExpCnt != ~0u || LgkmCnt != ~0u || VsCnt != ~0u;
530   }
531 
532   bool hasWaitExceptVsCnt() const {
533     return VmCnt != ~0u || ExpCnt != ~0u || LgkmCnt != ~0u;
534   }
535 
536   bool hasWaitVsCnt() const {
537     return VsCnt != ~0u;
538   }
539 
540   bool dominates(const Waitcnt &Other) const {
541     return VmCnt <= Other.VmCnt && ExpCnt <= Other.ExpCnt &&
542            LgkmCnt <= Other.LgkmCnt && VsCnt <= Other.VsCnt;
543   }
544 
545   Waitcnt combined(const Waitcnt &Other) const {
546     return Waitcnt(std::min(VmCnt, Other.VmCnt), std::min(ExpCnt, Other.ExpCnt),
547                    std::min(LgkmCnt, Other.LgkmCnt),
548                    std::min(VsCnt, Other.VsCnt));
549   }
550 };
551 
552 /// \returns Vmcnt bit mask for given isa \p Version.
553 unsigned getVmcntBitMask(const IsaVersion &Version);
554 
555 /// \returns Expcnt bit mask for given isa \p Version.
556 unsigned getExpcntBitMask(const IsaVersion &Version);
557 
558 /// \returns Lgkmcnt bit mask for given isa \p Version.
559 unsigned getLgkmcntBitMask(const IsaVersion &Version);
560 
561 /// \returns Waitcnt bit mask for given isa \p Version.
562 unsigned getWaitcntBitMask(const IsaVersion &Version);
563 
564 /// \returns Decoded Vmcnt from given \p Waitcnt for given isa \p Version.
565 unsigned decodeVmcnt(const IsaVersion &Version, unsigned Waitcnt);
566 
567 /// \returns Decoded Expcnt from given \p Waitcnt for given isa \p Version.
568 unsigned decodeExpcnt(const IsaVersion &Version, unsigned Waitcnt);
569 
570 /// \returns Decoded Lgkmcnt from given \p Waitcnt for given isa \p Version.
571 unsigned decodeLgkmcnt(const IsaVersion &Version, unsigned Waitcnt);
572 
573 /// Decodes Vmcnt, Expcnt and Lgkmcnt from given \p Waitcnt for given isa
574 /// \p Version, and writes decoded values into \p Vmcnt, \p Expcnt and
575 /// \p Lgkmcnt respectively.
576 ///
577 /// \details \p Vmcnt, \p Expcnt and \p Lgkmcnt are decoded as follows:
578 ///     \p Vmcnt = \p Waitcnt[3:0]                      (pre-gfx9 only)
579 ///     \p Vmcnt = \p Waitcnt[3:0] | \p Waitcnt[15:14]  (gfx9+ only)
580 ///     \p Expcnt = \p Waitcnt[6:4]
581 ///     \p Lgkmcnt = \p Waitcnt[11:8]                   (pre-gfx10 only)
582 ///     \p Lgkmcnt = \p Waitcnt[13:8]                   (gfx10+ only)
583 void decodeWaitcnt(const IsaVersion &Version, unsigned Waitcnt,
584                    unsigned &Vmcnt, unsigned &Expcnt, unsigned &Lgkmcnt);
585 
586 Waitcnt decodeWaitcnt(const IsaVersion &Version, unsigned Encoded);
587 
588 /// \returns \p Waitcnt with encoded \p Vmcnt for given isa \p Version.
589 unsigned encodeVmcnt(const IsaVersion &Version, unsigned Waitcnt,
590                      unsigned Vmcnt);
591 
592 /// \returns \p Waitcnt with encoded \p Expcnt for given isa \p Version.
593 unsigned encodeExpcnt(const IsaVersion &Version, unsigned Waitcnt,
594                       unsigned Expcnt);
595 
596 /// \returns \p Waitcnt with encoded \p Lgkmcnt for given isa \p Version.
597 unsigned encodeLgkmcnt(const IsaVersion &Version, unsigned Waitcnt,
598                        unsigned Lgkmcnt);
599 
600 /// Encodes \p Vmcnt, \p Expcnt and \p Lgkmcnt into Waitcnt for given isa
601 /// \p Version.
602 ///
603 /// \details \p Vmcnt, \p Expcnt and \p Lgkmcnt are encoded as follows:
604 ///     Waitcnt[3:0]   = \p Vmcnt       (pre-gfx9 only)
605 ///     Waitcnt[3:0]   = \p Vmcnt[3:0]  (gfx9+ only)
606 ///     Waitcnt[6:4]   = \p Expcnt
607 ///     Waitcnt[11:8]  = \p Lgkmcnt     (pre-gfx10 only)
608 ///     Waitcnt[13:8]  = \p Lgkmcnt     (gfx10+ only)
609 ///     Waitcnt[15:14] = \p Vmcnt[5:4]  (gfx9+ only)
610 ///
611 /// \returns Waitcnt with encoded \p Vmcnt, \p Expcnt and \p Lgkmcnt for given
612 /// isa \p Version.
613 unsigned encodeWaitcnt(const IsaVersion &Version,
614                        unsigned Vmcnt, unsigned Expcnt, unsigned Lgkmcnt);
615 
616 unsigned encodeWaitcnt(const IsaVersion &Version, const Waitcnt &Decoded);
617 
618 namespace Hwreg {
619 
620 LLVM_READONLY
621 int64_t getHwregId(const StringRef Name, const MCSubtargetInfo &STI);
622 
623 LLVM_READNONE
624 bool isValidHwreg(int64_t Id);
625 
626 LLVM_READNONE
627 bool isValidHwregOffset(int64_t Offset);
628 
629 LLVM_READNONE
630 bool isValidHwregWidth(int64_t Width);
631 
632 LLVM_READNONE
633 uint64_t encodeHwreg(uint64_t Id, uint64_t Offset, uint64_t Width);
634 
635 LLVM_READNONE
636 StringRef getHwreg(unsigned Id, const MCSubtargetInfo &STI);
637 
638 void decodeHwreg(unsigned Val, unsigned &Id, unsigned &Offset, unsigned &Width);
639 
640 } // namespace Hwreg
641 
642 namespace DepCtr {
643 
644 int getDefaultDepCtrEncoding(const MCSubtargetInfo &STI);
645 int encodeDepCtr(const StringRef Name, int64_t Val, unsigned &UsedOprMask,
646                  const MCSubtargetInfo &STI);
647 bool isSymbolicDepCtrEncoding(unsigned Code, bool &HasNonDefaultVal,
648                               const MCSubtargetInfo &STI);
649 bool decodeDepCtr(unsigned Code, int &Id, StringRef &Name, unsigned &Val,
650                   bool &IsDefault, const MCSubtargetInfo &STI);
651 
652 } // namespace DepCtr
653 
654 namespace Exp {
655 
656 bool getTgtName(unsigned Id, StringRef &Name, int &Index);
657 
658 LLVM_READONLY
659 unsigned getTgtId(const StringRef Name);
660 
661 LLVM_READNONE
662 bool isSupportedTgtId(unsigned Id, const MCSubtargetInfo &STI);
663 
664 } // namespace Exp
665 
666 namespace MTBUFFormat {
667 
668 LLVM_READNONE
669 int64_t encodeDfmtNfmt(unsigned Dfmt, unsigned Nfmt);
670 
671 void decodeDfmtNfmt(unsigned Format, unsigned &Dfmt, unsigned &Nfmt);
672 
673 int64_t getDfmt(const StringRef Name);
674 
675 StringRef getDfmtName(unsigned Id);
676 
677 int64_t getNfmt(const StringRef Name, const MCSubtargetInfo &STI);
678 
679 StringRef getNfmtName(unsigned Id, const MCSubtargetInfo &STI);
680 
681 bool isValidDfmtNfmt(unsigned Val, const MCSubtargetInfo &STI);
682 
683 bool isValidNfmt(unsigned Val, const MCSubtargetInfo &STI);
684 
685 int64_t getUnifiedFormat(const StringRef Name);
686 
687 StringRef getUnifiedFormatName(unsigned Id);
688 
689 bool isValidUnifiedFormat(unsigned Val);
690 
691 int64_t convertDfmtNfmt2Ufmt(unsigned Dfmt, unsigned Nfmt);
692 
693 bool isValidFormatEncoding(unsigned Val, const MCSubtargetInfo &STI);
694 
695 unsigned getDefaultFormatEncoding(const MCSubtargetInfo &STI);
696 
697 } // namespace MTBUFFormat
698 
699 namespace SendMsg {
700 
701 LLVM_READONLY
702 int64_t getMsgId(const StringRef Name, const MCSubtargetInfo &STI);
703 
704 LLVM_READONLY
705 int64_t getMsgOpId(int64_t MsgId, const StringRef Name);
706 
707 LLVM_READNONE
708 StringRef getMsgName(int64_t MsgId, const MCSubtargetInfo &STI);
709 
710 LLVM_READNONE
711 StringRef getMsgOpName(int64_t MsgId, int64_t OpId);
712 
713 LLVM_READNONE
714 bool isValidMsgId(int64_t MsgId);
715 
716 LLVM_READNONE
717 bool isValidMsgOp(int64_t MsgId, int64_t OpId, const MCSubtargetInfo &STI,
718                   bool Strict = true);
719 
720 LLVM_READNONE
721 bool isValidMsgStream(int64_t MsgId, int64_t OpId, int64_t StreamId,
722                       const MCSubtargetInfo &STI, bool Strict = true);
723 
724 LLVM_READNONE
725 bool msgRequiresOp(int64_t MsgId);
726 
727 LLVM_READNONE
728 bool msgSupportsStream(int64_t MsgId, int64_t OpId);
729 
730 void decodeMsg(unsigned Val,
731                uint16_t &MsgId,
732                uint16_t &OpId,
733                uint16_t &StreamId);
734 
735 LLVM_READNONE
736 uint64_t encodeMsg(uint64_t MsgId,
737                    uint64_t OpId,
738                    uint64_t StreamId);
739 
740 } // namespace SendMsg
741 
742 
743 unsigned getInitialPSInputAddr(const Function &F);
744 
745 bool getHasColorExport(const Function &F);
746 
747 bool getHasDepthExport(const Function &F);
748 
749 LLVM_READNONE
750 bool isShader(CallingConv::ID CC);
751 
752 LLVM_READNONE
753 bool isGraphics(CallingConv::ID CC);
754 
755 LLVM_READNONE
756 bool isCompute(CallingConv::ID CC);
757 
758 LLVM_READNONE
759 bool isEntryFunctionCC(CallingConv::ID CC);
760 
761 // These functions are considered entrypoints into the current module, i.e. they
762 // are allowed to be called from outside the current module. This is different
763 // from isEntryFunctionCC, which is only true for functions that are entered by
764 // the hardware. Module entry points include all entry functions but also
765 // include functions that can be called from other functions inside or outside
766 // the current module. Module entry functions are allowed to allocate LDS.
767 LLVM_READNONE
768 bool isModuleEntryFunctionCC(CallingConv::ID CC);
769 
770 bool isKernelCC(const Function *Func);
771 
772 // FIXME: Remove this when calling conventions cleaned up
773 LLVM_READNONE
774 inline bool isKernel(CallingConv::ID CC) {
775   switch (CC) {
776   case CallingConv::AMDGPU_KERNEL:
777   case CallingConv::SPIR_KERNEL:
778     return true;
779   default:
780     return false;
781   }
782 }
783 
784 bool hasXNACK(const MCSubtargetInfo &STI);
785 bool hasSRAMECC(const MCSubtargetInfo &STI);
786 bool hasMIMG_R128(const MCSubtargetInfo &STI);
787 bool hasGFX10A16(const MCSubtargetInfo &STI);
788 bool hasG16(const MCSubtargetInfo &STI);
789 bool hasPackedD16(const MCSubtargetInfo &STI);
790 
791 bool isSI(const MCSubtargetInfo &STI);
792 bool isCI(const MCSubtargetInfo &STI);
793 bool isVI(const MCSubtargetInfo &STI);
794 bool isGFX9(const MCSubtargetInfo &STI);
795 bool isGFX9_GFX10(const MCSubtargetInfo &STI);
796 bool isGFX8Plus(const MCSubtargetInfo &STI);
797 bool isGFX9Plus(const MCSubtargetInfo &STI);
798 bool isGFX10(const MCSubtargetInfo &STI);
799 bool isGFX10Plus(const MCSubtargetInfo &STI);
800 bool isNotGFX10Plus(const MCSubtargetInfo &STI);
801 bool isGFX10Before1030(const MCSubtargetInfo &STI);
802 bool isGCN3Encoding(const MCSubtargetInfo &STI);
803 bool isGFX10_AEncoding(const MCSubtargetInfo &STI);
804 bool isGFX10_BEncoding(const MCSubtargetInfo &STI);
805 bool hasGFX10_3Insts(const MCSubtargetInfo &STI);
806 bool isGFX90A(const MCSubtargetInfo &STI);
807 bool isGFX940(const MCSubtargetInfo &STI);
808 bool hasArchitectedFlatScratch(const MCSubtargetInfo &STI);
809 bool hasMAIInsts(const MCSubtargetInfo &STI);
810 int getTotalNumVGPRs(bool has90AInsts, int32_t ArgNumAGPR, int32_t ArgNumVGPR);
811 
812 /// Is Reg - scalar register
813 bool isSGPR(unsigned Reg, const MCRegisterInfo* TRI);
814 
815 /// If \p Reg is a pseudo reg, return the correct hardware register given
816 /// \p STI otherwise return \p Reg.
817 unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI);
818 
819 /// Convert hardware register \p Reg to a pseudo register
820 LLVM_READNONE
821 unsigned mc2PseudoReg(unsigned Reg);
822 
823 /// Can this operand also contain immediate values?
824 bool isSISrcOperand(const MCInstrDesc &Desc, unsigned OpNo);
825 
826 /// Is this floating-point operand?
827 bool isSISrcFPOperand(const MCInstrDesc &Desc, unsigned OpNo);
828 
829 /// Does this operand support only inlinable literals?
830 bool isSISrcInlinableOperand(const MCInstrDesc &Desc, unsigned OpNo);
831 
832 /// Get the size in bits of a register from the register class \p RC.
833 unsigned getRegBitWidth(unsigned RCID);
834 
835 /// Get the size in bits of a register from the register class \p RC.
836 unsigned getRegBitWidth(const MCRegisterClass &RC);
837 
838 /// Get size of register operand
839 unsigned getRegOperandSize(const MCRegisterInfo *MRI, const MCInstrDesc &Desc,
840                            unsigned OpNo);
841 
842 LLVM_READNONE
843 inline unsigned getOperandSize(const MCOperandInfo &OpInfo) {
844   switch (OpInfo.OperandType) {
845   case AMDGPU::OPERAND_REG_IMM_INT32:
846   case AMDGPU::OPERAND_REG_IMM_FP32:
847   case AMDGPU::OPERAND_REG_IMM_FP32_DEFERRED:
848   case AMDGPU::OPERAND_REG_INLINE_C_INT32:
849   case AMDGPU::OPERAND_REG_INLINE_C_FP32:
850   case AMDGPU::OPERAND_REG_INLINE_AC_INT32:
851   case AMDGPU::OPERAND_REG_INLINE_AC_FP32:
852   case AMDGPU::OPERAND_REG_IMM_V2INT32:
853   case AMDGPU::OPERAND_REG_IMM_V2FP32:
854   case AMDGPU::OPERAND_REG_INLINE_C_V2INT32:
855   case AMDGPU::OPERAND_REG_INLINE_C_V2FP32:
856   case AMDGPU::OPERAND_KIMM32:
857   case AMDGPU::OPERAND_KIMM16: // mandatory literal is always size 4
858     return 4;
859 
860   case AMDGPU::OPERAND_REG_IMM_INT64:
861   case AMDGPU::OPERAND_REG_IMM_FP64:
862   case AMDGPU::OPERAND_REG_INLINE_C_INT64:
863   case AMDGPU::OPERAND_REG_INLINE_C_FP64:
864   case AMDGPU::OPERAND_REG_INLINE_AC_FP64:
865     return 8;
866 
867   case AMDGPU::OPERAND_REG_IMM_INT16:
868   case AMDGPU::OPERAND_REG_IMM_FP16:
869   case AMDGPU::OPERAND_REG_IMM_FP16_DEFERRED:
870   case AMDGPU::OPERAND_REG_INLINE_C_INT16:
871   case AMDGPU::OPERAND_REG_INLINE_C_FP16:
872   case AMDGPU::OPERAND_REG_INLINE_C_V2INT16:
873   case AMDGPU::OPERAND_REG_INLINE_C_V2FP16:
874   case AMDGPU::OPERAND_REG_INLINE_AC_INT16:
875   case AMDGPU::OPERAND_REG_INLINE_AC_FP16:
876   case AMDGPU::OPERAND_REG_INLINE_AC_V2INT16:
877   case AMDGPU::OPERAND_REG_INLINE_AC_V2FP16:
878   case AMDGPU::OPERAND_REG_IMM_V2INT16:
879   case AMDGPU::OPERAND_REG_IMM_V2FP16:
880     return 2;
881 
882   default:
883     llvm_unreachable("unhandled operand type");
884   }
885 }
886 
887 LLVM_READNONE
888 inline unsigned getOperandSize(const MCInstrDesc &Desc, unsigned OpNo) {
889   return getOperandSize(Desc.OpInfo[OpNo]);
890 }
891 
892 /// Is this literal inlinable, and not one of the values intended for floating
893 /// point values.
894 LLVM_READNONE
895 inline bool isInlinableIntLiteral(int64_t Literal) {
896   return Literal >= -16 && Literal <= 64;
897 }
898 
899 /// Is this literal inlinable
900 LLVM_READNONE
901 bool isInlinableLiteral64(int64_t Literal, bool HasInv2Pi);
902 
903 LLVM_READNONE
904 bool isInlinableLiteral32(int32_t Literal, bool HasInv2Pi);
905 
906 LLVM_READNONE
907 bool isInlinableLiteral16(int16_t Literal, bool HasInv2Pi);
908 
909 LLVM_READNONE
910 bool isInlinableLiteralV216(int32_t Literal, bool HasInv2Pi);
911 
912 LLVM_READNONE
913 bool isInlinableIntLiteralV216(int32_t Literal);
914 
915 LLVM_READNONE
916 bool isFoldableLiteralV216(int32_t Literal, bool HasInv2Pi);
917 
918 bool isArgPassedInSGPR(const Argument *Arg);
919 
920 LLVM_READONLY
921 bool isLegalSMRDEncodedUnsignedOffset(const MCSubtargetInfo &ST,
922                                       int64_t EncodedOffset);
923 
924 LLVM_READONLY
925 bool isLegalSMRDEncodedSignedOffset(const MCSubtargetInfo &ST,
926                                     int64_t EncodedOffset,
927                                     bool IsBuffer);
928 
929 /// Convert \p ByteOffset to dwords if the subtarget uses dword SMRD immediate
930 /// offsets.
931 uint64_t convertSMRDOffsetUnits(const MCSubtargetInfo &ST, uint64_t ByteOffset);
932 
933 /// \returns The encoding that will be used for \p ByteOffset in the
934 /// SMRD offset field, or None if it won't fit. On GFX9 and GFX10
935 /// S_LOAD instructions have a signed offset, on other subtargets it is
936 /// unsigned. S_BUFFER has an unsigned offset for all subtargets.
937 Optional<int64_t> getSMRDEncodedOffset(const MCSubtargetInfo &ST,
938                                        int64_t ByteOffset, bool IsBuffer);
939 
940 /// \return The encoding that can be used for a 32-bit literal offset in an SMRD
941 /// instruction. This is only useful on CI.s
942 Optional<int64_t> getSMRDEncodedLiteralOffset32(const MCSubtargetInfo &ST,
943                                                 int64_t ByteOffset);
944 
945 /// For FLAT segment the offset must be positive;
946 /// MSB is ignored and forced to zero.
947 ///
948 /// \return The number of bits available for the offset field in flat
949 /// instructions.
950 unsigned getNumFlatOffsetBits(const MCSubtargetInfo &ST, bool Signed);
951 
952 /// \returns true if this offset is small enough to fit in the SMRD
953 /// offset field.  \p ByteOffset should be the offset in bytes and
954 /// not the encoded offset.
955 bool isLegalSMRDImmOffset(const MCSubtargetInfo &ST, int64_t ByteOffset);
956 
957 bool splitMUBUFOffset(uint32_t Imm, uint32_t &SOffset, uint32_t &ImmOffset,
958                       const GCNSubtarget *Subtarget,
959                       Align Alignment = Align(4));
960 
961 LLVM_READNONE
962 inline bool isLegal64BitDPPControl(unsigned DC) {
963   return DC >= DPP::ROW_NEWBCAST_FIRST && DC <= DPP::ROW_NEWBCAST_LAST;
964 }
965 
966 /// \returns true if the intrinsic is divergent
967 bool isIntrinsicSourceOfDivergence(unsigned IntrID);
968 
969 // Track defaults for fields in the MODE register.
970 struct SIModeRegisterDefaults {
971   /// Floating point opcodes that support exception flag gathering quiet and
972   /// propagate signaling NaN inputs per IEEE 754-2008. Min_dx10 and max_dx10
973   /// become IEEE 754- 2008 compliant due to signaling NaN propagation and
974   /// quieting.
975   bool IEEE : 1;
976 
977   /// Used by the vector ALU to force DX10-style treatment of NaNs: when set,
978   /// clamp NaN to zero; otherwise, pass NaN through.
979   bool DX10Clamp : 1;
980 
981   /// If this is set, neither input or output denormals are flushed for most f32
982   /// instructions.
983   bool FP32InputDenormals : 1;
984   bool FP32OutputDenormals : 1;
985 
986   /// If this is set, neither input or output denormals are flushed for both f64
987   /// and f16/v2f16 instructions.
988   bool FP64FP16InputDenormals : 1;
989   bool FP64FP16OutputDenormals : 1;
990 
991   SIModeRegisterDefaults() :
992     IEEE(true),
993     DX10Clamp(true),
994     FP32InputDenormals(true),
995     FP32OutputDenormals(true),
996     FP64FP16InputDenormals(true),
997     FP64FP16OutputDenormals(true) {}
998 
999   SIModeRegisterDefaults(const Function &F);
1000 
1001   static SIModeRegisterDefaults getDefaultForCallingConv(CallingConv::ID CC) {
1002     SIModeRegisterDefaults Mode;
1003     Mode.IEEE = !AMDGPU::isShader(CC);
1004     return Mode;
1005   }
1006 
1007   bool operator ==(const SIModeRegisterDefaults Other) const {
1008     return IEEE == Other.IEEE && DX10Clamp == Other.DX10Clamp &&
1009            FP32InputDenormals == Other.FP32InputDenormals &&
1010            FP32OutputDenormals == Other.FP32OutputDenormals &&
1011            FP64FP16InputDenormals == Other.FP64FP16InputDenormals &&
1012            FP64FP16OutputDenormals == Other.FP64FP16OutputDenormals;
1013   }
1014 
1015   bool allFP32Denormals() const {
1016     return FP32InputDenormals && FP32OutputDenormals;
1017   }
1018 
1019   bool allFP64FP16Denormals() const {
1020     return FP64FP16InputDenormals && FP64FP16OutputDenormals;
1021   }
1022 
1023   /// Get the encoding value for the FP_DENORM bits of the mode register for the
1024   /// FP32 denormal mode.
1025   uint32_t fpDenormModeSPValue() const {
1026     if (FP32InputDenormals && FP32OutputDenormals)
1027       return FP_DENORM_FLUSH_NONE;
1028     if (FP32InputDenormals)
1029       return FP_DENORM_FLUSH_OUT;
1030     if (FP32OutputDenormals)
1031       return FP_DENORM_FLUSH_IN;
1032     return FP_DENORM_FLUSH_IN_FLUSH_OUT;
1033   }
1034 
1035   /// Get the encoding value for the FP_DENORM bits of the mode register for the
1036   /// FP64/FP16 denormal mode.
1037   uint32_t fpDenormModeDPValue() const {
1038     if (FP64FP16InputDenormals && FP64FP16OutputDenormals)
1039       return FP_DENORM_FLUSH_NONE;
1040     if (FP64FP16InputDenormals)
1041       return FP_DENORM_FLUSH_OUT;
1042     if (FP64FP16OutputDenormals)
1043       return FP_DENORM_FLUSH_IN;
1044     return FP_DENORM_FLUSH_IN_FLUSH_OUT;
1045   }
1046 
1047   /// Returns true if a flag is compatible if it's enabled in the callee, but
1048   /// disabled in the caller.
1049   static bool oneWayCompatible(bool CallerMode, bool CalleeMode) {
1050     return CallerMode == CalleeMode || (!CallerMode && CalleeMode);
1051   }
1052 
1053   // FIXME: Inlining should be OK for dx10-clamp, since the caller's mode should
1054   // be able to override.
1055   bool isInlineCompatible(SIModeRegisterDefaults CalleeMode) const {
1056     if (DX10Clamp != CalleeMode.DX10Clamp)
1057       return false;
1058     if (IEEE != CalleeMode.IEEE)
1059       return false;
1060 
1061     // Allow inlining denormals enabled into denormals flushed functions.
1062     return oneWayCompatible(FP64FP16InputDenormals, CalleeMode.FP64FP16InputDenormals) &&
1063            oneWayCompatible(FP64FP16OutputDenormals, CalleeMode.FP64FP16OutputDenormals) &&
1064            oneWayCompatible(FP32InputDenormals, CalleeMode.FP32InputDenormals) &&
1065            oneWayCompatible(FP32OutputDenormals, CalleeMode.FP32OutputDenormals);
1066   }
1067 };
1068 
1069 } // end namespace AMDGPU
1070 
1071 raw_ostream &operator<<(raw_ostream &OS,
1072                         const AMDGPU::IsaInfo::TargetIDSetting S);
1073 
1074 } // end namespace llvm
1075 
1076 #endif // LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
1077