1 //===- AMDGPUBaseInfo.h - Top level definitions for AMDGPU ------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #ifndef LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
10 #define LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
11 
12 #include "SIDefines.h"
13 #include "llvm/IR/CallingConv.h"
14 #include "llvm/Support/Alignment.h"
15 
16 struct amd_kernel_code_t;
17 
18 namespace llvm {
19 
20 struct Align;
21 class Argument;
22 class Function;
23 class GCNSubtarget;
24 class GlobalValue;
25 class MCRegisterClass;
26 class MCRegisterInfo;
27 class MCSubtargetInfo;
28 class StringRef;
29 class Triple;
30 
31 namespace amdhsa {
32 struct kernel_descriptor_t;
33 }
34 
35 namespace AMDGPU {
36 
37 struct IsaVersion;
38 
39 /// \returns HSA OS ABI Version identification.
40 Optional<uint8_t> getHsaAbiVersion(const MCSubtargetInfo *STI);
41 /// \returns True if HSA OS ABI Version identification is 2,
42 /// false otherwise.
43 bool isHsaAbiVersion2(const MCSubtargetInfo *STI);
44 /// \returns True if HSA OS ABI Version identification is 3,
45 /// false otherwise.
46 bool isHsaAbiVersion3(const MCSubtargetInfo *STI);
47 /// \returns True if HSA OS ABI Version identification is 4,
48 /// false otherwise.
49 bool isHsaAbiVersion4(const MCSubtargetInfo *STI);
50 /// \returns True if HSA OS ABI Version identification is 5,
51 /// false otherwise.
52 bool isHsaAbiVersion5(const MCSubtargetInfo *STI);
53 /// \returns True if HSA OS ABI Version identification is 3 and above,
54 /// false otherwise.
55 bool isHsaAbiVersion3AndAbove(const MCSubtargetInfo *STI);
56 
57 /// \returns The offset of the multigrid_sync_arg argument from implicitarg_ptr
58 unsigned getMultigridSyncArgImplicitArgPosition();
59 
60 /// \returns The offset of the hostcall pointer argument from implicitarg_ptr
61 unsigned getHostcallImplicitArgPosition();
62 
63 /// \returns Code object version.
64 unsigned getAmdhsaCodeObjectVersion();
65 
66 struct GcnBufferFormatInfo {
67   unsigned Format;
68   unsigned BitsPerComp;
69   unsigned NumComponents;
70   unsigned NumFormat;
71   unsigned DataFormat;
72 };
73 
74 struct MAIInstInfo {
75   uint16_t Opcode;
76   bool is_dgemm;
77   bool is_gfx940_xdl;
78 };
79 
80 #define GET_MIMGBaseOpcode_DECL
81 #define GET_MIMGDim_DECL
82 #define GET_MIMGEncoding_DECL
83 #define GET_MIMGLZMapping_DECL
84 #define GET_MIMGMIPMapping_DECL
85 #define GET_MIMGBiASMapping_DECL
86 #define GET_MAIInstInfoTable_DECL
87 #include "AMDGPUGenSearchableTables.inc"
88 
89 namespace IsaInfo {
90 
91 enum {
92   // The closed Vulkan driver sets 96, which limits the wave count to 8 but
93   // doesn't spill SGPRs as much as when 80 is set.
94   FIXED_NUM_SGPRS_FOR_INIT_BUG = 96,
95   TRAP_NUM_SGPRS = 16
96 };
97 
98 enum class TargetIDSetting {
99   Unsupported,
100   Any,
101   Off,
102   On
103 };
104 
105 class AMDGPUTargetID {
106 private:
107   const MCSubtargetInfo &STI;
108   TargetIDSetting XnackSetting;
109   TargetIDSetting SramEccSetting;
110 
111 public:
112   explicit AMDGPUTargetID(const MCSubtargetInfo &STI);
113   ~AMDGPUTargetID() = default;
114 
115   /// \return True if the current xnack setting is not "Unsupported".
116   bool isXnackSupported() const {
117     return XnackSetting != TargetIDSetting::Unsupported;
118   }
119 
120   /// \returns True if the current xnack setting is "On" or "Any".
121   bool isXnackOnOrAny() const {
122     return XnackSetting == TargetIDSetting::On ||
123         XnackSetting == TargetIDSetting::Any;
124   }
125 
126   /// \returns True if current xnack setting is "On" or "Off",
127   /// false otherwise.
128   bool isXnackOnOrOff() const {
129     return getXnackSetting() == TargetIDSetting::On ||
130         getXnackSetting() == TargetIDSetting::Off;
131   }
132 
133   /// \returns The current xnack TargetIDSetting, possible options are
134   /// "Unsupported", "Any", "Off", and "On".
135   TargetIDSetting getXnackSetting() const {
136     return XnackSetting;
137   }
138 
139   /// Sets xnack setting to \p NewXnackSetting.
140   void setXnackSetting(TargetIDSetting NewXnackSetting) {
141     XnackSetting = NewXnackSetting;
142   }
143 
144   /// \return True if the current sramecc setting is not "Unsupported".
145   bool isSramEccSupported() const {
146     return SramEccSetting != TargetIDSetting::Unsupported;
147   }
148 
149   /// \returns True if the current sramecc setting is "On" or "Any".
150   bool isSramEccOnOrAny() const {
151   return SramEccSetting == TargetIDSetting::On ||
152       SramEccSetting == TargetIDSetting::Any;
153   }
154 
155   /// \returns True if current sramecc setting is "On" or "Off",
156   /// false otherwise.
157   bool isSramEccOnOrOff() const {
158     return getSramEccSetting() == TargetIDSetting::On ||
159         getSramEccSetting() == TargetIDSetting::Off;
160   }
161 
162   /// \returns The current sramecc TargetIDSetting, possible options are
163   /// "Unsupported", "Any", "Off", and "On".
164   TargetIDSetting getSramEccSetting() const {
165     return SramEccSetting;
166   }
167 
168   /// Sets sramecc setting to \p NewSramEccSetting.
169   void setSramEccSetting(TargetIDSetting NewSramEccSetting) {
170     SramEccSetting = NewSramEccSetting;
171   }
172 
173   void setTargetIDFromFeaturesString(StringRef FS);
174   void setTargetIDFromTargetIDStream(StringRef TargetID);
175 
176   /// \returns String representation of an object.
177   std::string toString() const;
178 };
179 
180 /// \returns Wavefront size for given subtarget \p STI.
181 unsigned getWavefrontSize(const MCSubtargetInfo *STI);
182 
183 /// \returns Local memory size in bytes for given subtarget \p STI.
184 unsigned getLocalMemorySize(const MCSubtargetInfo *STI);
185 
186 /// \returns Number of execution units per compute unit for given subtarget \p
187 /// STI.
188 unsigned getEUsPerCU(const MCSubtargetInfo *STI);
189 
190 /// \returns Maximum number of work groups per compute unit for given subtarget
191 /// \p STI and limited by given \p FlatWorkGroupSize.
192 unsigned getMaxWorkGroupsPerCU(const MCSubtargetInfo *STI,
193                                unsigned FlatWorkGroupSize);
194 
195 /// \returns Minimum number of waves per execution unit for given subtarget \p
196 /// STI.
197 unsigned getMinWavesPerEU(const MCSubtargetInfo *STI);
198 
199 /// \returns Maximum number of waves per execution unit for given subtarget \p
200 /// STI without any kind of limitation.
201 unsigned getMaxWavesPerEU(const MCSubtargetInfo *STI);
202 
203 /// \returns Number of waves per execution unit required to support the given \p
204 /// FlatWorkGroupSize.
205 unsigned getWavesPerEUForWorkGroup(const MCSubtargetInfo *STI,
206                                    unsigned FlatWorkGroupSize);
207 
208 /// \returns Minimum flat work group size for given subtarget \p STI.
209 unsigned getMinFlatWorkGroupSize(const MCSubtargetInfo *STI);
210 
211 /// \returns Maximum flat work group size for given subtarget \p STI.
212 unsigned getMaxFlatWorkGroupSize(const MCSubtargetInfo *STI);
213 
214 /// \returns Number of waves per work group for given subtarget \p STI and
215 /// \p FlatWorkGroupSize.
216 unsigned getWavesPerWorkGroup(const MCSubtargetInfo *STI,
217                               unsigned FlatWorkGroupSize);
218 
219 /// \returns SGPR allocation granularity for given subtarget \p STI.
220 unsigned getSGPRAllocGranule(const MCSubtargetInfo *STI);
221 
222 /// \returns SGPR encoding granularity for given subtarget \p STI.
223 unsigned getSGPREncodingGranule(const MCSubtargetInfo *STI);
224 
225 /// \returns Total number of SGPRs for given subtarget \p STI.
226 unsigned getTotalNumSGPRs(const MCSubtargetInfo *STI);
227 
228 /// \returns Addressable number of SGPRs for given subtarget \p STI.
229 unsigned getAddressableNumSGPRs(const MCSubtargetInfo *STI);
230 
231 /// \returns Minimum number of SGPRs that meets the given number of waves per
232 /// execution unit requirement for given subtarget \p STI.
233 unsigned getMinNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU);
234 
235 /// \returns Maximum number of SGPRs that meets the given number of waves per
236 /// execution unit requirement for given subtarget \p STI.
237 unsigned getMaxNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU,
238                         bool Addressable);
239 
240 /// \returns Number of extra SGPRs implicitly required by given subtarget \p
241 /// STI when the given special registers are used.
242 unsigned getNumExtraSGPRs(const MCSubtargetInfo *STI, bool VCCUsed,
243                           bool FlatScrUsed, bool XNACKUsed);
244 
245 /// \returns Number of extra SGPRs implicitly required by given subtarget \p
246 /// STI when the given special registers are used. XNACK is inferred from
247 /// \p STI.
248 unsigned getNumExtraSGPRs(const MCSubtargetInfo *STI, bool VCCUsed,
249                           bool FlatScrUsed);
250 
251 /// \returns Number of SGPR blocks needed for given subtarget \p STI when
252 /// \p NumSGPRs are used. \p NumSGPRs should already include any special
253 /// register counts.
254 unsigned getNumSGPRBlocks(const MCSubtargetInfo *STI, unsigned NumSGPRs);
255 
256 /// \returns VGPR allocation granularity for given subtarget \p STI.
257 ///
258 /// For subtargets which support it, \p EnableWavefrontSize32 should match
259 /// the ENABLE_WAVEFRONT_SIZE32 kernel descriptor field.
260 unsigned getVGPRAllocGranule(const MCSubtargetInfo *STI,
261                              Optional<bool> EnableWavefrontSize32 = None);
262 
263 /// \returns VGPR encoding granularity for given subtarget \p STI.
264 ///
265 /// For subtargets which support it, \p EnableWavefrontSize32 should match
266 /// the ENABLE_WAVEFRONT_SIZE32 kernel descriptor field.
267 unsigned getVGPREncodingGranule(const MCSubtargetInfo *STI,
268                                 Optional<bool> EnableWavefrontSize32 = None);
269 
270 /// \returns Total number of VGPRs for given subtarget \p STI.
271 unsigned getTotalNumVGPRs(const MCSubtargetInfo *STI);
272 
273 /// \returns Addressable number of VGPRs for given subtarget \p STI.
274 unsigned getAddressableNumVGPRs(const MCSubtargetInfo *STI);
275 
276 /// \returns Minimum number of VGPRs that meets given number of waves per
277 /// execution unit requirement for given subtarget \p STI.
278 unsigned getMinNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU);
279 
280 /// \returns Maximum number of VGPRs that meets given number of waves per
281 /// execution unit requirement for given subtarget \p STI.
282 unsigned getMaxNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU);
283 
284 /// \returns Number of VGPR blocks needed for given subtarget \p STI when
285 /// \p NumVGPRs are used.
286 ///
287 /// For subtargets which support it, \p EnableWavefrontSize32 should match the
288 /// ENABLE_WAVEFRONT_SIZE32 kernel descriptor field.
289 unsigned getNumVGPRBlocks(const MCSubtargetInfo *STI, unsigned NumSGPRs,
290                           Optional<bool> EnableWavefrontSize32 = None);
291 
292 } // end namespace IsaInfo
293 
294 LLVM_READONLY
295 int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx);
296 
297 LLVM_READONLY
298 int getSOPPWithRelaxation(uint16_t Opcode);
299 
300 struct MIMGBaseOpcodeInfo {
301   MIMGBaseOpcode BaseOpcode;
302   bool Store;
303   bool Atomic;
304   bool AtomicX2;
305   bool Sampler;
306   bool Gather4;
307 
308   uint8_t NumExtraArgs;
309   bool Gradients;
310   bool G16;
311   bool Coordinates;
312   bool LodOrClampOrMip;
313   bool HasD16;
314   bool MSAA;
315   bool BVH;
316 };
317 
318 LLVM_READONLY
319 const MIMGBaseOpcodeInfo *getMIMGBaseOpcode(unsigned Opc);
320 
321 LLVM_READONLY
322 const MIMGBaseOpcodeInfo *getMIMGBaseOpcodeInfo(unsigned BaseOpcode);
323 
324 struct MIMGDimInfo {
325   MIMGDim Dim;
326   uint8_t NumCoords;
327   uint8_t NumGradients;
328   bool MSAA;
329   bool DA;
330   uint8_t Encoding;
331   const char *AsmSuffix;
332 };
333 
334 LLVM_READONLY
335 const MIMGDimInfo *getMIMGDimInfo(unsigned DimEnum);
336 
337 LLVM_READONLY
338 const MIMGDimInfo *getMIMGDimInfoByEncoding(uint8_t DimEnc);
339 
340 LLVM_READONLY
341 const MIMGDimInfo *getMIMGDimInfoByAsmSuffix(StringRef AsmSuffix);
342 
343 struct MIMGLZMappingInfo {
344   MIMGBaseOpcode L;
345   MIMGBaseOpcode LZ;
346 };
347 
348 struct MIMGMIPMappingInfo {
349   MIMGBaseOpcode MIP;
350   MIMGBaseOpcode NONMIP;
351 };
352 
353 struct MIMGBiasMappingInfo {
354   MIMGBaseOpcode Bias;
355   MIMGBaseOpcode NoBias;
356 };
357 
358 struct MIMGOffsetMappingInfo {
359   MIMGBaseOpcode Offset;
360   MIMGBaseOpcode NoOffset;
361 };
362 
363 struct MIMGG16MappingInfo {
364   MIMGBaseOpcode G;
365   MIMGBaseOpcode G16;
366 };
367 
368 LLVM_READONLY
369 const MIMGLZMappingInfo *getMIMGLZMappingInfo(unsigned L);
370 
371 struct WMMAOpcodeMappingInfo {
372   unsigned Opcode2Addr;
373   unsigned Opcode3Addr;
374 };
375 
376 LLVM_READONLY
377 const MIMGMIPMappingInfo *getMIMGMIPMappingInfo(unsigned MIP);
378 
379 LLVM_READONLY
380 const MIMGBiasMappingInfo *getMIMGBiasMappingInfo(unsigned Bias);
381 
382 LLVM_READONLY
383 const MIMGOffsetMappingInfo *getMIMGOffsetMappingInfo(unsigned Offset);
384 
385 LLVM_READONLY
386 const MIMGG16MappingInfo *getMIMGG16MappingInfo(unsigned G);
387 
388 LLVM_READONLY
389 int getMIMGOpcode(unsigned BaseOpcode, unsigned MIMGEncoding,
390                   unsigned VDataDwords, unsigned VAddrDwords);
391 
392 LLVM_READONLY
393 int getMaskedMIMGOp(unsigned Opc, unsigned NewChannels);
394 
395 LLVM_READONLY
396 unsigned getAddrSizeMIMGOp(const MIMGBaseOpcodeInfo *BaseOpcode,
397                            const MIMGDimInfo *Dim, bool IsA16,
398                            bool IsG16Supported);
399 
400 struct MIMGInfo {
401   uint16_t Opcode;
402   uint16_t BaseOpcode;
403   uint8_t MIMGEncoding;
404   uint8_t VDataDwords;
405   uint8_t VAddrDwords;
406   uint8_t VAddrOperands;
407 };
408 
409 LLVM_READONLY
410 const MIMGInfo *getMIMGInfo(unsigned Opc);
411 
412 LLVM_READONLY
413 int getMTBUFBaseOpcode(unsigned Opc);
414 
415 LLVM_READONLY
416 int getMTBUFOpcode(unsigned BaseOpc, unsigned Elements);
417 
418 LLVM_READONLY
419 int getMTBUFElements(unsigned Opc);
420 
421 LLVM_READONLY
422 bool getMTBUFHasVAddr(unsigned Opc);
423 
424 LLVM_READONLY
425 bool getMTBUFHasSrsrc(unsigned Opc);
426 
427 LLVM_READONLY
428 bool getMTBUFHasSoffset(unsigned Opc);
429 
430 LLVM_READONLY
431 int getMUBUFBaseOpcode(unsigned Opc);
432 
433 LLVM_READONLY
434 int getMUBUFOpcode(unsigned BaseOpc, unsigned Elements);
435 
436 LLVM_READONLY
437 int getMUBUFElements(unsigned Opc);
438 
439 LLVM_READONLY
440 bool getMUBUFHasVAddr(unsigned Opc);
441 
442 LLVM_READONLY
443 bool getMUBUFHasSrsrc(unsigned Opc);
444 
445 LLVM_READONLY
446 bool getMUBUFHasSoffset(unsigned Opc);
447 
448 LLVM_READONLY
449 bool getMUBUFIsBufferInv(unsigned Opc);
450 
451 LLVM_READONLY
452 bool getSMEMIsBuffer(unsigned Opc);
453 
454 LLVM_READONLY
455 bool getVOP1IsSingle(unsigned Opc);
456 
457 LLVM_READONLY
458 bool getVOP2IsSingle(unsigned Opc);
459 
460 LLVM_READONLY
461 bool getVOP3IsSingle(unsigned Opc);
462 
463 LLVM_READONLY
464 bool isVOPC64DPP(unsigned Opc);
465 
466 /// Returns true if MAI operation is a double precision GEMM.
467 LLVM_READONLY
468 bool getMAIIsDGEMM(unsigned Opc);
469 
470 LLVM_READONLY
471 bool getMAIIsGFX940XDL(unsigned Opc);
472 
473 LLVM_READONLY
474 const GcnBufferFormatInfo *getGcnBufferFormatInfo(uint8_t BitsPerComp,
475                                                   uint8_t NumComponents,
476                                                   uint8_t NumFormat,
477                                                   const MCSubtargetInfo &STI);
478 LLVM_READONLY
479 const GcnBufferFormatInfo *getGcnBufferFormatInfo(uint8_t Format,
480                                                   const MCSubtargetInfo &STI);
481 
482 LLVM_READONLY
483 int getMCOpcode(uint16_t Opcode, unsigned Gen);
484 
485 LLVM_READONLY
486 unsigned mapWMMA2AddrTo3AddrOpcode(unsigned Opc);
487 
488 LLVM_READONLY
489 unsigned mapWMMA3AddrTo2AddrOpcode(unsigned Opc);
490 
491 void initDefaultAMDKernelCodeT(amd_kernel_code_t &Header,
492                                const MCSubtargetInfo *STI);
493 
494 amdhsa::kernel_descriptor_t getDefaultAmdhsaKernelDescriptor(
495     const MCSubtargetInfo *STI);
496 
497 bool isGroupSegment(const GlobalValue *GV);
498 bool isGlobalSegment(const GlobalValue *GV);
499 bool isReadOnlySegment(const GlobalValue *GV);
500 
501 /// \returns True if constants should be emitted to .text section for given
502 /// target triple \p TT, false otherwise.
503 bool shouldEmitConstantsToTextSection(const Triple &TT);
504 
505 /// \returns Integer value requested using \p F's \p Name attribute.
506 ///
507 /// \returns \p Default if attribute is not present.
508 ///
509 /// \returns \p Default and emits error if requested value cannot be converted
510 /// to integer.
511 int getIntegerAttribute(const Function &F, StringRef Name, int Default);
512 
513 /// \returns A pair of integer values requested using \p F's \p Name attribute
514 /// in "first[,second]" format ("second" is optional unless \p OnlyFirstRequired
515 /// is false).
516 ///
517 /// \returns \p Default if attribute is not present.
518 ///
519 /// \returns \p Default and emits error if one of the requested values cannot be
520 /// converted to integer, or \p OnlyFirstRequired is false and "second" value is
521 /// not present.
522 std::pair<int, int> getIntegerPairAttribute(const Function &F,
523                                             StringRef Name,
524                                             std::pair<int, int> Default,
525                                             bool OnlyFirstRequired = false);
526 
527 /// Represents the counter values to wait for in an s_waitcnt instruction.
528 ///
529 /// Large values (including the maximum possible integer) can be used to
530 /// represent "don't care" waits.
531 struct Waitcnt {
532   unsigned VmCnt = ~0u;
533   unsigned ExpCnt = ~0u;
534   unsigned LgkmCnt = ~0u;
535   unsigned VsCnt = ~0u;
536 
537   Waitcnt() = default;
538   Waitcnt(unsigned VmCnt, unsigned ExpCnt, unsigned LgkmCnt, unsigned VsCnt)
539       : VmCnt(VmCnt), ExpCnt(ExpCnt), LgkmCnt(LgkmCnt), VsCnt(VsCnt) {}
540 
541   static Waitcnt allZero(bool HasVscnt) {
542     return Waitcnt(0, 0, 0, HasVscnt ? 0 : ~0u);
543   }
544   static Waitcnt allZeroExceptVsCnt() { return Waitcnt(0, 0, 0, ~0u); }
545 
546   bool hasWait() const {
547     return VmCnt != ~0u || ExpCnt != ~0u || LgkmCnt != ~0u || VsCnt != ~0u;
548   }
549 
550   bool hasWaitExceptVsCnt() const {
551     return VmCnt != ~0u || ExpCnt != ~0u || LgkmCnt != ~0u;
552   }
553 
554   bool hasWaitVsCnt() const {
555     return VsCnt != ~0u;
556   }
557 
558   bool dominates(const Waitcnt &Other) const {
559     return VmCnt <= Other.VmCnt && ExpCnt <= Other.ExpCnt &&
560            LgkmCnt <= Other.LgkmCnt && VsCnt <= Other.VsCnt;
561   }
562 
563   Waitcnt combined(const Waitcnt &Other) const {
564     return Waitcnt(std::min(VmCnt, Other.VmCnt), std::min(ExpCnt, Other.ExpCnt),
565                    std::min(LgkmCnt, Other.LgkmCnt),
566                    std::min(VsCnt, Other.VsCnt));
567   }
568 };
569 
570 /// \returns Vmcnt bit mask for given isa \p Version.
571 unsigned getVmcntBitMask(const IsaVersion &Version);
572 
573 /// \returns Expcnt bit mask for given isa \p Version.
574 unsigned getExpcntBitMask(const IsaVersion &Version);
575 
576 /// \returns Lgkmcnt bit mask for given isa \p Version.
577 unsigned getLgkmcntBitMask(const IsaVersion &Version);
578 
579 /// \returns Waitcnt bit mask for given isa \p Version.
580 unsigned getWaitcntBitMask(const IsaVersion &Version);
581 
582 /// \returns Decoded Vmcnt from given \p Waitcnt for given isa \p Version.
583 unsigned decodeVmcnt(const IsaVersion &Version, unsigned Waitcnt);
584 
585 /// \returns Decoded Expcnt from given \p Waitcnt for given isa \p Version.
586 unsigned decodeExpcnt(const IsaVersion &Version, unsigned Waitcnt);
587 
588 /// \returns Decoded Lgkmcnt from given \p Waitcnt for given isa \p Version.
589 unsigned decodeLgkmcnt(const IsaVersion &Version, unsigned Waitcnt);
590 
591 /// Decodes Vmcnt, Expcnt and Lgkmcnt from given \p Waitcnt for given isa
592 /// \p Version, and writes decoded values into \p Vmcnt, \p Expcnt and
593 /// \p Lgkmcnt respectively.
594 ///
595 /// \details \p Vmcnt, \p Expcnt and \p Lgkmcnt are decoded as follows:
596 ///     \p Vmcnt = \p Waitcnt[3:0]        (pre-gfx9)
597 ///     \p Vmcnt = \p Waitcnt[15:14,3:0]  (gfx9,10)
598 ///     \p Vmcnt = \p Waitcnt[15:10]      (gfx11+)
599 ///     \p Expcnt = \p Waitcnt[6:4]       (pre-gfx11)
600 ///     \p Expcnt = \p Waitcnt[2:0]       (gfx11+)
601 ///     \p Lgkmcnt = \p Waitcnt[11:8]     (pre-gfx10)
602 ///     \p Lgkmcnt = \p Waitcnt[13:8]     (gfx10)
603 ///     \p Lgkmcnt = \p Waitcnt[9:4]      (gfx11+)
604 void decodeWaitcnt(const IsaVersion &Version, unsigned Waitcnt,
605                    unsigned &Vmcnt, unsigned &Expcnt, unsigned &Lgkmcnt);
606 
607 Waitcnt decodeWaitcnt(const IsaVersion &Version, unsigned Encoded);
608 
609 /// \returns \p Waitcnt with encoded \p Vmcnt for given isa \p Version.
610 unsigned encodeVmcnt(const IsaVersion &Version, unsigned Waitcnt,
611                      unsigned Vmcnt);
612 
613 /// \returns \p Waitcnt with encoded \p Expcnt for given isa \p Version.
614 unsigned encodeExpcnt(const IsaVersion &Version, unsigned Waitcnt,
615                       unsigned Expcnt);
616 
617 /// \returns \p Waitcnt with encoded \p Lgkmcnt for given isa \p Version.
618 unsigned encodeLgkmcnt(const IsaVersion &Version, unsigned Waitcnt,
619                        unsigned Lgkmcnt);
620 
621 /// Encodes \p Vmcnt, \p Expcnt and \p Lgkmcnt into Waitcnt for given isa
622 /// \p Version.
623 ///
624 /// \details \p Vmcnt, \p Expcnt and \p Lgkmcnt are encoded as follows:
625 ///     Waitcnt[2:0]   = \p Expcnt      (gfx11+)
626 ///     Waitcnt[3:0]   = \p Vmcnt       (pre-gfx9)
627 ///     Waitcnt[3:0]   = \p Vmcnt[3:0]  (gfx9,10)
628 ///     Waitcnt[6:4]   = \p Expcnt      (pre-gfx11)
629 ///     Waitcnt[9:4]   = \p Lgkmcnt     (gfx11+)
630 ///     Waitcnt[11:8]  = \p Lgkmcnt     (pre-gfx10)
631 ///     Waitcnt[13:8]  = \p Lgkmcnt     (gfx10)
632 ///     Waitcnt[15:10] = \p Vmcnt       (gfx11+)
633 ///     Waitcnt[15:14] = \p Vmcnt[5:4]  (gfx9,10)
634 ///
635 /// \returns Waitcnt with encoded \p Vmcnt, \p Expcnt and \p Lgkmcnt for given
636 /// isa \p Version.
637 unsigned encodeWaitcnt(const IsaVersion &Version,
638                        unsigned Vmcnt, unsigned Expcnt, unsigned Lgkmcnt);
639 
640 unsigned encodeWaitcnt(const IsaVersion &Version, const Waitcnt &Decoded);
641 
642 namespace Hwreg {
643 
644 LLVM_READONLY
645 int64_t getHwregId(const StringRef Name, const MCSubtargetInfo &STI);
646 
647 LLVM_READNONE
648 bool isValidHwreg(int64_t Id);
649 
650 LLVM_READNONE
651 bool isValidHwregOffset(int64_t Offset);
652 
653 LLVM_READNONE
654 bool isValidHwregWidth(int64_t Width);
655 
656 LLVM_READNONE
657 uint64_t encodeHwreg(uint64_t Id, uint64_t Offset, uint64_t Width);
658 
659 LLVM_READNONE
660 StringRef getHwreg(unsigned Id, const MCSubtargetInfo &STI);
661 
662 void decodeHwreg(unsigned Val, unsigned &Id, unsigned &Offset, unsigned &Width);
663 
664 } // namespace Hwreg
665 
666 namespace DepCtr {
667 
668 int getDefaultDepCtrEncoding(const MCSubtargetInfo &STI);
669 int encodeDepCtr(const StringRef Name, int64_t Val, unsigned &UsedOprMask,
670                  const MCSubtargetInfo &STI);
671 bool isSymbolicDepCtrEncoding(unsigned Code, bool &HasNonDefaultVal,
672                               const MCSubtargetInfo &STI);
673 bool decodeDepCtr(unsigned Code, int &Id, StringRef &Name, unsigned &Val,
674                   bool &IsDefault, const MCSubtargetInfo &STI);
675 
676 } // namespace DepCtr
677 
678 namespace Exp {
679 
680 bool getTgtName(unsigned Id, StringRef &Name, int &Index);
681 
682 LLVM_READONLY
683 unsigned getTgtId(const StringRef Name);
684 
685 LLVM_READNONE
686 bool isSupportedTgtId(unsigned Id, const MCSubtargetInfo &STI);
687 
688 } // namespace Exp
689 
690 namespace MTBUFFormat {
691 
692 LLVM_READNONE
693 int64_t encodeDfmtNfmt(unsigned Dfmt, unsigned Nfmt);
694 
695 void decodeDfmtNfmt(unsigned Format, unsigned &Dfmt, unsigned &Nfmt);
696 
697 int64_t getDfmt(const StringRef Name);
698 
699 StringRef getDfmtName(unsigned Id);
700 
701 int64_t getNfmt(const StringRef Name, const MCSubtargetInfo &STI);
702 
703 StringRef getNfmtName(unsigned Id, const MCSubtargetInfo &STI);
704 
705 bool isValidDfmtNfmt(unsigned Val, const MCSubtargetInfo &STI);
706 
707 bool isValidNfmt(unsigned Val, const MCSubtargetInfo &STI);
708 
709 int64_t getUnifiedFormat(const StringRef Name, const MCSubtargetInfo &STI);
710 
711 StringRef getUnifiedFormatName(unsigned Id, const MCSubtargetInfo &STI);
712 
713 bool isValidUnifiedFormat(unsigned Val, const MCSubtargetInfo &STI);
714 
715 int64_t convertDfmtNfmt2Ufmt(unsigned Dfmt, unsigned Nfmt,
716                              const MCSubtargetInfo &STI);
717 
718 bool isValidFormatEncoding(unsigned Val, const MCSubtargetInfo &STI);
719 
720 unsigned getDefaultFormatEncoding(const MCSubtargetInfo &STI);
721 
722 } // namespace MTBUFFormat
723 
724 namespace SendMsg {
725 
726 LLVM_READONLY
727 int64_t getMsgId(const StringRef Name, const MCSubtargetInfo &STI);
728 
729 LLVM_READONLY
730 int64_t getMsgOpId(int64_t MsgId, const StringRef Name);
731 
732 LLVM_READNONE
733 StringRef getMsgName(int64_t MsgId, const MCSubtargetInfo &STI);
734 
735 LLVM_READNONE
736 StringRef getMsgOpName(int64_t MsgId, int64_t OpId, const MCSubtargetInfo &STI);
737 
738 LLVM_READNONE
739 bool isValidMsgId(int64_t MsgId, const MCSubtargetInfo &STI);
740 
741 LLVM_READNONE
742 bool isValidMsgOp(int64_t MsgId, int64_t OpId, const MCSubtargetInfo &STI,
743                   bool Strict = true);
744 
745 LLVM_READNONE
746 bool isValidMsgStream(int64_t MsgId, int64_t OpId, int64_t StreamId,
747                       const MCSubtargetInfo &STI, bool Strict = true);
748 
749 LLVM_READNONE
750 bool msgRequiresOp(int64_t MsgId, const MCSubtargetInfo &STI);
751 
752 LLVM_READNONE
753 bool msgSupportsStream(int64_t MsgId, int64_t OpId, const MCSubtargetInfo &STI);
754 
755 void decodeMsg(unsigned Val, uint16_t &MsgId, uint16_t &OpId,
756                uint16_t &StreamId, const MCSubtargetInfo &STI);
757 
758 LLVM_READNONE
759 uint64_t encodeMsg(uint64_t MsgId,
760                    uint64_t OpId,
761                    uint64_t StreamId);
762 
763 } // namespace SendMsg
764 
765 
766 unsigned getInitialPSInputAddr(const Function &F);
767 
768 bool getHasColorExport(const Function &F);
769 
770 bool getHasDepthExport(const Function &F);
771 
772 LLVM_READNONE
773 bool isShader(CallingConv::ID CC);
774 
775 LLVM_READNONE
776 bool isGraphics(CallingConv::ID CC);
777 
778 LLVM_READNONE
779 bool isCompute(CallingConv::ID CC);
780 
781 LLVM_READNONE
782 bool isEntryFunctionCC(CallingConv::ID CC);
783 
784 // These functions are considered entrypoints into the current module, i.e. they
785 // are allowed to be called from outside the current module. This is different
786 // from isEntryFunctionCC, which is only true for functions that are entered by
787 // the hardware. Module entry points include all entry functions but also
788 // include functions that can be called from other functions inside or outside
789 // the current module. Module entry functions are allowed to allocate LDS.
790 LLVM_READNONE
791 bool isModuleEntryFunctionCC(CallingConv::ID CC);
792 
793 bool isKernelCC(const Function *Func);
794 
795 // FIXME: Remove this when calling conventions cleaned up
796 LLVM_READNONE
797 inline bool isKernel(CallingConv::ID CC) {
798   switch (CC) {
799   case CallingConv::AMDGPU_KERNEL:
800   case CallingConv::SPIR_KERNEL:
801     return true;
802   default:
803     return false;
804   }
805 }
806 
807 bool hasXNACK(const MCSubtargetInfo &STI);
808 bool hasSRAMECC(const MCSubtargetInfo &STI);
809 bool hasMIMG_R128(const MCSubtargetInfo &STI);
810 bool hasGFX10A16(const MCSubtargetInfo &STI);
811 bool hasG16(const MCSubtargetInfo &STI);
812 bool hasPackedD16(const MCSubtargetInfo &STI);
813 
814 bool isSI(const MCSubtargetInfo &STI);
815 bool isCI(const MCSubtargetInfo &STI);
816 bool isVI(const MCSubtargetInfo &STI);
817 bool isGFX9(const MCSubtargetInfo &STI);
818 bool isGFX9_GFX10(const MCSubtargetInfo &STI);
819 bool isGFX8_GFX9_GFX10(const MCSubtargetInfo &STI);
820 bool isGFX8Plus(const MCSubtargetInfo &STI);
821 bool isGFX9Plus(const MCSubtargetInfo &STI);
822 bool isGFX10(const MCSubtargetInfo &STI);
823 bool isGFX10Plus(const MCSubtargetInfo &STI);
824 bool isNotGFX10Plus(const MCSubtargetInfo &STI);
825 bool isGFX10Before1030(const MCSubtargetInfo &STI);
826 bool isGFX11(const MCSubtargetInfo &STI);
827 bool isGFX11Plus(const MCSubtargetInfo &STI);
828 bool isNotGFX11Plus(const MCSubtargetInfo &STI);
829 bool isGCN3Encoding(const MCSubtargetInfo &STI);
830 bool isGFX10_AEncoding(const MCSubtargetInfo &STI);
831 bool isGFX10_BEncoding(const MCSubtargetInfo &STI);
832 bool hasGFX10_3Insts(const MCSubtargetInfo &STI);
833 bool isGFX90A(const MCSubtargetInfo &STI);
834 bool isGFX940(const MCSubtargetInfo &STI);
835 bool hasArchitectedFlatScratch(const MCSubtargetInfo &STI);
836 bool hasMAIInsts(const MCSubtargetInfo &STI);
837 bool hasVOPD(const MCSubtargetInfo &STI);
838 int getTotalNumVGPRs(bool has90AInsts, int32_t ArgNumAGPR, int32_t ArgNumVGPR);
839 
840 /// Is Reg - scalar register
841 bool isSGPR(unsigned Reg, const MCRegisterInfo* TRI);
842 
843 /// If \p Reg is a pseudo reg, return the correct hardware register given
844 /// \p STI otherwise return \p Reg.
845 unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI);
846 
847 /// Convert hardware register \p Reg to a pseudo register
848 LLVM_READNONE
849 unsigned mc2PseudoReg(unsigned Reg);
850 
851 /// Can this operand also contain immediate values?
852 bool isSISrcOperand(const MCInstrDesc &Desc, unsigned OpNo);
853 
854 /// Is this floating-point operand?
855 bool isSISrcFPOperand(const MCInstrDesc &Desc, unsigned OpNo);
856 
857 /// Does this operand support only inlinable literals?
858 bool isSISrcInlinableOperand(const MCInstrDesc &Desc, unsigned OpNo);
859 
860 /// Get the size in bits of a register from the register class \p RC.
861 unsigned getRegBitWidth(unsigned RCID);
862 
863 /// Get the size in bits of a register from the register class \p RC.
864 unsigned getRegBitWidth(const MCRegisterClass &RC);
865 
866 /// Get size of register operand
867 unsigned getRegOperandSize(const MCRegisterInfo *MRI, const MCInstrDesc &Desc,
868                            unsigned OpNo);
869 
870 LLVM_READNONE
871 inline unsigned getOperandSize(const MCOperandInfo &OpInfo) {
872   switch (OpInfo.OperandType) {
873   case AMDGPU::OPERAND_REG_IMM_INT32:
874   case AMDGPU::OPERAND_REG_IMM_FP32:
875   case AMDGPU::OPERAND_REG_IMM_FP32_DEFERRED:
876   case AMDGPU::OPERAND_REG_INLINE_C_INT32:
877   case AMDGPU::OPERAND_REG_INLINE_C_FP32:
878   case AMDGPU::OPERAND_REG_INLINE_AC_INT32:
879   case AMDGPU::OPERAND_REG_INLINE_AC_FP32:
880   case AMDGPU::OPERAND_REG_IMM_V2INT32:
881   case AMDGPU::OPERAND_REG_IMM_V2FP32:
882   case AMDGPU::OPERAND_REG_INLINE_C_V2INT32:
883   case AMDGPU::OPERAND_REG_INLINE_C_V2FP32:
884   case AMDGPU::OPERAND_KIMM32:
885   case AMDGPU::OPERAND_KIMM16: // mandatory literal is always size 4
886     return 4;
887 
888   case AMDGPU::OPERAND_REG_IMM_INT64:
889   case AMDGPU::OPERAND_REG_IMM_FP64:
890   case AMDGPU::OPERAND_REG_INLINE_C_INT64:
891   case AMDGPU::OPERAND_REG_INLINE_C_FP64:
892   case AMDGPU::OPERAND_REG_INLINE_AC_FP64:
893     return 8;
894 
895   case AMDGPU::OPERAND_REG_IMM_INT16:
896   case AMDGPU::OPERAND_REG_IMM_FP16:
897   case AMDGPU::OPERAND_REG_IMM_FP16_DEFERRED:
898   case AMDGPU::OPERAND_REG_INLINE_C_INT16:
899   case AMDGPU::OPERAND_REG_INLINE_C_FP16:
900   case AMDGPU::OPERAND_REG_INLINE_C_V2INT16:
901   case AMDGPU::OPERAND_REG_INLINE_C_V2FP16:
902   case AMDGPU::OPERAND_REG_INLINE_AC_INT16:
903   case AMDGPU::OPERAND_REG_INLINE_AC_FP16:
904   case AMDGPU::OPERAND_REG_INLINE_AC_V2INT16:
905   case AMDGPU::OPERAND_REG_INLINE_AC_V2FP16:
906   case AMDGPU::OPERAND_REG_IMM_V2INT16:
907   case AMDGPU::OPERAND_REG_IMM_V2FP16:
908     return 2;
909 
910   default:
911     llvm_unreachable("unhandled operand type");
912   }
913 }
914 
915 LLVM_READNONE
916 inline unsigned getOperandSize(const MCInstrDesc &Desc, unsigned OpNo) {
917   return getOperandSize(Desc.OpInfo[OpNo]);
918 }
919 
920 /// Is this literal inlinable, and not one of the values intended for floating
921 /// point values.
922 LLVM_READNONE
923 inline bool isInlinableIntLiteral(int64_t Literal) {
924   return Literal >= -16 && Literal <= 64;
925 }
926 
927 /// Is this literal inlinable
928 LLVM_READNONE
929 bool isInlinableLiteral64(int64_t Literal, bool HasInv2Pi);
930 
931 LLVM_READNONE
932 bool isInlinableLiteral32(int32_t Literal, bool HasInv2Pi);
933 
934 LLVM_READNONE
935 bool isInlinableLiteral16(int16_t Literal, bool HasInv2Pi);
936 
937 LLVM_READNONE
938 bool isInlinableLiteralV216(int32_t Literal, bool HasInv2Pi);
939 
940 LLVM_READNONE
941 bool isInlinableIntLiteralV216(int32_t Literal);
942 
943 LLVM_READNONE
944 bool isFoldableLiteralV216(int32_t Literal, bool HasInv2Pi);
945 
946 bool isArgPassedInSGPR(const Argument *Arg);
947 
948 LLVM_READONLY
949 bool isLegalSMRDEncodedUnsignedOffset(const MCSubtargetInfo &ST,
950                                       int64_t EncodedOffset);
951 
952 LLVM_READONLY
953 bool isLegalSMRDEncodedSignedOffset(const MCSubtargetInfo &ST,
954                                     int64_t EncodedOffset,
955                                     bool IsBuffer);
956 
957 /// Convert \p ByteOffset to dwords if the subtarget uses dword SMRD immediate
958 /// offsets.
959 uint64_t convertSMRDOffsetUnits(const MCSubtargetInfo &ST, uint64_t ByteOffset);
960 
961 /// \returns The encoding that will be used for \p ByteOffset in the
962 /// SMRD offset field, or None if it won't fit. On GFX9 and GFX10
963 /// S_LOAD instructions have a signed offset, on other subtargets it is
964 /// unsigned. S_BUFFER has an unsigned offset for all subtargets.
965 Optional<int64_t> getSMRDEncodedOffset(const MCSubtargetInfo &ST,
966                                        int64_t ByteOffset, bool IsBuffer);
967 
968 /// \return The encoding that can be used for a 32-bit literal offset in an SMRD
969 /// instruction. This is only useful on CI.s
970 Optional<int64_t> getSMRDEncodedLiteralOffset32(const MCSubtargetInfo &ST,
971                                                 int64_t ByteOffset);
972 
973 /// For FLAT segment the offset must be positive;
974 /// MSB is ignored and forced to zero.
975 ///
976 /// \return The number of bits available for the offset field in flat
977 /// instructions.
978 unsigned getNumFlatOffsetBits(const MCSubtargetInfo &ST, bool Signed);
979 
980 /// \returns true if this offset is small enough to fit in the SMRD
981 /// offset field.  \p ByteOffset should be the offset in bytes and
982 /// not the encoded offset.
983 bool isLegalSMRDImmOffset(const MCSubtargetInfo &ST, int64_t ByteOffset);
984 
985 bool splitMUBUFOffset(uint32_t Imm, uint32_t &SOffset, uint32_t &ImmOffset,
986                       const GCNSubtarget *Subtarget,
987                       Align Alignment = Align(4));
988 
989 LLVM_READNONE
990 inline bool isLegal64BitDPPControl(unsigned DC) {
991   return DC >= DPP::ROW_NEWBCAST_FIRST && DC <= DPP::ROW_NEWBCAST_LAST;
992 }
993 
994 /// \returns true if the intrinsic is divergent
995 bool isIntrinsicSourceOfDivergence(unsigned IntrID);
996 
997 // Track defaults for fields in the MODE register.
998 struct SIModeRegisterDefaults {
999   /// Floating point opcodes that support exception flag gathering quiet and
1000   /// propagate signaling NaN inputs per IEEE 754-2008. Min_dx10 and max_dx10
1001   /// become IEEE 754- 2008 compliant due to signaling NaN propagation and
1002   /// quieting.
1003   bool IEEE : 1;
1004 
1005   /// Used by the vector ALU to force DX10-style treatment of NaNs: when set,
1006   /// clamp NaN to zero; otherwise, pass NaN through.
1007   bool DX10Clamp : 1;
1008 
1009   /// If this is set, neither input or output denormals are flushed for most f32
1010   /// instructions.
1011   bool FP32InputDenormals : 1;
1012   bool FP32OutputDenormals : 1;
1013 
1014   /// If this is set, neither input or output denormals are flushed for both f64
1015   /// and f16/v2f16 instructions.
1016   bool FP64FP16InputDenormals : 1;
1017   bool FP64FP16OutputDenormals : 1;
1018 
1019   SIModeRegisterDefaults() :
1020     IEEE(true),
1021     DX10Clamp(true),
1022     FP32InputDenormals(true),
1023     FP32OutputDenormals(true),
1024     FP64FP16InputDenormals(true),
1025     FP64FP16OutputDenormals(true) {}
1026 
1027   SIModeRegisterDefaults(const Function &F);
1028 
1029   static SIModeRegisterDefaults getDefaultForCallingConv(CallingConv::ID CC) {
1030     SIModeRegisterDefaults Mode;
1031     Mode.IEEE = !AMDGPU::isShader(CC);
1032     return Mode;
1033   }
1034 
1035   bool operator ==(const SIModeRegisterDefaults Other) const {
1036     return IEEE == Other.IEEE && DX10Clamp == Other.DX10Clamp &&
1037            FP32InputDenormals == Other.FP32InputDenormals &&
1038            FP32OutputDenormals == Other.FP32OutputDenormals &&
1039            FP64FP16InputDenormals == Other.FP64FP16InputDenormals &&
1040            FP64FP16OutputDenormals == Other.FP64FP16OutputDenormals;
1041   }
1042 
1043   bool allFP32Denormals() const {
1044     return FP32InputDenormals && FP32OutputDenormals;
1045   }
1046 
1047   bool allFP64FP16Denormals() const {
1048     return FP64FP16InputDenormals && FP64FP16OutputDenormals;
1049   }
1050 
1051   /// Get the encoding value for the FP_DENORM bits of the mode register for the
1052   /// FP32 denormal mode.
1053   uint32_t fpDenormModeSPValue() const {
1054     if (FP32InputDenormals && FP32OutputDenormals)
1055       return FP_DENORM_FLUSH_NONE;
1056     if (FP32InputDenormals)
1057       return FP_DENORM_FLUSH_OUT;
1058     if (FP32OutputDenormals)
1059       return FP_DENORM_FLUSH_IN;
1060     return FP_DENORM_FLUSH_IN_FLUSH_OUT;
1061   }
1062 
1063   /// Get the encoding value for the FP_DENORM bits of the mode register for the
1064   /// FP64/FP16 denormal mode.
1065   uint32_t fpDenormModeDPValue() const {
1066     if (FP64FP16InputDenormals && FP64FP16OutputDenormals)
1067       return FP_DENORM_FLUSH_NONE;
1068     if (FP64FP16InputDenormals)
1069       return FP_DENORM_FLUSH_OUT;
1070     if (FP64FP16OutputDenormals)
1071       return FP_DENORM_FLUSH_IN;
1072     return FP_DENORM_FLUSH_IN_FLUSH_OUT;
1073   }
1074 
1075   /// Returns true if a flag is compatible if it's enabled in the callee, but
1076   /// disabled in the caller.
1077   static bool oneWayCompatible(bool CallerMode, bool CalleeMode) {
1078     return CallerMode == CalleeMode || (!CallerMode && CalleeMode);
1079   }
1080 
1081   // FIXME: Inlining should be OK for dx10-clamp, since the caller's mode should
1082   // be able to override.
1083   bool isInlineCompatible(SIModeRegisterDefaults CalleeMode) const {
1084     if (DX10Clamp != CalleeMode.DX10Clamp)
1085       return false;
1086     if (IEEE != CalleeMode.IEEE)
1087       return false;
1088 
1089     // Allow inlining denormals enabled into denormals flushed functions.
1090     return oneWayCompatible(FP64FP16InputDenormals, CalleeMode.FP64FP16InputDenormals) &&
1091            oneWayCompatible(FP64FP16OutputDenormals, CalleeMode.FP64FP16OutputDenormals) &&
1092            oneWayCompatible(FP32InputDenormals, CalleeMode.FP32InputDenormals) &&
1093            oneWayCompatible(FP32OutputDenormals, CalleeMode.FP32OutputDenormals);
1094   }
1095 };
1096 
1097 } // end namespace AMDGPU
1098 
1099 raw_ostream &operator<<(raw_ostream &OS,
1100                         const AMDGPU::IsaInfo::TargetIDSetting S);
1101 
1102 } // end namespace llvm
1103 
1104 #endif // LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
1105