1 //===- AMDGPUBaseInfo.h - Top level definitions for AMDGPU ------*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
10 #ifndef LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
11 #define LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
12 
13 #include "AMDKernelCodeT.h"
14 #include "SIDefines.h"
15 #include "llvm/ADT/StringRef.h"
16 #include "llvm/IR/CallingConv.h"
17 #include "llvm/MC/MCInstrDesc.h"
18 #include "llvm/Support/Compiler.h"
19 #include "llvm/Support/ErrorHandling.h"
20 #include <cstdint>
21 #include <utility>
22 
23 #define GET_INSTRINFO_OPERAND_ENUM
24 #include "AMDGPUGenInstrInfo.inc"
25 #undef GET_INSTRINFO_OPERAND_ENUM
26 
27 namespace llvm {
28 
29 class FeatureBitset;
30 class Function;
31 class GlobalValue;
32 class MachineMemOperand;
33 class MCContext;
34 class MCRegisterClass;
35 class MCRegisterInfo;
36 class MCSection;
37 class MCSubtargetInfo;
38 class Triple;
39 
40 namespace AMDGPU {
41 namespace IsaInfo {
42 
43 enum {
44   // The closed Vulkan driver sets 96, which limits the wave count to 8 but
45   // doesn't spill SGPRs as much as when 80 is set.
46   FIXED_NUM_SGPRS_FOR_INIT_BUG = 96
47 };
48 
49 /// \brief Instruction set architecture version.
50 struct IsaVersion {
51   unsigned Major;
52   unsigned Minor;
53   unsigned Stepping;
54 };
55 
56 /// \returns Isa version for given subtarget \p Features.
57 IsaVersion getIsaVersion(const FeatureBitset &Features);
58 
59 /// \returns Wavefront size for given subtarget \p Features.
60 unsigned getWavefrontSize(const FeatureBitset &Features);
61 
62 /// \returns Local memory size in bytes for given subtarget \p Features.
63 unsigned getLocalMemorySize(const FeatureBitset &Features);
64 
65 /// \returns Number of execution units per compute unit for given subtarget \p
66 /// Features.
67 unsigned getEUsPerCU(const FeatureBitset &Features);
68 
69 /// \returns Maximum number of work groups per compute unit for given subtarget
70 /// \p Features and limited by given \p FlatWorkGroupSize.
71 unsigned getMaxWorkGroupsPerCU(const FeatureBitset &Features,
72                                unsigned FlatWorkGroupSize);
73 
74 /// \returns Maximum number of waves per compute unit for given subtarget \p
75 /// Features without any kind of limitation.
76 unsigned getMaxWavesPerCU(const FeatureBitset &Features);
77 
78 /// \returns Maximum number of waves per compute unit for given subtarget \p
79 /// Features and limited by given \p FlatWorkGroupSize.
80 unsigned getMaxWavesPerCU(const FeatureBitset &Features,
81                           unsigned FlatWorkGroupSize);
82 
83 /// \returns Minimum number of waves per execution unit for given subtarget \p
84 /// Features.
85 unsigned getMinWavesPerEU(const FeatureBitset &Features);
86 
87 /// \returns Maximum number of waves per execution unit for given subtarget \p
88 /// Features without any kind of limitation.
89 unsigned getMaxWavesPerEU(const FeatureBitset &Features);
90 
91 /// \returns Maximum number of waves per execution unit for given subtarget \p
92 /// Features and limited by given \p FlatWorkGroupSize.
93 unsigned getMaxWavesPerEU(const FeatureBitset &Features,
94                           unsigned FlatWorkGroupSize);
95 
96 /// \returns Minimum flat work group size for given subtarget \p Features.
97 unsigned getMinFlatWorkGroupSize(const FeatureBitset &Features);
98 
99 /// \returns Maximum flat work group size for given subtarget \p Features.
100 unsigned getMaxFlatWorkGroupSize(const FeatureBitset &Features);
101 
102 /// \returns Number of waves per work group for given subtarget \p Features and
103 /// limited by given \p FlatWorkGroupSize.
104 unsigned getWavesPerWorkGroup(const FeatureBitset &Features,
105                               unsigned FlatWorkGroupSize);
106 
107 /// \returns SGPR allocation granularity for given subtarget \p Features.
108 unsigned getSGPRAllocGranule(const FeatureBitset &Features);
109 
110 /// \returns SGPR encoding granularity for given subtarget \p Features.
111 unsigned getSGPREncodingGranule(const FeatureBitset &Features);
112 
113 /// \returns Total number of SGPRs for given subtarget \p Features.
114 unsigned getTotalNumSGPRs(const FeatureBitset &Features);
115 
116 /// \returns Addressable number of SGPRs for given subtarget \p Features.
117 unsigned getAddressableNumSGPRs(const FeatureBitset &Features);
118 
119 /// \returns Minimum number of SGPRs that meets the given number of waves per
120 /// execution unit requirement for given subtarget \p Features.
121 unsigned getMinNumSGPRs(const FeatureBitset &Features, unsigned WavesPerEU);
122 
123 /// \returns Maximum number of SGPRs that meets the given number of waves per
124 /// execution unit requirement for given subtarget \p Features.
125 unsigned getMaxNumSGPRs(const FeatureBitset &Features, unsigned WavesPerEU,
126                         bool Addressable);
127 
128 /// \returns VGPR allocation granularity for given subtarget \p Features.
129 unsigned getVGPRAllocGranule(const FeatureBitset &Features);
130 
131 /// \returns VGPR encoding granularity for given subtarget \p Features.
132 unsigned getVGPREncodingGranule(const FeatureBitset &Features);
133 
134 /// \returns Total number of VGPRs for given subtarget \p Features.
135 unsigned getTotalNumVGPRs(const FeatureBitset &Features);
136 
137 /// \returns Addressable number of VGPRs for given subtarget \p Features.
138 unsigned getAddressableNumVGPRs(const FeatureBitset &Features);
139 
140 /// \returns Minimum number of VGPRs that meets given number of waves per
141 /// execution unit requirement for given subtarget \p Features.
142 unsigned getMinNumVGPRs(const FeatureBitset &Features, unsigned WavesPerEU);
143 
144 /// \returns Maximum number of VGPRs that meets given number of waves per
145 /// execution unit requirement for given subtarget \p Features.
146 unsigned getMaxNumVGPRs(const FeatureBitset &Features, unsigned WavesPerEU);
147 
148 } // end namespace IsaInfo
149 
150 LLVM_READONLY
151 int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx);
152 
153 void initDefaultAMDKernelCodeT(amd_kernel_code_t &Header,
154                                const FeatureBitset &Features);
155 MCSection *getHSATextSection(MCContext &Ctx);
156 
157 MCSection *getHSADataGlobalAgentSection(MCContext &Ctx);
158 
159 MCSection *getHSADataGlobalProgramSection(MCContext &Ctx);
160 
161 MCSection *getHSARodataReadonlyAgentSection(MCContext &Ctx);
162 
163 bool isGroupSegment(const GlobalValue *GV);
164 bool isGlobalSegment(const GlobalValue *GV);
165 bool isReadOnlySegment(const GlobalValue *GV);
166 
167 /// \returns True if constants should be emitted to .text section for given
168 /// target triple \p TT, false otherwise.
169 bool shouldEmitConstantsToTextSection(const Triple &TT);
170 
171 /// \returns Integer value requested using \p F's \p Name attribute.
172 ///
173 /// \returns \p Default if attribute is not present.
174 ///
175 /// \returns \p Default and emits error if requested value cannot be converted
176 /// to integer.
177 int getIntegerAttribute(const Function &F, StringRef Name, int Default);
178 
179 /// \returns A pair of integer values requested using \p F's \p Name attribute
180 /// in "first[,second]" format ("second" is optional unless \p OnlyFirstRequired
181 /// is false).
182 ///
183 /// \returns \p Default if attribute is not present.
184 ///
185 /// \returns \p Default and emits error if one of the requested values cannot be
186 /// converted to integer, or \p OnlyFirstRequired is false and "second" value is
187 /// not present.
188 std::pair<int, int> getIntegerPairAttribute(const Function &F,
189                                             StringRef Name,
190                                             std::pair<int, int> Default,
191                                             bool OnlyFirstRequired = false);
192 
193 /// \returns Vmcnt bit mask for given isa \p Version.
194 unsigned getVmcntBitMask(const IsaInfo::IsaVersion &Version);
195 
196 /// \returns Expcnt bit mask for given isa \p Version.
197 unsigned getExpcntBitMask(const IsaInfo::IsaVersion &Version);
198 
199 /// \returns Lgkmcnt bit mask for given isa \p Version.
200 unsigned getLgkmcntBitMask(const IsaInfo::IsaVersion &Version);
201 
202 /// \returns Waitcnt bit mask for given isa \p Version.
203 unsigned getWaitcntBitMask(const IsaInfo::IsaVersion &Version);
204 
205 /// \returns Decoded Vmcnt from given \p Waitcnt for given isa \p Version.
206 unsigned decodeVmcnt(const IsaInfo::IsaVersion &Version, unsigned Waitcnt);
207 
208 /// \returns Decoded Expcnt from given \p Waitcnt for given isa \p Version.
209 unsigned decodeExpcnt(const IsaInfo::IsaVersion &Version, unsigned Waitcnt);
210 
211 /// \returns Decoded Lgkmcnt from given \p Waitcnt for given isa \p Version.
212 unsigned decodeLgkmcnt(const IsaInfo::IsaVersion &Version, unsigned Waitcnt);
213 
214 /// \brief Decodes Vmcnt, Expcnt and Lgkmcnt from given \p Waitcnt for given isa
215 /// \p Version, and writes decoded values into \p Vmcnt, \p Expcnt and
216 /// \p Lgkmcnt respectively.
217 ///
218 /// \details \p Vmcnt, \p Expcnt and \p Lgkmcnt are decoded as follows:
219 ///     \p Vmcnt = \p Waitcnt[3:0]                      (pre-gfx9 only)
220 ///     \p Vmcnt = \p Waitcnt[3:0] | \p Waitcnt[15:14]  (gfx9+ only)
221 ///     \p Expcnt = \p Waitcnt[6:4]
222 ///     \p Lgkmcnt = \p Waitcnt[11:8]
223 void decodeWaitcnt(const IsaInfo::IsaVersion &Version, unsigned Waitcnt,
224                    unsigned &Vmcnt, unsigned &Expcnt, unsigned &Lgkmcnt);
225 
226 /// \returns \p Waitcnt with encoded \p Vmcnt for given isa \p Version.
227 unsigned encodeVmcnt(const IsaInfo::IsaVersion &Version, unsigned Waitcnt,
228                      unsigned Vmcnt);
229 
230 /// \returns \p Waitcnt with encoded \p Expcnt for given isa \p Version.
231 unsigned encodeExpcnt(const IsaInfo::IsaVersion &Version, unsigned Waitcnt,
232                       unsigned Expcnt);
233 
234 /// \returns \p Waitcnt with encoded \p Lgkmcnt for given isa \p Version.
235 unsigned encodeLgkmcnt(const IsaInfo::IsaVersion &Version, unsigned Waitcnt,
236                        unsigned Lgkmcnt);
237 
238 /// \brief Encodes \p Vmcnt, \p Expcnt and \p Lgkmcnt into Waitcnt for given isa
239 /// \p Version.
240 ///
241 /// \details \p Vmcnt, \p Expcnt and \p Lgkmcnt are encoded as follows:
242 ///     Waitcnt[3:0]   = \p Vmcnt       (pre-gfx9 only)
243 ///     Waitcnt[3:0]   = \p Vmcnt[3:0]  (gfx9+ only)
244 ///     Waitcnt[6:4]   = \p Expcnt
245 ///     Waitcnt[11:8]  = \p Lgkmcnt
246 ///     Waitcnt[15:14] = \p Vmcnt[5:4]  (gfx9+ only)
247 ///
248 /// \returns Waitcnt with encoded \p Vmcnt, \p Expcnt and \p Lgkmcnt for given
249 /// isa \p Version.
250 unsigned encodeWaitcnt(const IsaInfo::IsaVersion &Version,
251                        unsigned Vmcnt, unsigned Expcnt, unsigned Lgkmcnt);
252 
253 unsigned getInitialPSInputAddr(const Function &F);
254 
255 bool isShader(CallingConv::ID cc);
256 bool isCompute(CallingConv::ID cc);
257 
258 bool isSI(const MCSubtargetInfo &STI);
259 bool isCI(const MCSubtargetInfo &STI);
260 bool isVI(const MCSubtargetInfo &STI);
261 
262 /// If \p Reg is a pseudo reg, return the correct hardware register given
263 /// \p STI otherwise return \p Reg.
264 unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI);
265 
266 /// \brief Can this operand also contain immediate values?
267 bool isSISrcOperand(const MCInstrDesc &Desc, unsigned OpNo);
268 
269 /// \brief Is this floating-point operand?
270 bool isSISrcFPOperand(const MCInstrDesc &Desc, unsigned OpNo);
271 
272 /// \brief Does this opearnd support only inlinable literals?
273 bool isSISrcInlinableOperand(const MCInstrDesc &Desc, unsigned OpNo);
274 
275 /// \brief Get the size in bits of a register from the register class \p RC.
276 unsigned getRegBitWidth(unsigned RCID);
277 
278 /// \brief Get the size in bits of a register from the register class \p RC.
279 unsigned getRegBitWidth(const MCRegisterClass &RC);
280 
281 /// \brief Get size of register operand
282 unsigned getRegOperandSize(const MCRegisterInfo *MRI, const MCInstrDesc &Desc,
283                            unsigned OpNo);
284 
285 LLVM_READNONE
286 inline unsigned getOperandSize(const MCOperandInfo &OpInfo) {
287   switch (OpInfo.OperandType) {
288   case AMDGPU::OPERAND_REG_IMM_INT32:
289   case AMDGPU::OPERAND_REG_IMM_FP32:
290   case AMDGPU::OPERAND_REG_INLINE_C_INT32:
291   case AMDGPU::OPERAND_REG_INLINE_C_FP32:
292     return 4;
293 
294   case AMDGPU::OPERAND_REG_IMM_INT64:
295   case AMDGPU::OPERAND_REG_IMM_FP64:
296   case AMDGPU::OPERAND_REG_INLINE_C_INT64:
297   case AMDGPU::OPERAND_REG_INLINE_C_FP64:
298     return 8;
299 
300   case AMDGPU::OPERAND_REG_IMM_INT16:
301   case AMDGPU::OPERAND_REG_IMM_FP16:
302   case AMDGPU::OPERAND_REG_INLINE_C_INT16:
303   case AMDGPU::OPERAND_REG_INLINE_C_FP16:
304   case AMDGPU::OPERAND_REG_INLINE_C_V2INT16:
305   case AMDGPU::OPERAND_REG_INLINE_C_V2FP16:
306     return 2;
307 
308   default:
309     llvm_unreachable("unhandled operand type");
310   }
311 }
312 
313 LLVM_READNONE
314 inline unsigned getOperandSize(const MCInstrDesc &Desc, unsigned OpNo) {
315   return getOperandSize(Desc.OpInfo[OpNo]);
316 }
317 
318 /// \brief Is this literal inlinable
319 LLVM_READNONE
320 bool isInlinableLiteral64(int64_t Literal, bool HasInv2Pi);
321 
322 LLVM_READNONE
323 bool isInlinableLiteral32(int32_t Literal, bool HasInv2Pi);
324 
325 LLVM_READNONE
326 bool isInlinableLiteral16(int16_t Literal, bool HasInv2Pi);
327 
328 LLVM_READNONE
329 bool isInlinableLiteralV216(int32_t Literal, bool HasInv2Pi);
330 
331 bool isUniformMMO(const MachineMemOperand *MMO);
332 
333 /// \returns The encoding that will be used for \p ByteOffset in the SMRD
334 /// offset field.
335 int64_t getSMRDEncodedOffset(const MCSubtargetInfo &ST, int64_t ByteOffset);
336 
337 /// \returns true if this offset is small enough to fit in the SMRD
338 /// offset field.  \p ByteOffset should be the offset in bytes and
339 /// not the encoded offset.
340 bool isLegalSMRDImmOffset(const MCSubtargetInfo &ST, int64_t ByteOffset);
341 
342 } // end namespace AMDGPU
343 } // end namespace llvm
344 
345 #endif // LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
346