1 //===- AMDGPUBaseInfo.h - Top level definitions for AMDGPU ------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #ifndef LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
10 #define LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
11 
12 #include "SIDefines.h"
13 #include "llvm/IR/CallingConv.h"
14 #include "llvm/Support/Alignment.h"
15 
16 struct amd_kernel_code_t;
17 
18 namespace llvm {
19 
20 struct Align;
21 class Argument;
22 class Function;
23 class GCNSubtarget;
24 class GlobalValue;
25 class MCRegisterClass;
26 class MCRegisterInfo;
27 class MCSubtargetInfo;
28 class StringRef;
29 class Triple;
30 
31 namespace amdhsa {
32 struct kernel_descriptor_t;
33 }
34 
35 namespace AMDGPU {
36 
37 struct IsaVersion;
38 
39 /// \returns HSA OS ABI Version identification.
40 Optional<uint8_t> getHsaAbiVersion(const MCSubtargetInfo *STI);
41 /// \returns True if HSA OS ABI Version identification is 2,
42 /// false otherwise.
43 bool isHsaAbiVersion2(const MCSubtargetInfo *STI);
44 /// \returns True if HSA OS ABI Version identification is 3,
45 /// false otherwise.
46 bool isHsaAbiVersion3(const MCSubtargetInfo *STI);
47 /// \returns True if HSA OS ABI Version identification is 4,
48 /// false otherwise.
49 bool isHsaAbiVersion4(const MCSubtargetInfo *STI);
50 /// \returns True if HSA OS ABI Version identification is 5,
51 /// false otherwise.
52 bool isHsaAbiVersion5(const MCSubtargetInfo *STI);
53 /// \returns True if HSA OS ABI Version identification is 3 and above,
54 /// false otherwise.
55 bool isHsaAbiVersion3AndAbove(const MCSubtargetInfo *STI);
56 
57 /// \returns The offset of the hostcall pointer argument from implicitarg_ptr
58 unsigned getHostcallImplicitArgPosition();
59 
60 /// \returns The offset of the heap ptr argument from implicitarg_ptr
61 unsigned getHeapPtrImplicitArgPosition();
62 
63 /// \returns Code object version.
64 unsigned getAmdhsaCodeObjectVersion();
65 
66 struct GcnBufferFormatInfo {
67   unsigned Format;
68   unsigned BitsPerComp;
69   unsigned NumComponents;
70   unsigned NumFormat;
71   unsigned DataFormat;
72 };
73 
74 #define GET_MIMGBaseOpcode_DECL
75 #define GET_MIMGDim_DECL
76 #define GET_MIMGEncoding_DECL
77 #define GET_MIMGLZMapping_DECL
78 #define GET_MIMGMIPMapping_DECL
79 #define GET_MIMGBiASMapping_DECL
80 #include "AMDGPUGenSearchableTables.inc"
81 
82 namespace IsaInfo {
83 
84 enum {
85   // The closed Vulkan driver sets 96, which limits the wave count to 8 but
86   // doesn't spill SGPRs as much as when 80 is set.
87   FIXED_NUM_SGPRS_FOR_INIT_BUG = 96,
88   TRAP_NUM_SGPRS = 16
89 };
90 
91 enum class TargetIDSetting {
92   Unsupported,
93   Any,
94   Off,
95   On
96 };
97 
98 class AMDGPUTargetID {
99 private:
100   const MCSubtargetInfo &STI;
101   TargetIDSetting XnackSetting;
102   TargetIDSetting SramEccSetting;
103 
104 public:
105   explicit AMDGPUTargetID(const MCSubtargetInfo &STI);
106   ~AMDGPUTargetID() = default;
107 
108   /// \return True if the current xnack setting is not "Unsupported".
109   bool isXnackSupported() const {
110     return XnackSetting != TargetIDSetting::Unsupported;
111   }
112 
113   /// \returns True if the current xnack setting is "On" or "Any".
114   bool isXnackOnOrAny() const {
115     return XnackSetting == TargetIDSetting::On ||
116         XnackSetting == TargetIDSetting::Any;
117   }
118 
119   /// \returns True if current xnack setting is "On" or "Off",
120   /// false otherwise.
121   bool isXnackOnOrOff() const {
122     return getXnackSetting() == TargetIDSetting::On ||
123         getXnackSetting() == TargetIDSetting::Off;
124   }
125 
126   /// \returns The current xnack TargetIDSetting, possible options are
127   /// "Unsupported", "Any", "Off", and "On".
128   TargetIDSetting getXnackSetting() const {
129     return XnackSetting;
130   }
131 
132   /// Sets xnack setting to \p NewXnackSetting.
133   void setXnackSetting(TargetIDSetting NewXnackSetting) {
134     XnackSetting = NewXnackSetting;
135   }
136 
137   /// \return True if the current sramecc setting is not "Unsupported".
138   bool isSramEccSupported() const {
139     return SramEccSetting != TargetIDSetting::Unsupported;
140   }
141 
142   /// \returns True if the current sramecc setting is "On" or "Any".
143   bool isSramEccOnOrAny() const {
144   return SramEccSetting == TargetIDSetting::On ||
145       SramEccSetting == TargetIDSetting::Any;
146   }
147 
148   /// \returns True if current sramecc setting is "On" or "Off",
149   /// false otherwise.
150   bool isSramEccOnOrOff() const {
151     return getSramEccSetting() == TargetIDSetting::On ||
152         getSramEccSetting() == TargetIDSetting::Off;
153   }
154 
155   /// \returns The current sramecc TargetIDSetting, possible options are
156   /// "Unsupported", "Any", "Off", and "On".
157   TargetIDSetting getSramEccSetting() const {
158     return SramEccSetting;
159   }
160 
161   /// Sets sramecc setting to \p NewSramEccSetting.
162   void setSramEccSetting(TargetIDSetting NewSramEccSetting) {
163     SramEccSetting = NewSramEccSetting;
164   }
165 
166   void setTargetIDFromFeaturesString(StringRef FS);
167   void setTargetIDFromTargetIDStream(StringRef TargetID);
168 
169   /// \returns String representation of an object.
170   std::string toString() const;
171 };
172 
173 /// \returns Wavefront size for given subtarget \p STI.
174 unsigned getWavefrontSize(const MCSubtargetInfo *STI);
175 
176 /// \returns Local memory size in bytes for given subtarget \p STI.
177 unsigned getLocalMemorySize(const MCSubtargetInfo *STI);
178 
179 /// \returns Number of execution units per compute unit for given subtarget \p
180 /// STI.
181 unsigned getEUsPerCU(const MCSubtargetInfo *STI);
182 
183 /// \returns Maximum number of work groups per compute unit for given subtarget
184 /// \p STI and limited by given \p FlatWorkGroupSize.
185 unsigned getMaxWorkGroupsPerCU(const MCSubtargetInfo *STI,
186                                unsigned FlatWorkGroupSize);
187 
188 /// \returns Minimum number of waves per execution unit for given subtarget \p
189 /// STI.
190 unsigned getMinWavesPerEU(const MCSubtargetInfo *STI);
191 
192 /// \returns Maximum number of waves per execution unit for given subtarget \p
193 /// STI without any kind of limitation.
194 unsigned getMaxWavesPerEU(const MCSubtargetInfo *STI);
195 
196 /// \returns Number of waves per execution unit required to support the given \p
197 /// FlatWorkGroupSize.
198 unsigned getWavesPerEUForWorkGroup(const MCSubtargetInfo *STI,
199                                    unsigned FlatWorkGroupSize);
200 
201 /// \returns Minimum flat work group size for given subtarget \p STI.
202 unsigned getMinFlatWorkGroupSize(const MCSubtargetInfo *STI);
203 
204 /// \returns Maximum flat work group size for given subtarget \p STI.
205 unsigned getMaxFlatWorkGroupSize(const MCSubtargetInfo *STI);
206 
207 /// \returns Number of waves per work group for given subtarget \p STI and
208 /// \p FlatWorkGroupSize.
209 unsigned getWavesPerWorkGroup(const MCSubtargetInfo *STI,
210                               unsigned FlatWorkGroupSize);
211 
212 /// \returns SGPR allocation granularity for given subtarget \p STI.
213 unsigned getSGPRAllocGranule(const MCSubtargetInfo *STI);
214 
215 /// \returns SGPR encoding granularity for given subtarget \p STI.
216 unsigned getSGPREncodingGranule(const MCSubtargetInfo *STI);
217 
218 /// \returns Total number of SGPRs for given subtarget \p STI.
219 unsigned getTotalNumSGPRs(const MCSubtargetInfo *STI);
220 
221 /// \returns Addressable number of SGPRs for given subtarget \p STI.
222 unsigned getAddressableNumSGPRs(const MCSubtargetInfo *STI);
223 
224 /// \returns Minimum number of SGPRs that meets the given number of waves per
225 /// execution unit requirement for given subtarget \p STI.
226 unsigned getMinNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU);
227 
228 /// \returns Maximum number of SGPRs that meets the given number of waves per
229 /// execution unit requirement for given subtarget \p STI.
230 unsigned getMaxNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU,
231                         bool Addressable);
232 
233 /// \returns Number of extra SGPRs implicitly required by given subtarget \p
234 /// STI when the given special registers are used.
235 unsigned getNumExtraSGPRs(const MCSubtargetInfo *STI, bool VCCUsed,
236                           bool FlatScrUsed, bool XNACKUsed);
237 
238 /// \returns Number of extra SGPRs implicitly required by given subtarget \p
239 /// STI when the given special registers are used. XNACK is inferred from
240 /// \p STI.
241 unsigned getNumExtraSGPRs(const MCSubtargetInfo *STI, bool VCCUsed,
242                           bool FlatScrUsed);
243 
244 /// \returns Number of SGPR blocks needed for given subtarget \p STI when
245 /// \p NumSGPRs are used. \p NumSGPRs should already include any special
246 /// register counts.
247 unsigned getNumSGPRBlocks(const MCSubtargetInfo *STI, unsigned NumSGPRs);
248 
249 /// \returns VGPR allocation granularity for given subtarget \p STI.
250 ///
251 /// For subtargets which support it, \p EnableWavefrontSize32 should match
252 /// the ENABLE_WAVEFRONT_SIZE32 kernel descriptor field.
253 unsigned getVGPRAllocGranule(const MCSubtargetInfo *STI,
254                              Optional<bool> EnableWavefrontSize32 = None);
255 
256 /// \returns VGPR encoding granularity for given subtarget \p STI.
257 ///
258 /// For subtargets which support it, \p EnableWavefrontSize32 should match
259 /// the ENABLE_WAVEFRONT_SIZE32 kernel descriptor field.
260 unsigned getVGPREncodingGranule(const MCSubtargetInfo *STI,
261                                 Optional<bool> EnableWavefrontSize32 = None);
262 
263 /// \returns Total number of VGPRs for given subtarget \p STI.
264 unsigned getTotalNumVGPRs(const MCSubtargetInfo *STI);
265 
266 /// \returns Addressable number of VGPRs for given subtarget \p STI.
267 unsigned getAddressableNumVGPRs(const MCSubtargetInfo *STI);
268 
269 /// \returns Minimum number of VGPRs that meets given number of waves per
270 /// execution unit requirement for given subtarget \p STI.
271 unsigned getMinNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU);
272 
273 /// \returns Maximum number of VGPRs that meets given number of waves per
274 /// execution unit requirement for given subtarget \p STI.
275 unsigned getMaxNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU);
276 
277 /// \returns Number of VGPR blocks needed for given subtarget \p STI when
278 /// \p NumVGPRs are used.
279 ///
280 /// For subtargets which support it, \p EnableWavefrontSize32 should match the
281 /// ENABLE_WAVEFRONT_SIZE32 kernel descriptor field.
282 unsigned getNumVGPRBlocks(const MCSubtargetInfo *STI, unsigned NumSGPRs,
283                           Optional<bool> EnableWavefrontSize32 = None);
284 
285 } // end namespace IsaInfo
286 
287 LLVM_READONLY
288 int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx);
289 
290 LLVM_READONLY
291 int getSOPPWithRelaxation(uint16_t Opcode);
292 
293 struct MIMGBaseOpcodeInfo {
294   MIMGBaseOpcode BaseOpcode;
295   bool Store;
296   bool Atomic;
297   bool AtomicX2;
298   bool Sampler;
299   bool Gather4;
300 
301   uint8_t NumExtraArgs;
302   bool Gradients;
303   bool G16;
304   bool Coordinates;
305   bool LodOrClampOrMip;
306   bool HasD16;
307   bool MSAA;
308   bool BVH;
309 };
310 
311 LLVM_READONLY
312 const MIMGBaseOpcodeInfo *getMIMGBaseOpcode(unsigned Opc);
313 
314 LLVM_READONLY
315 const MIMGBaseOpcodeInfo *getMIMGBaseOpcodeInfo(unsigned BaseOpcode);
316 
317 struct MIMGDimInfo {
318   MIMGDim Dim;
319   uint8_t NumCoords;
320   uint8_t NumGradients;
321   bool MSAA;
322   bool DA;
323   uint8_t Encoding;
324   const char *AsmSuffix;
325 };
326 
327 LLVM_READONLY
328 const MIMGDimInfo *getMIMGDimInfo(unsigned DimEnum);
329 
330 LLVM_READONLY
331 const MIMGDimInfo *getMIMGDimInfoByEncoding(uint8_t DimEnc);
332 
333 LLVM_READONLY
334 const MIMGDimInfo *getMIMGDimInfoByAsmSuffix(StringRef AsmSuffix);
335 
336 struct MIMGLZMappingInfo {
337   MIMGBaseOpcode L;
338   MIMGBaseOpcode LZ;
339 };
340 
341 struct MIMGMIPMappingInfo {
342   MIMGBaseOpcode MIP;
343   MIMGBaseOpcode NONMIP;
344 };
345 
346 struct MIMGBiasMappingInfo {
347   MIMGBaseOpcode Bias;
348   MIMGBaseOpcode NoBias;
349 };
350 
351 struct MIMGOffsetMappingInfo {
352   MIMGBaseOpcode Offset;
353   MIMGBaseOpcode NoOffset;
354 };
355 
356 struct MIMGG16MappingInfo {
357   MIMGBaseOpcode G;
358   MIMGBaseOpcode G16;
359 };
360 
361 LLVM_READONLY
362 const MIMGLZMappingInfo *getMIMGLZMappingInfo(unsigned L);
363 
364 LLVM_READONLY
365 const MIMGMIPMappingInfo *getMIMGMIPMappingInfo(unsigned MIP);
366 
367 LLVM_READONLY
368 const MIMGBiasMappingInfo *getMIMGBiasMappingInfo(unsigned Bias);
369 
370 LLVM_READONLY
371 const MIMGOffsetMappingInfo *getMIMGOffsetMappingInfo(unsigned Offset);
372 
373 LLVM_READONLY
374 const MIMGG16MappingInfo *getMIMGG16MappingInfo(unsigned G);
375 
376 LLVM_READONLY
377 int getMIMGOpcode(unsigned BaseOpcode, unsigned MIMGEncoding,
378                   unsigned VDataDwords, unsigned VAddrDwords);
379 
380 LLVM_READONLY
381 int getMaskedMIMGOp(unsigned Opc, unsigned NewChannels);
382 
383 LLVM_READONLY
384 unsigned getAddrSizeMIMGOp(const MIMGBaseOpcodeInfo *BaseOpcode,
385                            const MIMGDimInfo *Dim, bool IsA16,
386                            bool IsG16Supported);
387 
388 struct MIMGInfo {
389   uint16_t Opcode;
390   uint16_t BaseOpcode;
391   uint8_t MIMGEncoding;
392   uint8_t VDataDwords;
393   uint8_t VAddrDwords;
394 };
395 
396 LLVM_READONLY
397 const MIMGInfo *getMIMGInfo(unsigned Opc);
398 
399 LLVM_READONLY
400 int getMTBUFBaseOpcode(unsigned Opc);
401 
402 LLVM_READONLY
403 int getMTBUFOpcode(unsigned BaseOpc, unsigned Elements);
404 
405 LLVM_READONLY
406 int getMTBUFElements(unsigned Opc);
407 
408 LLVM_READONLY
409 bool getMTBUFHasVAddr(unsigned Opc);
410 
411 LLVM_READONLY
412 bool getMTBUFHasSrsrc(unsigned Opc);
413 
414 LLVM_READONLY
415 bool getMTBUFHasSoffset(unsigned Opc);
416 
417 LLVM_READONLY
418 int getMUBUFBaseOpcode(unsigned Opc);
419 
420 LLVM_READONLY
421 int getMUBUFOpcode(unsigned BaseOpc, unsigned Elements);
422 
423 LLVM_READONLY
424 int getMUBUFElements(unsigned Opc);
425 
426 LLVM_READONLY
427 bool getMUBUFHasVAddr(unsigned Opc);
428 
429 LLVM_READONLY
430 bool getMUBUFHasSrsrc(unsigned Opc);
431 
432 LLVM_READONLY
433 bool getMUBUFHasSoffset(unsigned Opc);
434 
435 LLVM_READONLY
436 bool getMUBUFIsBufferInv(unsigned Opc);
437 
438 LLVM_READONLY
439 bool getSMEMIsBuffer(unsigned Opc);
440 
441 LLVM_READONLY
442 bool getVOP1IsSingle(unsigned Opc);
443 
444 LLVM_READONLY
445 bool getVOP2IsSingle(unsigned Opc);
446 
447 LLVM_READONLY
448 bool getVOP3IsSingle(unsigned Opc);
449 
450 LLVM_READONLY
451 const GcnBufferFormatInfo *getGcnBufferFormatInfo(uint8_t BitsPerComp,
452                                                   uint8_t NumComponents,
453                                                   uint8_t NumFormat,
454                                                   const MCSubtargetInfo &STI);
455 LLVM_READONLY
456 const GcnBufferFormatInfo *getGcnBufferFormatInfo(uint8_t Format,
457                                                   const MCSubtargetInfo &STI);
458 
459 LLVM_READONLY
460 int getMCOpcode(uint16_t Opcode, unsigned Gen);
461 
462 void initDefaultAMDKernelCodeT(amd_kernel_code_t &Header,
463                                const MCSubtargetInfo *STI);
464 
465 amdhsa::kernel_descriptor_t getDefaultAmdhsaKernelDescriptor(
466     const MCSubtargetInfo *STI);
467 
468 bool isGroupSegment(const GlobalValue *GV);
469 bool isGlobalSegment(const GlobalValue *GV);
470 bool isReadOnlySegment(const GlobalValue *GV);
471 
472 /// \returns True if constants should be emitted to .text section for given
473 /// target triple \p TT, false otherwise.
474 bool shouldEmitConstantsToTextSection(const Triple &TT);
475 
476 /// \returns Integer value requested using \p F's \p Name attribute.
477 ///
478 /// \returns \p Default if attribute is not present.
479 ///
480 /// \returns \p Default and emits error if requested value cannot be converted
481 /// to integer.
482 int getIntegerAttribute(const Function &F, StringRef Name, int Default);
483 
484 /// \returns A pair of integer values requested using \p F's \p Name attribute
485 /// in "first[,second]" format ("second" is optional unless \p OnlyFirstRequired
486 /// is false).
487 ///
488 /// \returns \p Default if attribute is not present.
489 ///
490 /// \returns \p Default and emits error if one of the requested values cannot be
491 /// converted to integer, or \p OnlyFirstRequired is false and "second" value is
492 /// not present.
493 std::pair<int, int> getIntegerPairAttribute(const Function &F,
494                                             StringRef Name,
495                                             std::pair<int, int> Default,
496                                             bool OnlyFirstRequired = false);
497 
498 /// Represents the counter values to wait for in an s_waitcnt instruction.
499 ///
500 /// Large values (including the maximum possible integer) can be used to
501 /// represent "don't care" waits.
502 struct Waitcnt {
503   unsigned VmCnt = ~0u;
504   unsigned ExpCnt = ~0u;
505   unsigned LgkmCnt = ~0u;
506   unsigned VsCnt = ~0u;
507 
508   Waitcnt() = default;
509   Waitcnt(unsigned VmCnt, unsigned ExpCnt, unsigned LgkmCnt, unsigned VsCnt)
510       : VmCnt(VmCnt), ExpCnt(ExpCnt), LgkmCnt(LgkmCnt), VsCnt(VsCnt) {}
511 
512   static Waitcnt allZero(bool HasVscnt) {
513     return Waitcnt(0, 0, 0, HasVscnt ? 0 : ~0u);
514   }
515   static Waitcnt allZeroExceptVsCnt() { return Waitcnt(0, 0, 0, ~0u); }
516 
517   bool hasWait() const {
518     return VmCnt != ~0u || ExpCnt != ~0u || LgkmCnt != ~0u || VsCnt != ~0u;
519   }
520 
521   bool hasWaitExceptVsCnt() const {
522     return VmCnt != ~0u || ExpCnt != ~0u || LgkmCnt != ~0u;
523   }
524 
525   bool hasWaitVsCnt() const {
526     return VsCnt != ~0u;
527   }
528 
529   bool dominates(const Waitcnt &Other) const {
530     return VmCnt <= Other.VmCnt && ExpCnt <= Other.ExpCnt &&
531            LgkmCnt <= Other.LgkmCnt && VsCnt <= Other.VsCnt;
532   }
533 
534   Waitcnt combined(const Waitcnt &Other) const {
535     return Waitcnt(std::min(VmCnt, Other.VmCnt), std::min(ExpCnt, Other.ExpCnt),
536                    std::min(LgkmCnt, Other.LgkmCnt),
537                    std::min(VsCnt, Other.VsCnt));
538   }
539 };
540 
541 /// \returns Vmcnt bit mask for given isa \p Version.
542 unsigned getVmcntBitMask(const IsaVersion &Version);
543 
544 /// \returns Expcnt bit mask for given isa \p Version.
545 unsigned getExpcntBitMask(const IsaVersion &Version);
546 
547 /// \returns Lgkmcnt bit mask for given isa \p Version.
548 unsigned getLgkmcntBitMask(const IsaVersion &Version);
549 
550 /// \returns Waitcnt bit mask for given isa \p Version.
551 unsigned getWaitcntBitMask(const IsaVersion &Version);
552 
553 /// \returns Decoded Vmcnt from given \p Waitcnt for given isa \p Version.
554 unsigned decodeVmcnt(const IsaVersion &Version, unsigned Waitcnt);
555 
556 /// \returns Decoded Expcnt from given \p Waitcnt for given isa \p Version.
557 unsigned decodeExpcnt(const IsaVersion &Version, unsigned Waitcnt);
558 
559 /// \returns Decoded Lgkmcnt from given \p Waitcnt for given isa \p Version.
560 unsigned decodeLgkmcnt(const IsaVersion &Version, unsigned Waitcnt);
561 
562 /// Decodes Vmcnt, Expcnt and Lgkmcnt from given \p Waitcnt for given isa
563 /// \p Version, and writes decoded values into \p Vmcnt, \p Expcnt and
564 /// \p Lgkmcnt respectively.
565 ///
566 /// \details \p Vmcnt, \p Expcnt and \p Lgkmcnt are decoded as follows:
567 ///     \p Vmcnt = \p Waitcnt[3:0]                      (pre-gfx9 only)
568 ///     \p Vmcnt = \p Waitcnt[3:0] | \p Waitcnt[15:14]  (gfx9+ only)
569 ///     \p Expcnt = \p Waitcnt[6:4]
570 ///     \p Lgkmcnt = \p Waitcnt[11:8]                   (pre-gfx10 only)
571 ///     \p Lgkmcnt = \p Waitcnt[13:8]                   (gfx10+ only)
572 void decodeWaitcnt(const IsaVersion &Version, unsigned Waitcnt,
573                    unsigned &Vmcnt, unsigned &Expcnt, unsigned &Lgkmcnt);
574 
575 Waitcnt decodeWaitcnt(const IsaVersion &Version, unsigned Encoded);
576 
577 /// \returns \p Waitcnt with encoded \p Vmcnt for given isa \p Version.
578 unsigned encodeVmcnt(const IsaVersion &Version, unsigned Waitcnt,
579                      unsigned Vmcnt);
580 
581 /// \returns \p Waitcnt with encoded \p Expcnt for given isa \p Version.
582 unsigned encodeExpcnt(const IsaVersion &Version, unsigned Waitcnt,
583                       unsigned Expcnt);
584 
585 /// \returns \p Waitcnt with encoded \p Lgkmcnt for given isa \p Version.
586 unsigned encodeLgkmcnt(const IsaVersion &Version, unsigned Waitcnt,
587                        unsigned Lgkmcnt);
588 
589 /// Encodes \p Vmcnt, \p Expcnt and \p Lgkmcnt into Waitcnt for given isa
590 /// \p Version.
591 ///
592 /// \details \p Vmcnt, \p Expcnt and \p Lgkmcnt are encoded as follows:
593 ///     Waitcnt[3:0]   = \p Vmcnt       (pre-gfx9 only)
594 ///     Waitcnt[3:0]   = \p Vmcnt[3:0]  (gfx9+ only)
595 ///     Waitcnt[6:4]   = \p Expcnt
596 ///     Waitcnt[11:8]  = \p Lgkmcnt     (pre-gfx10 only)
597 ///     Waitcnt[13:8]  = \p Lgkmcnt     (gfx10+ only)
598 ///     Waitcnt[15:14] = \p Vmcnt[5:4]  (gfx9+ only)
599 ///
600 /// \returns Waitcnt with encoded \p Vmcnt, \p Expcnt and \p Lgkmcnt for given
601 /// isa \p Version.
602 unsigned encodeWaitcnt(const IsaVersion &Version,
603                        unsigned Vmcnt, unsigned Expcnt, unsigned Lgkmcnt);
604 
605 unsigned encodeWaitcnt(const IsaVersion &Version, const Waitcnt &Decoded);
606 
607 namespace Hwreg {
608 
609 LLVM_READONLY
610 int64_t getHwregId(const StringRef Name, const MCSubtargetInfo &STI);
611 
612 LLVM_READNONE
613 bool isValidHwreg(int64_t Id, const MCSubtargetInfo &STI);
614 
615 LLVM_READNONE
616 bool isValidHwreg(int64_t Id);
617 
618 LLVM_READNONE
619 bool isValidHwregOffset(int64_t Offset);
620 
621 LLVM_READNONE
622 bool isValidHwregWidth(int64_t Width);
623 
624 LLVM_READNONE
625 uint64_t encodeHwreg(uint64_t Id, uint64_t Offset, uint64_t Width);
626 
627 LLVM_READNONE
628 StringRef getHwreg(unsigned Id, const MCSubtargetInfo &STI);
629 
630 void decodeHwreg(unsigned Val, unsigned &Id, unsigned &Offset, unsigned &Width);
631 
632 } // namespace Hwreg
633 
634 namespace Exp {
635 
636 bool getTgtName(unsigned Id, StringRef &Name, int &Index);
637 
638 LLVM_READONLY
639 unsigned getTgtId(const StringRef Name);
640 
641 LLVM_READNONE
642 bool isSupportedTgtId(unsigned Id, const MCSubtargetInfo &STI);
643 
644 } // namespace Exp
645 
646 namespace MTBUFFormat {
647 
648 LLVM_READNONE
649 int64_t encodeDfmtNfmt(unsigned Dfmt, unsigned Nfmt);
650 
651 void decodeDfmtNfmt(unsigned Format, unsigned &Dfmt, unsigned &Nfmt);
652 
653 int64_t getDfmt(const StringRef Name);
654 
655 StringRef getDfmtName(unsigned Id);
656 
657 int64_t getNfmt(const StringRef Name, const MCSubtargetInfo &STI);
658 
659 StringRef getNfmtName(unsigned Id, const MCSubtargetInfo &STI);
660 
661 bool isValidDfmtNfmt(unsigned Val, const MCSubtargetInfo &STI);
662 
663 bool isValidNfmt(unsigned Val, const MCSubtargetInfo &STI);
664 
665 int64_t getUnifiedFormat(const StringRef Name);
666 
667 StringRef getUnifiedFormatName(unsigned Id);
668 
669 bool isValidUnifiedFormat(unsigned Val);
670 
671 int64_t convertDfmtNfmt2Ufmt(unsigned Dfmt, unsigned Nfmt);
672 
673 bool isValidFormatEncoding(unsigned Val, const MCSubtargetInfo &STI);
674 
675 unsigned getDefaultFormatEncoding(const MCSubtargetInfo &STI);
676 
677 } // namespace MTBUFFormat
678 
679 namespace SendMsg {
680 
681 LLVM_READONLY
682 int64_t getMsgId(const StringRef Name);
683 
684 LLVM_READONLY
685 int64_t getMsgOpId(int64_t MsgId, const StringRef Name);
686 
687 LLVM_READNONE
688 StringRef getMsgName(int64_t MsgId);
689 
690 LLVM_READNONE
691 StringRef getMsgOpName(int64_t MsgId, int64_t OpId);
692 
693 LLVM_READNONE
694 bool isValidMsgId(int64_t MsgId, const MCSubtargetInfo &STI, bool Strict = true);
695 
696 LLVM_READNONE
697 bool isValidMsgOp(int64_t MsgId, int64_t OpId, const MCSubtargetInfo &STI,
698                   bool Strict = true);
699 
700 LLVM_READNONE
701 bool isValidMsgStream(int64_t MsgId, int64_t OpId, int64_t StreamId,
702                       const MCSubtargetInfo &STI, bool Strict = true);
703 
704 LLVM_READNONE
705 bool msgRequiresOp(int64_t MsgId);
706 
707 LLVM_READNONE
708 bool msgSupportsStream(int64_t MsgId, int64_t OpId);
709 
710 void decodeMsg(unsigned Val,
711                uint16_t &MsgId,
712                uint16_t &OpId,
713                uint16_t &StreamId);
714 
715 LLVM_READNONE
716 uint64_t encodeMsg(uint64_t MsgId,
717                    uint64_t OpId,
718                    uint64_t StreamId);
719 
720 } // namespace SendMsg
721 
722 
723 unsigned getInitialPSInputAddr(const Function &F);
724 
725 bool getHasColorExport(const Function &F);
726 
727 bool getHasDepthExport(const Function &F);
728 
729 LLVM_READNONE
730 bool isShader(CallingConv::ID CC);
731 
732 LLVM_READNONE
733 bool isGraphics(CallingConv::ID CC);
734 
735 LLVM_READNONE
736 bool isCompute(CallingConv::ID CC);
737 
738 LLVM_READNONE
739 bool isEntryFunctionCC(CallingConv::ID CC);
740 
741 // These functions are considered entrypoints into the current module, i.e. they
742 // are allowed to be called from outside the current module. This is different
743 // from isEntryFunctionCC, which is only true for functions that are entered by
744 // the hardware. Module entry points include all entry functions but also
745 // include functions that can be called from other functions inside or outside
746 // the current module. Module entry functions are allowed to allocate LDS.
747 LLVM_READNONE
748 bool isModuleEntryFunctionCC(CallingConv::ID CC);
749 
750 bool isKernelCC(const Function *Func);
751 
752 // FIXME: Remove this when calling conventions cleaned up
753 LLVM_READNONE
754 inline bool isKernel(CallingConv::ID CC) {
755   switch (CC) {
756   case CallingConv::AMDGPU_KERNEL:
757   case CallingConv::SPIR_KERNEL:
758     return true;
759   default:
760     return false;
761   }
762 }
763 
764 bool hasXNACK(const MCSubtargetInfo &STI);
765 bool hasSRAMECC(const MCSubtargetInfo &STI);
766 bool hasMIMG_R128(const MCSubtargetInfo &STI);
767 bool hasGFX10A16(const MCSubtargetInfo &STI);
768 bool hasG16(const MCSubtargetInfo &STI);
769 bool hasPackedD16(const MCSubtargetInfo &STI);
770 
771 bool isSI(const MCSubtargetInfo &STI);
772 bool isCI(const MCSubtargetInfo &STI);
773 bool isVI(const MCSubtargetInfo &STI);
774 bool isGFX9(const MCSubtargetInfo &STI);
775 bool isGFX9Plus(const MCSubtargetInfo &STI);
776 bool isGFX10(const MCSubtargetInfo &STI);
777 bool isGFX10Plus(const MCSubtargetInfo &STI);
778 bool isGCN3Encoding(const MCSubtargetInfo &STI);
779 bool isGFX10_AEncoding(const MCSubtargetInfo &STI);
780 bool isGFX10_BEncoding(const MCSubtargetInfo &STI);
781 bool hasGFX10_3Insts(const MCSubtargetInfo &STI);
782 bool isGFX90A(const MCSubtargetInfo &STI);
783 bool isGFX940(const MCSubtargetInfo &STI);
784 bool hasArchitectedFlatScratch(const MCSubtargetInfo &STI);
785 bool hasMAIInsts(const MCSubtargetInfo &STI);
786 int getTotalNumVGPRs(bool has90AInsts, int32_t ArgNumAGPR, int32_t ArgNumVGPR);
787 
788 /// Is Reg - scalar register
789 bool isSGPR(unsigned Reg, const MCRegisterInfo* TRI);
790 
791 /// If \p Reg is a pseudo reg, return the correct hardware register given
792 /// \p STI otherwise return \p Reg.
793 unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI);
794 
795 /// Convert hardware register \p Reg to a pseudo register
796 LLVM_READNONE
797 unsigned mc2PseudoReg(unsigned Reg);
798 
799 /// Can this operand also contain immediate values?
800 bool isSISrcOperand(const MCInstrDesc &Desc, unsigned OpNo);
801 
802 /// Is this floating-point operand?
803 bool isSISrcFPOperand(const MCInstrDesc &Desc, unsigned OpNo);
804 
805 /// Does this operand support only inlinable literals?
806 bool isSISrcInlinableOperand(const MCInstrDesc &Desc, unsigned OpNo);
807 
808 /// Get the size in bits of a register from the register class \p RC.
809 unsigned getRegBitWidth(unsigned RCID);
810 
811 /// Get the size in bits of a register from the register class \p RC.
812 unsigned getRegBitWidth(const MCRegisterClass &RC);
813 
814 /// Get size of register operand
815 unsigned getRegOperandSize(const MCRegisterInfo *MRI, const MCInstrDesc &Desc,
816                            unsigned OpNo);
817 
818 LLVM_READNONE
819 inline unsigned getOperandSize(const MCOperandInfo &OpInfo) {
820   switch (OpInfo.OperandType) {
821   case AMDGPU::OPERAND_REG_IMM_INT32:
822   case AMDGPU::OPERAND_REG_IMM_FP32:
823   case AMDGPU::OPERAND_REG_IMM_FP32_DEFERRED:
824   case AMDGPU::OPERAND_REG_INLINE_C_INT32:
825   case AMDGPU::OPERAND_REG_INLINE_C_FP32:
826   case AMDGPU::OPERAND_REG_INLINE_AC_INT32:
827   case AMDGPU::OPERAND_REG_INLINE_AC_FP32:
828   case AMDGPU::OPERAND_REG_IMM_V2INT32:
829   case AMDGPU::OPERAND_REG_IMM_V2FP32:
830   case AMDGPU::OPERAND_REG_INLINE_C_V2INT32:
831   case AMDGPU::OPERAND_REG_INLINE_C_V2FP32:
832   case AMDGPU::OPERAND_KIMM32:
833   case AMDGPU::OPERAND_KIMM16: // mandatory literal is always size 4
834     return 4;
835 
836   case AMDGPU::OPERAND_REG_IMM_INT64:
837   case AMDGPU::OPERAND_REG_IMM_FP64:
838   case AMDGPU::OPERAND_REG_INLINE_C_INT64:
839   case AMDGPU::OPERAND_REG_INLINE_C_FP64:
840   case AMDGPU::OPERAND_REG_INLINE_AC_FP64:
841     return 8;
842 
843   case AMDGPU::OPERAND_REG_IMM_INT16:
844   case AMDGPU::OPERAND_REG_IMM_FP16:
845   case AMDGPU::OPERAND_REG_IMM_FP16_DEFERRED:
846   case AMDGPU::OPERAND_REG_INLINE_C_INT16:
847   case AMDGPU::OPERAND_REG_INLINE_C_FP16:
848   case AMDGPU::OPERAND_REG_INLINE_C_V2INT16:
849   case AMDGPU::OPERAND_REG_INLINE_C_V2FP16:
850   case AMDGPU::OPERAND_REG_INLINE_AC_INT16:
851   case AMDGPU::OPERAND_REG_INLINE_AC_FP16:
852   case AMDGPU::OPERAND_REG_INLINE_AC_V2INT16:
853   case AMDGPU::OPERAND_REG_INLINE_AC_V2FP16:
854   case AMDGPU::OPERAND_REG_IMM_V2INT16:
855   case AMDGPU::OPERAND_REG_IMM_V2FP16:
856     return 2;
857 
858   default:
859     llvm_unreachable("unhandled operand type");
860   }
861 }
862 
863 LLVM_READNONE
864 inline unsigned getOperandSize(const MCInstrDesc &Desc, unsigned OpNo) {
865   return getOperandSize(Desc.OpInfo[OpNo]);
866 }
867 
868 /// Is this literal inlinable, and not one of the values intended for floating
869 /// point values.
870 LLVM_READNONE
871 inline bool isInlinableIntLiteral(int64_t Literal) {
872   return Literal >= -16 && Literal <= 64;
873 }
874 
875 /// Is this literal inlinable
876 LLVM_READNONE
877 bool isInlinableLiteral64(int64_t Literal, bool HasInv2Pi);
878 
879 LLVM_READNONE
880 bool isInlinableLiteral32(int32_t Literal, bool HasInv2Pi);
881 
882 LLVM_READNONE
883 bool isInlinableLiteral16(int16_t Literal, bool HasInv2Pi);
884 
885 LLVM_READNONE
886 bool isInlinableLiteralV216(int32_t Literal, bool HasInv2Pi);
887 
888 LLVM_READNONE
889 bool isInlinableIntLiteralV216(int32_t Literal);
890 
891 LLVM_READNONE
892 bool isFoldableLiteralV216(int32_t Literal, bool HasInv2Pi);
893 
894 bool isArgPassedInSGPR(const Argument *Arg);
895 
896 LLVM_READONLY
897 bool isLegalSMRDEncodedUnsignedOffset(const MCSubtargetInfo &ST,
898                                       int64_t EncodedOffset);
899 
900 LLVM_READONLY
901 bool isLegalSMRDEncodedSignedOffset(const MCSubtargetInfo &ST,
902                                     int64_t EncodedOffset,
903                                     bool IsBuffer);
904 
905 /// Convert \p ByteOffset to dwords if the subtarget uses dword SMRD immediate
906 /// offsets.
907 uint64_t convertSMRDOffsetUnits(const MCSubtargetInfo &ST, uint64_t ByteOffset);
908 
909 /// \returns The encoding that will be used for \p ByteOffset in the
910 /// SMRD offset field, or None if it won't fit. On GFX9 and GFX10
911 /// S_LOAD instructions have a signed offset, on other subtargets it is
912 /// unsigned. S_BUFFER has an unsigned offset for all subtargets.
913 Optional<int64_t> getSMRDEncodedOffset(const MCSubtargetInfo &ST,
914                                        int64_t ByteOffset, bool IsBuffer);
915 
916 /// \return The encoding that can be used for a 32-bit literal offset in an SMRD
917 /// instruction. This is only useful on CI.s
918 Optional<int64_t> getSMRDEncodedLiteralOffset32(const MCSubtargetInfo &ST,
919                                                 int64_t ByteOffset);
920 
921 /// For FLAT segment the offset must be positive;
922 /// MSB is ignored and forced to zero.
923 ///
924 /// \return The number of bits available for the offset field in flat
925 /// instructions.
926 unsigned getNumFlatOffsetBits(const MCSubtargetInfo &ST, bool Signed);
927 
928 /// \returns true if this offset is small enough to fit in the SMRD
929 /// offset field.  \p ByteOffset should be the offset in bytes and
930 /// not the encoded offset.
931 bool isLegalSMRDImmOffset(const MCSubtargetInfo &ST, int64_t ByteOffset);
932 
933 bool splitMUBUFOffset(uint32_t Imm, uint32_t &SOffset, uint32_t &ImmOffset,
934                       const GCNSubtarget *Subtarget,
935                       Align Alignment = Align(4));
936 
937 LLVM_READNONE
938 inline bool isLegal64BitDPPControl(unsigned DC) {
939   return DC >= DPP::ROW_NEWBCAST_FIRST && DC <= DPP::ROW_NEWBCAST_LAST;
940 }
941 
942 /// \returns true if the intrinsic is divergent
943 bool isIntrinsicSourceOfDivergence(unsigned IntrID);
944 
945 // Track defaults for fields in the MODE register.
946 struct SIModeRegisterDefaults {
947   /// Floating point opcodes that support exception flag gathering quiet and
948   /// propagate signaling NaN inputs per IEEE 754-2008. Min_dx10 and max_dx10
949   /// become IEEE 754- 2008 compliant due to signaling NaN propagation and
950   /// quieting.
951   bool IEEE : 1;
952 
953   /// Used by the vector ALU to force DX10-style treatment of NaNs: when set,
954   /// clamp NaN to zero; otherwise, pass NaN through.
955   bool DX10Clamp : 1;
956 
957   /// If this is set, neither input or output denormals are flushed for most f32
958   /// instructions.
959   bool FP32InputDenormals : 1;
960   bool FP32OutputDenormals : 1;
961 
962   /// If this is set, neither input or output denormals are flushed for both f64
963   /// and f16/v2f16 instructions.
964   bool FP64FP16InputDenormals : 1;
965   bool FP64FP16OutputDenormals : 1;
966 
967   SIModeRegisterDefaults() :
968     IEEE(true),
969     DX10Clamp(true),
970     FP32InputDenormals(true),
971     FP32OutputDenormals(true),
972     FP64FP16InputDenormals(true),
973     FP64FP16OutputDenormals(true) {}
974 
975   SIModeRegisterDefaults(const Function &F);
976 
977   static SIModeRegisterDefaults getDefaultForCallingConv(CallingConv::ID CC) {
978     SIModeRegisterDefaults Mode;
979     Mode.IEEE = !AMDGPU::isShader(CC);
980     return Mode;
981   }
982 
983   bool operator ==(const SIModeRegisterDefaults Other) const {
984     return IEEE == Other.IEEE && DX10Clamp == Other.DX10Clamp &&
985            FP32InputDenormals == Other.FP32InputDenormals &&
986            FP32OutputDenormals == Other.FP32OutputDenormals &&
987            FP64FP16InputDenormals == Other.FP64FP16InputDenormals &&
988            FP64FP16OutputDenormals == Other.FP64FP16OutputDenormals;
989   }
990 
991   bool allFP32Denormals() const {
992     return FP32InputDenormals && FP32OutputDenormals;
993   }
994 
995   bool allFP64FP16Denormals() const {
996     return FP64FP16InputDenormals && FP64FP16OutputDenormals;
997   }
998 
999   /// Get the encoding value for the FP_DENORM bits of the mode register for the
1000   /// FP32 denormal mode.
1001   uint32_t fpDenormModeSPValue() const {
1002     if (FP32InputDenormals && FP32OutputDenormals)
1003       return FP_DENORM_FLUSH_NONE;
1004     if (FP32InputDenormals)
1005       return FP_DENORM_FLUSH_OUT;
1006     if (FP32OutputDenormals)
1007       return FP_DENORM_FLUSH_IN;
1008     return FP_DENORM_FLUSH_IN_FLUSH_OUT;
1009   }
1010 
1011   /// Get the encoding value for the FP_DENORM bits of the mode register for the
1012   /// FP64/FP16 denormal mode.
1013   uint32_t fpDenormModeDPValue() const {
1014     if (FP64FP16InputDenormals && FP64FP16OutputDenormals)
1015       return FP_DENORM_FLUSH_NONE;
1016     if (FP64FP16InputDenormals)
1017       return FP_DENORM_FLUSH_OUT;
1018     if (FP64FP16OutputDenormals)
1019       return FP_DENORM_FLUSH_IN;
1020     return FP_DENORM_FLUSH_IN_FLUSH_OUT;
1021   }
1022 
1023   /// Returns true if a flag is compatible if it's enabled in the callee, but
1024   /// disabled in the caller.
1025   static bool oneWayCompatible(bool CallerMode, bool CalleeMode) {
1026     return CallerMode == CalleeMode || (!CallerMode && CalleeMode);
1027   }
1028 
1029   // FIXME: Inlining should be OK for dx10-clamp, since the caller's mode should
1030   // be able to override.
1031   bool isInlineCompatible(SIModeRegisterDefaults CalleeMode) const {
1032     if (DX10Clamp != CalleeMode.DX10Clamp)
1033       return false;
1034     if (IEEE != CalleeMode.IEEE)
1035       return false;
1036 
1037     // Allow inlining denormals enabled into denormals flushed functions.
1038     return oneWayCompatible(FP64FP16InputDenormals, CalleeMode.FP64FP16InputDenormals) &&
1039            oneWayCompatible(FP64FP16OutputDenormals, CalleeMode.FP64FP16OutputDenormals) &&
1040            oneWayCompatible(FP32InputDenormals, CalleeMode.FP32InputDenormals) &&
1041            oneWayCompatible(FP32OutputDenormals, CalleeMode.FP32OutputDenormals);
1042   }
1043 };
1044 
1045 } // end namespace AMDGPU
1046 
1047 raw_ostream &operator<<(raw_ostream &OS,
1048                         const AMDGPU::IsaInfo::TargetIDSetting S);
1049 
1050 } // end namespace llvm
1051 
1052 #endif // LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
1053