1 //===- AMDGPUBaseInfo.h - Top level definitions for AMDGPU ------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #ifndef LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
10 #define LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
11 
12 #include "AMDGPU.h"
13 #include "AMDKernelCodeT.h"
14 #include "SIDefines.h"
15 #include "llvm/ADT/StringRef.h"
16 #include "llvm/IR/CallingConv.h"
17 #include "llvm/MC/MCInstrDesc.h"
18 #include "llvm/Support/AMDHSAKernelDescriptor.h"
19 #include "llvm/Support/Compiler.h"
20 #include "llvm/Support/ErrorHandling.h"
21 #include "llvm/Support/TargetParser.h"
22 #include <cstdint>
23 #include <string>
24 #include <utility>
25 
26 namespace llvm {
27 
28 class Argument;
29 class AMDGPUSubtarget;
30 class FeatureBitset;
31 class Function;
32 class GCNSubtarget;
33 class GlobalValue;
34 class MCContext;
35 class MCRegisterClass;
36 class MCRegisterInfo;
37 class MCSection;
38 class MCSubtargetInfo;
39 class MachineMemOperand;
40 class Triple;
41 
42 namespace AMDGPU {
43 
44 #define GET_MIMGBaseOpcode_DECL
45 #define GET_MIMGDim_DECL
46 #define GET_MIMGEncoding_DECL
47 #define GET_MIMGLZMapping_DECL
48 #define GET_MIMGMIPMapping_DECL
49 #include "AMDGPUGenSearchableTables.inc"
50 
51 namespace IsaInfo {
52 
53 enum {
54   // The closed Vulkan driver sets 96, which limits the wave count to 8 but
55   // doesn't spill SGPRs as much as when 80 is set.
56   FIXED_NUM_SGPRS_FOR_INIT_BUG = 96,
57   TRAP_NUM_SGPRS = 16
58 };
59 
60 /// Streams isa version string for given subtarget \p STI into \p Stream.
61 void streamIsaVersion(const MCSubtargetInfo *STI, raw_ostream &Stream);
62 
63 /// \returns True if given subtarget \p STI supports code object version 3,
64 /// false otherwise.
65 bool hasCodeObjectV3(const MCSubtargetInfo *STI);
66 
67 /// \returns Wavefront size for given subtarget \p STI.
68 unsigned getWavefrontSize(const MCSubtargetInfo *STI);
69 
70 /// \returns Local memory size in bytes for given subtarget \p STI.
71 unsigned getLocalMemorySize(const MCSubtargetInfo *STI);
72 
73 /// \returns Number of execution units per compute unit for given subtarget \p
74 /// STI.
75 unsigned getEUsPerCU(const MCSubtargetInfo *STI);
76 
77 /// \returns Maximum number of work groups per compute unit for given subtarget
78 /// \p STI and limited by given \p FlatWorkGroupSize.
79 unsigned getMaxWorkGroupsPerCU(const MCSubtargetInfo *STI,
80                                unsigned FlatWorkGroupSize);
81 
82 /// \returns Maximum number of waves per compute unit for given subtarget \p
83 /// STI without any kind of limitation.
84 unsigned getMaxWavesPerCU(const MCSubtargetInfo *STI);
85 
86 /// \returns Maximum number of waves per compute unit for given subtarget \p
87 /// STI and limited by given \p FlatWorkGroupSize.
88 unsigned getMaxWavesPerCU(const MCSubtargetInfo *STI,
89                           unsigned FlatWorkGroupSize);
90 
91 /// \returns Minimum number of waves per execution unit for given subtarget \p
92 /// STI.
93 unsigned getMinWavesPerEU(const MCSubtargetInfo *STI);
94 
95 /// \returns Maximum number of waves per execution unit for given subtarget \p
96 /// STI without any kind of limitation.
97 unsigned getMaxWavesPerEU();
98 
99 /// \returns Maximum number of waves per execution unit for given subtarget \p
100 /// STI and limited by given \p FlatWorkGroupSize.
101 unsigned getMaxWavesPerEU(const MCSubtargetInfo *STI,
102                           unsigned FlatWorkGroupSize);
103 
104 /// \returns Minimum flat work group size for given subtarget \p STI.
105 unsigned getMinFlatWorkGroupSize(const MCSubtargetInfo *STI);
106 
107 /// \returns Maximum flat work group size for given subtarget \p STI.
108 unsigned getMaxFlatWorkGroupSize(const MCSubtargetInfo *STI);
109 
110 /// \returns Number of waves per work group for given subtarget \p STI and
111 /// limited by given \p FlatWorkGroupSize.
112 unsigned getWavesPerWorkGroup(const MCSubtargetInfo *STI,
113                               unsigned FlatWorkGroupSize);
114 
115 /// \returns SGPR allocation granularity for given subtarget \p STI.
116 unsigned getSGPRAllocGranule(const MCSubtargetInfo *STI);
117 
118 /// \returns SGPR encoding granularity for given subtarget \p STI.
119 unsigned getSGPREncodingGranule(const MCSubtargetInfo *STI);
120 
121 /// \returns Total number of SGPRs for given subtarget \p STI.
122 unsigned getTotalNumSGPRs(const MCSubtargetInfo *STI);
123 
124 /// \returns Addressable number of SGPRs for given subtarget \p STI.
125 unsigned getAddressableNumSGPRs(const MCSubtargetInfo *STI);
126 
127 /// \returns Minimum number of SGPRs that meets the given number of waves per
128 /// execution unit requirement for given subtarget \p STI.
129 unsigned getMinNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU);
130 
131 /// \returns Maximum number of SGPRs that meets the given number of waves per
132 /// execution unit requirement for given subtarget \p STI.
133 unsigned getMaxNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU,
134                         bool Addressable);
135 
136 /// \returns Number of extra SGPRs implicitly required by given subtarget \p
137 /// STI when the given special registers are used.
138 unsigned getNumExtraSGPRs(const MCSubtargetInfo *STI, bool VCCUsed,
139                           bool FlatScrUsed, bool XNACKUsed);
140 
141 /// \returns Number of extra SGPRs implicitly required by given subtarget \p
142 /// STI when the given special registers are used. XNACK is inferred from
143 /// \p STI.
144 unsigned getNumExtraSGPRs(const MCSubtargetInfo *STI, bool VCCUsed,
145                           bool FlatScrUsed);
146 
147 /// \returns Number of SGPR blocks needed for given subtarget \p STI when
148 /// \p NumSGPRs are used. \p NumSGPRs should already include any special
149 /// register counts.
150 unsigned getNumSGPRBlocks(const MCSubtargetInfo *STI, unsigned NumSGPRs);
151 
152 /// \returns VGPR allocation granularity for given subtarget \p STI.
153 ///
154 /// For subtargets which support it, \p EnableWavefrontSize32 should match
155 /// the ENABLE_WAVEFRONT_SIZE32 kernel descriptor field.
156 unsigned getVGPRAllocGranule(const MCSubtargetInfo *STI,
157                              Optional<bool> EnableWavefrontSize32 = None);
158 
159 /// \returns VGPR encoding granularity for given subtarget \p STI.
160 ///
161 /// For subtargets which support it, \p EnableWavefrontSize32 should match
162 /// the ENABLE_WAVEFRONT_SIZE32 kernel descriptor field.
163 unsigned getVGPREncodingGranule(const MCSubtargetInfo *STI,
164                                 Optional<bool> EnableWavefrontSize32 = None);
165 
166 /// \returns Total number of VGPRs for given subtarget \p STI.
167 unsigned getTotalNumVGPRs(const MCSubtargetInfo *STI);
168 
169 /// \returns Addressable number of VGPRs for given subtarget \p STI.
170 unsigned getAddressableNumVGPRs(const MCSubtargetInfo *STI);
171 
172 /// \returns Minimum number of VGPRs that meets given number of waves per
173 /// execution unit requirement for given subtarget \p STI.
174 unsigned getMinNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU);
175 
176 /// \returns Maximum number of VGPRs that meets given number of waves per
177 /// execution unit requirement for given subtarget \p STI.
178 unsigned getMaxNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU);
179 
180 /// \returns Number of VGPR blocks needed for given subtarget \p STI when
181 /// \p NumVGPRs are used.
182 ///
183 /// For subtargets which support it, \p EnableWavefrontSize32 should match the
184 /// ENABLE_WAVEFRONT_SIZE32 kernel descriptor field.
185 unsigned getNumVGPRBlocks(const MCSubtargetInfo *STI, unsigned NumSGPRs,
186                           Optional<bool> EnableWavefrontSize32 = None);
187 
188 } // end namespace IsaInfo
189 
190 LLVM_READONLY
191 int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx);
192 
193 struct MIMGBaseOpcodeInfo {
194   MIMGBaseOpcode BaseOpcode;
195   bool Store;
196   bool Atomic;
197   bool AtomicX2;
198   bool Sampler;
199   bool Gather4;
200 
201   uint8_t NumExtraArgs;
202   bool Gradients;
203   bool Coordinates;
204   bool LodOrClampOrMip;
205   bool HasD16;
206 };
207 
208 LLVM_READONLY
209 const MIMGBaseOpcodeInfo *getMIMGBaseOpcodeInfo(unsigned BaseOpcode);
210 
211 struct MIMGDimInfo {
212   MIMGDim Dim;
213   uint8_t NumCoords;
214   uint8_t NumGradients;
215   bool DA;
216   uint8_t Encoding;
217   const char *AsmSuffix;
218 };
219 
220 LLVM_READONLY
221 const MIMGDimInfo *getMIMGDimInfo(unsigned DimEnum);
222 
223 LLVM_READONLY
224 const MIMGDimInfo *getMIMGDimInfoByEncoding(uint8_t DimEnc);
225 
226 LLVM_READONLY
227 const MIMGDimInfo *getMIMGDimInfoByAsmSuffix(StringRef AsmSuffix);
228 
229 struct MIMGLZMappingInfo {
230   MIMGBaseOpcode L;
231   MIMGBaseOpcode LZ;
232 };
233 
234 struct MIMGMIPMappingInfo {
235   MIMGBaseOpcode MIP;
236   MIMGBaseOpcode NONMIP;
237 };
238 
239 LLVM_READONLY
240 const MIMGLZMappingInfo *getMIMGLZMappingInfo(unsigned L);
241 
242 LLVM_READONLY
243 const MIMGMIPMappingInfo *getMIMGMIPMappingInfo(unsigned L);
244 
245 LLVM_READONLY
246 int getMIMGOpcode(unsigned BaseOpcode, unsigned MIMGEncoding,
247                   unsigned VDataDwords, unsigned VAddrDwords);
248 
249 LLVM_READONLY
250 int getMaskedMIMGOp(unsigned Opc, unsigned NewChannels);
251 
252 struct MIMGInfo {
253   uint16_t Opcode;
254   uint16_t BaseOpcode;
255   uint8_t MIMGEncoding;
256   uint8_t VDataDwords;
257   uint8_t VAddrDwords;
258 };
259 
260 LLVM_READONLY
261 const MIMGInfo *getMIMGInfo(unsigned Opc);
262 
263 LLVM_READONLY
264 int getMUBUFBaseOpcode(unsigned Opc);
265 
266 LLVM_READONLY
267 int getMUBUFOpcode(unsigned BaseOpc, unsigned Dwords);
268 
269 LLVM_READONLY
270 int getMUBUFDwords(unsigned Opc);
271 
272 LLVM_READONLY
273 bool getMUBUFHasVAddr(unsigned Opc);
274 
275 LLVM_READONLY
276 bool getMUBUFHasSrsrc(unsigned Opc);
277 
278 LLVM_READONLY
279 bool getMUBUFHasSoffset(unsigned Opc);
280 
281 LLVM_READONLY
282 int getMCOpcode(uint16_t Opcode, unsigned Gen);
283 
284 void initDefaultAMDKernelCodeT(amd_kernel_code_t &Header,
285                                const MCSubtargetInfo *STI);
286 
287 amdhsa::kernel_descriptor_t getDefaultAmdhsaKernelDescriptor(
288     const MCSubtargetInfo *STI);
289 
290 bool isGroupSegment(const GlobalValue *GV);
291 bool isGlobalSegment(const GlobalValue *GV);
292 bool isReadOnlySegment(const GlobalValue *GV);
293 
294 /// \returns True if constants should be emitted to .text section for given
295 /// target triple \p TT, false otherwise.
296 bool shouldEmitConstantsToTextSection(const Triple &TT);
297 
298 /// \returns Integer value requested using \p F's \p Name attribute.
299 ///
300 /// \returns \p Default if attribute is not present.
301 ///
302 /// \returns \p Default and emits error if requested value cannot be converted
303 /// to integer.
304 int getIntegerAttribute(const Function &F, StringRef Name, int Default);
305 
306 /// \returns A pair of integer values requested using \p F's \p Name attribute
307 /// in "first[,second]" format ("second" is optional unless \p OnlyFirstRequired
308 /// is false).
309 ///
310 /// \returns \p Default if attribute is not present.
311 ///
312 /// \returns \p Default and emits error if one of the requested values cannot be
313 /// converted to integer, or \p OnlyFirstRequired is false and "second" value is
314 /// not present.
315 std::pair<int, int> getIntegerPairAttribute(const Function &F,
316                                             StringRef Name,
317                                             std::pair<int, int> Default,
318                                             bool OnlyFirstRequired = false);
319 
320 /// Represents the counter values to wait for in an s_waitcnt instruction.
321 ///
322 /// Large values (including the maximum possible integer) can be used to
323 /// represent "don't care" waits.
324 struct Waitcnt {
325   unsigned VmCnt = ~0u;
326   unsigned ExpCnt = ~0u;
327   unsigned LgkmCnt = ~0u;
328   unsigned VsCnt = ~0u;
329 
330   Waitcnt() {}
331   Waitcnt(unsigned VmCnt, unsigned ExpCnt, unsigned LgkmCnt, unsigned VsCnt)
332       : VmCnt(VmCnt), ExpCnt(ExpCnt), LgkmCnt(LgkmCnt), VsCnt(VsCnt) {}
333 
334   static Waitcnt allZero(const IsaVersion &Version) {
335     return Waitcnt(0, 0, 0, Version.Major >= 10 ? 0 : ~0u);
336   }
337   static Waitcnt allZeroExceptVsCnt() { return Waitcnt(0, 0, 0, ~0u); }
338 
339   bool hasWait() const {
340     return VmCnt != ~0u || ExpCnt != ~0u || LgkmCnt != ~0u || VsCnt != ~0u;
341   }
342 
343   bool dominates(const Waitcnt &Other) const {
344     return VmCnt <= Other.VmCnt && ExpCnt <= Other.ExpCnt &&
345            LgkmCnt <= Other.LgkmCnt && VsCnt <= Other.VsCnt;
346   }
347 
348   Waitcnt combined(const Waitcnt &Other) const {
349     return Waitcnt(std::min(VmCnt, Other.VmCnt), std::min(ExpCnt, Other.ExpCnt),
350                    std::min(LgkmCnt, Other.LgkmCnt),
351                    std::min(VsCnt, Other.VsCnt));
352   }
353 };
354 
355 /// \returns Vmcnt bit mask for given isa \p Version.
356 unsigned getVmcntBitMask(const IsaVersion &Version);
357 
358 /// \returns Expcnt bit mask for given isa \p Version.
359 unsigned getExpcntBitMask(const IsaVersion &Version);
360 
361 /// \returns Lgkmcnt bit mask for given isa \p Version.
362 unsigned getLgkmcntBitMask(const IsaVersion &Version);
363 
364 /// \returns Waitcnt bit mask for given isa \p Version.
365 unsigned getWaitcntBitMask(const IsaVersion &Version);
366 
367 /// \returns Decoded Vmcnt from given \p Waitcnt for given isa \p Version.
368 unsigned decodeVmcnt(const IsaVersion &Version, unsigned Waitcnt);
369 
370 /// \returns Decoded Expcnt from given \p Waitcnt for given isa \p Version.
371 unsigned decodeExpcnt(const IsaVersion &Version, unsigned Waitcnt);
372 
373 /// \returns Decoded Lgkmcnt from given \p Waitcnt for given isa \p Version.
374 unsigned decodeLgkmcnt(const IsaVersion &Version, unsigned Waitcnt);
375 
376 /// Decodes Vmcnt, Expcnt and Lgkmcnt from given \p Waitcnt for given isa
377 /// \p Version, and writes decoded values into \p Vmcnt, \p Expcnt and
378 /// \p Lgkmcnt respectively.
379 ///
380 /// \details \p Vmcnt, \p Expcnt and \p Lgkmcnt are decoded as follows:
381 ///     \p Vmcnt = \p Waitcnt[3:0]                      (pre-gfx9 only)
382 ///     \p Vmcnt = \p Waitcnt[3:0] | \p Waitcnt[15:14]  (gfx9+ only)
383 ///     \p Expcnt = \p Waitcnt[6:4]
384 ///     \p Lgkmcnt = \p Waitcnt[11:8]                   (pre-gfx10 only)
385 ///     \p Lgkmcnt = \p Waitcnt[13:8]                   (gfx10+ only)
386 void decodeWaitcnt(const IsaVersion &Version, unsigned Waitcnt,
387                    unsigned &Vmcnt, unsigned &Expcnt, unsigned &Lgkmcnt);
388 
389 Waitcnt decodeWaitcnt(const IsaVersion &Version, unsigned Encoded);
390 
391 /// \returns \p Waitcnt with encoded \p Vmcnt for given isa \p Version.
392 unsigned encodeVmcnt(const IsaVersion &Version, unsigned Waitcnt,
393                      unsigned Vmcnt);
394 
395 /// \returns \p Waitcnt with encoded \p Expcnt for given isa \p Version.
396 unsigned encodeExpcnt(const IsaVersion &Version, unsigned Waitcnt,
397                       unsigned Expcnt);
398 
399 /// \returns \p Waitcnt with encoded \p Lgkmcnt for given isa \p Version.
400 unsigned encodeLgkmcnt(const IsaVersion &Version, unsigned Waitcnt,
401                        unsigned Lgkmcnt);
402 
403 /// Encodes \p Vmcnt, \p Expcnt and \p Lgkmcnt into Waitcnt for given isa
404 /// \p Version.
405 ///
406 /// \details \p Vmcnt, \p Expcnt and \p Lgkmcnt are encoded as follows:
407 ///     Waitcnt[3:0]   = \p Vmcnt       (pre-gfx9 only)
408 ///     Waitcnt[3:0]   = \p Vmcnt[3:0]  (gfx9+ only)
409 ///     Waitcnt[6:4]   = \p Expcnt
410 ///     Waitcnt[11:8]  = \p Lgkmcnt     (pre-gfx10 only)
411 ///     Waitcnt[13:8]  = \p Lgkmcnt     (gfx10+ only)
412 ///     Waitcnt[15:14] = \p Vmcnt[5:4]  (gfx9+ only)
413 ///
414 /// \returns Waitcnt with encoded \p Vmcnt, \p Expcnt and \p Lgkmcnt for given
415 /// isa \p Version.
416 unsigned encodeWaitcnt(const IsaVersion &Version,
417                        unsigned Vmcnt, unsigned Expcnt, unsigned Lgkmcnt);
418 
419 unsigned encodeWaitcnt(const IsaVersion &Version, const Waitcnt &Decoded);
420 
421 namespace Hwreg {
422 
423 LLVM_READONLY
424 int64_t getHwregId(const StringRef Name);
425 
426 LLVM_READNONE
427 bool isValidHwreg(int64_t Id, const MCSubtargetInfo &STI);
428 
429 LLVM_READNONE
430 bool isValidHwreg(int64_t Id);
431 
432 LLVM_READNONE
433 bool isValidHwregOffset(int64_t Offset);
434 
435 LLVM_READNONE
436 bool isValidHwregWidth(int64_t Width);
437 
438 LLVM_READNONE
439 int64_t encodeHwreg(int64_t Id, int64_t Offset, int64_t Width);
440 
441 LLVM_READNONE
442 StringRef getHwreg(unsigned Id, const MCSubtargetInfo &STI);
443 
444 void decodeHwreg(unsigned Val, unsigned &Id, unsigned &Offset, unsigned &Width);
445 
446 } // namespace Hwreg
447 
448 unsigned getInitialPSInputAddr(const Function &F);
449 
450 LLVM_READNONE
451 bool isShader(CallingConv::ID CC);
452 
453 LLVM_READNONE
454 bool isCompute(CallingConv::ID CC);
455 
456 LLVM_READNONE
457 bool isEntryFunctionCC(CallingConv::ID CC);
458 
459 // FIXME: Remove this when calling conventions cleaned up
460 LLVM_READNONE
461 inline bool isKernel(CallingConv::ID CC) {
462   switch (CC) {
463   case CallingConv::AMDGPU_KERNEL:
464   case CallingConv::SPIR_KERNEL:
465     return true;
466   default:
467     return false;
468   }
469 }
470 
471 bool hasXNACK(const MCSubtargetInfo &STI);
472 bool hasSRAMECC(const MCSubtargetInfo &STI);
473 bool hasMIMG_R128(const MCSubtargetInfo &STI);
474 bool hasPackedD16(const MCSubtargetInfo &STI);
475 
476 bool isSI(const MCSubtargetInfo &STI);
477 bool isCI(const MCSubtargetInfo &STI);
478 bool isVI(const MCSubtargetInfo &STI);
479 bool isGFX9(const MCSubtargetInfo &STI);
480 bool isGFX10(const MCSubtargetInfo &STI);
481 
482 /// Is Reg - scalar register
483 bool isSGPR(unsigned Reg, const MCRegisterInfo* TRI);
484 
485 /// Is there any intersection between registers
486 bool isRegIntersect(unsigned Reg0, unsigned Reg1, const MCRegisterInfo* TRI);
487 
488 /// If \p Reg is a pseudo reg, return the correct hardware register given
489 /// \p STI otherwise return \p Reg.
490 unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI);
491 
492 /// Convert hardware register \p Reg to a pseudo register
493 LLVM_READNONE
494 unsigned mc2PseudoReg(unsigned Reg);
495 
496 /// Can this operand also contain immediate values?
497 bool isSISrcOperand(const MCInstrDesc &Desc, unsigned OpNo);
498 
499 /// Is this floating-point operand?
500 bool isSISrcFPOperand(const MCInstrDesc &Desc, unsigned OpNo);
501 
502 /// Does this opearnd support only inlinable literals?
503 bool isSISrcInlinableOperand(const MCInstrDesc &Desc, unsigned OpNo);
504 
505 /// Get the size in bits of a register from the register class \p RC.
506 unsigned getRegBitWidth(unsigned RCID);
507 
508 /// Get the size in bits of a register from the register class \p RC.
509 unsigned getRegBitWidth(const MCRegisterClass &RC);
510 
511 /// Get size of register operand
512 unsigned getRegOperandSize(const MCRegisterInfo *MRI, const MCInstrDesc &Desc,
513                            unsigned OpNo);
514 
515 LLVM_READNONE
516 inline unsigned getOperandSize(const MCOperandInfo &OpInfo) {
517   switch (OpInfo.OperandType) {
518   case AMDGPU::OPERAND_REG_IMM_INT32:
519   case AMDGPU::OPERAND_REG_IMM_FP32:
520   case AMDGPU::OPERAND_REG_INLINE_C_INT32:
521   case AMDGPU::OPERAND_REG_INLINE_C_FP32:
522     return 4;
523 
524   case AMDGPU::OPERAND_REG_IMM_INT64:
525   case AMDGPU::OPERAND_REG_IMM_FP64:
526   case AMDGPU::OPERAND_REG_INLINE_C_INT64:
527   case AMDGPU::OPERAND_REG_INLINE_C_FP64:
528     return 8;
529 
530   case AMDGPU::OPERAND_REG_IMM_INT16:
531   case AMDGPU::OPERAND_REG_IMM_FP16:
532   case AMDGPU::OPERAND_REG_INLINE_C_INT16:
533   case AMDGPU::OPERAND_REG_INLINE_C_FP16:
534   case AMDGPU::OPERAND_REG_INLINE_C_V2INT16:
535   case AMDGPU::OPERAND_REG_INLINE_C_V2FP16:
536   case AMDGPU::OPERAND_REG_IMM_V2INT16:
537   case AMDGPU::OPERAND_REG_IMM_V2FP16:
538     return 2;
539 
540   default:
541     llvm_unreachable("unhandled operand type");
542   }
543 }
544 
545 LLVM_READNONE
546 inline unsigned getOperandSize(const MCInstrDesc &Desc, unsigned OpNo) {
547   return getOperandSize(Desc.OpInfo[OpNo]);
548 }
549 
550 /// Is this literal inlinable
551 LLVM_READNONE
552 bool isInlinableLiteral64(int64_t Literal, bool HasInv2Pi);
553 
554 LLVM_READNONE
555 bool isInlinableLiteral32(int32_t Literal, bool HasInv2Pi);
556 
557 LLVM_READNONE
558 bool isInlinableLiteral16(int16_t Literal, bool HasInv2Pi);
559 
560 LLVM_READNONE
561 bool isInlinableLiteralV216(int32_t Literal, bool HasInv2Pi);
562 
563 bool isArgPassedInSGPR(const Argument *Arg);
564 
565 /// \returns The encoding that will be used for \p ByteOffset in the SMRD
566 /// offset field.
567 int64_t getSMRDEncodedOffset(const MCSubtargetInfo &ST, int64_t ByteOffset);
568 
569 /// \returns true if this offset is small enough to fit in the SMRD
570 /// offset field.  \p ByteOffset should be the offset in bytes and
571 /// not the encoded offset.
572 bool isLegalSMRDImmOffset(const MCSubtargetInfo &ST, int64_t ByteOffset);
573 
574 bool splitMUBUFOffset(uint32_t Imm, uint32_t &SOffset, uint32_t &ImmOffset,
575                       const GCNSubtarget *Subtarget, uint32_t Align = 4);
576 
577 /// \returns true if the intrinsic is divergent
578 bool isIntrinsicSourceOfDivergence(unsigned IntrID);
579 
580 
581 // Track defaults for fields in the MODE registser.
582 struct SIModeRegisterDefaults {
583   /// Floating point opcodes that support exception flag gathering quiet and
584   /// propagate signaling NaN inputs per IEEE 754-2008. Min_dx10 and max_dx10
585   /// become IEEE 754- 2008 compliant due to signaling NaN propagation and
586   /// quieting.
587   bool IEEE : 1;
588 
589   /// Used by the vector ALU to force DX10-style treatment of NaNs: when set,
590   /// clamp NaN to zero; otherwise, pass NaN through.
591   bool DX10Clamp : 1;
592 
593   // TODO: FP mode fields
594 
595   SIModeRegisterDefaults() :
596     IEEE(true),
597     DX10Clamp(true) {}
598 
599   SIModeRegisterDefaults(const Function &F);
600 
601   static SIModeRegisterDefaults getDefaultForCallingConv(CallingConv::ID CC) {
602     SIModeRegisterDefaults Mode;
603     Mode.DX10Clamp = true;
604     Mode.IEEE = AMDGPU::isCompute(CC);
605     return Mode;
606   }
607 
608   bool operator ==(const SIModeRegisterDefaults Other) const {
609     return IEEE == Other.IEEE && DX10Clamp == Other.DX10Clamp;
610   }
611 
612   // FIXME: Inlining should be OK for dx10-clamp, since the caller's mode should
613   // be able to override.
614   bool isInlineCompatible(SIModeRegisterDefaults CalleeMode) const {
615     return *this == CalleeMode;
616   }
617 };
618 
619 } // end namespace AMDGPU
620 } // end namespace llvm
621 
622 #endif // LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
623