1 //===-- AMDGPUBaseInfo.h - Top level definitions for AMDGPU -----*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
10 #ifndef LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
11 #define LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
12 
13 #include "AMDKernelCodeT.h"
14 
15 namespace llvm {
16 
17 class FeatureBitset;
18 class Function;
19 class GlobalValue;
20 class MCContext;
21 class MCSection;
22 class MCSubtargetInfo;
23 
24 namespace AMDGPU {
25 
26 struct IsaVersion {
27   unsigned Major;
28   unsigned Minor;
29   unsigned Stepping;
30 };
31 
32 IsaVersion getIsaVersion(const FeatureBitset &Features);
33 void initDefaultAMDKernelCodeT(amd_kernel_code_t &Header,
34                                const FeatureBitset &Features);
35 MCSection *getHSATextSection(MCContext &Ctx);
36 
37 MCSection *getHSADataGlobalAgentSection(MCContext &Ctx);
38 
39 MCSection *getHSADataGlobalProgramSection(MCContext &Ctx);
40 
41 MCSection *getHSARodataReadonlyAgentSection(MCContext &Ctx);
42 
43 bool isGroupSegment(const GlobalValue *GV);
44 bool isGlobalSegment(const GlobalValue *GV);
45 bool isReadOnlySegment(const GlobalValue *GV);
46 
47 unsigned getShaderType(const Function &F);
48 unsigned getInitialPSInputAddr(const Function &F);
49 
50 
51 bool isSI(const MCSubtargetInfo &STI);
52 bool isCI(const MCSubtargetInfo &STI);
53 bool isVI(const MCSubtargetInfo &STI);
54 
55 /// If \p Reg is a pseudo reg, return the correct hardware register given
56 /// \p STI otherwise return \p Reg.
57 unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI);
58 
59 } // end namespace AMDGPU
60 } // end namespace llvm
61 
62 #endif
63