1 //===- AMDGPUBaseInfo.h - Top level definitions for AMDGPU ------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #ifndef LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
10 #define LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
11 
12 #include "SIDefines.h"
13 #include "llvm/IR/CallingConv.h"
14 #include "llvm/Support/Alignment.h"
15 
16 struct amd_kernel_code_t;
17 
18 namespace llvm {
19 
20 struct Align;
21 class Argument;
22 class Function;
23 class GCNSubtarget;
24 class GlobalValue;
25 class MCRegisterClass;
26 class MCRegisterInfo;
27 class MCSubtargetInfo;
28 class StringRef;
29 class Triple;
30 
31 namespace amdhsa {
32 struct kernel_descriptor_t;
33 }
34 
35 namespace AMDGPU {
36 
37 struct IsaVersion;
38 
39 /// \returns HSA OS ABI Version identification.
40 Optional<uint8_t> getHsaAbiVersion(const MCSubtargetInfo *STI);
41 /// \returns True if HSA OS ABI Version identification is 2,
42 /// false otherwise.
43 bool isHsaAbiVersion2(const MCSubtargetInfo *STI);
44 /// \returns True if HSA OS ABI Version identification is 3,
45 /// false otherwise.
46 bool isHsaAbiVersion3(const MCSubtargetInfo *STI);
47 /// \returns True if HSA OS ABI Version identification is 4,
48 /// false otherwise.
49 bool isHsaAbiVersion4(const MCSubtargetInfo *STI);
50 /// \returns True if HSA OS ABI Version identification is 3 or 4,
51 /// false otherwise.
52 bool isHsaAbiVersion3Or4(const MCSubtargetInfo *STI);
53 
54 struct GcnBufferFormatInfo {
55   unsigned Format;
56   unsigned BitsPerComp;
57   unsigned NumComponents;
58   unsigned NumFormat;
59   unsigned DataFormat;
60 };
61 
62 #define GET_MIMGBaseOpcode_DECL
63 #define GET_MIMGDim_DECL
64 #define GET_MIMGEncoding_DECL
65 #define GET_MIMGLZMapping_DECL
66 #define GET_MIMGMIPMapping_DECL
67 #include "AMDGPUGenSearchableTables.inc"
68 
69 namespace IsaInfo {
70 
71 enum {
72   // The closed Vulkan driver sets 96, which limits the wave count to 8 but
73   // doesn't spill SGPRs as much as when 80 is set.
74   FIXED_NUM_SGPRS_FOR_INIT_BUG = 96,
75   TRAP_NUM_SGPRS = 16
76 };
77 
78 enum class TargetIDSetting {
79   Unsupported,
80   Any,
81   Off,
82   On
83 };
84 
85 class AMDGPUTargetID {
86 private:
87   const MCSubtargetInfo &STI;
88   TargetIDSetting XnackSetting;
89   TargetIDSetting SramEccSetting;
90 
91 public:
92   explicit AMDGPUTargetID(const MCSubtargetInfo &STI);
93   ~AMDGPUTargetID() = default;
94 
95   /// \return True if the current xnack setting is not "Unsupported".
96   bool isXnackSupported() const {
97     return XnackSetting != TargetIDSetting::Unsupported;
98   }
99 
100   /// \returns True if the current xnack setting is "On" or "Any".
101   bool isXnackOnOrAny() const {
102     return XnackSetting == TargetIDSetting::On ||
103         XnackSetting == TargetIDSetting::Any;
104   }
105 
106   /// \returns True if current xnack setting is "On" or "Off",
107   /// false otherwise.
108   bool isXnackOnOrOff() const {
109     return getXnackSetting() == TargetIDSetting::On ||
110         getXnackSetting() == TargetIDSetting::Off;
111   }
112 
113   /// \returns The current xnack TargetIDSetting, possible options are
114   /// "Unsupported", "Any", "Off", and "On".
115   TargetIDSetting getXnackSetting() const {
116     return XnackSetting;
117   }
118 
119   /// Sets xnack setting to \p NewXnackSetting.
120   void setXnackSetting(TargetIDSetting NewXnackSetting) {
121     XnackSetting = NewXnackSetting;
122   }
123 
124   /// \return True if the current sramecc setting is not "Unsupported".
125   bool isSramEccSupported() const {
126     return SramEccSetting != TargetIDSetting::Unsupported;
127   }
128 
129   /// \returns True if the current sramecc setting is "On" or "Any".
130   bool isSramEccOnOrAny() const {
131   return SramEccSetting == TargetIDSetting::On ||
132       SramEccSetting == TargetIDSetting::Any;
133   }
134 
135   /// \returns True if current sramecc setting is "On" or "Off",
136   /// false otherwise.
137   bool isSramEccOnOrOff() const {
138     return getSramEccSetting() == TargetIDSetting::On ||
139         getSramEccSetting() == TargetIDSetting::Off;
140   }
141 
142   /// \returns The current sramecc TargetIDSetting, possible options are
143   /// "Unsupported", "Any", "Off", and "On".
144   TargetIDSetting getSramEccSetting() const {
145     return SramEccSetting;
146   }
147 
148   /// Sets sramecc setting to \p NewSramEccSetting.
149   void setSramEccSetting(TargetIDSetting NewSramEccSetting) {
150     SramEccSetting = NewSramEccSetting;
151   }
152 
153   void setTargetIDFromFeaturesString(StringRef FS);
154   void setTargetIDFromTargetIDStream(StringRef TargetID);
155 
156   /// \returns String representation of an object.
157   std::string toString() const;
158 };
159 
160 /// \returns Wavefront size for given subtarget \p STI.
161 unsigned getWavefrontSize(const MCSubtargetInfo *STI);
162 
163 /// \returns Local memory size in bytes for given subtarget \p STI.
164 unsigned getLocalMemorySize(const MCSubtargetInfo *STI);
165 
166 /// \returns Number of execution units per compute unit for given subtarget \p
167 /// STI.
168 unsigned getEUsPerCU(const MCSubtargetInfo *STI);
169 
170 /// \returns Maximum number of work groups per compute unit for given subtarget
171 /// \p STI and limited by given \p FlatWorkGroupSize.
172 unsigned getMaxWorkGroupsPerCU(const MCSubtargetInfo *STI,
173                                unsigned FlatWorkGroupSize);
174 
175 /// \returns Minimum number of waves per execution unit for given subtarget \p
176 /// STI.
177 unsigned getMinWavesPerEU(const MCSubtargetInfo *STI);
178 
179 /// \returns Maximum number of waves per execution unit for given subtarget \p
180 /// STI without any kind of limitation.
181 unsigned getMaxWavesPerEU(const MCSubtargetInfo *STI);
182 
183 /// \returns Number of waves per execution unit required to support the given \p
184 /// FlatWorkGroupSize.
185 unsigned getWavesPerEUForWorkGroup(const MCSubtargetInfo *STI,
186                                    unsigned FlatWorkGroupSize);
187 
188 /// \returns Minimum flat work group size for given subtarget \p STI.
189 unsigned getMinFlatWorkGroupSize(const MCSubtargetInfo *STI);
190 
191 /// \returns Maximum flat work group size for given subtarget \p STI.
192 unsigned getMaxFlatWorkGroupSize(const MCSubtargetInfo *STI);
193 
194 /// \returns Number of waves per work group for given subtarget \p STI and
195 /// \p FlatWorkGroupSize.
196 unsigned getWavesPerWorkGroup(const MCSubtargetInfo *STI,
197                               unsigned FlatWorkGroupSize);
198 
199 /// \returns SGPR allocation granularity for given subtarget \p STI.
200 unsigned getSGPRAllocGranule(const MCSubtargetInfo *STI);
201 
202 /// \returns SGPR encoding granularity for given subtarget \p STI.
203 unsigned getSGPREncodingGranule(const MCSubtargetInfo *STI);
204 
205 /// \returns Total number of SGPRs for given subtarget \p STI.
206 unsigned getTotalNumSGPRs(const MCSubtargetInfo *STI);
207 
208 /// \returns Addressable number of SGPRs for given subtarget \p STI.
209 unsigned getAddressableNumSGPRs(const MCSubtargetInfo *STI);
210 
211 /// \returns Minimum number of SGPRs that meets the given number of waves per
212 /// execution unit requirement for given subtarget \p STI.
213 unsigned getMinNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU);
214 
215 /// \returns Maximum number of SGPRs that meets the given number of waves per
216 /// execution unit requirement for given subtarget \p STI.
217 unsigned getMaxNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU,
218                         bool Addressable);
219 
220 /// \returns Number of extra SGPRs implicitly required by given subtarget \p
221 /// STI when the given special registers are used.
222 unsigned getNumExtraSGPRs(const MCSubtargetInfo *STI, bool VCCUsed,
223                           bool FlatScrUsed, bool XNACKUsed);
224 
225 /// \returns Number of extra SGPRs implicitly required by given subtarget \p
226 /// STI when the given special registers are used. XNACK is inferred from
227 /// \p STI.
228 unsigned getNumExtraSGPRs(const MCSubtargetInfo *STI, bool VCCUsed,
229                           bool FlatScrUsed);
230 
231 /// \returns Number of SGPR blocks needed for given subtarget \p STI when
232 /// \p NumSGPRs are used. \p NumSGPRs should already include any special
233 /// register counts.
234 unsigned getNumSGPRBlocks(const MCSubtargetInfo *STI, unsigned NumSGPRs);
235 
236 /// \returns VGPR allocation granularity for given subtarget \p STI.
237 ///
238 /// For subtargets which support it, \p EnableWavefrontSize32 should match
239 /// the ENABLE_WAVEFRONT_SIZE32 kernel descriptor field.
240 unsigned getVGPRAllocGranule(const MCSubtargetInfo *STI,
241                              Optional<bool> EnableWavefrontSize32 = None);
242 
243 /// \returns VGPR encoding granularity for given subtarget \p STI.
244 ///
245 /// For subtargets which support it, \p EnableWavefrontSize32 should match
246 /// the ENABLE_WAVEFRONT_SIZE32 kernel descriptor field.
247 unsigned getVGPREncodingGranule(const MCSubtargetInfo *STI,
248                                 Optional<bool> EnableWavefrontSize32 = None);
249 
250 /// \returns Total number of VGPRs for given subtarget \p STI.
251 unsigned getTotalNumVGPRs(const MCSubtargetInfo *STI);
252 
253 /// \returns Addressable number of VGPRs for given subtarget \p STI.
254 unsigned getAddressableNumVGPRs(const MCSubtargetInfo *STI);
255 
256 /// \returns Minimum number of VGPRs that meets given number of waves per
257 /// execution unit requirement for given subtarget \p STI.
258 unsigned getMinNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU);
259 
260 /// \returns Maximum number of VGPRs that meets given number of waves per
261 /// execution unit requirement for given subtarget \p STI.
262 unsigned getMaxNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU);
263 
264 /// \returns Number of VGPR blocks needed for given subtarget \p STI when
265 /// \p NumVGPRs are used.
266 ///
267 /// For subtargets which support it, \p EnableWavefrontSize32 should match the
268 /// ENABLE_WAVEFRONT_SIZE32 kernel descriptor field.
269 unsigned getNumVGPRBlocks(const MCSubtargetInfo *STI, unsigned NumSGPRs,
270                           Optional<bool> EnableWavefrontSize32 = None);
271 
272 } // end namespace IsaInfo
273 
274 LLVM_READONLY
275 int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx);
276 
277 LLVM_READONLY
278 int getSOPPWithRelaxation(uint16_t Opcode);
279 
280 struct MIMGBaseOpcodeInfo {
281   MIMGBaseOpcode BaseOpcode;
282   bool Store;
283   bool Atomic;
284   bool AtomicX2;
285   bool Sampler;
286   bool Gather4;
287 
288   uint8_t NumExtraArgs;
289   bool Gradients;
290   bool G16;
291   bool Coordinates;
292   bool LodOrClampOrMip;
293   bool HasD16;
294   bool MSAA;
295 };
296 
297 LLVM_READONLY
298 const MIMGBaseOpcodeInfo *getMIMGBaseOpcodeInfo(unsigned BaseOpcode);
299 
300 struct MIMGDimInfo {
301   MIMGDim Dim;
302   uint8_t NumCoords;
303   uint8_t NumGradients;
304   bool MSAA;
305   bool DA;
306   uint8_t Encoding;
307   const char *AsmSuffix;
308 };
309 
310 LLVM_READONLY
311 const MIMGDimInfo *getMIMGDimInfo(unsigned DimEnum);
312 
313 LLVM_READONLY
314 const MIMGDimInfo *getMIMGDimInfoByEncoding(uint8_t DimEnc);
315 
316 LLVM_READONLY
317 const MIMGDimInfo *getMIMGDimInfoByAsmSuffix(StringRef AsmSuffix);
318 
319 struct MIMGLZMappingInfo {
320   MIMGBaseOpcode L;
321   MIMGBaseOpcode LZ;
322 };
323 
324 struct MIMGMIPMappingInfo {
325   MIMGBaseOpcode MIP;
326   MIMGBaseOpcode NONMIP;
327 };
328 
329 struct MIMGG16MappingInfo {
330   MIMGBaseOpcode G;
331   MIMGBaseOpcode G16;
332 };
333 
334 LLVM_READONLY
335 const MIMGLZMappingInfo *getMIMGLZMappingInfo(unsigned L);
336 
337 LLVM_READONLY
338 const MIMGMIPMappingInfo *getMIMGMIPMappingInfo(unsigned MIP);
339 
340 LLVM_READONLY
341 const MIMGG16MappingInfo *getMIMGG16MappingInfo(unsigned G);
342 
343 LLVM_READONLY
344 int getMIMGOpcode(unsigned BaseOpcode, unsigned MIMGEncoding,
345                   unsigned VDataDwords, unsigned VAddrDwords);
346 
347 LLVM_READONLY
348 int getMaskedMIMGOp(unsigned Opc, unsigned NewChannels);
349 
350 struct MIMGInfo {
351   uint16_t Opcode;
352   uint16_t BaseOpcode;
353   uint8_t MIMGEncoding;
354   uint8_t VDataDwords;
355   uint8_t VAddrDwords;
356 };
357 
358 LLVM_READONLY
359 const MIMGInfo *getMIMGInfo(unsigned Opc);
360 
361 LLVM_READONLY
362 int getMTBUFBaseOpcode(unsigned Opc);
363 
364 LLVM_READONLY
365 int getMTBUFOpcode(unsigned BaseOpc, unsigned Elements);
366 
367 LLVM_READONLY
368 int getMTBUFElements(unsigned Opc);
369 
370 LLVM_READONLY
371 bool getMTBUFHasVAddr(unsigned Opc);
372 
373 LLVM_READONLY
374 bool getMTBUFHasSrsrc(unsigned Opc);
375 
376 LLVM_READONLY
377 bool getMTBUFHasSoffset(unsigned Opc);
378 
379 LLVM_READONLY
380 int getMUBUFBaseOpcode(unsigned Opc);
381 
382 LLVM_READONLY
383 int getMUBUFOpcode(unsigned BaseOpc, unsigned Elements);
384 
385 LLVM_READONLY
386 int getMUBUFElements(unsigned Opc);
387 
388 LLVM_READONLY
389 bool getMUBUFHasVAddr(unsigned Opc);
390 
391 LLVM_READONLY
392 bool getMUBUFHasSrsrc(unsigned Opc);
393 
394 LLVM_READONLY
395 bool getMUBUFHasSoffset(unsigned Opc);
396 
397 LLVM_READONLY
398 bool getSMEMIsBuffer(unsigned Opc);
399 
400 LLVM_READONLY
401 bool getVOP1IsSingle(unsigned Opc);
402 
403 LLVM_READONLY
404 bool getVOP2IsSingle(unsigned Opc);
405 
406 LLVM_READONLY
407 bool getVOP3IsSingle(unsigned Opc);
408 
409 LLVM_READONLY
410 const GcnBufferFormatInfo *getGcnBufferFormatInfo(uint8_t BitsPerComp,
411                                                   uint8_t NumComponents,
412                                                   uint8_t NumFormat,
413                                                   const MCSubtargetInfo &STI);
414 LLVM_READONLY
415 const GcnBufferFormatInfo *getGcnBufferFormatInfo(uint8_t Format,
416                                                   const MCSubtargetInfo &STI);
417 
418 LLVM_READONLY
419 int getMCOpcode(uint16_t Opcode, unsigned Gen);
420 
421 void initDefaultAMDKernelCodeT(amd_kernel_code_t &Header,
422                                const MCSubtargetInfo *STI);
423 
424 amdhsa::kernel_descriptor_t getDefaultAmdhsaKernelDescriptor(
425     const MCSubtargetInfo *STI);
426 
427 bool isGroupSegment(const GlobalValue *GV);
428 bool isGlobalSegment(const GlobalValue *GV);
429 bool isReadOnlySegment(const GlobalValue *GV);
430 
431 /// \returns True if constants should be emitted to .text section for given
432 /// target triple \p TT, false otherwise.
433 bool shouldEmitConstantsToTextSection(const Triple &TT);
434 
435 /// \returns Integer value requested using \p F's \p Name attribute.
436 ///
437 /// \returns \p Default if attribute is not present.
438 ///
439 /// \returns \p Default and emits error if requested value cannot be converted
440 /// to integer.
441 int getIntegerAttribute(const Function &F, StringRef Name, int Default);
442 
443 /// \returns A pair of integer values requested using \p F's \p Name attribute
444 /// in "first[,second]" format ("second" is optional unless \p OnlyFirstRequired
445 /// is false).
446 ///
447 /// \returns \p Default if attribute is not present.
448 ///
449 /// \returns \p Default and emits error if one of the requested values cannot be
450 /// converted to integer, or \p OnlyFirstRequired is false and "second" value is
451 /// not present.
452 std::pair<int, int> getIntegerPairAttribute(const Function &F,
453                                             StringRef Name,
454                                             std::pair<int, int> Default,
455                                             bool OnlyFirstRequired = false);
456 
457 /// Represents the counter values to wait for in an s_waitcnt instruction.
458 ///
459 /// Large values (including the maximum possible integer) can be used to
460 /// represent "don't care" waits.
461 struct Waitcnt {
462   unsigned VmCnt = ~0u;
463   unsigned ExpCnt = ~0u;
464   unsigned LgkmCnt = ~0u;
465   unsigned VsCnt = ~0u;
466 
467   Waitcnt() {}
468   Waitcnt(unsigned VmCnt, unsigned ExpCnt, unsigned LgkmCnt, unsigned VsCnt)
469       : VmCnt(VmCnt), ExpCnt(ExpCnt), LgkmCnt(LgkmCnt), VsCnt(VsCnt) {}
470 
471   static Waitcnt allZero(bool HasVscnt) {
472     return Waitcnt(0, 0, 0, HasVscnt ? 0 : ~0u);
473   }
474   static Waitcnt allZeroExceptVsCnt() { return Waitcnt(0, 0, 0, ~0u); }
475 
476   bool hasWait() const {
477     return VmCnt != ~0u || ExpCnt != ~0u || LgkmCnt != ~0u || VsCnt != ~0u;
478   }
479 
480   bool dominates(const Waitcnt &Other) const {
481     return VmCnt <= Other.VmCnt && ExpCnt <= Other.ExpCnt &&
482            LgkmCnt <= Other.LgkmCnt && VsCnt <= Other.VsCnt;
483   }
484 
485   Waitcnt combined(const Waitcnt &Other) const {
486     return Waitcnt(std::min(VmCnt, Other.VmCnt), std::min(ExpCnt, Other.ExpCnt),
487                    std::min(LgkmCnt, Other.LgkmCnt),
488                    std::min(VsCnt, Other.VsCnt));
489   }
490 };
491 
492 /// \returns Vmcnt bit mask for given isa \p Version.
493 unsigned getVmcntBitMask(const IsaVersion &Version);
494 
495 /// \returns Expcnt bit mask for given isa \p Version.
496 unsigned getExpcntBitMask(const IsaVersion &Version);
497 
498 /// \returns Lgkmcnt bit mask for given isa \p Version.
499 unsigned getLgkmcntBitMask(const IsaVersion &Version);
500 
501 /// \returns Waitcnt bit mask for given isa \p Version.
502 unsigned getWaitcntBitMask(const IsaVersion &Version);
503 
504 /// \returns Decoded Vmcnt from given \p Waitcnt for given isa \p Version.
505 unsigned decodeVmcnt(const IsaVersion &Version, unsigned Waitcnt);
506 
507 /// \returns Decoded Expcnt from given \p Waitcnt for given isa \p Version.
508 unsigned decodeExpcnt(const IsaVersion &Version, unsigned Waitcnt);
509 
510 /// \returns Decoded Lgkmcnt from given \p Waitcnt for given isa \p Version.
511 unsigned decodeLgkmcnt(const IsaVersion &Version, unsigned Waitcnt);
512 
513 /// Decodes Vmcnt, Expcnt and Lgkmcnt from given \p Waitcnt for given isa
514 /// \p Version, and writes decoded values into \p Vmcnt, \p Expcnt and
515 /// \p Lgkmcnt respectively.
516 ///
517 /// \details \p Vmcnt, \p Expcnt and \p Lgkmcnt are decoded as follows:
518 ///     \p Vmcnt = \p Waitcnt[3:0]                      (pre-gfx9 only)
519 ///     \p Vmcnt = \p Waitcnt[3:0] | \p Waitcnt[15:14]  (gfx9+ only)
520 ///     \p Expcnt = \p Waitcnt[6:4]
521 ///     \p Lgkmcnt = \p Waitcnt[11:8]                   (pre-gfx10 only)
522 ///     \p Lgkmcnt = \p Waitcnt[13:8]                   (gfx10+ only)
523 void decodeWaitcnt(const IsaVersion &Version, unsigned Waitcnt,
524                    unsigned &Vmcnt, unsigned &Expcnt, unsigned &Lgkmcnt);
525 
526 Waitcnt decodeWaitcnt(const IsaVersion &Version, unsigned Encoded);
527 
528 /// \returns \p Waitcnt with encoded \p Vmcnt for given isa \p Version.
529 unsigned encodeVmcnt(const IsaVersion &Version, unsigned Waitcnt,
530                      unsigned Vmcnt);
531 
532 /// \returns \p Waitcnt with encoded \p Expcnt for given isa \p Version.
533 unsigned encodeExpcnt(const IsaVersion &Version, unsigned Waitcnt,
534                       unsigned Expcnt);
535 
536 /// \returns \p Waitcnt with encoded \p Lgkmcnt for given isa \p Version.
537 unsigned encodeLgkmcnt(const IsaVersion &Version, unsigned Waitcnt,
538                        unsigned Lgkmcnt);
539 
540 /// Encodes \p Vmcnt, \p Expcnt and \p Lgkmcnt into Waitcnt for given isa
541 /// \p Version.
542 ///
543 /// \details \p Vmcnt, \p Expcnt and \p Lgkmcnt are encoded as follows:
544 ///     Waitcnt[3:0]   = \p Vmcnt       (pre-gfx9 only)
545 ///     Waitcnt[3:0]   = \p Vmcnt[3:0]  (gfx9+ only)
546 ///     Waitcnt[6:4]   = \p Expcnt
547 ///     Waitcnt[11:8]  = \p Lgkmcnt     (pre-gfx10 only)
548 ///     Waitcnt[13:8]  = \p Lgkmcnt     (gfx10+ only)
549 ///     Waitcnt[15:14] = \p Vmcnt[5:4]  (gfx9+ only)
550 ///
551 /// \returns Waitcnt with encoded \p Vmcnt, \p Expcnt and \p Lgkmcnt for given
552 /// isa \p Version.
553 unsigned encodeWaitcnt(const IsaVersion &Version,
554                        unsigned Vmcnt, unsigned Expcnt, unsigned Lgkmcnt);
555 
556 unsigned encodeWaitcnt(const IsaVersion &Version, const Waitcnt &Decoded);
557 
558 namespace Hwreg {
559 
560 LLVM_READONLY
561 int64_t getHwregId(const StringRef Name);
562 
563 LLVM_READNONE
564 bool isValidHwreg(int64_t Id, const MCSubtargetInfo &STI);
565 
566 LLVM_READNONE
567 bool isValidHwreg(int64_t Id);
568 
569 LLVM_READNONE
570 bool isValidHwregOffset(int64_t Offset);
571 
572 LLVM_READNONE
573 bool isValidHwregWidth(int64_t Width);
574 
575 LLVM_READNONE
576 uint64_t encodeHwreg(uint64_t Id, uint64_t Offset, uint64_t Width);
577 
578 LLVM_READNONE
579 StringRef getHwreg(unsigned Id, const MCSubtargetInfo &STI);
580 
581 void decodeHwreg(unsigned Val, unsigned &Id, unsigned &Offset, unsigned &Width);
582 
583 } // namespace Hwreg
584 
585 namespace Exp {
586 
587 bool getTgtName(unsigned Id, StringRef &Name, int &Index);
588 
589 LLVM_READONLY
590 unsigned getTgtId(const StringRef Name);
591 
592 LLVM_READNONE
593 bool isSupportedTgtId(unsigned Id, const MCSubtargetInfo &STI);
594 
595 } // namespace Exp
596 
597 namespace MTBUFFormat {
598 
599 LLVM_READNONE
600 int64_t encodeDfmtNfmt(unsigned Dfmt, unsigned Nfmt);
601 
602 void decodeDfmtNfmt(unsigned Format, unsigned &Dfmt, unsigned &Nfmt);
603 
604 int64_t getDfmt(const StringRef Name);
605 
606 StringRef getDfmtName(unsigned Id);
607 
608 int64_t getNfmt(const StringRef Name, const MCSubtargetInfo &STI);
609 
610 StringRef getNfmtName(unsigned Id, const MCSubtargetInfo &STI);
611 
612 bool isValidDfmtNfmt(unsigned Val, const MCSubtargetInfo &STI);
613 
614 bool isValidNfmt(unsigned Val, const MCSubtargetInfo &STI);
615 
616 int64_t getUnifiedFormat(const StringRef Name);
617 
618 StringRef getUnifiedFormatName(unsigned Id);
619 
620 bool isValidUnifiedFormat(unsigned Val);
621 
622 int64_t convertDfmtNfmt2Ufmt(unsigned Dfmt, unsigned Nfmt);
623 
624 bool isValidFormatEncoding(unsigned Val, const MCSubtargetInfo &STI);
625 
626 unsigned getDefaultFormatEncoding(const MCSubtargetInfo &STI);
627 
628 } // namespace MTBUFFormat
629 
630 namespace SendMsg {
631 
632 LLVM_READONLY
633 int64_t getMsgId(const StringRef Name);
634 
635 LLVM_READONLY
636 int64_t getMsgOpId(int64_t MsgId, const StringRef Name);
637 
638 LLVM_READNONE
639 StringRef getMsgName(int64_t MsgId);
640 
641 LLVM_READNONE
642 StringRef getMsgOpName(int64_t MsgId, int64_t OpId);
643 
644 LLVM_READNONE
645 bool isValidMsgId(int64_t MsgId, const MCSubtargetInfo &STI, bool Strict = true);
646 
647 LLVM_READNONE
648 bool isValidMsgOp(int64_t MsgId, int64_t OpId, const MCSubtargetInfo &STI,
649                   bool Strict = true);
650 
651 LLVM_READNONE
652 bool isValidMsgStream(int64_t MsgId, int64_t OpId, int64_t StreamId,
653                       const MCSubtargetInfo &STI, bool Strict = true);
654 
655 LLVM_READNONE
656 bool msgRequiresOp(int64_t MsgId);
657 
658 LLVM_READNONE
659 bool msgSupportsStream(int64_t MsgId, int64_t OpId);
660 
661 void decodeMsg(unsigned Val,
662                uint16_t &MsgId,
663                uint16_t &OpId,
664                uint16_t &StreamId);
665 
666 LLVM_READNONE
667 uint64_t encodeMsg(uint64_t MsgId,
668                    uint64_t OpId,
669                    uint64_t StreamId);
670 
671 } // namespace SendMsg
672 
673 
674 unsigned getInitialPSInputAddr(const Function &F);
675 
676 LLVM_READNONE
677 bool isShader(CallingConv::ID CC);
678 
679 LLVM_READNONE
680 bool isGraphics(CallingConv::ID CC);
681 
682 LLVM_READNONE
683 bool isCompute(CallingConv::ID CC);
684 
685 LLVM_READNONE
686 bool isEntryFunctionCC(CallingConv::ID CC);
687 
688 // These functions are considered entrypoints into the current module, i.e. they
689 // are allowed to be called from outside the current module. This is different
690 // from isEntryFunctionCC, which is only true for functions that are entered by
691 // the hardware. Module entry points include all entry functions but also
692 // include functions that can be called from other functions inside or outside
693 // the current module. Module entry functions are allowed to allocate LDS.
694 LLVM_READNONE
695 bool isModuleEntryFunctionCC(CallingConv::ID CC);
696 
697 // FIXME: Remove this when calling conventions cleaned up
698 LLVM_READNONE
699 inline bool isKernel(CallingConv::ID CC) {
700   switch (CC) {
701   case CallingConv::AMDGPU_KERNEL:
702   case CallingConv::SPIR_KERNEL:
703     return true;
704   default:
705     return false;
706   }
707 }
708 
709 bool hasXNACK(const MCSubtargetInfo &STI);
710 bool hasSRAMECC(const MCSubtargetInfo &STI);
711 bool hasMIMG_R128(const MCSubtargetInfo &STI);
712 bool hasGFX10A16(const MCSubtargetInfo &STI);
713 bool hasG16(const MCSubtargetInfo &STI);
714 bool hasPackedD16(const MCSubtargetInfo &STI);
715 
716 bool isSI(const MCSubtargetInfo &STI);
717 bool isCI(const MCSubtargetInfo &STI);
718 bool isVI(const MCSubtargetInfo &STI);
719 bool isGFX9(const MCSubtargetInfo &STI);
720 bool isGFX9Plus(const MCSubtargetInfo &STI);
721 bool isGFX10(const MCSubtargetInfo &STI);
722 bool isGFX10Plus(const MCSubtargetInfo &STI);
723 bool isGCN3Encoding(const MCSubtargetInfo &STI);
724 bool isGFX10_BEncoding(const MCSubtargetInfo &STI);
725 bool hasGFX10_3Insts(const MCSubtargetInfo &STI);
726 bool isGFX90A(const MCSubtargetInfo &STI);
727 
728 /// Is Reg - scalar register
729 bool isSGPR(unsigned Reg, const MCRegisterInfo* TRI);
730 
731 /// Is there any intersection between registers
732 bool isRegIntersect(unsigned Reg0, unsigned Reg1, const MCRegisterInfo* TRI);
733 
734 /// If \p Reg is a pseudo reg, return the correct hardware register given
735 /// \p STI otherwise return \p Reg.
736 unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI);
737 
738 /// Convert hardware register \p Reg to a pseudo register
739 LLVM_READNONE
740 unsigned mc2PseudoReg(unsigned Reg);
741 
742 /// Can this operand also contain immediate values?
743 bool isSISrcOperand(const MCInstrDesc &Desc, unsigned OpNo);
744 
745 /// Is this floating-point operand?
746 bool isSISrcFPOperand(const MCInstrDesc &Desc, unsigned OpNo);
747 
748 /// Does this opearnd support only inlinable literals?
749 bool isSISrcInlinableOperand(const MCInstrDesc &Desc, unsigned OpNo);
750 
751 /// Get the size in bits of a register from the register class \p RC.
752 unsigned getRegBitWidth(unsigned RCID);
753 
754 /// Get the size in bits of a register from the register class \p RC.
755 unsigned getRegBitWidth(const MCRegisterClass &RC);
756 
757 /// Get size of register operand
758 unsigned getRegOperandSize(const MCRegisterInfo *MRI, const MCInstrDesc &Desc,
759                            unsigned OpNo);
760 
761 LLVM_READNONE
762 inline unsigned getOperandSize(const MCOperandInfo &OpInfo) {
763   switch (OpInfo.OperandType) {
764   case AMDGPU::OPERAND_REG_IMM_INT32:
765   case AMDGPU::OPERAND_REG_IMM_FP32:
766   case AMDGPU::OPERAND_REG_INLINE_C_INT32:
767   case AMDGPU::OPERAND_REG_INLINE_C_FP32:
768   case AMDGPU::OPERAND_REG_INLINE_AC_INT32:
769   case AMDGPU::OPERAND_REG_INLINE_AC_FP32:
770   case AMDGPU::OPERAND_REG_IMM_V2INT32:
771   case AMDGPU::OPERAND_REG_IMM_V2FP32:
772   case AMDGPU::OPERAND_REG_INLINE_C_V2INT32:
773   case AMDGPU::OPERAND_REG_INLINE_C_V2FP32:
774     return 4;
775 
776   case AMDGPU::OPERAND_REG_IMM_INT64:
777   case AMDGPU::OPERAND_REG_IMM_FP64:
778   case AMDGPU::OPERAND_REG_INLINE_C_INT64:
779   case AMDGPU::OPERAND_REG_INLINE_C_FP64:
780   case AMDGPU::OPERAND_REG_INLINE_AC_FP64:
781     return 8;
782 
783   case AMDGPU::OPERAND_REG_IMM_INT16:
784   case AMDGPU::OPERAND_REG_IMM_FP16:
785   case AMDGPU::OPERAND_REG_INLINE_C_INT16:
786   case AMDGPU::OPERAND_REG_INLINE_C_FP16:
787   case AMDGPU::OPERAND_REG_INLINE_C_V2INT16:
788   case AMDGPU::OPERAND_REG_INLINE_C_V2FP16:
789   case AMDGPU::OPERAND_REG_INLINE_AC_INT16:
790   case AMDGPU::OPERAND_REG_INLINE_AC_FP16:
791   case AMDGPU::OPERAND_REG_INLINE_AC_V2INT16:
792   case AMDGPU::OPERAND_REG_INLINE_AC_V2FP16:
793   case AMDGPU::OPERAND_REG_IMM_V2INT16:
794   case AMDGPU::OPERAND_REG_IMM_V2FP16:
795     return 2;
796 
797   default:
798     llvm_unreachable("unhandled operand type");
799   }
800 }
801 
802 LLVM_READNONE
803 inline unsigned getOperandSize(const MCInstrDesc &Desc, unsigned OpNo) {
804   return getOperandSize(Desc.OpInfo[OpNo]);
805 }
806 
807 /// Is this literal inlinable, and not one of the values intended for floating
808 /// point values.
809 LLVM_READNONE
810 inline bool isInlinableIntLiteral(int64_t Literal) {
811   return Literal >= -16 && Literal <= 64;
812 }
813 
814 /// Is this literal inlinable
815 LLVM_READNONE
816 bool isInlinableLiteral64(int64_t Literal, bool HasInv2Pi);
817 
818 LLVM_READNONE
819 bool isInlinableLiteral32(int32_t Literal, bool HasInv2Pi);
820 
821 LLVM_READNONE
822 bool isInlinableLiteral16(int16_t Literal, bool HasInv2Pi);
823 
824 LLVM_READNONE
825 bool isInlinableLiteralV216(int32_t Literal, bool HasInv2Pi);
826 
827 LLVM_READNONE
828 bool isInlinableIntLiteralV216(int32_t Literal);
829 
830 LLVM_READNONE
831 bool isFoldableLiteralV216(int32_t Literal, bool HasInv2Pi);
832 
833 bool isArgPassedInSGPR(const Argument *Arg);
834 
835 LLVM_READONLY
836 bool isLegalSMRDEncodedUnsignedOffset(const MCSubtargetInfo &ST,
837                                       int64_t EncodedOffset);
838 
839 LLVM_READONLY
840 bool isLegalSMRDEncodedSignedOffset(const MCSubtargetInfo &ST,
841                                     int64_t EncodedOffset,
842                                     bool IsBuffer);
843 
844 /// Convert \p ByteOffset to dwords if the subtarget uses dword SMRD immediate
845 /// offsets.
846 uint64_t convertSMRDOffsetUnits(const MCSubtargetInfo &ST, uint64_t ByteOffset);
847 
848 /// \returns The encoding that will be used for \p ByteOffset in the
849 /// SMRD offset field, or None if it won't fit. On GFX9 and GFX10
850 /// S_LOAD instructions have a signed offset, on other subtargets it is
851 /// unsigned. S_BUFFER has an unsigned offset for all subtargets.
852 Optional<int64_t> getSMRDEncodedOffset(const MCSubtargetInfo &ST,
853                                        int64_t ByteOffset, bool IsBuffer);
854 
855 /// \return The encoding that can be used for a 32-bit literal offset in an SMRD
856 /// instruction. This is only useful on CI.s
857 Optional<int64_t> getSMRDEncodedLiteralOffset32(const MCSubtargetInfo &ST,
858                                                 int64_t ByteOffset);
859 
860 /// For FLAT segment the offset must be positive;
861 /// MSB is ignored and forced to zero.
862 ///
863 /// \return The number of bits available for the offset field in flat
864 /// instructions.
865 unsigned getNumFlatOffsetBits(const MCSubtargetInfo &ST, bool Signed);
866 
867 /// \returns true if this offset is small enough to fit in the SMRD
868 /// offset field.  \p ByteOffset should be the offset in bytes and
869 /// not the encoded offset.
870 bool isLegalSMRDImmOffset(const MCSubtargetInfo &ST, int64_t ByteOffset);
871 
872 bool splitMUBUFOffset(uint32_t Imm, uint32_t &SOffset, uint32_t &ImmOffset,
873                       const GCNSubtarget *Subtarget,
874                       Align Alignment = Align(4));
875 
876 LLVM_READNONE
877 inline bool isLegal64BitDPPControl(unsigned DC) {
878   return DC >= DPP::ROW_NEWBCAST_FIRST && DC <= DPP::ROW_NEWBCAST_LAST;
879 }
880 
881 /// \returns true if the intrinsic is divergent
882 bool isIntrinsicSourceOfDivergence(unsigned IntrID);
883 
884 // Track defaults for fields in the MODE registser.
885 struct SIModeRegisterDefaults {
886   /// Floating point opcodes that support exception flag gathering quiet and
887   /// propagate signaling NaN inputs per IEEE 754-2008. Min_dx10 and max_dx10
888   /// become IEEE 754- 2008 compliant due to signaling NaN propagation and
889   /// quieting.
890   bool IEEE : 1;
891 
892   /// Used by the vector ALU to force DX10-style treatment of NaNs: when set,
893   /// clamp NaN to zero; otherwise, pass NaN through.
894   bool DX10Clamp : 1;
895 
896   /// If this is set, neither input or output denormals are flushed for most f32
897   /// instructions.
898   bool FP32InputDenormals : 1;
899   bool FP32OutputDenormals : 1;
900 
901   /// If this is set, neither input or output denormals are flushed for both f64
902   /// and f16/v2f16 instructions.
903   bool FP64FP16InputDenormals : 1;
904   bool FP64FP16OutputDenormals : 1;
905 
906   SIModeRegisterDefaults() :
907     IEEE(true),
908     DX10Clamp(true),
909     FP32InputDenormals(true),
910     FP32OutputDenormals(true),
911     FP64FP16InputDenormals(true),
912     FP64FP16OutputDenormals(true) {}
913 
914   SIModeRegisterDefaults(const Function &F);
915 
916   static SIModeRegisterDefaults getDefaultForCallingConv(CallingConv::ID CC) {
917     SIModeRegisterDefaults Mode;
918     Mode.IEEE = !AMDGPU::isShader(CC);
919     return Mode;
920   }
921 
922   bool operator ==(const SIModeRegisterDefaults Other) const {
923     return IEEE == Other.IEEE && DX10Clamp == Other.DX10Clamp &&
924            FP32InputDenormals == Other.FP32InputDenormals &&
925            FP32OutputDenormals == Other.FP32OutputDenormals &&
926            FP64FP16InputDenormals == Other.FP64FP16InputDenormals &&
927            FP64FP16OutputDenormals == Other.FP64FP16OutputDenormals;
928   }
929 
930   bool allFP32Denormals() const {
931     return FP32InputDenormals && FP32OutputDenormals;
932   }
933 
934   bool allFP64FP16Denormals() const {
935     return FP64FP16InputDenormals && FP64FP16OutputDenormals;
936   }
937 
938   /// Get the encoding value for the FP_DENORM bits of the mode register for the
939   /// FP32 denormal mode.
940   uint32_t fpDenormModeSPValue() const {
941     if (FP32InputDenormals && FP32OutputDenormals)
942       return FP_DENORM_FLUSH_NONE;
943     if (FP32InputDenormals)
944       return FP_DENORM_FLUSH_OUT;
945     if (FP32OutputDenormals)
946       return FP_DENORM_FLUSH_IN;
947     return FP_DENORM_FLUSH_IN_FLUSH_OUT;
948   }
949 
950   /// Get the encoding value for the FP_DENORM bits of the mode register for the
951   /// FP64/FP16 denormal mode.
952   uint32_t fpDenormModeDPValue() const {
953     if (FP64FP16InputDenormals && FP64FP16OutputDenormals)
954       return FP_DENORM_FLUSH_NONE;
955     if (FP64FP16InputDenormals)
956       return FP_DENORM_FLUSH_OUT;
957     if (FP64FP16OutputDenormals)
958       return FP_DENORM_FLUSH_IN;
959     return FP_DENORM_FLUSH_IN_FLUSH_OUT;
960   }
961 
962   /// Returns true if a flag is compatible if it's enabled in the callee, but
963   /// disabled in the caller.
964   static bool oneWayCompatible(bool CallerMode, bool CalleeMode) {
965     return CallerMode == CalleeMode || (!CallerMode && CalleeMode);
966   }
967 
968   // FIXME: Inlining should be OK for dx10-clamp, since the caller's mode should
969   // be able to override.
970   bool isInlineCompatible(SIModeRegisterDefaults CalleeMode) const {
971     if (DX10Clamp != CalleeMode.DX10Clamp)
972       return false;
973     if (IEEE != CalleeMode.IEEE)
974       return false;
975 
976     // Allow inlining denormals enabled into denormals flushed functions.
977     return oneWayCompatible(FP64FP16InputDenormals, CalleeMode.FP64FP16InputDenormals) &&
978            oneWayCompatible(FP64FP16OutputDenormals, CalleeMode.FP64FP16OutputDenormals) &&
979            oneWayCompatible(FP32InputDenormals, CalleeMode.FP32InputDenormals) &&
980            oneWayCompatible(FP32OutputDenormals, CalleeMode.FP32OutputDenormals);
981   }
982 };
983 
984 } // end namespace AMDGPU
985 
986 raw_ostream &operator<<(raw_ostream &OS,
987                         const AMDGPU::IsaInfo::TargetIDSetting S);
988 
989 } // end namespace llvm
990 
991 #endif // LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
992