1 //===- AMDGPUBaseInfo.h - Top level definitions for AMDGPU ------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #ifndef LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
10 #define LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
11 
12 #include "AMDGPU.h"
13 #include "AMDKernelCodeT.h"
14 #include "SIDefines.h"
15 #include "llvm/ADT/StringRef.h"
16 #include "llvm/IR/CallingConv.h"
17 #include "llvm/MC/MCInstrDesc.h"
18 #include "llvm/Support/AMDHSAKernelDescriptor.h"
19 #include "llvm/Support/Compiler.h"
20 #include "llvm/Support/ErrorHandling.h"
21 #include "llvm/Support/TargetParser.h"
22 #include <cstdint>
23 #include <string>
24 #include <utility>
25 
26 namespace llvm {
27 
28 class Argument;
29 class AMDGPUSubtarget;
30 class FeatureBitset;
31 class Function;
32 class GCNSubtarget;
33 class GlobalValue;
34 class MCContext;
35 class MCRegisterClass;
36 class MCRegisterInfo;
37 class MCSection;
38 class MCSubtargetInfo;
39 class MachineMemOperand;
40 class Triple;
41 
42 namespace AMDGPU {
43 
44 struct GcnBufferFormatInfo {
45   unsigned Format;
46   unsigned BitsPerComp;
47   unsigned NumComponents;
48   unsigned NumFormat;
49   unsigned DataFormat;
50 };
51 
52 #define GET_MIMGBaseOpcode_DECL
53 #define GET_MIMGDim_DECL
54 #define GET_MIMGEncoding_DECL
55 #define GET_MIMGLZMapping_DECL
56 #define GET_MIMGMIPMapping_DECL
57 #include "AMDGPUGenSearchableTables.inc"
58 
59 namespace IsaInfo {
60 
61 enum {
62   // The closed Vulkan driver sets 96, which limits the wave count to 8 but
63   // doesn't spill SGPRs as much as when 80 is set.
64   FIXED_NUM_SGPRS_FOR_INIT_BUG = 96,
65   TRAP_NUM_SGPRS = 16
66 };
67 
68 /// Streams isa version string for given subtarget \p STI into \p Stream.
69 void streamIsaVersion(const MCSubtargetInfo *STI, raw_ostream &Stream);
70 
71 /// \returns True if given subtarget \p STI supports code object version 3,
72 /// false otherwise.
73 bool hasCodeObjectV3(const MCSubtargetInfo *STI);
74 
75 /// \returns Wavefront size for given subtarget \p STI.
76 unsigned getWavefrontSize(const MCSubtargetInfo *STI);
77 
78 /// \returns Local memory size in bytes for given subtarget \p STI.
79 unsigned getLocalMemorySize(const MCSubtargetInfo *STI);
80 
81 /// \returns Number of execution units per compute unit for given subtarget \p
82 /// STI.
83 unsigned getEUsPerCU(const MCSubtargetInfo *STI);
84 
85 /// \returns Maximum number of work groups per compute unit for given subtarget
86 /// \p STI and limited by given \p FlatWorkGroupSize.
87 unsigned getMaxWorkGroupsPerCU(const MCSubtargetInfo *STI,
88                                unsigned FlatWorkGroupSize);
89 
90 /// \returns Minimum number of waves per execution unit for given subtarget \p
91 /// STI.
92 unsigned getMinWavesPerEU(const MCSubtargetInfo *STI);
93 
94 /// \returns Maximum number of waves per execution unit for given subtarget \p
95 /// STI without any kind of limitation.
96 unsigned getMaxWavesPerEU(const MCSubtargetInfo *STI);
97 
98 /// \returns Number of waves per execution unit required to support the given \p
99 /// FlatWorkGroupSize.
100 unsigned getWavesPerEUForWorkGroup(const MCSubtargetInfo *STI,
101                                    unsigned FlatWorkGroupSize);
102 
103 /// \returns Minimum flat work group size for given subtarget \p STI.
104 unsigned getMinFlatWorkGroupSize(const MCSubtargetInfo *STI);
105 
106 /// \returns Maximum flat work group size for given subtarget \p STI.
107 unsigned getMaxFlatWorkGroupSize(const MCSubtargetInfo *STI);
108 
109 /// \returns Number of waves per work group for given subtarget \p STI and
110 /// \p FlatWorkGroupSize.
111 unsigned getWavesPerWorkGroup(const MCSubtargetInfo *STI,
112                               unsigned FlatWorkGroupSize);
113 
114 /// \returns SGPR allocation granularity for given subtarget \p STI.
115 unsigned getSGPRAllocGranule(const MCSubtargetInfo *STI);
116 
117 /// \returns SGPR encoding granularity for given subtarget \p STI.
118 unsigned getSGPREncodingGranule(const MCSubtargetInfo *STI);
119 
120 /// \returns Total number of SGPRs for given subtarget \p STI.
121 unsigned getTotalNumSGPRs(const MCSubtargetInfo *STI);
122 
123 /// \returns Addressable number of SGPRs for given subtarget \p STI.
124 unsigned getAddressableNumSGPRs(const MCSubtargetInfo *STI);
125 
126 /// \returns Minimum number of SGPRs that meets the given number of waves per
127 /// execution unit requirement for given subtarget \p STI.
128 unsigned getMinNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU);
129 
130 /// \returns Maximum number of SGPRs that meets the given number of waves per
131 /// execution unit requirement for given subtarget \p STI.
132 unsigned getMaxNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU,
133                         bool Addressable);
134 
135 /// \returns Number of extra SGPRs implicitly required by given subtarget \p
136 /// STI when the given special registers are used.
137 unsigned getNumExtraSGPRs(const MCSubtargetInfo *STI, bool VCCUsed,
138                           bool FlatScrUsed, bool XNACKUsed);
139 
140 /// \returns Number of extra SGPRs implicitly required by given subtarget \p
141 /// STI when the given special registers are used. XNACK is inferred from
142 /// \p STI.
143 unsigned getNumExtraSGPRs(const MCSubtargetInfo *STI, bool VCCUsed,
144                           bool FlatScrUsed);
145 
146 /// \returns Number of SGPR blocks needed for given subtarget \p STI when
147 /// \p NumSGPRs are used. \p NumSGPRs should already include any special
148 /// register counts.
149 unsigned getNumSGPRBlocks(const MCSubtargetInfo *STI, unsigned NumSGPRs);
150 
151 /// \returns VGPR allocation granularity for given subtarget \p STI.
152 ///
153 /// For subtargets which support it, \p EnableWavefrontSize32 should match
154 /// the ENABLE_WAVEFRONT_SIZE32 kernel descriptor field.
155 unsigned getVGPRAllocGranule(const MCSubtargetInfo *STI,
156                              Optional<bool> EnableWavefrontSize32 = None);
157 
158 /// \returns VGPR encoding granularity for given subtarget \p STI.
159 ///
160 /// For subtargets which support it, \p EnableWavefrontSize32 should match
161 /// the ENABLE_WAVEFRONT_SIZE32 kernel descriptor field.
162 unsigned getVGPREncodingGranule(const MCSubtargetInfo *STI,
163                                 Optional<bool> EnableWavefrontSize32 = None);
164 
165 /// \returns Total number of VGPRs for given subtarget \p STI.
166 unsigned getTotalNumVGPRs(const MCSubtargetInfo *STI);
167 
168 /// \returns Addressable number of VGPRs for given subtarget \p STI.
169 unsigned getAddressableNumVGPRs(const MCSubtargetInfo *STI);
170 
171 /// \returns Minimum number of VGPRs that meets given number of waves per
172 /// execution unit requirement for given subtarget \p STI.
173 unsigned getMinNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU);
174 
175 /// \returns Maximum number of VGPRs that meets given number of waves per
176 /// execution unit requirement for given subtarget \p STI.
177 unsigned getMaxNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU);
178 
179 /// \returns Number of VGPR blocks needed for given subtarget \p STI when
180 /// \p NumVGPRs are used.
181 ///
182 /// For subtargets which support it, \p EnableWavefrontSize32 should match the
183 /// ENABLE_WAVEFRONT_SIZE32 kernel descriptor field.
184 unsigned getNumVGPRBlocks(const MCSubtargetInfo *STI, unsigned NumSGPRs,
185                           Optional<bool> EnableWavefrontSize32 = None);
186 
187 } // end namespace IsaInfo
188 
189 LLVM_READONLY
190 int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx);
191 
192 LLVM_READONLY
193 int getSOPPWithRelaxation(uint16_t Opcode);
194 
195 struct MIMGBaseOpcodeInfo {
196   MIMGBaseOpcode BaseOpcode;
197   bool Store;
198   bool Atomic;
199   bool AtomicX2;
200   bool Sampler;
201   bool Gather4;
202 
203   uint8_t NumExtraArgs;
204   bool Gradients;
205   bool Coordinates;
206   bool LodOrClampOrMip;
207   bool HasD16;
208 };
209 
210 LLVM_READONLY
211 const MIMGBaseOpcodeInfo *getMIMGBaseOpcodeInfo(unsigned BaseOpcode);
212 
213 struct MIMGDimInfo {
214   MIMGDim Dim;
215   uint8_t NumCoords;
216   uint8_t NumGradients;
217   bool DA;
218   uint8_t Encoding;
219   const char *AsmSuffix;
220 };
221 
222 LLVM_READONLY
223 const MIMGDimInfo *getMIMGDimInfo(unsigned DimEnum);
224 
225 LLVM_READONLY
226 const MIMGDimInfo *getMIMGDimInfoByEncoding(uint8_t DimEnc);
227 
228 LLVM_READONLY
229 const MIMGDimInfo *getMIMGDimInfoByAsmSuffix(StringRef AsmSuffix);
230 
231 struct MIMGLZMappingInfo {
232   MIMGBaseOpcode L;
233   MIMGBaseOpcode LZ;
234 };
235 
236 struct MIMGMIPMappingInfo {
237   MIMGBaseOpcode MIP;
238   MIMGBaseOpcode NONMIP;
239 };
240 
241 LLVM_READONLY
242 const MIMGLZMappingInfo *getMIMGLZMappingInfo(unsigned L);
243 
244 LLVM_READONLY
245 const MIMGMIPMappingInfo *getMIMGMIPMappingInfo(unsigned L);
246 
247 LLVM_READONLY
248 int getMIMGOpcode(unsigned BaseOpcode, unsigned MIMGEncoding,
249                   unsigned VDataDwords, unsigned VAddrDwords);
250 
251 LLVM_READONLY
252 int getMaskedMIMGOp(unsigned Opc, unsigned NewChannels);
253 
254 struct MIMGInfo {
255   uint16_t Opcode;
256   uint16_t BaseOpcode;
257   uint8_t MIMGEncoding;
258   uint8_t VDataDwords;
259   uint8_t VAddrDwords;
260 };
261 
262 LLVM_READONLY
263 const MIMGInfo *getMIMGInfo(unsigned Opc);
264 
265 LLVM_READONLY
266 int getMTBUFBaseOpcode(unsigned Opc);
267 
268 LLVM_READONLY
269 int getMTBUFOpcode(unsigned BaseOpc, unsigned Elements);
270 
271 LLVM_READONLY
272 int getMTBUFElements(unsigned Opc);
273 
274 LLVM_READONLY
275 bool getMTBUFHasVAddr(unsigned Opc);
276 
277 LLVM_READONLY
278 bool getMTBUFHasSrsrc(unsigned Opc);
279 
280 LLVM_READONLY
281 bool getMTBUFHasSoffset(unsigned Opc);
282 
283 LLVM_READONLY
284 int getMUBUFBaseOpcode(unsigned Opc);
285 
286 LLVM_READONLY
287 int getMUBUFOpcode(unsigned BaseOpc, unsigned Elements);
288 
289 LLVM_READONLY
290 int getMUBUFElements(unsigned Opc);
291 
292 LLVM_READONLY
293 bool getMUBUFHasVAddr(unsigned Opc);
294 
295 LLVM_READONLY
296 bool getMUBUFHasSrsrc(unsigned Opc);
297 
298 LLVM_READONLY
299 bool getMUBUFHasSoffset(unsigned Opc);
300 
301 LLVM_READONLY
302 const GcnBufferFormatInfo *getGcnBufferFormatInfo(uint8_t BitsPerComp,
303                                                   uint8_t NumComponents,
304                                                   uint8_t NumFormat,
305                                                   const MCSubtargetInfo &STI);
306 LLVM_READONLY
307 const GcnBufferFormatInfo *getGcnBufferFormatInfo(uint8_t Format,
308                                                   const MCSubtargetInfo &STI);
309 
310 LLVM_READONLY
311 int getMCOpcode(uint16_t Opcode, unsigned Gen);
312 
313 void initDefaultAMDKernelCodeT(amd_kernel_code_t &Header,
314                                const MCSubtargetInfo *STI);
315 
316 amdhsa::kernel_descriptor_t getDefaultAmdhsaKernelDescriptor(
317     const MCSubtargetInfo *STI);
318 
319 bool isGroupSegment(const GlobalValue *GV);
320 bool isGlobalSegment(const GlobalValue *GV);
321 bool isReadOnlySegment(const GlobalValue *GV);
322 
323 /// \returns True if constants should be emitted to .text section for given
324 /// target triple \p TT, false otherwise.
325 bool shouldEmitConstantsToTextSection(const Triple &TT);
326 
327 /// \returns Integer value requested using \p F's \p Name attribute.
328 ///
329 /// \returns \p Default if attribute is not present.
330 ///
331 /// \returns \p Default and emits error if requested value cannot be converted
332 /// to integer.
333 int getIntegerAttribute(const Function &F, StringRef Name, int Default);
334 
335 /// \returns A pair of integer values requested using \p F's \p Name attribute
336 /// in "first[,second]" format ("second" is optional unless \p OnlyFirstRequired
337 /// is false).
338 ///
339 /// \returns \p Default if attribute is not present.
340 ///
341 /// \returns \p Default and emits error if one of the requested values cannot be
342 /// converted to integer, or \p OnlyFirstRequired is false and "second" value is
343 /// not present.
344 std::pair<int, int> getIntegerPairAttribute(const Function &F,
345                                             StringRef Name,
346                                             std::pair<int, int> Default,
347                                             bool OnlyFirstRequired = false);
348 
349 /// Represents the counter values to wait for in an s_waitcnt instruction.
350 ///
351 /// Large values (including the maximum possible integer) can be used to
352 /// represent "don't care" waits.
353 struct Waitcnt {
354   unsigned VmCnt = ~0u;
355   unsigned ExpCnt = ~0u;
356   unsigned LgkmCnt = ~0u;
357   unsigned VsCnt = ~0u;
358 
359   Waitcnt() {}
360   Waitcnt(unsigned VmCnt, unsigned ExpCnt, unsigned LgkmCnt, unsigned VsCnt)
361       : VmCnt(VmCnt), ExpCnt(ExpCnt), LgkmCnt(LgkmCnt), VsCnt(VsCnt) {}
362 
363   static Waitcnt allZero(const IsaVersion &Version) {
364     return Waitcnt(0, 0, 0, Version.Major >= 10 ? 0 : ~0u);
365   }
366   static Waitcnt allZeroExceptVsCnt() { return Waitcnt(0, 0, 0, ~0u); }
367 
368   bool hasWait() const {
369     return VmCnt != ~0u || ExpCnt != ~0u || LgkmCnt != ~0u || VsCnt != ~0u;
370   }
371 
372   bool dominates(const Waitcnt &Other) const {
373     return VmCnt <= Other.VmCnt && ExpCnt <= Other.ExpCnt &&
374            LgkmCnt <= Other.LgkmCnt && VsCnt <= Other.VsCnt;
375   }
376 
377   Waitcnt combined(const Waitcnt &Other) const {
378     return Waitcnt(std::min(VmCnt, Other.VmCnt), std::min(ExpCnt, Other.ExpCnt),
379                    std::min(LgkmCnt, Other.LgkmCnt),
380                    std::min(VsCnt, Other.VsCnt));
381   }
382 };
383 
384 /// \returns Vmcnt bit mask for given isa \p Version.
385 unsigned getVmcntBitMask(const IsaVersion &Version);
386 
387 /// \returns Expcnt bit mask for given isa \p Version.
388 unsigned getExpcntBitMask(const IsaVersion &Version);
389 
390 /// \returns Lgkmcnt bit mask for given isa \p Version.
391 unsigned getLgkmcntBitMask(const IsaVersion &Version);
392 
393 /// \returns Waitcnt bit mask for given isa \p Version.
394 unsigned getWaitcntBitMask(const IsaVersion &Version);
395 
396 /// \returns Decoded Vmcnt from given \p Waitcnt for given isa \p Version.
397 unsigned decodeVmcnt(const IsaVersion &Version, unsigned Waitcnt);
398 
399 /// \returns Decoded Expcnt from given \p Waitcnt for given isa \p Version.
400 unsigned decodeExpcnt(const IsaVersion &Version, unsigned Waitcnt);
401 
402 /// \returns Decoded Lgkmcnt from given \p Waitcnt for given isa \p Version.
403 unsigned decodeLgkmcnt(const IsaVersion &Version, unsigned Waitcnt);
404 
405 /// Decodes Vmcnt, Expcnt and Lgkmcnt from given \p Waitcnt for given isa
406 /// \p Version, and writes decoded values into \p Vmcnt, \p Expcnt and
407 /// \p Lgkmcnt respectively.
408 ///
409 /// \details \p Vmcnt, \p Expcnt and \p Lgkmcnt are decoded as follows:
410 ///     \p Vmcnt = \p Waitcnt[3:0]                      (pre-gfx9 only)
411 ///     \p Vmcnt = \p Waitcnt[3:0] | \p Waitcnt[15:14]  (gfx9+ only)
412 ///     \p Expcnt = \p Waitcnt[6:4]
413 ///     \p Lgkmcnt = \p Waitcnt[11:8]                   (pre-gfx10 only)
414 ///     \p Lgkmcnt = \p Waitcnt[13:8]                   (gfx10+ only)
415 void decodeWaitcnt(const IsaVersion &Version, unsigned Waitcnt,
416                    unsigned &Vmcnt, unsigned &Expcnt, unsigned &Lgkmcnt);
417 
418 Waitcnt decodeWaitcnt(const IsaVersion &Version, unsigned Encoded);
419 
420 /// \returns \p Waitcnt with encoded \p Vmcnt for given isa \p Version.
421 unsigned encodeVmcnt(const IsaVersion &Version, unsigned Waitcnt,
422                      unsigned Vmcnt);
423 
424 /// \returns \p Waitcnt with encoded \p Expcnt for given isa \p Version.
425 unsigned encodeExpcnt(const IsaVersion &Version, unsigned Waitcnt,
426                       unsigned Expcnt);
427 
428 /// \returns \p Waitcnt with encoded \p Lgkmcnt for given isa \p Version.
429 unsigned encodeLgkmcnt(const IsaVersion &Version, unsigned Waitcnt,
430                        unsigned Lgkmcnt);
431 
432 /// Encodes \p Vmcnt, \p Expcnt and \p Lgkmcnt into Waitcnt for given isa
433 /// \p Version.
434 ///
435 /// \details \p Vmcnt, \p Expcnt and \p Lgkmcnt are encoded as follows:
436 ///     Waitcnt[3:0]   = \p Vmcnt       (pre-gfx9 only)
437 ///     Waitcnt[3:0]   = \p Vmcnt[3:0]  (gfx9+ only)
438 ///     Waitcnt[6:4]   = \p Expcnt
439 ///     Waitcnt[11:8]  = \p Lgkmcnt     (pre-gfx10 only)
440 ///     Waitcnt[13:8]  = \p Lgkmcnt     (gfx10+ only)
441 ///     Waitcnt[15:14] = \p Vmcnt[5:4]  (gfx9+ only)
442 ///
443 /// \returns Waitcnt with encoded \p Vmcnt, \p Expcnt and \p Lgkmcnt for given
444 /// isa \p Version.
445 unsigned encodeWaitcnt(const IsaVersion &Version,
446                        unsigned Vmcnt, unsigned Expcnt, unsigned Lgkmcnt);
447 
448 unsigned encodeWaitcnt(const IsaVersion &Version, const Waitcnt &Decoded);
449 
450 namespace Hwreg {
451 
452 LLVM_READONLY
453 int64_t getHwregId(const StringRef Name);
454 
455 LLVM_READNONE
456 bool isValidHwreg(int64_t Id, const MCSubtargetInfo &STI);
457 
458 LLVM_READNONE
459 bool isValidHwreg(int64_t Id);
460 
461 LLVM_READNONE
462 bool isValidHwregOffset(int64_t Offset);
463 
464 LLVM_READNONE
465 bool isValidHwregWidth(int64_t Width);
466 
467 LLVM_READNONE
468 uint64_t encodeHwreg(uint64_t Id, uint64_t Offset, uint64_t Width);
469 
470 LLVM_READNONE
471 StringRef getHwreg(unsigned Id, const MCSubtargetInfo &STI);
472 
473 void decodeHwreg(unsigned Val, unsigned &Id, unsigned &Offset, unsigned &Width);
474 
475 } // namespace Hwreg
476 
477 namespace SendMsg {
478 
479 LLVM_READONLY
480 int64_t getMsgId(const StringRef Name);
481 
482 LLVM_READONLY
483 int64_t getMsgOpId(int64_t MsgId, const StringRef Name);
484 
485 LLVM_READNONE
486 StringRef getMsgName(int64_t MsgId);
487 
488 LLVM_READNONE
489 StringRef getMsgOpName(int64_t MsgId, int64_t OpId);
490 
491 LLVM_READNONE
492 bool isValidMsgId(int64_t MsgId, const MCSubtargetInfo &STI, bool Strict = true);
493 
494 LLVM_READNONE
495 bool isValidMsgOp(int64_t MsgId, int64_t OpId, bool Strict = true);
496 
497 LLVM_READNONE
498 bool isValidMsgStream(int64_t MsgId, int64_t OpId, int64_t StreamId, bool Strict = true);
499 
500 LLVM_READNONE
501 bool msgRequiresOp(int64_t MsgId);
502 
503 LLVM_READNONE
504 bool msgSupportsStream(int64_t MsgId, int64_t OpId);
505 
506 void decodeMsg(unsigned Val,
507                uint16_t &MsgId,
508                uint16_t &OpId,
509                uint16_t &StreamId);
510 
511 LLVM_READNONE
512 uint64_t encodeMsg(uint64_t MsgId,
513                    uint64_t OpId,
514                    uint64_t StreamId);
515 
516 } // namespace SendMsg
517 
518 
519 unsigned getInitialPSInputAddr(const Function &F);
520 
521 LLVM_READNONE
522 bool isShader(CallingConv::ID CC);
523 
524 LLVM_READNONE
525 bool isCompute(CallingConv::ID CC);
526 
527 LLVM_READNONE
528 bool isEntryFunctionCC(CallingConv::ID CC);
529 
530 // FIXME: Remove this when calling conventions cleaned up
531 LLVM_READNONE
532 inline bool isKernel(CallingConv::ID CC) {
533   switch (CC) {
534   case CallingConv::AMDGPU_KERNEL:
535   case CallingConv::SPIR_KERNEL:
536     return true;
537   default:
538     return false;
539   }
540 }
541 
542 bool hasXNACK(const MCSubtargetInfo &STI);
543 bool hasSRAMECC(const MCSubtargetInfo &STI);
544 bool hasMIMG_R128(const MCSubtargetInfo &STI);
545 bool hasGFX10A16(const MCSubtargetInfo &STI);
546 bool hasPackedD16(const MCSubtargetInfo &STI);
547 
548 bool isSI(const MCSubtargetInfo &STI);
549 bool isCI(const MCSubtargetInfo &STI);
550 bool isVI(const MCSubtargetInfo &STI);
551 bool isGFX9(const MCSubtargetInfo &STI);
552 bool isGFX10(const MCSubtargetInfo &STI);
553 
554 /// Is Reg - scalar register
555 bool isSGPR(unsigned Reg, const MCRegisterInfo* TRI);
556 
557 /// Is there any intersection between registers
558 bool isRegIntersect(unsigned Reg0, unsigned Reg1, const MCRegisterInfo* TRI);
559 
560 /// If \p Reg is a pseudo reg, return the correct hardware register given
561 /// \p STI otherwise return \p Reg.
562 unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI);
563 
564 /// Convert hardware register \p Reg to a pseudo register
565 LLVM_READNONE
566 unsigned mc2PseudoReg(unsigned Reg);
567 
568 /// Can this operand also contain immediate values?
569 bool isSISrcOperand(const MCInstrDesc &Desc, unsigned OpNo);
570 
571 /// Is this floating-point operand?
572 bool isSISrcFPOperand(const MCInstrDesc &Desc, unsigned OpNo);
573 
574 /// Does this opearnd support only inlinable literals?
575 bool isSISrcInlinableOperand(const MCInstrDesc &Desc, unsigned OpNo);
576 
577 /// Get the size in bits of a register from the register class \p RC.
578 unsigned getRegBitWidth(unsigned RCID);
579 
580 /// Get the size in bits of a register from the register class \p RC.
581 unsigned getRegBitWidth(const MCRegisterClass &RC);
582 
583 /// Get size of register operand
584 unsigned getRegOperandSize(const MCRegisterInfo *MRI, const MCInstrDesc &Desc,
585                            unsigned OpNo);
586 
587 LLVM_READNONE
588 inline unsigned getOperandSize(const MCOperandInfo &OpInfo) {
589   switch (OpInfo.OperandType) {
590   case AMDGPU::OPERAND_REG_IMM_INT32:
591   case AMDGPU::OPERAND_REG_IMM_FP32:
592   case AMDGPU::OPERAND_REG_INLINE_C_INT32:
593   case AMDGPU::OPERAND_REG_INLINE_C_FP32:
594   case AMDGPU::OPERAND_REG_INLINE_AC_INT32:
595   case AMDGPU::OPERAND_REG_INLINE_AC_FP32:
596     return 4;
597 
598   case AMDGPU::OPERAND_REG_IMM_INT64:
599   case AMDGPU::OPERAND_REG_IMM_FP64:
600   case AMDGPU::OPERAND_REG_INLINE_C_INT64:
601   case AMDGPU::OPERAND_REG_INLINE_C_FP64:
602     return 8;
603 
604   case AMDGPU::OPERAND_REG_IMM_INT16:
605   case AMDGPU::OPERAND_REG_IMM_FP16:
606   case AMDGPU::OPERAND_REG_INLINE_C_INT16:
607   case AMDGPU::OPERAND_REG_INLINE_C_FP16:
608   case AMDGPU::OPERAND_REG_INLINE_C_V2INT16:
609   case AMDGPU::OPERAND_REG_INLINE_C_V2FP16:
610   case AMDGPU::OPERAND_REG_INLINE_AC_INT16:
611   case AMDGPU::OPERAND_REG_INLINE_AC_FP16:
612   case AMDGPU::OPERAND_REG_INLINE_AC_V2INT16:
613   case AMDGPU::OPERAND_REG_INLINE_AC_V2FP16:
614   case AMDGPU::OPERAND_REG_IMM_V2INT16:
615   case AMDGPU::OPERAND_REG_IMM_V2FP16:
616     return 2;
617 
618   default:
619     llvm_unreachable("unhandled operand type");
620   }
621 }
622 
623 LLVM_READNONE
624 inline unsigned getOperandSize(const MCInstrDesc &Desc, unsigned OpNo) {
625   return getOperandSize(Desc.OpInfo[OpNo]);
626 }
627 
628 /// Is this literal inlinable
629 LLVM_READNONE
630 bool isInlinableLiteral64(int64_t Literal, bool HasInv2Pi);
631 
632 LLVM_READNONE
633 bool isInlinableLiteral32(int32_t Literal, bool HasInv2Pi);
634 
635 LLVM_READNONE
636 bool isInlinableLiteral16(int16_t Literal, bool HasInv2Pi);
637 
638 LLVM_READNONE
639 bool isInlinableLiteralV216(int32_t Literal, bool HasInv2Pi);
640 
641 bool isArgPassedInSGPR(const Argument *Arg);
642 
643 /// Convert \p ByteOffset to dwords if the subtarget uses dword SMRD immediate
644 /// offsets.
645 uint64_t convertSMRDOffsetUnits(const MCSubtargetInfo &ST, uint64_t ByteOffset);
646 
647 /// \returns The encoding that will be used for \p ByteOffset in the
648 /// SMRD offset field, or None if it won't fit. On GFX9 and GFX10
649 /// S_LOAD instructions have a signed offset, on other subtargets it is
650 /// unsigned. S_BUFFER has an unsigned offset for all subtargets.
651 Optional<int64_t> getSMRDEncodedOffset(const MCSubtargetInfo &ST,
652                                        int64_t ByteOffset, bool IsBuffer);
653 
654 /// \return The encoding that can be used for a 32-bit literal offset in an SMRD
655 /// instruction. This is only useful on CI.s
656 Optional<int64_t> getSMRDEncodedLiteralOffset32(const MCSubtargetInfo &ST,
657                                                 int64_t ByteOffset);
658 
659 /// \returns true if this offset is small enough to fit in the SMRD
660 /// offset field.  \p ByteOffset should be the offset in bytes and
661 /// not the encoded offset.
662 bool isLegalSMRDImmOffset(const MCSubtargetInfo &ST, int64_t ByteOffset);
663 
664 bool splitMUBUFOffset(uint32_t Imm, uint32_t &SOffset, uint32_t &ImmOffset,
665                       const GCNSubtarget *Subtarget, uint32_t Align = 4);
666 
667 /// \returns true if the intrinsic is divergent
668 bool isIntrinsicSourceOfDivergence(unsigned IntrID);
669 
670 // Track defaults for fields in the MODE registser.
671 struct SIModeRegisterDefaults {
672   /// Floating point opcodes that support exception flag gathering quiet and
673   /// propagate signaling NaN inputs per IEEE 754-2008. Min_dx10 and max_dx10
674   /// become IEEE 754- 2008 compliant due to signaling NaN propagation and
675   /// quieting.
676   bool IEEE : 1;
677 
678   /// Used by the vector ALU to force DX10-style treatment of NaNs: when set,
679   /// clamp NaN to zero; otherwise, pass NaN through.
680   bool DX10Clamp : 1;
681 
682   /// If this is set, neither input or output denormals are flushed for most f32
683   /// instructions.
684   bool FP32InputDenormals : 1;
685   bool FP32OutputDenormals : 1;
686 
687   /// If this is set, neither input or output denormals are flushed for both f64
688   /// and f16/v2f16 instructions.
689   bool FP64FP16InputDenormals : 1;
690   bool FP64FP16OutputDenormals : 1;
691 
692   SIModeRegisterDefaults() :
693     IEEE(true),
694     DX10Clamp(true),
695     FP32InputDenormals(true),
696     FP32OutputDenormals(true),
697     FP64FP16InputDenormals(true),
698     FP64FP16OutputDenormals(true) {}
699 
700   SIModeRegisterDefaults(const Function &F);
701 
702   static SIModeRegisterDefaults getDefaultForCallingConv(CallingConv::ID CC) {
703     const bool IsCompute = AMDGPU::isCompute(CC);
704 
705     SIModeRegisterDefaults Mode;
706     Mode.IEEE = IsCompute;
707     return Mode;
708   }
709 
710   bool operator ==(const SIModeRegisterDefaults Other) const {
711     return IEEE == Other.IEEE && DX10Clamp == Other.DX10Clamp &&
712            FP32InputDenormals == Other.FP32InputDenormals &&
713            FP32OutputDenormals == Other.FP32OutputDenormals &&
714            FP64FP16InputDenormals == Other.FP64FP16InputDenormals &&
715            FP64FP16OutputDenormals == Other.FP64FP16OutputDenormals;
716   }
717 
718   bool allFP32Denormals() const {
719     return FP32InputDenormals && FP32OutputDenormals;
720   }
721 
722   bool allFP64FP16Denormals() const {
723     return FP64FP16InputDenormals && FP64FP16OutputDenormals;
724   }
725 
726   /// Get the encoding value for the FP_DENORM bits of the mode register for the
727   /// FP32 denormal mode.
728   uint32_t fpDenormModeSPValue() const {
729     if (FP32InputDenormals && FP32OutputDenormals)
730       return FP_DENORM_FLUSH_NONE;
731     if (FP32InputDenormals)
732       return FP_DENORM_FLUSH_OUT;
733     if (FP32OutputDenormals)
734       return FP_DENORM_FLUSH_IN;
735     return FP_DENORM_FLUSH_IN_FLUSH_OUT;
736   }
737 
738   /// Get the encoding value for the FP_DENORM bits of the mode register for the
739   /// FP64/FP16 denormal mode.
740   uint32_t fpDenormModeDPValue() const {
741     if (FP64FP16InputDenormals && FP64FP16OutputDenormals)
742       return FP_DENORM_FLUSH_NONE;
743     if (FP64FP16InputDenormals)
744       return FP_DENORM_FLUSH_OUT;
745     if (FP64FP16OutputDenormals)
746       return FP_DENORM_FLUSH_IN;
747     return FP_DENORM_FLUSH_IN_FLUSH_OUT;
748   }
749 
750   /// Returns true if a flag is compatible if it's enabled in the callee, but
751   /// disabled in the caller.
752   static bool oneWayCompatible(bool CallerMode, bool CalleeMode) {
753     return CallerMode == CalleeMode || (CallerMode && !CalleeMode);
754   }
755 
756   // FIXME: Inlining should be OK for dx10-clamp, since the caller's mode should
757   // be able to override.
758   bool isInlineCompatible(SIModeRegisterDefaults CalleeMode) const {
759     if (DX10Clamp != CalleeMode.DX10Clamp)
760       return false;
761     if (IEEE != CalleeMode.IEEE)
762       return false;
763 
764     // Allow inlining denormals enabled into denormals flushed functions.
765     return oneWayCompatible(FP64FP16InputDenormals, CalleeMode.FP64FP16InputDenormals) &&
766            oneWayCompatible(FP64FP16OutputDenormals, CalleeMode.FP64FP16OutputDenormals) &&
767            oneWayCompatible(FP32InputDenormals, CalleeMode.FP32InputDenormals) &&
768            oneWayCompatible(FP32OutputDenormals, CalleeMode.FP32OutputDenormals);
769   }
770 };
771 
772 } // end namespace AMDGPU
773 } // end namespace llvm
774 
775 #endif // LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
776