1 //===-- AMDGPUBaseInfo.h - Top level definitions for AMDGPU -----*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #ifndef LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H 11 #define LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H 12 13 #include "AMDKernelCodeT.h" 14 #include "llvm/IR/CallingConv.h" 15 16 #include "SIDefines.h" 17 18 #define GET_INSTRINFO_OPERAND_ENUM 19 #include "AMDGPUGenInstrInfo.inc" 20 #undef GET_INSTRINFO_OPERAND_ENUM 21 22 namespace llvm { 23 24 class FeatureBitset; 25 class Function; 26 class GlobalValue; 27 class MCContext; 28 class MCInstrDesc; 29 class MCRegisterClass; 30 class MCRegisterInfo; 31 class MCSection; 32 class MCSubtargetInfo; 33 34 namespace AMDGPU { 35 36 LLVM_READONLY 37 int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx); 38 39 struct IsaVersion { 40 unsigned Major; 41 unsigned Minor; 42 unsigned Stepping; 43 }; 44 45 IsaVersion getIsaVersion(const FeatureBitset &Features); 46 void initDefaultAMDKernelCodeT(amd_kernel_code_t &Header, 47 const FeatureBitset &Features); 48 MCSection *getHSATextSection(MCContext &Ctx); 49 50 MCSection *getHSADataGlobalAgentSection(MCContext &Ctx); 51 52 MCSection *getHSADataGlobalProgramSection(MCContext &Ctx); 53 54 MCSection *getHSARodataReadonlyAgentSection(MCContext &Ctx); 55 56 bool isGroupSegment(const GlobalValue *GV); 57 bool isGlobalSegment(const GlobalValue *GV); 58 bool isReadOnlySegment(const GlobalValue *GV); 59 60 /// \returns True if constants should be emitted to .text section for given 61 /// target triple \p TT, false otherwise. 62 bool shouldEmitConstantsToTextSection(const Triple &TT); 63 64 /// \returns Integer value requested using \p F's \p Name attribute. 65 /// 66 /// \returns \p Default if attribute is not present. 67 /// 68 /// \returns \p Default and emits error if requested value cannot be converted 69 /// to integer. 70 int getIntegerAttribute(const Function &F, StringRef Name, int Default); 71 72 /// \returns A pair of integer values requested using \p F's \p Name attribute 73 /// in "first[,second]" format ("second" is optional unless \p OnlyFirstRequired 74 /// is false). 75 /// 76 /// \returns \p Default if attribute is not present. 77 /// 78 /// \returns \p Default and emits error if one of the requested values cannot be 79 /// converted to integer, or \p OnlyFirstRequired is false and "second" value is 80 /// not present. 81 std::pair<int, int> getIntegerPairAttribute(const Function &F, 82 StringRef Name, 83 std::pair<int, int> Default, 84 bool OnlyFirstRequired = false); 85 86 /// \returns Waitcnt bit mask for given isa \p Version. 87 unsigned getWaitcntBitMask(IsaVersion Version); 88 89 /// \returns Vmcnt bit mask for given isa \p Version. 90 unsigned getVmcntBitMask(IsaVersion Version); 91 92 /// \returns Expcnt bit mask for given isa \p Version. 93 unsigned getExpcntBitMask(IsaVersion Version); 94 95 /// \returns Lgkmcnt bit mask for given isa \p Version. 96 unsigned getLgkmcntBitMask(IsaVersion Version); 97 98 /// \returns Decoded Vmcnt from given \p Waitcnt for given isa \p Version. 99 unsigned decodeVmcnt(IsaVersion Version, unsigned Waitcnt); 100 101 /// \returns Decoded Expcnt from given \p Waitcnt for given isa \p Version. 102 unsigned decodeExpcnt(IsaVersion Version, unsigned Waitcnt); 103 104 /// \returns Decoded Lgkmcnt from given \p Waitcnt for given isa \p Version. 105 unsigned decodeLgkmcnt(IsaVersion Version, unsigned Waitcnt); 106 107 /// \brief Decodes Vmcnt, Expcnt and Lgkmcnt from given \p Waitcnt for given isa 108 /// \p Version, and writes decoded values into \p Vmcnt, \p Expcnt and 109 /// \p Lgkmcnt respectively. 110 /// 111 /// \details \p Vmcnt, \p Expcnt and \p Lgkmcnt are decoded as follows: 112 /// \p Vmcnt = \p Waitcnt[3:0] 113 /// \p Expcnt = \p Waitcnt[6:4] 114 /// \p Lgkmcnt = \p Waitcnt[11:8] 115 void decodeWaitcnt(IsaVersion Version, unsigned Waitcnt, 116 unsigned &Vmcnt, unsigned &Expcnt, unsigned &Lgkmcnt); 117 118 /// \returns \p Waitcnt with encoded \p Vmcnt for given isa \p Version. 119 unsigned encodeVmcnt(IsaVersion Version, unsigned Waitcnt, unsigned Vmcnt); 120 121 /// \returns \p Waitcnt with encoded \p Expcnt for given isa \p Version. 122 unsigned encodeExpcnt(IsaVersion Version, unsigned Waitcnt, unsigned Expcnt); 123 124 /// \returns \p Waitcnt with encoded \p Lgkmcnt for given isa \p Version. 125 unsigned encodeLgkmcnt(IsaVersion Version, unsigned Waitcnt, unsigned Lgkmcnt); 126 127 /// \brief Encodes \p Vmcnt, \p Expcnt and \p Lgkmcnt into Waitcnt for given isa 128 /// \p Version. 129 /// 130 /// \details \p Vmcnt, \p Expcnt and \p Lgkmcnt are encoded as follows: 131 /// Waitcnt[3:0] = \p Vmcnt 132 /// Waitcnt[6:4] = \p Expcnt 133 /// Waitcnt[11:8] = \p Lgkmcnt 134 /// 135 /// \returns Waitcnt with encoded \p Vmcnt, \p Expcnt and \p Lgkmcnt for given 136 /// isa \p Version. 137 unsigned encodeWaitcnt(IsaVersion Version, 138 unsigned Vmcnt, unsigned Expcnt, unsigned Lgkmcnt); 139 140 unsigned getInitialPSInputAddr(const Function &F); 141 142 bool isShader(CallingConv::ID cc); 143 bool isCompute(CallingConv::ID cc); 144 145 bool isSI(const MCSubtargetInfo &STI); 146 bool isCI(const MCSubtargetInfo &STI); 147 bool isVI(const MCSubtargetInfo &STI); 148 149 /// If \p Reg is a pseudo reg, return the correct hardware register given 150 /// \p STI otherwise return \p Reg. 151 unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI); 152 153 /// \brief Can this operand also contain immediate values? 154 bool isSISrcOperand(const MCInstrDesc &Desc, unsigned OpNo); 155 156 /// \brief Is this floating-point operand? 157 bool isSISrcFPOperand(const MCInstrDesc &Desc, unsigned OpNo); 158 159 /// \brief Does this opearnd support only inlinable literals? 160 bool isSISrcInlinableOperand(const MCInstrDesc &Desc, unsigned OpNo); 161 162 /// \brief Get the size in bits of a register from the register class \p RC. 163 unsigned getRegBitWidth(unsigned RCID); 164 165 /// \brief Get the size in bits of a register from the register class \p RC. 166 unsigned getRegBitWidth(const MCRegisterClass &RC); 167 168 /// \brief Get size of register operand 169 unsigned getRegOperandSize(const MCRegisterInfo *MRI, const MCInstrDesc &Desc, 170 unsigned OpNo); 171 172 LLVM_READNONE 173 inline unsigned getOperandSize(const MCOperandInfo &OpInfo) { 174 switch (OpInfo.OperandType) { 175 case AMDGPU::OPERAND_REG_IMM_INT32: 176 case AMDGPU::OPERAND_REG_IMM_FP32: 177 case AMDGPU::OPERAND_REG_INLINE_C_INT32: 178 case AMDGPU::OPERAND_REG_INLINE_C_FP32: 179 return 4; 180 181 case AMDGPU::OPERAND_REG_IMM_INT64: 182 case AMDGPU::OPERAND_REG_IMM_FP64: 183 case AMDGPU::OPERAND_REG_INLINE_C_INT64: 184 case AMDGPU::OPERAND_REG_INLINE_C_FP64: 185 return 8; 186 187 case AMDGPU::OPERAND_REG_IMM_INT16: 188 case AMDGPU::OPERAND_REG_IMM_FP16: 189 case AMDGPU::OPERAND_REG_INLINE_C_INT16: 190 case AMDGPU::OPERAND_REG_INLINE_C_FP16: 191 return 2; 192 193 default: 194 llvm_unreachable("unhandled operand type"); 195 } 196 } 197 198 LLVM_READNONE 199 inline unsigned getOperandSize(const MCInstrDesc &Desc, unsigned OpNo) { 200 return getOperandSize(Desc.OpInfo[OpNo]); 201 } 202 203 /// \brief Is this literal inlinable 204 LLVM_READNONE 205 bool isInlinableLiteral64(int64_t Literal, bool HasInv2Pi); 206 207 LLVM_READNONE 208 bool isInlinableLiteral32(int32_t Literal, bool HasInv2Pi); 209 210 LLVM_READNONE 211 bool isInlinableLiteral16(int16_t Literal, bool HasInv2Pi); 212 213 } // end namespace AMDGPU 214 } // end namespace llvm 215 216 #endif 217