1 //===- AMDGPUBaseInfo.h - Top level definitions for AMDGPU ------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #ifndef LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
10 #define LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
11 
12 #include "SIDefines.h"
13 #include "llvm/IR/CallingConv.h"
14 #include "llvm/Support/Alignment.h"
15 
16 struct amd_kernel_code_t;
17 
18 namespace llvm {
19 
20 struct Align;
21 class Argument;
22 class Function;
23 class GCNSubtarget;
24 class GlobalValue;
25 class MCRegisterClass;
26 class MCRegisterInfo;
27 class MCSubtargetInfo;
28 class StringRef;
29 class Triple;
30 
31 namespace amdhsa {
32 struct kernel_descriptor_t;
33 }
34 
35 namespace AMDGPU {
36 
37 struct IsaVersion;
38 
39 /// \returns HSA OS ABI Version identification.
40 Optional<uint8_t> getHsaAbiVersion(const MCSubtargetInfo *STI);
41 /// \returns True if HSA OS ABI Version identification is 2,
42 /// false otherwise.
43 bool isHsaAbiVersion2(const MCSubtargetInfo *STI);
44 /// \returns True if HSA OS ABI Version identification is 3,
45 /// false otherwise.
46 bool isHsaAbiVersion3(const MCSubtargetInfo *STI);
47 /// \returns True if HSA OS ABI Version identification is 4,
48 /// false otherwise.
49 bool isHsaAbiVersion4(const MCSubtargetInfo *STI);
50 /// \returns True if HSA OS ABI Version identification is 3 or 4,
51 /// false otherwise.
52 bool isHsaAbiVersion3Or4(const MCSubtargetInfo *STI);
53 
54 struct GcnBufferFormatInfo {
55   unsigned Format;
56   unsigned BitsPerComp;
57   unsigned NumComponents;
58   unsigned NumFormat;
59   unsigned DataFormat;
60 };
61 
62 #define GET_MIMGBaseOpcode_DECL
63 #define GET_MIMGDim_DECL
64 #define GET_MIMGEncoding_DECL
65 #define GET_MIMGLZMapping_DECL
66 #define GET_MIMGMIPMapping_DECL
67 #include "AMDGPUGenSearchableTables.inc"
68 
69 namespace IsaInfo {
70 
71 enum {
72   // The closed Vulkan driver sets 96, which limits the wave count to 8 but
73   // doesn't spill SGPRs as much as when 80 is set.
74   FIXED_NUM_SGPRS_FOR_INIT_BUG = 96,
75   TRAP_NUM_SGPRS = 16
76 };
77 
78 enum class TargetIDSetting {
79   Unsupported,
80   Any,
81   Off,
82   On
83 };
84 
85 class AMDGPUTargetID {
86 private:
87   const MCSubtargetInfo &STI;
88   TargetIDSetting XnackSetting;
89   TargetIDSetting SramEccSetting;
90 
91 public:
92   explicit AMDGPUTargetID(const MCSubtargetInfo &STI);
93   ~AMDGPUTargetID() = default;
94 
95   /// \return True if the current xnack setting is not "Unsupported".
96   bool isXnackSupported() const {
97     return XnackSetting != TargetIDSetting::Unsupported;
98   }
99 
100   /// \returns True if the current xnack setting is "On" or "Any".
101   bool isXnackOnOrAny() const {
102     return XnackSetting == TargetIDSetting::On ||
103         XnackSetting == TargetIDSetting::Any;
104   }
105 
106   /// \returns True if current xnack setting is "On" or "Off",
107   /// false otherwise.
108   bool isXnackOnOrOff() const {
109     return getXnackSetting() == TargetIDSetting::On ||
110         getXnackSetting() == TargetIDSetting::Off;
111   }
112 
113   /// \returns The current xnack TargetIDSetting, possible options are
114   /// "Unsupported", "Any", "Off", and "On".
115   TargetIDSetting getXnackSetting() const {
116     return XnackSetting;
117   }
118 
119   /// Sets xnack setting to \p NewXnackSetting.
120   void setXnackSetting(TargetIDSetting NewXnackSetting) {
121     XnackSetting = NewXnackSetting;
122   }
123 
124   /// \return True if the current sramecc setting is not "Unsupported".
125   bool isSramEccSupported() const {
126     return SramEccSetting != TargetIDSetting::Unsupported;
127   }
128 
129   /// \returns True if the current sramecc setting is "On" or "Any".
130   bool isSramEccOnOrAny() const {
131   return SramEccSetting == TargetIDSetting::On ||
132       SramEccSetting == TargetIDSetting::Any;
133   }
134 
135   /// \returns True if current sramecc setting is "On" or "Off",
136   /// false otherwise.
137   bool isSramEccOnOrOff() const {
138     return getSramEccSetting() == TargetIDSetting::On ||
139         getSramEccSetting() == TargetIDSetting::Off;
140   }
141 
142   /// \returns The current sramecc TargetIDSetting, possible options are
143   /// "Unsupported", "Any", "Off", and "On".
144   TargetIDSetting getSramEccSetting() const {
145     return SramEccSetting;
146   }
147 
148   /// Sets sramecc setting to \p NewSramEccSetting.
149   void setSramEccSetting(TargetIDSetting NewSramEccSetting) {
150     SramEccSetting = NewSramEccSetting;
151   }
152 
153   void setTargetIDFromFeaturesString(StringRef FS);
154   void setTargetIDFromTargetIDStream(StringRef TargetID);
155 
156   /// \returns String representation of an object.
157   std::string toString() const;
158 };
159 
160 /// \returns Wavefront size for given subtarget \p STI.
161 unsigned getWavefrontSize(const MCSubtargetInfo *STI);
162 
163 /// \returns Local memory size in bytes for given subtarget \p STI.
164 unsigned getLocalMemorySize(const MCSubtargetInfo *STI);
165 
166 /// \returns Number of execution units per compute unit for given subtarget \p
167 /// STI.
168 unsigned getEUsPerCU(const MCSubtargetInfo *STI);
169 
170 /// \returns Maximum number of work groups per compute unit for given subtarget
171 /// \p STI and limited by given \p FlatWorkGroupSize.
172 unsigned getMaxWorkGroupsPerCU(const MCSubtargetInfo *STI,
173                                unsigned FlatWorkGroupSize);
174 
175 /// \returns Minimum number of waves per execution unit for given subtarget \p
176 /// STI.
177 unsigned getMinWavesPerEU(const MCSubtargetInfo *STI);
178 
179 /// \returns Maximum number of waves per execution unit for given subtarget \p
180 /// STI without any kind of limitation.
181 unsigned getMaxWavesPerEU(const MCSubtargetInfo *STI);
182 
183 /// \returns Number of waves per execution unit required to support the given \p
184 /// FlatWorkGroupSize.
185 unsigned getWavesPerEUForWorkGroup(const MCSubtargetInfo *STI,
186                                    unsigned FlatWorkGroupSize);
187 
188 /// \returns Minimum flat work group size for given subtarget \p STI.
189 unsigned getMinFlatWorkGroupSize(const MCSubtargetInfo *STI);
190 
191 /// \returns Maximum flat work group size for given subtarget \p STI.
192 unsigned getMaxFlatWorkGroupSize(const MCSubtargetInfo *STI);
193 
194 /// \returns Number of waves per work group for given subtarget \p STI and
195 /// \p FlatWorkGroupSize.
196 unsigned getWavesPerWorkGroup(const MCSubtargetInfo *STI,
197                               unsigned FlatWorkGroupSize);
198 
199 /// \returns SGPR allocation granularity for given subtarget \p STI.
200 unsigned getSGPRAllocGranule(const MCSubtargetInfo *STI);
201 
202 /// \returns SGPR encoding granularity for given subtarget \p STI.
203 unsigned getSGPREncodingGranule(const MCSubtargetInfo *STI);
204 
205 /// \returns Total number of SGPRs for given subtarget \p STI.
206 unsigned getTotalNumSGPRs(const MCSubtargetInfo *STI);
207 
208 /// \returns Addressable number of SGPRs for given subtarget \p STI.
209 unsigned getAddressableNumSGPRs(const MCSubtargetInfo *STI);
210 
211 /// \returns Minimum number of SGPRs that meets the given number of waves per
212 /// execution unit requirement for given subtarget \p STI.
213 unsigned getMinNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU);
214 
215 /// \returns Maximum number of SGPRs that meets the given number of waves per
216 /// execution unit requirement for given subtarget \p STI.
217 unsigned getMaxNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU,
218                         bool Addressable);
219 
220 /// \returns Number of extra SGPRs implicitly required by given subtarget \p
221 /// STI when the given special registers are used.
222 unsigned getNumExtraSGPRs(const MCSubtargetInfo *STI, bool VCCUsed,
223                           bool FlatScrUsed, bool XNACKUsed);
224 
225 /// \returns Number of extra SGPRs implicitly required by given subtarget \p
226 /// STI when the given special registers are used. XNACK is inferred from
227 /// \p STI.
228 unsigned getNumExtraSGPRs(const MCSubtargetInfo *STI, bool VCCUsed,
229                           bool FlatScrUsed);
230 
231 /// \returns Number of SGPR blocks needed for given subtarget \p STI when
232 /// \p NumSGPRs are used. \p NumSGPRs should already include any special
233 /// register counts.
234 unsigned getNumSGPRBlocks(const MCSubtargetInfo *STI, unsigned NumSGPRs);
235 
236 /// \returns VGPR allocation granularity for given subtarget \p STI.
237 ///
238 /// For subtargets which support it, \p EnableWavefrontSize32 should match
239 /// the ENABLE_WAVEFRONT_SIZE32 kernel descriptor field.
240 unsigned getVGPRAllocGranule(const MCSubtargetInfo *STI,
241                              Optional<bool> EnableWavefrontSize32 = None);
242 
243 /// \returns VGPR encoding granularity for given subtarget \p STI.
244 ///
245 /// For subtargets which support it, \p EnableWavefrontSize32 should match
246 /// the ENABLE_WAVEFRONT_SIZE32 kernel descriptor field.
247 unsigned getVGPREncodingGranule(const MCSubtargetInfo *STI,
248                                 Optional<bool> EnableWavefrontSize32 = None);
249 
250 /// \returns Total number of VGPRs for given subtarget \p STI.
251 unsigned getTotalNumVGPRs(const MCSubtargetInfo *STI);
252 
253 /// \returns Addressable number of VGPRs for given subtarget \p STI.
254 unsigned getAddressableNumVGPRs(const MCSubtargetInfo *STI);
255 
256 /// \returns Minimum number of VGPRs that meets given number of waves per
257 /// execution unit requirement for given subtarget \p STI.
258 unsigned getMinNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU);
259 
260 /// \returns Maximum number of VGPRs that meets given number of waves per
261 /// execution unit requirement for given subtarget \p STI.
262 unsigned getMaxNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU);
263 
264 /// \returns Number of VGPR blocks needed for given subtarget \p STI when
265 /// \p NumVGPRs are used.
266 ///
267 /// For subtargets which support it, \p EnableWavefrontSize32 should match the
268 /// ENABLE_WAVEFRONT_SIZE32 kernel descriptor field.
269 unsigned getNumVGPRBlocks(const MCSubtargetInfo *STI, unsigned NumSGPRs,
270                           Optional<bool> EnableWavefrontSize32 = None);
271 
272 } // end namespace IsaInfo
273 
274 LLVM_READONLY
275 int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx);
276 
277 LLVM_READONLY
278 int getSOPPWithRelaxation(uint16_t Opcode);
279 
280 struct MIMGBaseOpcodeInfo {
281   MIMGBaseOpcode BaseOpcode;
282   bool Store;
283   bool Atomic;
284   bool AtomicX2;
285   bool Sampler;
286   bool Gather4;
287 
288   uint8_t NumExtraArgs;
289   bool Gradients;
290   bool G16;
291   bool Coordinates;
292   bool LodOrClampOrMip;
293   bool HasD16;
294   bool MSAA;
295 };
296 
297 LLVM_READONLY
298 const MIMGBaseOpcodeInfo *getMIMGBaseOpcodeInfo(unsigned BaseOpcode);
299 
300 struct MIMGDimInfo {
301   MIMGDim Dim;
302   uint8_t NumCoords;
303   uint8_t NumGradients;
304   bool MSAA;
305   bool DA;
306   uint8_t Encoding;
307   const char *AsmSuffix;
308 };
309 
310 LLVM_READONLY
311 const MIMGDimInfo *getMIMGDimInfo(unsigned DimEnum);
312 
313 LLVM_READONLY
314 const MIMGDimInfo *getMIMGDimInfoByEncoding(uint8_t DimEnc);
315 
316 LLVM_READONLY
317 const MIMGDimInfo *getMIMGDimInfoByAsmSuffix(StringRef AsmSuffix);
318 
319 struct MIMGLZMappingInfo {
320   MIMGBaseOpcode L;
321   MIMGBaseOpcode LZ;
322 };
323 
324 struct MIMGMIPMappingInfo {
325   MIMGBaseOpcode MIP;
326   MIMGBaseOpcode NONMIP;
327 };
328 
329 struct MIMGG16MappingInfo {
330   MIMGBaseOpcode G;
331   MIMGBaseOpcode G16;
332 };
333 
334 LLVM_READONLY
335 const MIMGLZMappingInfo *getMIMGLZMappingInfo(unsigned L);
336 
337 LLVM_READONLY
338 const MIMGMIPMappingInfo *getMIMGMIPMappingInfo(unsigned MIP);
339 
340 LLVM_READONLY
341 const MIMGG16MappingInfo *getMIMGG16MappingInfo(unsigned G);
342 
343 LLVM_READONLY
344 int getMIMGOpcode(unsigned BaseOpcode, unsigned MIMGEncoding,
345                   unsigned VDataDwords, unsigned VAddrDwords);
346 
347 LLVM_READONLY
348 int getMaskedMIMGOp(unsigned Opc, unsigned NewChannels);
349 
350 struct MIMGInfo {
351   uint16_t Opcode;
352   uint16_t BaseOpcode;
353   uint8_t MIMGEncoding;
354   uint8_t VDataDwords;
355   uint8_t VAddrDwords;
356 };
357 
358 LLVM_READONLY
359 const MIMGInfo *getMIMGInfo(unsigned Opc);
360 
361 LLVM_READONLY
362 int getMTBUFBaseOpcode(unsigned Opc);
363 
364 LLVM_READONLY
365 int getMTBUFOpcode(unsigned BaseOpc, unsigned Elements);
366 
367 LLVM_READONLY
368 int getMTBUFElements(unsigned Opc);
369 
370 LLVM_READONLY
371 bool getMTBUFHasVAddr(unsigned Opc);
372 
373 LLVM_READONLY
374 bool getMTBUFHasSrsrc(unsigned Opc);
375 
376 LLVM_READONLY
377 bool getMTBUFHasSoffset(unsigned Opc);
378 
379 LLVM_READONLY
380 int getMUBUFBaseOpcode(unsigned Opc);
381 
382 LLVM_READONLY
383 int getMUBUFOpcode(unsigned BaseOpc, unsigned Elements);
384 
385 LLVM_READONLY
386 int getMUBUFElements(unsigned Opc);
387 
388 LLVM_READONLY
389 bool getMUBUFHasVAddr(unsigned Opc);
390 
391 LLVM_READONLY
392 bool getMUBUFHasSrsrc(unsigned Opc);
393 
394 LLVM_READONLY
395 bool getMUBUFHasSoffset(unsigned Opc);
396 
397 LLVM_READONLY
398 bool getMUBUFIsBufferInv(unsigned Opc);
399 
400 LLVM_READONLY
401 bool getSMEMIsBuffer(unsigned Opc);
402 
403 LLVM_READONLY
404 bool getVOP1IsSingle(unsigned Opc);
405 
406 LLVM_READONLY
407 bool getVOP2IsSingle(unsigned Opc);
408 
409 LLVM_READONLY
410 bool getVOP3IsSingle(unsigned Opc);
411 
412 LLVM_READONLY
413 const GcnBufferFormatInfo *getGcnBufferFormatInfo(uint8_t BitsPerComp,
414                                                   uint8_t NumComponents,
415                                                   uint8_t NumFormat,
416                                                   const MCSubtargetInfo &STI);
417 LLVM_READONLY
418 const GcnBufferFormatInfo *getGcnBufferFormatInfo(uint8_t Format,
419                                                   const MCSubtargetInfo &STI);
420 
421 LLVM_READONLY
422 int getMCOpcode(uint16_t Opcode, unsigned Gen);
423 
424 void initDefaultAMDKernelCodeT(amd_kernel_code_t &Header,
425                                const MCSubtargetInfo *STI);
426 
427 amdhsa::kernel_descriptor_t getDefaultAmdhsaKernelDescriptor(
428     const MCSubtargetInfo *STI);
429 
430 bool isGroupSegment(const GlobalValue *GV);
431 bool isGlobalSegment(const GlobalValue *GV);
432 bool isReadOnlySegment(const GlobalValue *GV);
433 
434 /// \returns True if constants should be emitted to .text section for given
435 /// target triple \p TT, false otherwise.
436 bool shouldEmitConstantsToTextSection(const Triple &TT);
437 
438 /// \returns Integer value requested using \p F's \p Name attribute.
439 ///
440 /// \returns \p Default if attribute is not present.
441 ///
442 /// \returns \p Default and emits error if requested value cannot be converted
443 /// to integer.
444 int getIntegerAttribute(const Function &F, StringRef Name, int Default);
445 
446 /// \returns A pair of integer values requested using \p F's \p Name attribute
447 /// in "first[,second]" format ("second" is optional unless \p OnlyFirstRequired
448 /// is false).
449 ///
450 /// \returns \p Default if attribute is not present.
451 ///
452 /// \returns \p Default and emits error if one of the requested values cannot be
453 /// converted to integer, or \p OnlyFirstRequired is false and "second" value is
454 /// not present.
455 std::pair<int, int> getIntegerPairAttribute(const Function &F,
456                                             StringRef Name,
457                                             std::pair<int, int> Default,
458                                             bool OnlyFirstRequired = false);
459 
460 /// Represents the counter values to wait for in an s_waitcnt instruction.
461 ///
462 /// Large values (including the maximum possible integer) can be used to
463 /// represent "don't care" waits.
464 struct Waitcnt {
465   unsigned VmCnt = ~0u;
466   unsigned ExpCnt = ~0u;
467   unsigned LgkmCnt = ~0u;
468   unsigned VsCnt = ~0u;
469 
470   Waitcnt() {}
471   Waitcnt(unsigned VmCnt, unsigned ExpCnt, unsigned LgkmCnt, unsigned VsCnt)
472       : VmCnt(VmCnt), ExpCnt(ExpCnt), LgkmCnt(LgkmCnt), VsCnt(VsCnt) {}
473 
474   static Waitcnt allZero(bool HasVscnt) {
475     return Waitcnt(0, 0, 0, HasVscnt ? 0 : ~0u);
476   }
477   static Waitcnt allZeroExceptVsCnt() { return Waitcnt(0, 0, 0, ~0u); }
478 
479   bool hasWait() const {
480     return VmCnt != ~0u || ExpCnt != ~0u || LgkmCnt != ~0u || VsCnt != ~0u;
481   }
482 
483   bool hasWaitExceptVsCnt() const {
484     return VmCnt != ~0u || ExpCnt != ~0u || LgkmCnt != ~0u;
485   }
486 
487   bool hasWaitVsCnt() const {
488     return VsCnt != ~0u;
489   }
490 
491   bool dominates(const Waitcnt &Other) const {
492     return VmCnt <= Other.VmCnt && ExpCnt <= Other.ExpCnt &&
493            LgkmCnt <= Other.LgkmCnt && VsCnt <= Other.VsCnt;
494   }
495 
496   Waitcnt combined(const Waitcnt &Other) const {
497     return Waitcnt(std::min(VmCnt, Other.VmCnt), std::min(ExpCnt, Other.ExpCnt),
498                    std::min(LgkmCnt, Other.LgkmCnt),
499                    std::min(VsCnt, Other.VsCnt));
500   }
501 };
502 
503 /// \returns Vmcnt bit mask for given isa \p Version.
504 unsigned getVmcntBitMask(const IsaVersion &Version);
505 
506 /// \returns Expcnt bit mask for given isa \p Version.
507 unsigned getExpcntBitMask(const IsaVersion &Version);
508 
509 /// \returns Lgkmcnt bit mask for given isa \p Version.
510 unsigned getLgkmcntBitMask(const IsaVersion &Version);
511 
512 /// \returns Waitcnt bit mask for given isa \p Version.
513 unsigned getWaitcntBitMask(const IsaVersion &Version);
514 
515 /// \returns Decoded Vmcnt from given \p Waitcnt for given isa \p Version.
516 unsigned decodeVmcnt(const IsaVersion &Version, unsigned Waitcnt);
517 
518 /// \returns Decoded Expcnt from given \p Waitcnt for given isa \p Version.
519 unsigned decodeExpcnt(const IsaVersion &Version, unsigned Waitcnt);
520 
521 /// \returns Decoded Lgkmcnt from given \p Waitcnt for given isa \p Version.
522 unsigned decodeLgkmcnt(const IsaVersion &Version, unsigned Waitcnt);
523 
524 /// Decodes Vmcnt, Expcnt and Lgkmcnt from given \p Waitcnt for given isa
525 /// \p Version, and writes decoded values into \p Vmcnt, \p Expcnt and
526 /// \p Lgkmcnt respectively.
527 ///
528 /// \details \p Vmcnt, \p Expcnt and \p Lgkmcnt are decoded as follows:
529 ///     \p Vmcnt = \p Waitcnt[3:0]                      (pre-gfx9 only)
530 ///     \p Vmcnt = \p Waitcnt[3:0] | \p Waitcnt[15:14]  (gfx9+ only)
531 ///     \p Expcnt = \p Waitcnt[6:4]
532 ///     \p Lgkmcnt = \p Waitcnt[11:8]                   (pre-gfx10 only)
533 ///     \p Lgkmcnt = \p Waitcnt[13:8]                   (gfx10+ only)
534 void decodeWaitcnt(const IsaVersion &Version, unsigned Waitcnt,
535                    unsigned &Vmcnt, unsigned &Expcnt, unsigned &Lgkmcnt);
536 
537 Waitcnt decodeWaitcnt(const IsaVersion &Version, unsigned Encoded);
538 
539 /// \returns \p Waitcnt with encoded \p Vmcnt for given isa \p Version.
540 unsigned encodeVmcnt(const IsaVersion &Version, unsigned Waitcnt,
541                      unsigned Vmcnt);
542 
543 /// \returns \p Waitcnt with encoded \p Expcnt for given isa \p Version.
544 unsigned encodeExpcnt(const IsaVersion &Version, unsigned Waitcnt,
545                       unsigned Expcnt);
546 
547 /// \returns \p Waitcnt with encoded \p Lgkmcnt for given isa \p Version.
548 unsigned encodeLgkmcnt(const IsaVersion &Version, unsigned Waitcnt,
549                        unsigned Lgkmcnt);
550 
551 /// Encodes \p Vmcnt, \p Expcnt and \p Lgkmcnt into Waitcnt for given isa
552 /// \p Version.
553 ///
554 /// \details \p Vmcnt, \p Expcnt and \p Lgkmcnt are encoded as follows:
555 ///     Waitcnt[3:0]   = \p Vmcnt       (pre-gfx9 only)
556 ///     Waitcnt[3:0]   = \p Vmcnt[3:0]  (gfx9+ only)
557 ///     Waitcnt[6:4]   = \p Expcnt
558 ///     Waitcnt[11:8]  = \p Lgkmcnt     (pre-gfx10 only)
559 ///     Waitcnt[13:8]  = \p Lgkmcnt     (gfx10+ only)
560 ///     Waitcnt[15:14] = \p Vmcnt[5:4]  (gfx9+ only)
561 ///
562 /// \returns Waitcnt with encoded \p Vmcnt, \p Expcnt and \p Lgkmcnt for given
563 /// isa \p Version.
564 unsigned encodeWaitcnt(const IsaVersion &Version,
565                        unsigned Vmcnt, unsigned Expcnt, unsigned Lgkmcnt);
566 
567 unsigned encodeWaitcnt(const IsaVersion &Version, const Waitcnt &Decoded);
568 
569 namespace Hwreg {
570 
571 LLVM_READONLY
572 int64_t getHwregId(const StringRef Name);
573 
574 LLVM_READNONE
575 bool isValidHwreg(int64_t Id, const MCSubtargetInfo &STI);
576 
577 LLVM_READNONE
578 bool isValidHwreg(int64_t Id);
579 
580 LLVM_READNONE
581 bool isValidHwregOffset(int64_t Offset);
582 
583 LLVM_READNONE
584 bool isValidHwregWidth(int64_t Width);
585 
586 LLVM_READNONE
587 uint64_t encodeHwreg(uint64_t Id, uint64_t Offset, uint64_t Width);
588 
589 LLVM_READNONE
590 StringRef getHwreg(unsigned Id, const MCSubtargetInfo &STI);
591 
592 void decodeHwreg(unsigned Val, unsigned &Id, unsigned &Offset, unsigned &Width);
593 
594 } // namespace Hwreg
595 
596 namespace Exp {
597 
598 bool getTgtName(unsigned Id, StringRef &Name, int &Index);
599 
600 LLVM_READONLY
601 unsigned getTgtId(const StringRef Name);
602 
603 LLVM_READNONE
604 bool isSupportedTgtId(unsigned Id, const MCSubtargetInfo &STI);
605 
606 } // namespace Exp
607 
608 namespace MTBUFFormat {
609 
610 LLVM_READNONE
611 int64_t encodeDfmtNfmt(unsigned Dfmt, unsigned Nfmt);
612 
613 void decodeDfmtNfmt(unsigned Format, unsigned &Dfmt, unsigned &Nfmt);
614 
615 int64_t getDfmt(const StringRef Name);
616 
617 StringRef getDfmtName(unsigned Id);
618 
619 int64_t getNfmt(const StringRef Name, const MCSubtargetInfo &STI);
620 
621 StringRef getNfmtName(unsigned Id, const MCSubtargetInfo &STI);
622 
623 bool isValidDfmtNfmt(unsigned Val, const MCSubtargetInfo &STI);
624 
625 bool isValidNfmt(unsigned Val, const MCSubtargetInfo &STI);
626 
627 int64_t getUnifiedFormat(const StringRef Name);
628 
629 StringRef getUnifiedFormatName(unsigned Id);
630 
631 bool isValidUnifiedFormat(unsigned Val);
632 
633 int64_t convertDfmtNfmt2Ufmt(unsigned Dfmt, unsigned Nfmt);
634 
635 bool isValidFormatEncoding(unsigned Val, const MCSubtargetInfo &STI);
636 
637 unsigned getDefaultFormatEncoding(const MCSubtargetInfo &STI);
638 
639 } // namespace MTBUFFormat
640 
641 namespace SendMsg {
642 
643 LLVM_READONLY
644 int64_t getMsgId(const StringRef Name);
645 
646 LLVM_READONLY
647 int64_t getMsgOpId(int64_t MsgId, const StringRef Name);
648 
649 LLVM_READNONE
650 StringRef getMsgName(int64_t MsgId);
651 
652 LLVM_READNONE
653 StringRef getMsgOpName(int64_t MsgId, int64_t OpId);
654 
655 LLVM_READNONE
656 bool isValidMsgId(int64_t MsgId, const MCSubtargetInfo &STI, bool Strict = true);
657 
658 LLVM_READNONE
659 bool isValidMsgOp(int64_t MsgId, int64_t OpId, const MCSubtargetInfo &STI,
660                   bool Strict = true);
661 
662 LLVM_READNONE
663 bool isValidMsgStream(int64_t MsgId, int64_t OpId, int64_t StreamId,
664                       const MCSubtargetInfo &STI, bool Strict = true);
665 
666 LLVM_READNONE
667 bool msgRequiresOp(int64_t MsgId);
668 
669 LLVM_READNONE
670 bool msgSupportsStream(int64_t MsgId, int64_t OpId);
671 
672 void decodeMsg(unsigned Val,
673                uint16_t &MsgId,
674                uint16_t &OpId,
675                uint16_t &StreamId);
676 
677 LLVM_READNONE
678 uint64_t encodeMsg(uint64_t MsgId,
679                    uint64_t OpId,
680                    uint64_t StreamId);
681 
682 } // namespace SendMsg
683 
684 
685 unsigned getInitialPSInputAddr(const Function &F);
686 
687 LLVM_READNONE
688 bool isShader(CallingConv::ID CC);
689 
690 LLVM_READNONE
691 bool isGraphics(CallingConv::ID CC);
692 
693 LLVM_READNONE
694 bool isCompute(CallingConv::ID CC);
695 
696 LLVM_READNONE
697 bool isEntryFunctionCC(CallingConv::ID CC);
698 
699 // These functions are considered entrypoints into the current module, i.e. they
700 // are allowed to be called from outside the current module. This is different
701 // from isEntryFunctionCC, which is only true for functions that are entered by
702 // the hardware. Module entry points include all entry functions but also
703 // include functions that can be called from other functions inside or outside
704 // the current module. Module entry functions are allowed to allocate LDS.
705 LLVM_READNONE
706 bool isModuleEntryFunctionCC(CallingConv::ID CC);
707 
708 // FIXME: Remove this when calling conventions cleaned up
709 LLVM_READNONE
710 inline bool isKernel(CallingConv::ID CC) {
711   switch (CC) {
712   case CallingConv::AMDGPU_KERNEL:
713   case CallingConv::SPIR_KERNEL:
714     return true;
715   default:
716     return false;
717   }
718 }
719 
720 bool hasXNACK(const MCSubtargetInfo &STI);
721 bool hasSRAMECC(const MCSubtargetInfo &STI);
722 bool hasMIMG_R128(const MCSubtargetInfo &STI);
723 bool hasGFX10A16(const MCSubtargetInfo &STI);
724 bool hasG16(const MCSubtargetInfo &STI);
725 bool hasPackedD16(const MCSubtargetInfo &STI);
726 
727 bool isSI(const MCSubtargetInfo &STI);
728 bool isCI(const MCSubtargetInfo &STI);
729 bool isVI(const MCSubtargetInfo &STI);
730 bool isGFX9(const MCSubtargetInfo &STI);
731 bool isGFX9Plus(const MCSubtargetInfo &STI);
732 bool isGFX10(const MCSubtargetInfo &STI);
733 bool isGFX10Plus(const MCSubtargetInfo &STI);
734 bool isGCN3Encoding(const MCSubtargetInfo &STI);
735 bool isGFX10_BEncoding(const MCSubtargetInfo &STI);
736 bool hasGFX10_3Insts(const MCSubtargetInfo &STI);
737 bool isGFX90A(const MCSubtargetInfo &STI);
738 
739 /// Is Reg - scalar register
740 bool isSGPR(unsigned Reg, const MCRegisterInfo* TRI);
741 
742 /// Is there any intersection between registers
743 bool isRegIntersect(unsigned Reg0, unsigned Reg1, const MCRegisterInfo* TRI);
744 
745 /// If \p Reg is a pseudo reg, return the correct hardware register given
746 /// \p STI otherwise return \p Reg.
747 unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI);
748 
749 /// Convert hardware register \p Reg to a pseudo register
750 LLVM_READNONE
751 unsigned mc2PseudoReg(unsigned Reg);
752 
753 /// Can this operand also contain immediate values?
754 bool isSISrcOperand(const MCInstrDesc &Desc, unsigned OpNo);
755 
756 /// Is this floating-point operand?
757 bool isSISrcFPOperand(const MCInstrDesc &Desc, unsigned OpNo);
758 
759 /// Does this opearnd support only inlinable literals?
760 bool isSISrcInlinableOperand(const MCInstrDesc &Desc, unsigned OpNo);
761 
762 /// Get the size in bits of a register from the register class \p RC.
763 unsigned getRegBitWidth(unsigned RCID);
764 
765 /// Get the size in bits of a register from the register class \p RC.
766 unsigned getRegBitWidth(const MCRegisterClass &RC);
767 
768 /// Get size of register operand
769 unsigned getRegOperandSize(const MCRegisterInfo *MRI, const MCInstrDesc &Desc,
770                            unsigned OpNo);
771 
772 LLVM_READNONE
773 inline unsigned getOperandSize(const MCOperandInfo &OpInfo) {
774   switch (OpInfo.OperandType) {
775   case AMDGPU::OPERAND_REG_IMM_INT32:
776   case AMDGPU::OPERAND_REG_IMM_FP32:
777   case AMDGPU::OPERAND_REG_INLINE_C_INT32:
778   case AMDGPU::OPERAND_REG_INLINE_C_FP32:
779   case AMDGPU::OPERAND_REG_INLINE_AC_INT32:
780   case AMDGPU::OPERAND_REG_INLINE_AC_FP32:
781   case AMDGPU::OPERAND_REG_IMM_V2INT32:
782   case AMDGPU::OPERAND_REG_IMM_V2FP32:
783   case AMDGPU::OPERAND_REG_INLINE_C_V2INT32:
784   case AMDGPU::OPERAND_REG_INLINE_C_V2FP32:
785     return 4;
786 
787   case AMDGPU::OPERAND_REG_IMM_INT64:
788   case AMDGPU::OPERAND_REG_IMM_FP64:
789   case AMDGPU::OPERAND_REG_INLINE_C_INT64:
790   case AMDGPU::OPERAND_REG_INLINE_C_FP64:
791   case AMDGPU::OPERAND_REG_INLINE_AC_FP64:
792     return 8;
793 
794   case AMDGPU::OPERAND_REG_IMM_INT16:
795   case AMDGPU::OPERAND_REG_IMM_FP16:
796   case AMDGPU::OPERAND_REG_INLINE_C_INT16:
797   case AMDGPU::OPERAND_REG_INLINE_C_FP16:
798   case AMDGPU::OPERAND_REG_INLINE_C_V2INT16:
799   case AMDGPU::OPERAND_REG_INLINE_C_V2FP16:
800   case AMDGPU::OPERAND_REG_INLINE_AC_INT16:
801   case AMDGPU::OPERAND_REG_INLINE_AC_FP16:
802   case AMDGPU::OPERAND_REG_INLINE_AC_V2INT16:
803   case AMDGPU::OPERAND_REG_INLINE_AC_V2FP16:
804   case AMDGPU::OPERAND_REG_IMM_V2INT16:
805   case AMDGPU::OPERAND_REG_IMM_V2FP16:
806     return 2;
807 
808   default:
809     llvm_unreachable("unhandled operand type");
810   }
811 }
812 
813 LLVM_READNONE
814 inline unsigned getOperandSize(const MCInstrDesc &Desc, unsigned OpNo) {
815   return getOperandSize(Desc.OpInfo[OpNo]);
816 }
817 
818 /// Is this literal inlinable, and not one of the values intended for floating
819 /// point values.
820 LLVM_READNONE
821 inline bool isInlinableIntLiteral(int64_t Literal) {
822   return Literal >= -16 && Literal <= 64;
823 }
824 
825 /// Is this literal inlinable
826 LLVM_READNONE
827 bool isInlinableLiteral64(int64_t Literal, bool HasInv2Pi);
828 
829 LLVM_READNONE
830 bool isInlinableLiteral32(int32_t Literal, bool HasInv2Pi);
831 
832 LLVM_READNONE
833 bool isInlinableLiteral16(int16_t Literal, bool HasInv2Pi);
834 
835 LLVM_READNONE
836 bool isInlinableLiteralV216(int32_t Literal, bool HasInv2Pi);
837 
838 LLVM_READNONE
839 bool isInlinableIntLiteralV216(int32_t Literal);
840 
841 LLVM_READNONE
842 bool isFoldableLiteralV216(int32_t Literal, bool HasInv2Pi);
843 
844 bool isArgPassedInSGPR(const Argument *Arg);
845 
846 LLVM_READONLY
847 bool isLegalSMRDEncodedUnsignedOffset(const MCSubtargetInfo &ST,
848                                       int64_t EncodedOffset);
849 
850 LLVM_READONLY
851 bool isLegalSMRDEncodedSignedOffset(const MCSubtargetInfo &ST,
852                                     int64_t EncodedOffset,
853                                     bool IsBuffer);
854 
855 /// Convert \p ByteOffset to dwords if the subtarget uses dword SMRD immediate
856 /// offsets.
857 uint64_t convertSMRDOffsetUnits(const MCSubtargetInfo &ST, uint64_t ByteOffset);
858 
859 /// \returns The encoding that will be used for \p ByteOffset in the
860 /// SMRD offset field, or None if it won't fit. On GFX9 and GFX10
861 /// S_LOAD instructions have a signed offset, on other subtargets it is
862 /// unsigned. S_BUFFER has an unsigned offset for all subtargets.
863 Optional<int64_t> getSMRDEncodedOffset(const MCSubtargetInfo &ST,
864                                        int64_t ByteOffset, bool IsBuffer);
865 
866 /// \return The encoding that can be used for a 32-bit literal offset in an SMRD
867 /// instruction. This is only useful on CI.s
868 Optional<int64_t> getSMRDEncodedLiteralOffset32(const MCSubtargetInfo &ST,
869                                                 int64_t ByteOffset);
870 
871 /// For FLAT segment the offset must be positive;
872 /// MSB is ignored and forced to zero.
873 ///
874 /// \return The number of bits available for the offset field in flat
875 /// instructions.
876 unsigned getNumFlatOffsetBits(const MCSubtargetInfo &ST, bool Signed);
877 
878 /// \returns true if this offset is small enough to fit in the SMRD
879 /// offset field.  \p ByteOffset should be the offset in bytes and
880 /// not the encoded offset.
881 bool isLegalSMRDImmOffset(const MCSubtargetInfo &ST, int64_t ByteOffset);
882 
883 bool splitMUBUFOffset(uint32_t Imm, uint32_t &SOffset, uint32_t &ImmOffset,
884                       const GCNSubtarget *Subtarget,
885                       Align Alignment = Align(4));
886 
887 LLVM_READNONE
888 inline bool isLegal64BitDPPControl(unsigned DC) {
889   return DC >= DPP::ROW_NEWBCAST_FIRST && DC <= DPP::ROW_NEWBCAST_LAST;
890 }
891 
892 /// \returns true if the intrinsic is divergent
893 bool isIntrinsicSourceOfDivergence(unsigned IntrID);
894 
895 // Track defaults for fields in the MODE registser.
896 struct SIModeRegisterDefaults {
897   /// Floating point opcodes that support exception flag gathering quiet and
898   /// propagate signaling NaN inputs per IEEE 754-2008. Min_dx10 and max_dx10
899   /// become IEEE 754- 2008 compliant due to signaling NaN propagation and
900   /// quieting.
901   bool IEEE : 1;
902 
903   /// Used by the vector ALU to force DX10-style treatment of NaNs: when set,
904   /// clamp NaN to zero; otherwise, pass NaN through.
905   bool DX10Clamp : 1;
906 
907   /// If this is set, neither input or output denormals are flushed for most f32
908   /// instructions.
909   bool FP32InputDenormals : 1;
910   bool FP32OutputDenormals : 1;
911 
912   /// If this is set, neither input or output denormals are flushed for both f64
913   /// and f16/v2f16 instructions.
914   bool FP64FP16InputDenormals : 1;
915   bool FP64FP16OutputDenormals : 1;
916 
917   SIModeRegisterDefaults() :
918     IEEE(true),
919     DX10Clamp(true),
920     FP32InputDenormals(true),
921     FP32OutputDenormals(true),
922     FP64FP16InputDenormals(true),
923     FP64FP16OutputDenormals(true) {}
924 
925   SIModeRegisterDefaults(const Function &F);
926 
927   static SIModeRegisterDefaults getDefaultForCallingConv(CallingConv::ID CC) {
928     SIModeRegisterDefaults Mode;
929     Mode.IEEE = !AMDGPU::isShader(CC);
930     return Mode;
931   }
932 
933   bool operator ==(const SIModeRegisterDefaults Other) const {
934     return IEEE == Other.IEEE && DX10Clamp == Other.DX10Clamp &&
935            FP32InputDenormals == Other.FP32InputDenormals &&
936            FP32OutputDenormals == Other.FP32OutputDenormals &&
937            FP64FP16InputDenormals == Other.FP64FP16InputDenormals &&
938            FP64FP16OutputDenormals == Other.FP64FP16OutputDenormals;
939   }
940 
941   bool allFP32Denormals() const {
942     return FP32InputDenormals && FP32OutputDenormals;
943   }
944 
945   bool allFP64FP16Denormals() const {
946     return FP64FP16InputDenormals && FP64FP16OutputDenormals;
947   }
948 
949   /// Get the encoding value for the FP_DENORM bits of the mode register for the
950   /// FP32 denormal mode.
951   uint32_t fpDenormModeSPValue() const {
952     if (FP32InputDenormals && FP32OutputDenormals)
953       return FP_DENORM_FLUSH_NONE;
954     if (FP32InputDenormals)
955       return FP_DENORM_FLUSH_OUT;
956     if (FP32OutputDenormals)
957       return FP_DENORM_FLUSH_IN;
958     return FP_DENORM_FLUSH_IN_FLUSH_OUT;
959   }
960 
961   /// Get the encoding value for the FP_DENORM bits of the mode register for the
962   /// FP64/FP16 denormal mode.
963   uint32_t fpDenormModeDPValue() const {
964     if (FP64FP16InputDenormals && FP64FP16OutputDenormals)
965       return FP_DENORM_FLUSH_NONE;
966     if (FP64FP16InputDenormals)
967       return FP_DENORM_FLUSH_OUT;
968     if (FP64FP16OutputDenormals)
969       return FP_DENORM_FLUSH_IN;
970     return FP_DENORM_FLUSH_IN_FLUSH_OUT;
971   }
972 
973   /// Returns true if a flag is compatible if it's enabled in the callee, but
974   /// disabled in the caller.
975   static bool oneWayCompatible(bool CallerMode, bool CalleeMode) {
976     return CallerMode == CalleeMode || (!CallerMode && CalleeMode);
977   }
978 
979   // FIXME: Inlining should be OK for dx10-clamp, since the caller's mode should
980   // be able to override.
981   bool isInlineCompatible(SIModeRegisterDefaults CalleeMode) const {
982     if (DX10Clamp != CalleeMode.DX10Clamp)
983       return false;
984     if (IEEE != CalleeMode.IEEE)
985       return false;
986 
987     // Allow inlining denormals enabled into denormals flushed functions.
988     return oneWayCompatible(FP64FP16InputDenormals, CalleeMode.FP64FP16InputDenormals) &&
989            oneWayCompatible(FP64FP16OutputDenormals, CalleeMode.FP64FP16OutputDenormals) &&
990            oneWayCompatible(FP32InputDenormals, CalleeMode.FP32InputDenormals) &&
991            oneWayCompatible(FP32OutputDenormals, CalleeMode.FP32OutputDenormals);
992   }
993 };
994 
995 } // end namespace AMDGPU
996 
997 raw_ostream &operator<<(raw_ostream &OS,
998                         const AMDGPU::IsaInfo::TargetIDSetting S);
999 
1000 } // end namespace llvm
1001 
1002 #endif // LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
1003