1 //===-- AMDGPUBaseInfo.cpp - AMDGPU Base encoding information--------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 #include "AMDGPUBaseInfo.h"
10 #include "AMDGPU.h"
11 #include "SIDefines.h"
12 #include "llvm/IR/LLVMContext.h"
13 #include "llvm/IR/Function.h"
14 #include "llvm/IR/GlobalValue.h"
15 #include "llvm/MC/MCContext.h"
16 #include "llvm/MC/MCInstrInfo.h"
17 #include "llvm/MC/MCRegisterInfo.h"
18 #include "llvm/MC/MCSectionELF.h"
19 #include "llvm/MC/MCSubtargetInfo.h"
20 #include "llvm/MC/SubtargetFeature.h"
21 
22 #define GET_SUBTARGETINFO_ENUM
23 #include "AMDGPUGenSubtargetInfo.inc"
24 #undef GET_SUBTARGETINFO_ENUM
25 
26 #define GET_REGINFO_ENUM
27 #include "AMDGPUGenRegisterInfo.inc"
28 #undef GET_REGINFO_ENUM
29 
30 #define GET_INSTRINFO_NAMED_OPS
31 #define GET_INSTRINFO_ENUM
32 #include "AMDGPUGenInstrInfo.inc"
33 #undef GET_INSTRINFO_NAMED_OPS
34 #undef GET_INSTRINFO_ENUM
35 
36 namespace {
37 
38 /// \returns Bit mask for given bit \p Shift and bit \p Width.
39 unsigned getBitMask(unsigned Shift, unsigned Width) {
40   return ((1 << Width) - 1) << Shift;
41 }
42 
43 /// \brief Packs \p Src into \p Dst for given bit \p Shift and bit \p Width.
44 ///
45 /// \returns Packed \p Dst.
46 unsigned packBits(unsigned Src, unsigned Dst, unsigned Shift, unsigned Width) {
47   Dst &= ~(1 << Shift) & ~getBitMask(Shift, Width);
48   Dst |= (Src << Shift) & getBitMask(Shift, Width);
49   return Dst;
50 }
51 
52 /// \brief Unpacks bits from \p Src for given bit \p Shift and bit \p Width.
53 ///
54 /// \returns Unpacked bits.
55 unsigned unpackBits(unsigned Src, unsigned Shift, unsigned Width) {
56   return (Src & getBitMask(Shift, Width)) >> Shift;
57 }
58 
59 /// \returns Vmcnt bit shift.
60 unsigned getVmcntBitShift() { return 0; }
61 
62 /// \returns Vmcnt bit width.
63 unsigned getVmcntBitWidth() { return 4; }
64 
65 /// \returns Expcnt bit shift.
66 unsigned getExpcntBitShift() { return 4; }
67 
68 /// \returns Expcnt bit width.
69 unsigned getExpcntBitWidth() { return 3; }
70 
71 /// \returns Lgkmcnt bit shift.
72 unsigned getLgkmcntBitShift() { return 8; }
73 
74 /// \returns Lgkmcnt bit width.
75 unsigned getLgkmcntBitWidth() { return 4; }
76 
77 } // anonymous namespace
78 
79 namespace llvm {
80 namespace AMDGPU {
81 
82 IsaVersion getIsaVersion(const FeatureBitset &Features) {
83 
84   if (Features.test(FeatureISAVersion7_0_0))
85     return {7, 0, 0};
86 
87   if (Features.test(FeatureISAVersion7_0_1))
88     return {7, 0, 1};
89 
90   if (Features.test(FeatureISAVersion8_0_0))
91     return {8, 0, 0};
92 
93   if (Features.test(FeatureISAVersion8_0_1))
94     return {8, 0, 1};
95 
96   if (Features.test(FeatureISAVersion8_0_2))
97     return {8, 0, 2};
98 
99   if (Features.test(FeatureISAVersion8_0_3))
100     return {8, 0, 3};
101 
102   return {0, 0, 0};
103 }
104 
105 void initDefaultAMDKernelCodeT(amd_kernel_code_t &Header,
106                                const FeatureBitset &Features) {
107 
108   IsaVersion ISA = getIsaVersion(Features);
109 
110   memset(&Header, 0, sizeof(Header));
111 
112   Header.amd_kernel_code_version_major = 1;
113   Header.amd_kernel_code_version_minor = 0;
114   Header.amd_machine_kind = 1; // AMD_MACHINE_KIND_AMDGPU
115   Header.amd_machine_version_major = ISA.Major;
116   Header.amd_machine_version_minor = ISA.Minor;
117   Header.amd_machine_version_stepping = ISA.Stepping;
118   Header.kernel_code_entry_byte_offset = sizeof(Header);
119   // wavefront_size is specified as a power of 2: 2^6 = 64 threads.
120   Header.wavefront_size = 6;
121   // These alignment values are specified in powers of two, so alignment =
122   // 2^n.  The minimum alignment is 2^4 = 16.
123   Header.kernarg_segment_alignment = 4;
124   Header.group_segment_alignment = 4;
125   Header.private_segment_alignment = 4;
126 }
127 
128 MCSection *getHSATextSection(MCContext &Ctx) {
129   return Ctx.getELFSection(".hsatext", ELF::SHT_PROGBITS,
130                            ELF::SHF_ALLOC | ELF::SHF_WRITE |
131                            ELF::SHF_EXECINSTR |
132                            ELF::SHF_AMDGPU_HSA_AGENT |
133                            ELF::SHF_AMDGPU_HSA_CODE);
134 }
135 
136 MCSection *getHSADataGlobalAgentSection(MCContext &Ctx) {
137   return Ctx.getELFSection(".hsadata_global_agent", ELF::SHT_PROGBITS,
138                            ELF::SHF_ALLOC | ELF::SHF_WRITE |
139                            ELF::SHF_AMDGPU_HSA_GLOBAL |
140                            ELF::SHF_AMDGPU_HSA_AGENT);
141 }
142 
143 MCSection *getHSADataGlobalProgramSection(MCContext &Ctx) {
144   return  Ctx.getELFSection(".hsadata_global_program", ELF::SHT_PROGBITS,
145                             ELF::SHF_ALLOC | ELF::SHF_WRITE |
146                             ELF::SHF_AMDGPU_HSA_GLOBAL);
147 }
148 
149 MCSection *getHSARodataReadonlyAgentSection(MCContext &Ctx) {
150   return Ctx.getELFSection(".hsarodata_readonly_agent", ELF::SHT_PROGBITS,
151                            ELF::SHF_ALLOC | ELF::SHF_AMDGPU_HSA_READONLY |
152                            ELF::SHF_AMDGPU_HSA_AGENT);
153 }
154 
155 bool isGroupSegment(const GlobalValue *GV) {
156   return GV->getType()->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS;
157 }
158 
159 bool isGlobalSegment(const GlobalValue *GV) {
160   return GV->getType()->getAddressSpace() == AMDGPUAS::GLOBAL_ADDRESS;
161 }
162 
163 bool isReadOnlySegment(const GlobalValue *GV) {
164   return GV->getType()->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS;
165 }
166 
167 bool shouldEmitConstantsToTextSection(const Triple &TT) {
168   return TT.getOS() != Triple::AMDHSA;
169 }
170 
171 int getIntegerAttribute(const Function &F, StringRef Name, int Default) {
172   Attribute A = F.getFnAttribute(Name);
173   int Result = Default;
174 
175   if (A.isStringAttribute()) {
176     StringRef Str = A.getValueAsString();
177     if (Str.getAsInteger(0, Result)) {
178       LLVMContext &Ctx = F.getContext();
179       Ctx.emitError("can't parse integer attribute " + Name);
180     }
181   }
182 
183   return Result;
184 }
185 
186 std::pair<int, int> getIntegerPairAttribute(const Function &F,
187                                             StringRef Name,
188                                             std::pair<int, int> Default,
189                                             bool OnlyFirstRequired) {
190   Attribute A = F.getFnAttribute(Name);
191   if (!A.isStringAttribute())
192     return Default;
193 
194   LLVMContext &Ctx = F.getContext();
195   std::pair<int, int> Ints = Default;
196   std::pair<StringRef, StringRef> Strs = A.getValueAsString().split(',');
197   if (Strs.first.trim().getAsInteger(0, Ints.first)) {
198     Ctx.emitError("can't parse first integer attribute " + Name);
199     return Default;
200   }
201   if (Strs.second.trim().getAsInteger(0, Ints.second)) {
202     if (!OnlyFirstRequired || Strs.second.trim().size()) {
203       Ctx.emitError("can't parse second integer attribute " + Name);
204       return Default;
205     }
206   }
207 
208   return Ints;
209 }
210 
211 unsigned getWaitcntBitMask(IsaVersion Version) {
212   unsigned Vmcnt = getBitMask(getVmcntBitShift(), getVmcntBitWidth());
213   unsigned Expcnt = getBitMask(getExpcntBitShift(), getExpcntBitWidth());
214   unsigned Lgkmcnt = getBitMask(getLgkmcntBitShift(), getLgkmcntBitWidth());
215   return Vmcnt | Expcnt | Lgkmcnt;
216 }
217 
218 unsigned getVmcntBitMask(IsaVersion Version) {
219   return (1 << getVmcntBitWidth()) - 1;
220 }
221 
222 unsigned getExpcntBitMask(IsaVersion Version) {
223   return (1 << getExpcntBitWidth()) - 1;
224 }
225 
226 unsigned getLgkmcntBitMask(IsaVersion Version) {
227   return (1 << getLgkmcntBitWidth()) - 1;
228 }
229 
230 unsigned decodeVmcnt(IsaVersion Version, unsigned Waitcnt) {
231   return unpackBits(Waitcnt, getVmcntBitShift(), getVmcntBitWidth());
232 }
233 
234 unsigned decodeExpcnt(IsaVersion Version, unsigned Waitcnt) {
235   return unpackBits(Waitcnt, getExpcntBitShift(), getExpcntBitWidth());
236 }
237 
238 unsigned decodeLgkmcnt(IsaVersion Version, unsigned Waitcnt) {
239   return unpackBits(Waitcnt, getLgkmcntBitShift(), getLgkmcntBitWidth());
240 }
241 
242 void decodeWaitcnt(IsaVersion Version, unsigned Waitcnt,
243                    unsigned &Vmcnt, unsigned &Expcnt, unsigned &Lgkmcnt) {
244   Vmcnt = decodeVmcnt(Version, Waitcnt);
245   Expcnt = decodeExpcnt(Version, Waitcnt);
246   Lgkmcnt = decodeLgkmcnt(Version, Waitcnt);
247 }
248 
249 unsigned encodeVmcnt(IsaVersion Version, unsigned Waitcnt, unsigned Vmcnt) {
250   return packBits(Vmcnt, Waitcnt, getVmcntBitShift(), getVmcntBitWidth());
251 }
252 
253 unsigned encodeExpcnt(IsaVersion Version, unsigned Waitcnt, unsigned Expcnt) {
254   return packBits(Expcnt, Waitcnt, getExpcntBitShift(), getExpcntBitWidth());
255 }
256 
257 unsigned encodeLgkmcnt(IsaVersion Version, unsigned Waitcnt, unsigned Lgkmcnt) {
258   return packBits(Lgkmcnt, Waitcnt, getLgkmcntBitShift(), getLgkmcntBitWidth());
259 }
260 
261 unsigned encodeWaitcnt(IsaVersion Version,
262                        unsigned Vmcnt, unsigned Expcnt, unsigned Lgkmcnt) {
263   unsigned Waitcnt = getWaitcntBitMask(Version);;
264   Waitcnt = encodeVmcnt(Version, Waitcnt, Vmcnt);
265   Waitcnt = encodeExpcnt(Version, Waitcnt, Expcnt);
266   Waitcnt = encodeLgkmcnt(Version, Waitcnt, Lgkmcnt);
267   return Waitcnt;
268 }
269 
270 unsigned getInitialPSInputAddr(const Function &F) {
271   return getIntegerAttribute(F, "InitialPSInputAddr", 0);
272 }
273 
274 bool isShader(CallingConv::ID cc) {
275   switch(cc) {
276     case CallingConv::AMDGPU_VS:
277     case CallingConv::AMDGPU_GS:
278     case CallingConv::AMDGPU_PS:
279     case CallingConv::AMDGPU_CS:
280       return true;
281     default:
282       return false;
283   }
284 }
285 
286 bool isCompute(CallingConv::ID cc) {
287   return !isShader(cc) || cc == CallingConv::AMDGPU_CS;
288 }
289 
290 bool isSI(const MCSubtargetInfo &STI) {
291   return STI.getFeatureBits()[AMDGPU::FeatureSouthernIslands];
292 }
293 
294 bool isCI(const MCSubtargetInfo &STI) {
295   return STI.getFeatureBits()[AMDGPU::FeatureSeaIslands];
296 }
297 
298 bool isVI(const MCSubtargetInfo &STI) {
299   return STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands];
300 }
301 
302 unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI) {
303 
304   switch(Reg) {
305   default: break;
306   case AMDGPU::FLAT_SCR:
307     assert(!isSI(STI));
308     return isCI(STI) ? AMDGPU::FLAT_SCR_ci : AMDGPU::FLAT_SCR_vi;
309 
310   case AMDGPU::FLAT_SCR_LO:
311     assert(!isSI(STI));
312     return isCI(STI) ? AMDGPU::FLAT_SCR_LO_ci : AMDGPU::FLAT_SCR_LO_vi;
313 
314   case AMDGPU::FLAT_SCR_HI:
315     assert(!isSI(STI));
316     return isCI(STI) ? AMDGPU::FLAT_SCR_HI_ci : AMDGPU::FLAT_SCR_HI_vi;
317   }
318   return Reg;
319 }
320 
321 bool isSISrcOperand(const MCInstrDesc &Desc, unsigned OpNo) {
322   unsigned OpType = Desc.OpInfo[OpNo].OperandType;
323 
324   return OpType == AMDGPU::OPERAND_REG_IMM32_INT ||
325          OpType == AMDGPU::OPERAND_REG_IMM32_FP ||
326          OpType == AMDGPU::OPERAND_REG_INLINE_C_INT ||
327          OpType == AMDGPU::OPERAND_REG_INLINE_C_FP;
328 }
329 
330 bool isSISrcFPOperand(const MCInstrDesc &Desc, unsigned OpNo) {
331   unsigned OpType = Desc.OpInfo[OpNo].OperandType;
332 
333   return OpType == AMDGPU::OPERAND_REG_IMM32_FP ||
334          OpType == AMDGPU::OPERAND_REG_INLINE_C_FP;
335 }
336 
337 bool isSISrcInlinableOperand(const MCInstrDesc &Desc, unsigned OpNo) {
338   unsigned OpType = Desc.OpInfo[OpNo].OperandType;
339 
340   return OpType == AMDGPU::OPERAND_REG_INLINE_C_INT ||
341          OpType == AMDGPU::OPERAND_REG_INLINE_C_FP;
342 }
343 
344 // Avoid using MCRegisterClass::getSize, since that function will go away
345 // (move from MC* level to Target* level). Return size in bits.
346 unsigned getRegBitWidth(const MCRegisterClass &RC) {
347   switch (RC.getID()) {
348   case AMDGPU::SGPR_32RegClassID:
349   case AMDGPU::VGPR_32RegClassID:
350   case AMDGPU::VS_32RegClassID:
351   case AMDGPU::SReg_32RegClassID:
352   case AMDGPU::SReg_32_XM0RegClassID:
353     return 32;
354   case AMDGPU::SGPR_64RegClassID:
355   case AMDGPU::VS_64RegClassID:
356   case AMDGPU::SReg_64RegClassID:
357   case AMDGPU::VReg_64RegClassID:
358     return 64;
359   case AMDGPU::VReg_96RegClassID:
360     return 96;
361   case AMDGPU::SGPR_128RegClassID:
362   case AMDGPU::SReg_128RegClassID:
363   case AMDGPU::VReg_128RegClassID:
364     return 128;
365   case AMDGPU::SReg_256RegClassID:
366   case AMDGPU::VReg_256RegClassID:
367     return 256;
368   case AMDGPU::SReg_512RegClassID:
369   case AMDGPU::VReg_512RegClassID:
370     return 512;
371   default:
372     llvm_unreachable("Unexpected register class");
373   }
374 }
375 
376 unsigned getRegOperandSize(const MCRegisterInfo *MRI, const MCInstrDesc &Desc,
377                            unsigned OpNo) {
378   unsigned RCID = Desc.OpInfo[OpNo].RegClass;
379   return getRegBitWidth(MRI->getRegClass(RCID)) / 8;
380 }
381 
382 bool isInlinableLiteral64(int64_t Literal, bool IsVI) {
383   if (Literal >= -16 && Literal <= 64)
384     return true;
385 
386   double D = BitsToDouble(Literal);
387 
388   if (D == 0.5 || D == -0.5 ||
389       D == 1.0 || D == -1.0 ||
390       D == 2.0 || D == -2.0 ||
391       D == 4.0 || D == -4.0)
392     return true;
393 
394   if (IsVI && Literal == 0x3fc45f306dc9c882)
395     return true;
396 
397   return false;
398 }
399 
400 bool isInlinableLiteral32(int32_t Literal, bool IsVI) {
401   if (Literal >= -16 && Literal <= 64)
402     return true;
403 
404   float F = BitsToFloat(Literal);
405 
406   if (F == 0.5 || F == -0.5 ||
407       F == 1.0 || F == -1.0 ||
408       F == 2.0 || F == -2.0 ||
409       F == 4.0 || F == -4.0)
410     return true;
411 
412   if (IsVI && Literal == 0x3e22f983)
413     return true;
414 
415   return false;
416 }
417 
418 
419 } // End namespace AMDGPU
420 } // End namespace llvm
421