1 //===-- AMDGPUBaseInfo.cpp - AMDGPU Base encoding information--------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 #include "AMDGPUBaseInfo.h" 10 #include "llvm/MC/MCContext.h" 11 #include "llvm/MC/MCSectionELF.h" 12 #include "llvm/MC/SubtargetFeature.h" 13 14 #define GET_SUBTARGETINFO_ENUM 15 #include "AMDGPUGenSubtargetInfo.inc" 16 #undef GET_SUBTARGETINFO_ENUM 17 18 namespace llvm { 19 namespace AMDGPU { 20 21 IsaVersion getIsaVersion(const FeatureBitset &Features) { 22 23 if (Features.test(FeatureISAVersion7_0_0)) 24 return {7, 0, 0}; 25 26 if (Features.test(FeatureISAVersion7_0_1)) 27 return {7, 0, 1}; 28 29 if (Features.test(FeatureISAVersion8_0_0)) 30 return {8, 0, 0}; 31 32 if (Features.test(FeatureISAVersion8_0_1)) 33 return {8, 0, 1}; 34 35 return {0, 0, 0}; 36 } 37 38 void initDefaultAMDKernelCodeT(amd_kernel_code_t &Header, 39 const FeatureBitset &Features) { 40 41 IsaVersion ISA = getIsaVersion(Features); 42 43 memset(&Header, 0, sizeof(Header)); 44 45 Header.amd_kernel_code_version_major = 1; 46 Header.amd_kernel_code_version_minor = 0; 47 Header.amd_machine_kind = 1; // AMD_MACHINE_KIND_AMDGPU 48 Header.amd_machine_version_major = ISA.Major; 49 Header.amd_machine_version_minor = ISA.Minor; 50 Header.amd_machine_version_stepping = ISA.Stepping; 51 Header.kernel_code_entry_byte_offset = sizeof(Header); 52 // wavefront_size is specified as a power of 2: 2^6 = 64 threads. 53 Header.wavefront_size = 6; 54 // These alignment values are specified in powers of two, so alignment = 55 // 2^n. The minimum alignment is 2^4 = 16. 56 Header.kernarg_segment_alignment = 4; 57 Header.group_segment_alignment = 4; 58 Header.private_segment_alignment = 4; 59 } 60 61 MCSection *getHSATextSection(MCContext &Ctx) { 62 return Ctx.getELFSection(".hsatext", ELF::SHT_PROGBITS, 63 ELF::SHF_ALLOC | ELF::SHF_WRITE | 64 ELF::SHF_EXECINSTR | 65 ELF::SHF_AMDGPU_HSA_AGENT | 66 ELF::SHF_AMDGPU_HSA_CODE); 67 } 68 69 } // End namespace AMDGPU 70 } // End namespace llvm 71