1 //===- AMDGPUBaseInfo.cpp - AMDGPU Base encoding information --------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
10 #include "AMDGPUBaseInfo.h"
11 #include "AMDGPU.h"
12 #include "SIDefines.h"
13 #include "llvm/ADT/StringRef.h"
14 #include "llvm/ADT/Triple.h"
15 #include "llvm/BinaryFormat/ELF.h"
16 #include "llvm/CodeGen/MachineMemOperand.h"
17 #include "llvm/IR/Attributes.h"
18 #include "llvm/IR/Constants.h"
19 #include "llvm/IR/Function.h"
20 #include "llvm/IR/GlobalValue.h"
21 #include "llvm/IR/Instruction.h"
22 #include "llvm/IR/LLVMContext.h"
23 #include "llvm/IR/Module.h"
24 #include "llvm/MC/MCContext.h"
25 #include "llvm/MC/MCInstrDesc.h"
26 #include "llvm/MC/MCInstrInfo.h"
27 #include "llvm/MC/MCRegisterInfo.h"
28 #include "llvm/MC/MCSectionELF.h"
29 #include "llvm/MC/MCSubtargetInfo.h"
30 #include "llvm/MC/SubtargetFeature.h"
31 #include "llvm/Support/Casting.h"
32 #include "llvm/Support/ErrorHandling.h"
33 #include "llvm/Support/MathExtras.h"
34 #include <algorithm>
35 #include <cassert>
36 #include <cstdint>
37 #include <cstring>
38 #include <utility>
39 
40 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
41 
42 #define GET_INSTRINFO_NAMED_OPS
43 #define GET_INSTRMAP_INFO
44 #include "AMDGPUGenInstrInfo.inc"
45 #undef GET_INSTRMAP_INFO
46 #undef GET_INSTRINFO_NAMED_OPS
47 
48 namespace {
49 
50 /// \returns Bit mask for given bit \p Shift and bit \p Width.
51 unsigned getBitMask(unsigned Shift, unsigned Width) {
52   return ((1 << Width) - 1) << Shift;
53 }
54 
55 /// \brief Packs \p Src into \p Dst for given bit \p Shift and bit \p Width.
56 ///
57 /// \returns Packed \p Dst.
58 unsigned packBits(unsigned Src, unsigned Dst, unsigned Shift, unsigned Width) {
59   Dst &= ~(1 << Shift) & ~getBitMask(Shift, Width);
60   Dst |= (Src << Shift) & getBitMask(Shift, Width);
61   return Dst;
62 }
63 
64 /// \brief Unpacks bits from \p Src for given bit \p Shift and bit \p Width.
65 ///
66 /// \returns Unpacked bits.
67 unsigned unpackBits(unsigned Src, unsigned Shift, unsigned Width) {
68   return (Src & getBitMask(Shift, Width)) >> Shift;
69 }
70 
71 /// \returns Vmcnt bit shift (lower bits).
72 unsigned getVmcntBitShiftLo() { return 0; }
73 
74 /// \returns Vmcnt bit width (lower bits).
75 unsigned getVmcntBitWidthLo() { return 4; }
76 
77 /// \returns Expcnt bit shift.
78 unsigned getExpcntBitShift() { return 4; }
79 
80 /// \returns Expcnt bit width.
81 unsigned getExpcntBitWidth() { return 3; }
82 
83 /// \returns Lgkmcnt bit shift.
84 unsigned getLgkmcntBitShift() { return 8; }
85 
86 /// \returns Lgkmcnt bit width.
87 unsigned getLgkmcntBitWidth() { return 4; }
88 
89 /// \returns Vmcnt bit shift (higher bits).
90 unsigned getVmcntBitShiftHi() { return 14; }
91 
92 /// \returns Vmcnt bit width (higher bits).
93 unsigned getVmcntBitWidthHi() { return 2; }
94 
95 } // end namespace anonymous
96 
97 namespace llvm {
98 
99 static cl::opt<bool> EnablePackedInlinableLiterals(
100     "enable-packed-inlinable-literals",
101     cl::desc("Enable packed inlinable literals (v2f16, v2i16)"),
102     cl::init(false));
103 
104 namespace AMDGPU {
105 
106 LLVM_READNONE
107 static inline Channels indexToChannel(unsigned Channel) {
108   switch (Channel) {
109   case 1:
110     return AMDGPU::Channels_1;
111   case 2:
112     return AMDGPU::Channels_2;
113   case 3:
114     return AMDGPU::Channels_3;
115   case 4:
116     return AMDGPU::Channels_4;
117   default:
118     llvm_unreachable("invalid MIMG channel");
119   }
120 }
121 
122 
123 // FIXME: Need to handle d16 images correctly.
124 static unsigned rcToChannels(unsigned RCID) {
125   switch (RCID) {
126   case AMDGPU::VGPR_32RegClassID:
127     return 1;
128   case AMDGPU::VReg_64RegClassID:
129     return 2;
130   case AMDGPU::VReg_96RegClassID:
131     return 3;
132   case AMDGPU::VReg_128RegClassID:
133     return 4;
134   default:
135     llvm_unreachable("invalid MIMG register class");
136   }
137 }
138 
139 int getMaskedMIMGOp(const MCInstrInfo &MII, unsigned Opc, unsigned NewChannels) {
140   AMDGPU::Channels Channel = AMDGPU::indexToChannel(NewChannels);
141   unsigned OrigChannels = rcToChannels(MII.get(Opc).OpInfo[0].RegClass);
142   if (NewChannels == OrigChannels)
143     return Opc;
144 
145   switch (OrigChannels) {
146   case 1:
147     return AMDGPU::getMaskedMIMGOp1(Opc, Channel);
148   case 2:
149     return AMDGPU::getMaskedMIMGOp2(Opc, Channel);
150   case 3:
151     return AMDGPU::getMaskedMIMGOp3(Opc, Channel);
152   case 4:
153     return AMDGPU::getMaskedMIMGOp4(Opc, Channel);
154   default:
155     llvm_unreachable("invalid MIMG channel");
156   }
157 }
158 
159 int getMaskedMIMGAtomicOp(const MCInstrInfo &MII, unsigned Opc, unsigned NewChannels) {
160   assert(AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdst) != -1);
161   assert(NewChannels == 1 || NewChannels == 2 || NewChannels == 4);
162 
163   unsigned OrigChannels = rcToChannels(MII.get(Opc).OpInfo[0].RegClass);
164   assert(OrigChannels == 1 || OrigChannels == 2 || OrigChannels == 4);
165 
166   if (NewChannels == OrigChannels) return Opc;
167 
168   if (OrigChannels <= 2 && NewChannels <= 2) {
169     // This is an ordinary atomic (not an atomic_cmpswap)
170     return (OrigChannels == 1)?
171       AMDGPU::getMIMGAtomicOp1(Opc) : AMDGPU::getMIMGAtomicOp2(Opc);
172   } else if (OrigChannels >= 2 && NewChannels >= 2) {
173     // This is an atomic_cmpswap
174     return (OrigChannels == 2)?
175       AMDGPU::getMIMGAtomicOp1(Opc) : AMDGPU::getMIMGAtomicOp2(Opc);
176   } else { // invalid OrigChannels/NewChannels value
177     return -1;
178   }
179 }
180 
181 // Wrapper for Tablegen'd function.  enum Subtarget is not defined in any
182 // header files, so we need to wrap it in a function that takes unsigned
183 // instead.
184 int getMCOpcode(uint16_t Opcode, unsigned Gen) {
185   return getMCOpcodeGen(Opcode, static_cast<Subtarget>(Gen));
186 }
187 
188 namespace IsaInfo {
189 
190 IsaVersion getIsaVersion(const FeatureBitset &Features) {
191   // GCN GFX6 (Southern Islands (SI)).
192   if (Features.test(FeatureISAVersion6_0_0))
193     return {6, 0, 0};
194   if (Features.test(FeatureISAVersion6_0_1))
195     return {6, 0, 1};
196 
197   // GCN GFX7 (Sea Islands (CI)).
198   if (Features.test(FeatureISAVersion7_0_0))
199     return {7, 0, 0};
200   if (Features.test(FeatureISAVersion7_0_1))
201     return {7, 0, 1};
202   if (Features.test(FeatureISAVersion7_0_2))
203     return {7, 0, 2};
204   if (Features.test(FeatureISAVersion7_0_3))
205     return {7, 0, 3};
206   if (Features.test(FeatureISAVersion7_0_4))
207     return {7, 0, 4};
208 
209   // GCN GFX8 (Volcanic Islands (VI)).
210   if (Features.test(FeatureISAVersion8_0_0))
211     return {8, 0, 0};
212   if (Features.test(FeatureISAVersion8_0_1))
213     return {8, 0, 1};
214   if (Features.test(FeatureISAVersion8_0_2))
215     return {8, 0, 2};
216   if (Features.test(FeatureISAVersion8_0_3))
217     return {8, 0, 3};
218   if (Features.test(FeatureISAVersion8_1_0))
219     return {8, 1, 0};
220 
221   // GCN GFX9.
222   if (Features.test(FeatureISAVersion9_0_0))
223     return {9, 0, 0};
224   if (Features.test(FeatureISAVersion9_0_2))
225     return {9, 0, 2};
226 
227   if (!Features.test(FeatureGCN) || Features.test(FeatureSouthernIslands))
228     return {0, 0, 0};
229   return {7, 0, 0};
230 }
231 
232 void streamIsaVersion(const MCSubtargetInfo *STI, raw_ostream &Stream) {
233   auto TargetTriple = STI->getTargetTriple();
234   auto ISAVersion = IsaInfo::getIsaVersion(STI->getFeatureBits());
235 
236   Stream << TargetTriple.getArchName() << '-'
237          << TargetTriple.getVendorName() << '-'
238          << TargetTriple.getOSName() << '-'
239          << TargetTriple.getEnvironmentName() << '-'
240          << "gfx"
241          << ISAVersion.Major
242          << ISAVersion.Minor
243          << ISAVersion.Stepping;
244   Stream.flush();
245 }
246 
247 bool hasCodeObjectV3(const FeatureBitset &Features) {
248   return Features.test(FeatureCodeObjectV3);
249 }
250 
251 unsigned getWavefrontSize(const FeatureBitset &Features) {
252   if (Features.test(FeatureWavefrontSize16))
253     return 16;
254   if (Features.test(FeatureWavefrontSize32))
255     return 32;
256 
257   return 64;
258 }
259 
260 unsigned getLocalMemorySize(const FeatureBitset &Features) {
261   if (Features.test(FeatureLocalMemorySize32768))
262     return 32768;
263   if (Features.test(FeatureLocalMemorySize65536))
264     return 65536;
265 
266   return 0;
267 }
268 
269 unsigned getEUsPerCU(const FeatureBitset &Features) {
270   return 4;
271 }
272 
273 unsigned getMaxWorkGroupsPerCU(const FeatureBitset &Features,
274                                unsigned FlatWorkGroupSize) {
275   if (!Features.test(FeatureGCN))
276     return 8;
277   unsigned N = getWavesPerWorkGroup(Features, FlatWorkGroupSize);
278   if (N == 1)
279     return 40;
280   N = 40 / N;
281   return std::min(N, 16u);
282 }
283 
284 unsigned getMaxWavesPerCU(const FeatureBitset &Features) {
285   return getMaxWavesPerEU(Features) * getEUsPerCU(Features);
286 }
287 
288 unsigned getMaxWavesPerCU(const FeatureBitset &Features,
289                           unsigned FlatWorkGroupSize) {
290   return getWavesPerWorkGroup(Features, FlatWorkGroupSize);
291 }
292 
293 unsigned getMinWavesPerEU(const FeatureBitset &Features) {
294   return 1;
295 }
296 
297 unsigned getMaxWavesPerEU(const FeatureBitset &Features) {
298   if (!Features.test(FeatureGCN))
299     return 8;
300   // FIXME: Need to take scratch memory into account.
301   return 10;
302 }
303 
304 unsigned getMaxWavesPerEU(const FeatureBitset &Features,
305                           unsigned FlatWorkGroupSize) {
306   return alignTo(getMaxWavesPerCU(Features, FlatWorkGroupSize),
307                  getEUsPerCU(Features)) / getEUsPerCU(Features);
308 }
309 
310 unsigned getMinFlatWorkGroupSize(const FeatureBitset &Features) {
311   return 1;
312 }
313 
314 unsigned getMaxFlatWorkGroupSize(const FeatureBitset &Features) {
315   return 2048;
316 }
317 
318 unsigned getWavesPerWorkGroup(const FeatureBitset &Features,
319                               unsigned FlatWorkGroupSize) {
320   return alignTo(FlatWorkGroupSize, getWavefrontSize(Features)) /
321                  getWavefrontSize(Features);
322 }
323 
324 unsigned getSGPRAllocGranule(const FeatureBitset &Features) {
325   IsaVersion Version = getIsaVersion(Features);
326   if (Version.Major >= 8)
327     return 16;
328   return 8;
329 }
330 
331 unsigned getSGPREncodingGranule(const FeatureBitset &Features) {
332   return 8;
333 }
334 
335 unsigned getTotalNumSGPRs(const FeatureBitset &Features) {
336   IsaVersion Version = getIsaVersion(Features);
337   if (Version.Major >= 8)
338     return 800;
339   return 512;
340 }
341 
342 unsigned getAddressableNumSGPRs(const FeatureBitset &Features) {
343   if (Features.test(FeatureSGPRInitBug))
344     return FIXED_NUM_SGPRS_FOR_INIT_BUG;
345 
346   IsaVersion Version = getIsaVersion(Features);
347   if (Version.Major >= 8)
348     return 102;
349   return 104;
350 }
351 
352 unsigned getMinNumSGPRs(const FeatureBitset &Features, unsigned WavesPerEU) {
353   assert(WavesPerEU != 0);
354 
355   if (WavesPerEU >= getMaxWavesPerEU(Features))
356     return 0;
357   unsigned MinNumSGPRs =
358       alignDown(getTotalNumSGPRs(Features) / (WavesPerEU + 1),
359                 getSGPRAllocGranule(Features)) + 1;
360   return std::min(MinNumSGPRs, getAddressableNumSGPRs(Features));
361 }
362 
363 unsigned getMaxNumSGPRs(const FeatureBitset &Features, unsigned WavesPerEU,
364                         bool Addressable) {
365   assert(WavesPerEU != 0);
366 
367   IsaVersion Version = getIsaVersion(Features);
368   unsigned MaxNumSGPRs = alignDown(getTotalNumSGPRs(Features) / WavesPerEU,
369                                    getSGPRAllocGranule(Features));
370   unsigned AddressableNumSGPRs = getAddressableNumSGPRs(Features);
371   if (Version.Major >= 8 && !Addressable)
372     AddressableNumSGPRs = 112;
373   return std::min(MaxNumSGPRs, AddressableNumSGPRs);
374 }
375 
376 unsigned getVGPRAllocGranule(const FeatureBitset &Features) {
377   return 4;
378 }
379 
380 unsigned getVGPREncodingGranule(const FeatureBitset &Features) {
381   return getVGPRAllocGranule(Features);
382 }
383 
384 unsigned getTotalNumVGPRs(const FeatureBitset &Features) {
385   return 256;
386 }
387 
388 unsigned getAddressableNumVGPRs(const FeatureBitset &Features) {
389   return getTotalNumVGPRs(Features);
390 }
391 
392 unsigned getMinNumVGPRs(const FeatureBitset &Features, unsigned WavesPerEU) {
393   assert(WavesPerEU != 0);
394 
395   if (WavesPerEU >= getMaxWavesPerEU(Features))
396     return 0;
397   unsigned MinNumVGPRs =
398       alignDown(getTotalNumVGPRs(Features) / (WavesPerEU + 1),
399                 getVGPRAllocGranule(Features)) + 1;
400   return std::min(MinNumVGPRs, getAddressableNumVGPRs(Features));
401 }
402 
403 unsigned getMaxNumVGPRs(const FeatureBitset &Features, unsigned WavesPerEU) {
404   assert(WavesPerEU != 0);
405 
406   unsigned MaxNumVGPRs = alignDown(getTotalNumVGPRs(Features) / WavesPerEU,
407                                    getVGPRAllocGranule(Features));
408   unsigned AddressableNumVGPRs = getAddressableNumVGPRs(Features);
409   return std::min(MaxNumVGPRs, AddressableNumVGPRs);
410 }
411 
412 } // end namespace IsaInfo
413 
414 void initDefaultAMDKernelCodeT(amd_kernel_code_t &Header,
415                                const FeatureBitset &Features) {
416   IsaInfo::IsaVersion ISA = IsaInfo::getIsaVersion(Features);
417 
418   memset(&Header, 0, sizeof(Header));
419 
420   Header.amd_kernel_code_version_major = 1;
421   Header.amd_kernel_code_version_minor = 1;
422   Header.amd_machine_kind = 1; // AMD_MACHINE_KIND_AMDGPU
423   Header.amd_machine_version_major = ISA.Major;
424   Header.amd_machine_version_minor = ISA.Minor;
425   Header.amd_machine_version_stepping = ISA.Stepping;
426   Header.kernel_code_entry_byte_offset = sizeof(Header);
427   // wavefront_size is specified as a power of 2: 2^6 = 64 threads.
428   Header.wavefront_size = 6;
429 
430   // If the code object does not support indirect functions, then the value must
431   // be 0xffffffff.
432   Header.call_convention = -1;
433 
434   // These alignment values are specified in powers of two, so alignment =
435   // 2^n.  The minimum alignment is 2^4 = 16.
436   Header.kernarg_segment_alignment = 4;
437   Header.group_segment_alignment = 4;
438   Header.private_segment_alignment = 4;
439 }
440 
441 bool isGroupSegment(const GlobalValue *GV) {
442   return GV->getType()->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS;
443 }
444 
445 bool isGlobalSegment(const GlobalValue *GV) {
446   return GV->getType()->getAddressSpace() == AMDGPUAS::GLOBAL_ADDRESS;
447 }
448 
449 bool isReadOnlySegment(const GlobalValue *GV) {
450   return GV->getType()->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS;
451 }
452 
453 bool shouldEmitConstantsToTextSection(const Triple &TT) {
454   return TT.getOS() != Triple::AMDHSA;
455 }
456 
457 int getIntegerAttribute(const Function &F, StringRef Name, int Default) {
458   Attribute A = F.getFnAttribute(Name);
459   int Result = Default;
460 
461   if (A.isStringAttribute()) {
462     StringRef Str = A.getValueAsString();
463     if (Str.getAsInteger(0, Result)) {
464       LLVMContext &Ctx = F.getContext();
465       Ctx.emitError("can't parse integer attribute " + Name);
466     }
467   }
468 
469   return Result;
470 }
471 
472 std::pair<int, int> getIntegerPairAttribute(const Function &F,
473                                             StringRef Name,
474                                             std::pair<int, int> Default,
475                                             bool OnlyFirstRequired) {
476   Attribute A = F.getFnAttribute(Name);
477   if (!A.isStringAttribute())
478     return Default;
479 
480   LLVMContext &Ctx = F.getContext();
481   std::pair<int, int> Ints = Default;
482   std::pair<StringRef, StringRef> Strs = A.getValueAsString().split(',');
483   if (Strs.first.trim().getAsInteger(0, Ints.first)) {
484     Ctx.emitError("can't parse first integer attribute " + Name);
485     return Default;
486   }
487   if (Strs.second.trim().getAsInteger(0, Ints.second)) {
488     if (!OnlyFirstRequired || !Strs.second.trim().empty()) {
489       Ctx.emitError("can't parse second integer attribute " + Name);
490       return Default;
491     }
492   }
493 
494   return Ints;
495 }
496 
497 unsigned getVmcntBitMask(const IsaInfo::IsaVersion &Version) {
498   unsigned VmcntLo = (1 << getVmcntBitWidthLo()) - 1;
499   if (Version.Major < 9)
500     return VmcntLo;
501 
502   unsigned VmcntHi = ((1 << getVmcntBitWidthHi()) - 1) << getVmcntBitWidthLo();
503   return VmcntLo | VmcntHi;
504 }
505 
506 unsigned getExpcntBitMask(const IsaInfo::IsaVersion &Version) {
507   return (1 << getExpcntBitWidth()) - 1;
508 }
509 
510 unsigned getLgkmcntBitMask(const IsaInfo::IsaVersion &Version) {
511   return (1 << getLgkmcntBitWidth()) - 1;
512 }
513 
514 unsigned getWaitcntBitMask(const IsaInfo::IsaVersion &Version) {
515   unsigned VmcntLo = getBitMask(getVmcntBitShiftLo(), getVmcntBitWidthLo());
516   unsigned Expcnt = getBitMask(getExpcntBitShift(), getExpcntBitWidth());
517   unsigned Lgkmcnt = getBitMask(getLgkmcntBitShift(), getLgkmcntBitWidth());
518   unsigned Waitcnt = VmcntLo | Expcnt | Lgkmcnt;
519   if (Version.Major < 9)
520     return Waitcnt;
521 
522   unsigned VmcntHi = getBitMask(getVmcntBitShiftHi(), getVmcntBitWidthHi());
523   return Waitcnt | VmcntHi;
524 }
525 
526 unsigned decodeVmcnt(const IsaInfo::IsaVersion &Version, unsigned Waitcnt) {
527   unsigned VmcntLo =
528       unpackBits(Waitcnt, getVmcntBitShiftLo(), getVmcntBitWidthLo());
529   if (Version.Major < 9)
530     return VmcntLo;
531 
532   unsigned VmcntHi =
533       unpackBits(Waitcnt, getVmcntBitShiftHi(), getVmcntBitWidthHi());
534   VmcntHi <<= getVmcntBitWidthLo();
535   return VmcntLo | VmcntHi;
536 }
537 
538 unsigned decodeExpcnt(const IsaInfo::IsaVersion &Version, unsigned Waitcnt) {
539   return unpackBits(Waitcnt, getExpcntBitShift(), getExpcntBitWidth());
540 }
541 
542 unsigned decodeLgkmcnt(const IsaInfo::IsaVersion &Version, unsigned Waitcnt) {
543   return unpackBits(Waitcnt, getLgkmcntBitShift(), getLgkmcntBitWidth());
544 }
545 
546 void decodeWaitcnt(const IsaInfo::IsaVersion &Version, unsigned Waitcnt,
547                    unsigned &Vmcnt, unsigned &Expcnt, unsigned &Lgkmcnt) {
548   Vmcnt = decodeVmcnt(Version, Waitcnt);
549   Expcnt = decodeExpcnt(Version, Waitcnt);
550   Lgkmcnt = decodeLgkmcnt(Version, Waitcnt);
551 }
552 
553 unsigned encodeVmcnt(const IsaInfo::IsaVersion &Version, unsigned Waitcnt,
554                      unsigned Vmcnt) {
555   Waitcnt =
556       packBits(Vmcnt, Waitcnt, getVmcntBitShiftLo(), getVmcntBitWidthLo());
557   if (Version.Major < 9)
558     return Waitcnt;
559 
560   Vmcnt >>= getVmcntBitWidthLo();
561   return packBits(Vmcnt, Waitcnt, getVmcntBitShiftHi(), getVmcntBitWidthHi());
562 }
563 
564 unsigned encodeExpcnt(const IsaInfo::IsaVersion &Version, unsigned Waitcnt,
565                       unsigned Expcnt) {
566   return packBits(Expcnt, Waitcnt, getExpcntBitShift(), getExpcntBitWidth());
567 }
568 
569 unsigned encodeLgkmcnt(const IsaInfo::IsaVersion &Version, unsigned Waitcnt,
570                        unsigned Lgkmcnt) {
571   return packBits(Lgkmcnt, Waitcnt, getLgkmcntBitShift(), getLgkmcntBitWidth());
572 }
573 
574 unsigned encodeWaitcnt(const IsaInfo::IsaVersion &Version,
575                        unsigned Vmcnt, unsigned Expcnt, unsigned Lgkmcnt) {
576   unsigned Waitcnt = getWaitcntBitMask(Version);
577   Waitcnt = encodeVmcnt(Version, Waitcnt, Vmcnt);
578   Waitcnt = encodeExpcnt(Version, Waitcnt, Expcnt);
579   Waitcnt = encodeLgkmcnt(Version, Waitcnt, Lgkmcnt);
580   return Waitcnt;
581 }
582 
583 unsigned getInitialPSInputAddr(const Function &F) {
584   return getIntegerAttribute(F, "InitialPSInputAddr", 0);
585 }
586 
587 bool isShader(CallingConv::ID cc) {
588   switch(cc) {
589     case CallingConv::AMDGPU_VS:
590     case CallingConv::AMDGPU_LS:
591     case CallingConv::AMDGPU_HS:
592     case CallingConv::AMDGPU_ES:
593     case CallingConv::AMDGPU_GS:
594     case CallingConv::AMDGPU_PS:
595     case CallingConv::AMDGPU_CS:
596       return true;
597     default:
598       return false;
599   }
600 }
601 
602 bool isCompute(CallingConv::ID cc) {
603   return !isShader(cc) || cc == CallingConv::AMDGPU_CS;
604 }
605 
606 bool isEntryFunctionCC(CallingConv::ID CC) {
607   switch (CC) {
608   case CallingConv::AMDGPU_KERNEL:
609   case CallingConv::SPIR_KERNEL:
610   case CallingConv::AMDGPU_VS:
611   case CallingConv::AMDGPU_GS:
612   case CallingConv::AMDGPU_PS:
613   case CallingConv::AMDGPU_CS:
614   case CallingConv::AMDGPU_ES:
615   case CallingConv::AMDGPU_HS:
616   case CallingConv::AMDGPU_LS:
617     return true;
618   default:
619     return false;
620   }
621 }
622 
623 bool hasXNACK(const MCSubtargetInfo &STI) {
624   return STI.getFeatureBits()[AMDGPU::FeatureXNACK];
625 }
626 
627 bool isSI(const MCSubtargetInfo &STI) {
628   return STI.getFeatureBits()[AMDGPU::FeatureSouthernIslands];
629 }
630 
631 bool isCI(const MCSubtargetInfo &STI) {
632   return STI.getFeatureBits()[AMDGPU::FeatureSeaIslands];
633 }
634 
635 bool isVI(const MCSubtargetInfo &STI) {
636   return STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands];
637 }
638 
639 bool isGFX9(const MCSubtargetInfo &STI) {
640   return STI.getFeatureBits()[AMDGPU::FeatureGFX9];
641 }
642 
643 bool isGCN3Encoding(const MCSubtargetInfo &STI) {
644   return STI.getFeatureBits()[AMDGPU::FeatureGCN3Encoding];
645 }
646 
647 bool isSGPR(unsigned Reg, const MCRegisterInfo* TRI) {
648   const MCRegisterClass SGPRClass = TRI->getRegClass(AMDGPU::SReg_32RegClassID);
649   const unsigned FirstSubReg = TRI->getSubReg(Reg, 1);
650   return SGPRClass.contains(FirstSubReg != 0 ? FirstSubReg : Reg) ||
651     Reg == AMDGPU::SCC;
652 }
653 
654 bool isRegIntersect(unsigned Reg0, unsigned Reg1, const MCRegisterInfo* TRI) {
655   for (MCRegAliasIterator R(Reg0, TRI, true); R.isValid(); ++R) {
656     if (*R == Reg1) return true;
657   }
658   return false;
659 }
660 
661 #define MAP_REG2REG \
662   using namespace AMDGPU; \
663   switch(Reg) { \
664   default: return Reg; \
665   CASE_CI_VI(FLAT_SCR) \
666   CASE_CI_VI(FLAT_SCR_LO) \
667   CASE_CI_VI(FLAT_SCR_HI) \
668   CASE_VI_GFX9(TTMP0) \
669   CASE_VI_GFX9(TTMP1) \
670   CASE_VI_GFX9(TTMP2) \
671   CASE_VI_GFX9(TTMP3) \
672   CASE_VI_GFX9(TTMP4) \
673   CASE_VI_GFX9(TTMP5) \
674   CASE_VI_GFX9(TTMP6) \
675   CASE_VI_GFX9(TTMP7) \
676   CASE_VI_GFX9(TTMP8) \
677   CASE_VI_GFX9(TTMP9) \
678   CASE_VI_GFX9(TTMP10) \
679   CASE_VI_GFX9(TTMP11) \
680   CASE_VI_GFX9(TTMP12) \
681   CASE_VI_GFX9(TTMP13) \
682   CASE_VI_GFX9(TTMP14) \
683   CASE_VI_GFX9(TTMP15) \
684   CASE_VI_GFX9(TTMP0_TTMP1) \
685   CASE_VI_GFX9(TTMP2_TTMP3) \
686   CASE_VI_GFX9(TTMP4_TTMP5) \
687   CASE_VI_GFX9(TTMP6_TTMP7) \
688   CASE_VI_GFX9(TTMP8_TTMP9) \
689   CASE_VI_GFX9(TTMP10_TTMP11) \
690   CASE_VI_GFX9(TTMP12_TTMP13) \
691   CASE_VI_GFX9(TTMP14_TTMP15) \
692   CASE_VI_GFX9(TTMP0_TTMP1_TTMP2_TTMP3) \
693   CASE_VI_GFX9(TTMP4_TTMP5_TTMP6_TTMP7) \
694   CASE_VI_GFX9(TTMP8_TTMP9_TTMP10_TTMP11) \
695   CASE_VI_GFX9(TTMP12_TTMP13_TTMP14_TTMP15) \
696   CASE_VI_GFX9(TTMP0_TTMP1_TTMP2_TTMP3_TTMP4_TTMP5_TTMP6_TTMP7) \
697   CASE_VI_GFX9(TTMP4_TTMP5_TTMP6_TTMP7_TTMP8_TTMP9_TTMP10_TTMP11) \
698   CASE_VI_GFX9(TTMP8_TTMP9_TTMP10_TTMP11_TTMP12_TTMP13_TTMP14_TTMP15) \
699   CASE_VI_GFX9(TTMP0_TTMP1_TTMP2_TTMP3_TTMP4_TTMP5_TTMP6_TTMP7_TTMP8_TTMP9_TTMP10_TTMP11_TTMP12_TTMP13_TTMP14_TTMP15) \
700   }
701 
702 #define CASE_CI_VI(node) \
703   assert(!isSI(STI)); \
704   case node: return isCI(STI) ? node##_ci : node##_vi;
705 
706 #define CASE_VI_GFX9(node) \
707   case node: return isGFX9(STI) ? node##_gfx9 : node##_vi;
708 
709 unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI) {
710   MAP_REG2REG
711 }
712 
713 #undef CASE_CI_VI
714 #undef CASE_VI_GFX9
715 
716 #define CASE_CI_VI(node)   case node##_ci: case node##_vi:   return node;
717 #define CASE_VI_GFX9(node) case node##_vi: case node##_gfx9: return node;
718 
719 unsigned mc2PseudoReg(unsigned Reg) {
720   MAP_REG2REG
721 }
722 
723 #undef CASE_CI_VI
724 #undef CASE_VI_GFX9
725 #undef MAP_REG2REG
726 
727 bool isSISrcOperand(const MCInstrDesc &Desc, unsigned OpNo) {
728   assert(OpNo < Desc.NumOperands);
729   unsigned OpType = Desc.OpInfo[OpNo].OperandType;
730   return OpType >= AMDGPU::OPERAND_SRC_FIRST &&
731          OpType <= AMDGPU::OPERAND_SRC_LAST;
732 }
733 
734 bool isSISrcFPOperand(const MCInstrDesc &Desc, unsigned OpNo) {
735   assert(OpNo < Desc.NumOperands);
736   unsigned OpType = Desc.OpInfo[OpNo].OperandType;
737   switch (OpType) {
738   case AMDGPU::OPERAND_REG_IMM_FP32:
739   case AMDGPU::OPERAND_REG_IMM_FP64:
740   case AMDGPU::OPERAND_REG_IMM_FP16:
741   case AMDGPU::OPERAND_REG_INLINE_C_FP32:
742   case AMDGPU::OPERAND_REG_INLINE_C_FP64:
743   case AMDGPU::OPERAND_REG_INLINE_C_FP16:
744   case AMDGPU::OPERAND_REG_INLINE_C_V2FP16:
745     return true;
746   default:
747     return false;
748   }
749 }
750 
751 bool isSISrcInlinableOperand(const MCInstrDesc &Desc, unsigned OpNo) {
752   assert(OpNo < Desc.NumOperands);
753   unsigned OpType = Desc.OpInfo[OpNo].OperandType;
754   return OpType >= AMDGPU::OPERAND_REG_INLINE_C_FIRST &&
755          OpType <= AMDGPU::OPERAND_REG_INLINE_C_LAST;
756 }
757 
758 // Avoid using MCRegisterClass::getSize, since that function will go away
759 // (move from MC* level to Target* level). Return size in bits.
760 unsigned getRegBitWidth(unsigned RCID) {
761   switch (RCID) {
762   case AMDGPU::SGPR_32RegClassID:
763   case AMDGPU::VGPR_32RegClassID:
764   case AMDGPU::VS_32RegClassID:
765   case AMDGPU::SReg_32RegClassID:
766   case AMDGPU::SReg_32_XM0RegClassID:
767     return 32;
768   case AMDGPU::SGPR_64RegClassID:
769   case AMDGPU::VS_64RegClassID:
770   case AMDGPU::SReg_64RegClassID:
771   case AMDGPU::VReg_64RegClassID:
772     return 64;
773   case AMDGPU::VReg_96RegClassID:
774     return 96;
775   case AMDGPU::SGPR_128RegClassID:
776   case AMDGPU::SReg_128RegClassID:
777   case AMDGPU::VReg_128RegClassID:
778     return 128;
779   case AMDGPU::SReg_256RegClassID:
780   case AMDGPU::VReg_256RegClassID:
781     return 256;
782   case AMDGPU::SReg_512RegClassID:
783   case AMDGPU::VReg_512RegClassID:
784     return 512;
785   default:
786     llvm_unreachable("Unexpected register class");
787   }
788 }
789 
790 unsigned getRegBitWidth(const MCRegisterClass &RC) {
791   return getRegBitWidth(RC.getID());
792 }
793 
794 unsigned getRegOperandSize(const MCRegisterInfo *MRI, const MCInstrDesc &Desc,
795                            unsigned OpNo) {
796   assert(OpNo < Desc.NumOperands);
797   unsigned RCID = Desc.OpInfo[OpNo].RegClass;
798   return getRegBitWidth(MRI->getRegClass(RCID)) / 8;
799 }
800 
801 bool isInlinableLiteral64(int64_t Literal, bool HasInv2Pi) {
802   if (Literal >= -16 && Literal <= 64)
803     return true;
804 
805   uint64_t Val = static_cast<uint64_t>(Literal);
806   return (Val == DoubleToBits(0.0)) ||
807          (Val == DoubleToBits(1.0)) ||
808          (Val == DoubleToBits(-1.0)) ||
809          (Val == DoubleToBits(0.5)) ||
810          (Val == DoubleToBits(-0.5)) ||
811          (Val == DoubleToBits(2.0)) ||
812          (Val == DoubleToBits(-2.0)) ||
813          (Val == DoubleToBits(4.0)) ||
814          (Val == DoubleToBits(-4.0)) ||
815          (Val == 0x3fc45f306dc9c882 && HasInv2Pi);
816 }
817 
818 bool isInlinableLiteral32(int32_t Literal, bool HasInv2Pi) {
819   if (Literal >= -16 && Literal <= 64)
820     return true;
821 
822   // The actual type of the operand does not seem to matter as long
823   // as the bits match one of the inline immediate values.  For example:
824   //
825   // -nan has the hexadecimal encoding of 0xfffffffe which is -2 in decimal,
826   // so it is a legal inline immediate.
827   //
828   // 1065353216 has the hexadecimal encoding 0x3f800000 which is 1.0f in
829   // floating-point, so it is a legal inline immediate.
830 
831   uint32_t Val = static_cast<uint32_t>(Literal);
832   return (Val == FloatToBits(0.0f)) ||
833          (Val == FloatToBits(1.0f)) ||
834          (Val == FloatToBits(-1.0f)) ||
835          (Val == FloatToBits(0.5f)) ||
836          (Val == FloatToBits(-0.5f)) ||
837          (Val == FloatToBits(2.0f)) ||
838          (Val == FloatToBits(-2.0f)) ||
839          (Val == FloatToBits(4.0f)) ||
840          (Val == FloatToBits(-4.0f)) ||
841          (Val == 0x3e22f983 && HasInv2Pi);
842 }
843 
844 bool isInlinableLiteral16(int16_t Literal, bool HasInv2Pi) {
845   if (!HasInv2Pi)
846     return false;
847 
848   if (Literal >= -16 && Literal <= 64)
849     return true;
850 
851   uint16_t Val = static_cast<uint16_t>(Literal);
852   return Val == 0x3C00 || // 1.0
853          Val == 0xBC00 || // -1.0
854          Val == 0x3800 || // 0.5
855          Val == 0xB800 || // -0.5
856          Val == 0x4000 || // 2.0
857          Val == 0xC000 || // -2.0
858          Val == 0x4400 || // 4.0
859          Val == 0xC400 || // -4.0
860          Val == 0x3118;   // 1/2pi
861 }
862 
863 bool isInlinableLiteralV216(int32_t Literal, bool HasInv2Pi) {
864   assert(HasInv2Pi);
865 
866   if (!EnablePackedInlinableLiterals)
867     return false;
868 
869   int16_t Lo16 = static_cast<int16_t>(Literal);
870   int16_t Hi16 = static_cast<int16_t>(Literal >> 16);
871   return Lo16 == Hi16 && isInlinableLiteral16(Lo16, HasInv2Pi);
872 }
873 
874 bool isArgPassedInSGPR(const Argument *A) {
875   const Function *F = A->getParent();
876 
877   // Arguments to compute shaders are never a source of divergence.
878   CallingConv::ID CC = F->getCallingConv();
879   switch (CC) {
880   case CallingConv::AMDGPU_KERNEL:
881   case CallingConv::SPIR_KERNEL:
882     return true;
883   case CallingConv::AMDGPU_VS:
884   case CallingConv::AMDGPU_LS:
885   case CallingConv::AMDGPU_HS:
886   case CallingConv::AMDGPU_ES:
887   case CallingConv::AMDGPU_GS:
888   case CallingConv::AMDGPU_PS:
889   case CallingConv::AMDGPU_CS:
890     // For non-compute shaders, SGPR inputs are marked with either inreg or byval.
891     // Everything else is in VGPRs.
892     return F->getAttributes().hasParamAttribute(A->getArgNo(), Attribute::InReg) ||
893            F->getAttributes().hasParamAttribute(A->getArgNo(), Attribute::ByVal);
894   default:
895     // TODO: Should calls support inreg for SGPR inputs?
896     return false;
897   }
898 }
899 
900 // TODO: Should largely merge with AMDGPUTTIImpl::isSourceOfDivergence.
901 bool isUniformMMO(const MachineMemOperand *MMO) {
902   const Value *Ptr = MMO->getValue();
903   // UndefValue means this is a load of a kernel input.  These are uniform.
904   // Sometimes LDS instructions have constant pointers.
905   // If Ptr is null, then that means this mem operand contains a
906   // PseudoSourceValue like GOT.
907   if (!Ptr || isa<UndefValue>(Ptr) ||
908       isa<Constant>(Ptr) || isa<GlobalValue>(Ptr))
909     return true;
910 
911   if (const Argument *Arg = dyn_cast<Argument>(Ptr))
912     return isArgPassedInSGPR(Arg);
913 
914   const Instruction *I = dyn_cast<Instruction>(Ptr);
915   return I && I->getMetadata("amdgpu.uniform");
916 }
917 
918 int64_t getSMRDEncodedOffset(const MCSubtargetInfo &ST, int64_t ByteOffset) {
919   if (isGCN3Encoding(ST))
920     return ByteOffset;
921   return ByteOffset >> 2;
922 }
923 
924 bool isLegalSMRDImmOffset(const MCSubtargetInfo &ST, int64_t ByteOffset) {
925   int64_t EncodedOffset = getSMRDEncodedOffset(ST, ByteOffset);
926   return isGCN3Encoding(ST) ?
927     isUInt<20>(EncodedOffset) : isUInt<8>(EncodedOffset);
928 }
929 
930 } // end namespace AMDGPU
931 
932 } // end namespace llvm
933 
934 namespace llvm {
935 namespace AMDGPU {
936 
937 AMDGPUAS getAMDGPUAS(Triple T) {
938   auto Env = T.getEnvironmentName();
939   AMDGPUAS AS;
940   if (Env == "amdgiz" || Env == "amdgizcl") {
941     AS.FLAT_ADDRESS     = 0;
942     AS.PRIVATE_ADDRESS  = 5;
943     AS.REGION_ADDRESS   = 4;
944   }
945   else {
946     AS.FLAT_ADDRESS     = 4;
947     AS.PRIVATE_ADDRESS  = 0;
948     AS.REGION_ADDRESS   = 5;
949    }
950   return AS;
951 }
952 
953 AMDGPUAS getAMDGPUAS(const TargetMachine &M) {
954   return getAMDGPUAS(M.getTargetTriple());
955 }
956 
957 AMDGPUAS getAMDGPUAS(const Module &M) {
958   return getAMDGPUAS(Triple(M.getTargetTriple()));
959 }
960 } // namespace AMDGPU
961 } // namespace llvm
962