1 //===- AMDGPUBaseInfo.cpp - AMDGPU Base encoding information --------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
10 #include "AMDGPUBaseInfo.h"
11 #include "AMDGPU.h"
12 #include "SIDefines.h"
13 #include "llvm/ADT/StringRef.h"
14 #include "llvm/ADT/Triple.h"
15 #include "llvm/BinaryFormat/ELF.h"
16 #include "llvm/CodeGen/MachineMemOperand.h"
17 #include "llvm/IR/Attributes.h"
18 #include "llvm/IR/Constants.h"
19 #include "llvm/IR/Function.h"
20 #include "llvm/IR/GlobalValue.h"
21 #include "llvm/IR/Instruction.h"
22 #include "llvm/IR/LLVMContext.h"
23 #include "llvm/IR/Module.h"
24 #include "llvm/MC/MCContext.h"
25 #include "llvm/MC/MCInstrDesc.h"
26 #include "llvm/MC/MCInstrInfo.h"
27 #include "llvm/MC/MCRegisterInfo.h"
28 #include "llvm/MC/MCSectionELF.h"
29 #include "llvm/MC/MCSubtargetInfo.h"
30 #include "llvm/MC/SubtargetFeature.h"
31 #include "llvm/Support/Casting.h"
32 #include "llvm/Support/ErrorHandling.h"
33 #include "llvm/Support/MathExtras.h"
34 #include <algorithm>
35 #include <cassert>
36 #include <cstdint>
37 #include <cstring>
38 #include <utility>
39 
40 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
41 
42 #define GET_INSTRINFO_NAMED_OPS
43 #define GET_INSTRMAP_INFO
44 #include "AMDGPUGenInstrInfo.inc"
45 #undef GET_INSTRMAP_INFO
46 #undef GET_INSTRINFO_NAMED_OPS
47 
48 namespace {
49 
50 /// \returns Bit mask for given bit \p Shift and bit \p Width.
51 unsigned getBitMask(unsigned Shift, unsigned Width) {
52   return ((1 << Width) - 1) << Shift;
53 }
54 
55 /// \brief Packs \p Src into \p Dst for given bit \p Shift and bit \p Width.
56 ///
57 /// \returns Packed \p Dst.
58 unsigned packBits(unsigned Src, unsigned Dst, unsigned Shift, unsigned Width) {
59   Dst &= ~(1 << Shift) & ~getBitMask(Shift, Width);
60   Dst |= (Src << Shift) & getBitMask(Shift, Width);
61   return Dst;
62 }
63 
64 /// \brief Unpacks bits from \p Src for given bit \p Shift and bit \p Width.
65 ///
66 /// \returns Unpacked bits.
67 unsigned unpackBits(unsigned Src, unsigned Shift, unsigned Width) {
68   return (Src & getBitMask(Shift, Width)) >> Shift;
69 }
70 
71 /// \returns Vmcnt bit shift (lower bits).
72 unsigned getVmcntBitShiftLo() { return 0; }
73 
74 /// \returns Vmcnt bit width (lower bits).
75 unsigned getVmcntBitWidthLo() { return 4; }
76 
77 /// \returns Expcnt bit shift.
78 unsigned getExpcntBitShift() { return 4; }
79 
80 /// \returns Expcnt bit width.
81 unsigned getExpcntBitWidth() { return 3; }
82 
83 /// \returns Lgkmcnt bit shift.
84 unsigned getLgkmcntBitShift() { return 8; }
85 
86 /// \returns Lgkmcnt bit width.
87 unsigned getLgkmcntBitWidth() { return 4; }
88 
89 /// \returns Vmcnt bit shift (higher bits).
90 unsigned getVmcntBitShiftHi() { return 14; }
91 
92 /// \returns Vmcnt bit width (higher bits).
93 unsigned getVmcntBitWidthHi() { return 2; }
94 
95 } // end namespace anonymous
96 
97 namespace llvm {
98 
99 static cl::opt<bool> EnablePackedInlinableLiterals(
100     "enable-packed-inlinable-literals",
101     cl::desc("Enable packed inlinable literals (v2f16, v2i16)"),
102     cl::init(false));
103 
104 namespace AMDGPU {
105 
106 LLVM_READNONE
107 static inline Channels indexToChannel(unsigned Channel) {
108   switch (Channel) {
109   case 1:
110     return AMDGPU::Channels_1;
111   case 2:
112     return AMDGPU::Channels_2;
113   case 3:
114     return AMDGPU::Channels_3;
115   case 4:
116     return AMDGPU::Channels_4;
117   default:
118     llvm_unreachable("invalid MIMG channel");
119   }
120 }
121 
122 
123 // FIXME: Need to handle d16 images correctly.
124 static unsigned rcToChannels(unsigned RCID) {
125   switch (RCID) {
126   case AMDGPU::VGPR_32RegClassID:
127     return 1;
128   case AMDGPU::VReg_64RegClassID:
129     return 2;
130   case AMDGPU::VReg_96RegClassID:
131     return 3;
132   case AMDGPU::VReg_128RegClassID:
133     return 4;
134   default:
135     llvm_unreachable("invalid MIMG register class");
136   }
137 }
138 
139 int getMaskedMIMGOp(const MCInstrInfo &MII, unsigned Opc, unsigned NewChannels) {
140   AMDGPU::Channels Channel = AMDGPU::indexToChannel(NewChannels);
141   unsigned OrigChannels = rcToChannels(MII.get(Opc).OpInfo[0].RegClass);
142   if (NewChannels == OrigChannels)
143     return Opc;
144 
145   switch (OrigChannels) {
146   case 1:
147     return AMDGPU::getMaskedMIMGOp1(Opc, Channel);
148   case 2:
149     return AMDGPU::getMaskedMIMGOp2(Opc, Channel);
150   case 3:
151     return AMDGPU::getMaskedMIMGOp3(Opc, Channel);
152   case 4:
153     return AMDGPU::getMaskedMIMGOp4(Opc, Channel);
154   default:
155     llvm_unreachable("invalid MIMG channel");
156   }
157 }
158 
159 int getMaskedMIMGAtomicOp(const MCInstrInfo &MII, unsigned Opc, unsigned NewChannels) {
160   assert(AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdst) != -1);
161   assert(NewChannels == 1 || NewChannels == 2 || NewChannels == 4);
162 
163   unsigned OrigChannels = rcToChannels(MII.get(Opc).OpInfo[0].RegClass);
164   assert(OrigChannels == 1 || OrigChannels == 2 || OrigChannels == 4);
165 
166   if (NewChannels == OrigChannels) return Opc;
167 
168   if (OrigChannels <= 2 && NewChannels <= 2) {
169     // This is an ordinary atomic (not an atomic_cmpswap)
170     return (OrigChannels == 1)?
171       AMDGPU::getMIMGAtomicOp1(Opc) : AMDGPU::getMIMGAtomicOp2(Opc);
172   } else if (OrigChannels >= 2 && NewChannels >= 2) {
173     // This is an atomic_cmpswap
174     return (OrigChannels == 2)?
175       AMDGPU::getMIMGAtomicOp1(Opc) : AMDGPU::getMIMGAtomicOp2(Opc);
176   } else { // invalid OrigChannels/NewChannels value
177     return -1;
178   }
179 }
180 
181 // Wrapper for Tablegen'd function.  enum Subtarget is not defined in any
182 // header files, so we need to wrap it in a function that takes unsigned
183 // instead.
184 int getMCOpcode(uint16_t Opcode, unsigned Gen) {
185   return getMCOpcodeGen(Opcode, static_cast<Subtarget>(Gen));
186 }
187 
188 namespace IsaInfo {
189 
190 IsaVersion getIsaVersion(const FeatureBitset &Features) {
191   // GCN GFX6 (Southern Islands (SI)).
192   if (Features.test(FeatureISAVersion6_0_0))
193     return {6, 0, 0};
194   if (Features.test(FeatureISAVersion6_0_1))
195     return {6, 0, 1};
196 
197   // GCN GFX7 (Sea Islands (CI)).
198   if (Features.test(FeatureISAVersion7_0_0))
199     return {7, 0, 0};
200   if (Features.test(FeatureISAVersion7_0_1))
201     return {7, 0, 1};
202   if (Features.test(FeatureISAVersion7_0_2))
203     return {7, 0, 2};
204   if (Features.test(FeatureISAVersion7_0_3))
205     return {7, 0, 3};
206   if (Features.test(FeatureISAVersion7_0_4))
207     return {7, 0, 4};
208 
209   // GCN GFX8 (Volcanic Islands (VI)).
210   if (Features.test(FeatureISAVersion8_0_0))
211     return {8, 0, 0};
212   if (Features.test(FeatureISAVersion8_0_1))
213     return {8, 0, 1};
214   if (Features.test(FeatureISAVersion8_0_2))
215     return {8, 0, 2};
216   if (Features.test(FeatureISAVersion8_0_3))
217     return {8, 0, 3};
218   if (Features.test(FeatureISAVersion8_1_0))
219     return {8, 1, 0};
220 
221   // GCN GFX9.
222   if (Features.test(FeatureISAVersion9_0_0))
223     return {9, 0, 0};
224   if (Features.test(FeatureISAVersion9_0_2))
225     return {9, 0, 2};
226 
227   if (!Features.test(FeatureGCN) || Features.test(FeatureSouthernIslands))
228     return {0, 0, 0};
229   return {7, 0, 0};
230 }
231 
232 void streamIsaVersion(const MCSubtargetInfo *STI, raw_ostream &Stream) {
233   auto TargetTriple = STI->getTargetTriple();
234   auto ISAVersion = IsaInfo::getIsaVersion(STI->getFeatureBits());
235 
236   Stream << TargetTriple.getArchName() << '-'
237          << TargetTriple.getVendorName() << '-'
238          << TargetTriple.getOSName() << '-'
239          << TargetTriple.getEnvironmentName() << '-'
240          << "gfx"
241          << ISAVersion.Major
242          << ISAVersion.Minor
243          << ISAVersion.Stepping;
244   Stream.flush();
245 }
246 
247 bool hasCodeObjectV3(const FeatureBitset &Features) {
248   return Features.test(FeatureCodeObjectV3);
249 }
250 
251 unsigned getWavefrontSize(const FeatureBitset &Features) {
252   if (Features.test(FeatureWavefrontSize16))
253     return 16;
254   if (Features.test(FeatureWavefrontSize32))
255     return 32;
256 
257   return 64;
258 }
259 
260 unsigned getLocalMemorySize(const FeatureBitset &Features) {
261   if (Features.test(FeatureLocalMemorySize32768))
262     return 32768;
263   if (Features.test(FeatureLocalMemorySize65536))
264     return 65536;
265 
266   return 0;
267 }
268 
269 unsigned getEUsPerCU(const FeatureBitset &Features) {
270   return 4;
271 }
272 
273 unsigned getMaxWorkGroupsPerCU(const FeatureBitset &Features,
274                                unsigned FlatWorkGroupSize) {
275   if (!Features.test(FeatureGCN))
276     return 8;
277   unsigned N = getWavesPerWorkGroup(Features, FlatWorkGroupSize);
278   if (N == 1)
279     return 40;
280   N = 40 / N;
281   return std::min(N, 16u);
282 }
283 
284 unsigned getMaxWavesPerCU(const FeatureBitset &Features) {
285   return getMaxWavesPerEU(Features) * getEUsPerCU(Features);
286 }
287 
288 unsigned getMaxWavesPerCU(const FeatureBitset &Features,
289                           unsigned FlatWorkGroupSize) {
290   return getWavesPerWorkGroup(Features, FlatWorkGroupSize);
291 }
292 
293 unsigned getMinWavesPerEU(const FeatureBitset &Features) {
294   return 1;
295 }
296 
297 unsigned getMaxWavesPerEU(const FeatureBitset &Features) {
298   if (!Features.test(FeatureGCN))
299     return 8;
300   // FIXME: Need to take scratch memory into account.
301   return 10;
302 }
303 
304 unsigned getMaxWavesPerEU(const FeatureBitset &Features,
305                           unsigned FlatWorkGroupSize) {
306   return alignTo(getMaxWavesPerCU(Features, FlatWorkGroupSize),
307                  getEUsPerCU(Features)) / getEUsPerCU(Features);
308 }
309 
310 unsigned getMinFlatWorkGroupSize(const FeatureBitset &Features) {
311   return 1;
312 }
313 
314 unsigned getMaxFlatWorkGroupSize(const FeatureBitset &Features) {
315   return 2048;
316 }
317 
318 unsigned getWavesPerWorkGroup(const FeatureBitset &Features,
319                               unsigned FlatWorkGroupSize) {
320   return alignTo(FlatWorkGroupSize, getWavefrontSize(Features)) /
321                  getWavefrontSize(Features);
322 }
323 
324 unsigned getSGPRAllocGranule(const FeatureBitset &Features) {
325   IsaVersion Version = getIsaVersion(Features);
326   if (Version.Major >= 8)
327     return 16;
328   return 8;
329 }
330 
331 unsigned getSGPREncodingGranule(const FeatureBitset &Features) {
332   return 8;
333 }
334 
335 unsigned getTotalNumSGPRs(const FeatureBitset &Features) {
336   IsaVersion Version = getIsaVersion(Features);
337   if (Version.Major >= 8)
338     return 800;
339   return 512;
340 }
341 
342 unsigned getAddressableNumSGPRs(const FeatureBitset &Features) {
343   if (Features.test(FeatureSGPRInitBug))
344     return FIXED_NUM_SGPRS_FOR_INIT_BUG;
345 
346   IsaVersion Version = getIsaVersion(Features);
347   if (Version.Major >= 8)
348     return 102;
349   return 104;
350 }
351 
352 unsigned getMinNumSGPRs(const FeatureBitset &Features, unsigned WavesPerEU) {
353   assert(WavesPerEU != 0);
354 
355   if (WavesPerEU >= getMaxWavesPerEU(Features))
356     return 0;
357   unsigned MinNumSGPRs =
358       alignDown(getTotalNumSGPRs(Features) / (WavesPerEU + 1),
359                 getSGPRAllocGranule(Features)) + 1;
360   return std::min(MinNumSGPRs, getAddressableNumSGPRs(Features));
361 }
362 
363 unsigned getMaxNumSGPRs(const FeatureBitset &Features, unsigned WavesPerEU,
364                         bool Addressable) {
365   assert(WavesPerEU != 0);
366 
367   IsaVersion Version = getIsaVersion(Features);
368   unsigned MaxNumSGPRs = alignDown(getTotalNumSGPRs(Features) / WavesPerEU,
369                                    getSGPRAllocGranule(Features));
370   unsigned AddressableNumSGPRs = getAddressableNumSGPRs(Features);
371   if (Version.Major >= 8 && !Addressable)
372     AddressableNumSGPRs = 112;
373   return std::min(MaxNumSGPRs, AddressableNumSGPRs);
374 }
375 
376 unsigned getVGPRAllocGranule(const FeatureBitset &Features) {
377   return 4;
378 }
379 
380 unsigned getVGPREncodingGranule(const FeatureBitset &Features) {
381   return getVGPRAllocGranule(Features);
382 }
383 
384 unsigned getTotalNumVGPRs(const FeatureBitset &Features) {
385   return 256;
386 }
387 
388 unsigned getAddressableNumVGPRs(const FeatureBitset &Features) {
389   return getTotalNumVGPRs(Features);
390 }
391 
392 unsigned getMinNumVGPRs(const FeatureBitset &Features, unsigned WavesPerEU) {
393   assert(WavesPerEU != 0);
394 
395   if (WavesPerEU >= getMaxWavesPerEU(Features))
396     return 0;
397   unsigned MinNumVGPRs =
398       alignDown(getTotalNumVGPRs(Features) / (WavesPerEU + 1),
399                 getVGPRAllocGranule(Features)) + 1;
400   return std::min(MinNumVGPRs, getAddressableNumVGPRs(Features));
401 }
402 
403 unsigned getMaxNumVGPRs(const FeatureBitset &Features, unsigned WavesPerEU) {
404   assert(WavesPerEU != 0);
405 
406   unsigned MaxNumVGPRs = alignDown(getTotalNumVGPRs(Features) / WavesPerEU,
407                                    getVGPRAllocGranule(Features));
408   unsigned AddressableNumVGPRs = getAddressableNumVGPRs(Features);
409   return std::min(MaxNumVGPRs, AddressableNumVGPRs);
410 }
411 
412 } // end namespace IsaInfo
413 
414 void initDefaultAMDKernelCodeT(amd_kernel_code_t &Header,
415                                const FeatureBitset &Features) {
416   IsaInfo::IsaVersion ISA = IsaInfo::getIsaVersion(Features);
417 
418   memset(&Header, 0, sizeof(Header));
419 
420   Header.amd_kernel_code_version_major = 1;
421   Header.amd_kernel_code_version_minor = 1;
422   Header.amd_machine_kind = 1; // AMD_MACHINE_KIND_AMDGPU
423   Header.amd_machine_version_major = ISA.Major;
424   Header.amd_machine_version_minor = ISA.Minor;
425   Header.amd_machine_version_stepping = ISA.Stepping;
426   Header.kernel_code_entry_byte_offset = sizeof(Header);
427   // wavefront_size is specified as a power of 2: 2^6 = 64 threads.
428   Header.wavefront_size = 6;
429 
430   // If the code object does not support indirect functions, then the value must
431   // be 0xffffffff.
432   Header.call_convention = -1;
433 
434   // These alignment values are specified in powers of two, so alignment =
435   // 2^n.  The minimum alignment is 2^4 = 16.
436   Header.kernarg_segment_alignment = 4;
437   Header.group_segment_alignment = 4;
438   Header.private_segment_alignment = 4;
439 }
440 
441 bool isGroupSegment(const GlobalValue *GV) {
442   return GV->getType()->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS;
443 }
444 
445 bool isGlobalSegment(const GlobalValue *GV) {
446   return GV->getType()->getAddressSpace() == AMDGPUAS::GLOBAL_ADDRESS;
447 }
448 
449 bool isReadOnlySegment(const GlobalValue *GV) {
450   return GV->getType()->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS ||
451          GV->getType()->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS_32BIT;
452 }
453 
454 bool shouldEmitConstantsToTextSection(const Triple &TT) {
455   return TT.getOS() != Triple::AMDHSA;
456 }
457 
458 int getIntegerAttribute(const Function &F, StringRef Name, int Default) {
459   Attribute A = F.getFnAttribute(Name);
460   int Result = Default;
461 
462   if (A.isStringAttribute()) {
463     StringRef Str = A.getValueAsString();
464     if (Str.getAsInteger(0, Result)) {
465       LLVMContext &Ctx = F.getContext();
466       Ctx.emitError("can't parse integer attribute " + Name);
467     }
468   }
469 
470   return Result;
471 }
472 
473 std::pair<int, int> getIntegerPairAttribute(const Function &F,
474                                             StringRef Name,
475                                             std::pair<int, int> Default,
476                                             bool OnlyFirstRequired) {
477   Attribute A = F.getFnAttribute(Name);
478   if (!A.isStringAttribute())
479     return Default;
480 
481   LLVMContext &Ctx = F.getContext();
482   std::pair<int, int> Ints = Default;
483   std::pair<StringRef, StringRef> Strs = A.getValueAsString().split(',');
484   if (Strs.first.trim().getAsInteger(0, Ints.first)) {
485     Ctx.emitError("can't parse first integer attribute " + Name);
486     return Default;
487   }
488   if (Strs.second.trim().getAsInteger(0, Ints.second)) {
489     if (!OnlyFirstRequired || !Strs.second.trim().empty()) {
490       Ctx.emitError("can't parse second integer attribute " + Name);
491       return Default;
492     }
493   }
494 
495   return Ints;
496 }
497 
498 unsigned getVmcntBitMask(const IsaInfo::IsaVersion &Version) {
499   unsigned VmcntLo = (1 << getVmcntBitWidthLo()) - 1;
500   if (Version.Major < 9)
501     return VmcntLo;
502 
503   unsigned VmcntHi = ((1 << getVmcntBitWidthHi()) - 1) << getVmcntBitWidthLo();
504   return VmcntLo | VmcntHi;
505 }
506 
507 unsigned getExpcntBitMask(const IsaInfo::IsaVersion &Version) {
508   return (1 << getExpcntBitWidth()) - 1;
509 }
510 
511 unsigned getLgkmcntBitMask(const IsaInfo::IsaVersion &Version) {
512   return (1 << getLgkmcntBitWidth()) - 1;
513 }
514 
515 unsigned getWaitcntBitMask(const IsaInfo::IsaVersion &Version) {
516   unsigned VmcntLo = getBitMask(getVmcntBitShiftLo(), getVmcntBitWidthLo());
517   unsigned Expcnt = getBitMask(getExpcntBitShift(), getExpcntBitWidth());
518   unsigned Lgkmcnt = getBitMask(getLgkmcntBitShift(), getLgkmcntBitWidth());
519   unsigned Waitcnt = VmcntLo | Expcnt | Lgkmcnt;
520   if (Version.Major < 9)
521     return Waitcnt;
522 
523   unsigned VmcntHi = getBitMask(getVmcntBitShiftHi(), getVmcntBitWidthHi());
524   return Waitcnt | VmcntHi;
525 }
526 
527 unsigned decodeVmcnt(const IsaInfo::IsaVersion &Version, unsigned Waitcnt) {
528   unsigned VmcntLo =
529       unpackBits(Waitcnt, getVmcntBitShiftLo(), getVmcntBitWidthLo());
530   if (Version.Major < 9)
531     return VmcntLo;
532 
533   unsigned VmcntHi =
534       unpackBits(Waitcnt, getVmcntBitShiftHi(), getVmcntBitWidthHi());
535   VmcntHi <<= getVmcntBitWidthLo();
536   return VmcntLo | VmcntHi;
537 }
538 
539 unsigned decodeExpcnt(const IsaInfo::IsaVersion &Version, unsigned Waitcnt) {
540   return unpackBits(Waitcnt, getExpcntBitShift(), getExpcntBitWidth());
541 }
542 
543 unsigned decodeLgkmcnt(const IsaInfo::IsaVersion &Version, unsigned Waitcnt) {
544   return unpackBits(Waitcnt, getLgkmcntBitShift(), getLgkmcntBitWidth());
545 }
546 
547 void decodeWaitcnt(const IsaInfo::IsaVersion &Version, unsigned Waitcnt,
548                    unsigned &Vmcnt, unsigned &Expcnt, unsigned &Lgkmcnt) {
549   Vmcnt = decodeVmcnt(Version, Waitcnt);
550   Expcnt = decodeExpcnt(Version, Waitcnt);
551   Lgkmcnt = decodeLgkmcnt(Version, Waitcnt);
552 }
553 
554 unsigned encodeVmcnt(const IsaInfo::IsaVersion &Version, unsigned Waitcnt,
555                      unsigned Vmcnt) {
556   Waitcnt =
557       packBits(Vmcnt, Waitcnt, getVmcntBitShiftLo(), getVmcntBitWidthLo());
558   if (Version.Major < 9)
559     return Waitcnt;
560 
561   Vmcnt >>= getVmcntBitWidthLo();
562   return packBits(Vmcnt, Waitcnt, getVmcntBitShiftHi(), getVmcntBitWidthHi());
563 }
564 
565 unsigned encodeExpcnt(const IsaInfo::IsaVersion &Version, unsigned Waitcnt,
566                       unsigned Expcnt) {
567   return packBits(Expcnt, Waitcnt, getExpcntBitShift(), getExpcntBitWidth());
568 }
569 
570 unsigned encodeLgkmcnt(const IsaInfo::IsaVersion &Version, unsigned Waitcnt,
571                        unsigned Lgkmcnt) {
572   return packBits(Lgkmcnt, Waitcnt, getLgkmcntBitShift(), getLgkmcntBitWidth());
573 }
574 
575 unsigned encodeWaitcnt(const IsaInfo::IsaVersion &Version,
576                        unsigned Vmcnt, unsigned Expcnt, unsigned Lgkmcnt) {
577   unsigned Waitcnt = getWaitcntBitMask(Version);
578   Waitcnt = encodeVmcnt(Version, Waitcnt, Vmcnt);
579   Waitcnt = encodeExpcnt(Version, Waitcnt, Expcnt);
580   Waitcnt = encodeLgkmcnt(Version, Waitcnt, Lgkmcnt);
581   return Waitcnt;
582 }
583 
584 unsigned getInitialPSInputAddr(const Function &F) {
585   return getIntegerAttribute(F, "InitialPSInputAddr", 0);
586 }
587 
588 bool isShader(CallingConv::ID cc) {
589   switch(cc) {
590     case CallingConv::AMDGPU_VS:
591     case CallingConv::AMDGPU_LS:
592     case CallingConv::AMDGPU_HS:
593     case CallingConv::AMDGPU_ES:
594     case CallingConv::AMDGPU_GS:
595     case CallingConv::AMDGPU_PS:
596     case CallingConv::AMDGPU_CS:
597       return true;
598     default:
599       return false;
600   }
601 }
602 
603 bool isCompute(CallingConv::ID cc) {
604   return !isShader(cc) || cc == CallingConv::AMDGPU_CS;
605 }
606 
607 bool isEntryFunctionCC(CallingConv::ID CC) {
608   switch (CC) {
609   case CallingConv::AMDGPU_KERNEL:
610   case CallingConv::SPIR_KERNEL:
611   case CallingConv::AMDGPU_VS:
612   case CallingConv::AMDGPU_GS:
613   case CallingConv::AMDGPU_PS:
614   case CallingConv::AMDGPU_CS:
615   case CallingConv::AMDGPU_ES:
616   case CallingConv::AMDGPU_HS:
617   case CallingConv::AMDGPU_LS:
618     return true;
619   default:
620     return false;
621   }
622 }
623 
624 bool hasXNACK(const MCSubtargetInfo &STI) {
625   return STI.getFeatureBits()[AMDGPU::FeatureXNACK];
626 }
627 
628 bool hasMIMG_R128(const MCSubtargetInfo &STI) {
629   return STI.getFeatureBits()[AMDGPU::FeatureMIMG_R128];
630 }
631 
632 bool hasPackedD16(const MCSubtargetInfo &STI) {
633   return !STI.getFeatureBits()[AMDGPU::FeatureUnpackedD16VMem];
634 }
635 
636 bool isSI(const MCSubtargetInfo &STI) {
637   return STI.getFeatureBits()[AMDGPU::FeatureSouthernIslands];
638 }
639 
640 bool isCI(const MCSubtargetInfo &STI) {
641   return STI.getFeatureBits()[AMDGPU::FeatureSeaIslands];
642 }
643 
644 bool isVI(const MCSubtargetInfo &STI) {
645   return STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands];
646 }
647 
648 bool isGFX9(const MCSubtargetInfo &STI) {
649   return STI.getFeatureBits()[AMDGPU::FeatureGFX9];
650 }
651 
652 bool isGCN3Encoding(const MCSubtargetInfo &STI) {
653   return STI.getFeatureBits()[AMDGPU::FeatureGCN3Encoding];
654 }
655 
656 bool isSGPR(unsigned Reg, const MCRegisterInfo* TRI) {
657   const MCRegisterClass SGPRClass = TRI->getRegClass(AMDGPU::SReg_32RegClassID);
658   const unsigned FirstSubReg = TRI->getSubReg(Reg, 1);
659   return SGPRClass.contains(FirstSubReg != 0 ? FirstSubReg : Reg) ||
660     Reg == AMDGPU::SCC;
661 }
662 
663 bool isRegIntersect(unsigned Reg0, unsigned Reg1, const MCRegisterInfo* TRI) {
664   for (MCRegAliasIterator R(Reg0, TRI, true); R.isValid(); ++R) {
665     if (*R == Reg1) return true;
666   }
667   return false;
668 }
669 
670 #define MAP_REG2REG \
671   using namespace AMDGPU; \
672   switch(Reg) { \
673   default: return Reg; \
674   CASE_CI_VI(FLAT_SCR) \
675   CASE_CI_VI(FLAT_SCR_LO) \
676   CASE_CI_VI(FLAT_SCR_HI) \
677   CASE_VI_GFX9(TTMP0) \
678   CASE_VI_GFX9(TTMP1) \
679   CASE_VI_GFX9(TTMP2) \
680   CASE_VI_GFX9(TTMP3) \
681   CASE_VI_GFX9(TTMP4) \
682   CASE_VI_GFX9(TTMP5) \
683   CASE_VI_GFX9(TTMP6) \
684   CASE_VI_GFX9(TTMP7) \
685   CASE_VI_GFX9(TTMP8) \
686   CASE_VI_GFX9(TTMP9) \
687   CASE_VI_GFX9(TTMP10) \
688   CASE_VI_GFX9(TTMP11) \
689   CASE_VI_GFX9(TTMP12) \
690   CASE_VI_GFX9(TTMP13) \
691   CASE_VI_GFX9(TTMP14) \
692   CASE_VI_GFX9(TTMP15) \
693   CASE_VI_GFX9(TTMP0_TTMP1) \
694   CASE_VI_GFX9(TTMP2_TTMP3) \
695   CASE_VI_GFX9(TTMP4_TTMP5) \
696   CASE_VI_GFX9(TTMP6_TTMP7) \
697   CASE_VI_GFX9(TTMP8_TTMP9) \
698   CASE_VI_GFX9(TTMP10_TTMP11) \
699   CASE_VI_GFX9(TTMP12_TTMP13) \
700   CASE_VI_GFX9(TTMP14_TTMP15) \
701   CASE_VI_GFX9(TTMP0_TTMP1_TTMP2_TTMP3) \
702   CASE_VI_GFX9(TTMP4_TTMP5_TTMP6_TTMP7) \
703   CASE_VI_GFX9(TTMP8_TTMP9_TTMP10_TTMP11) \
704   CASE_VI_GFX9(TTMP12_TTMP13_TTMP14_TTMP15) \
705   CASE_VI_GFX9(TTMP0_TTMP1_TTMP2_TTMP3_TTMP4_TTMP5_TTMP6_TTMP7) \
706   CASE_VI_GFX9(TTMP4_TTMP5_TTMP6_TTMP7_TTMP8_TTMP9_TTMP10_TTMP11) \
707   CASE_VI_GFX9(TTMP8_TTMP9_TTMP10_TTMP11_TTMP12_TTMP13_TTMP14_TTMP15) \
708   CASE_VI_GFX9(TTMP0_TTMP1_TTMP2_TTMP3_TTMP4_TTMP5_TTMP6_TTMP7_TTMP8_TTMP9_TTMP10_TTMP11_TTMP12_TTMP13_TTMP14_TTMP15) \
709   }
710 
711 #define CASE_CI_VI(node) \
712   assert(!isSI(STI)); \
713   case node: return isCI(STI) ? node##_ci : node##_vi;
714 
715 #define CASE_VI_GFX9(node) \
716   case node: return isGFX9(STI) ? node##_gfx9 : node##_vi;
717 
718 unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI) {
719   MAP_REG2REG
720 }
721 
722 #undef CASE_CI_VI
723 #undef CASE_VI_GFX9
724 
725 #define CASE_CI_VI(node)   case node##_ci: case node##_vi:   return node;
726 #define CASE_VI_GFX9(node) case node##_vi: case node##_gfx9: return node;
727 
728 unsigned mc2PseudoReg(unsigned Reg) {
729   MAP_REG2REG
730 }
731 
732 #undef CASE_CI_VI
733 #undef CASE_VI_GFX9
734 #undef MAP_REG2REG
735 
736 bool isSISrcOperand(const MCInstrDesc &Desc, unsigned OpNo) {
737   assert(OpNo < Desc.NumOperands);
738   unsigned OpType = Desc.OpInfo[OpNo].OperandType;
739   return OpType >= AMDGPU::OPERAND_SRC_FIRST &&
740          OpType <= AMDGPU::OPERAND_SRC_LAST;
741 }
742 
743 bool isSISrcFPOperand(const MCInstrDesc &Desc, unsigned OpNo) {
744   assert(OpNo < Desc.NumOperands);
745   unsigned OpType = Desc.OpInfo[OpNo].OperandType;
746   switch (OpType) {
747   case AMDGPU::OPERAND_REG_IMM_FP32:
748   case AMDGPU::OPERAND_REG_IMM_FP64:
749   case AMDGPU::OPERAND_REG_IMM_FP16:
750   case AMDGPU::OPERAND_REG_INLINE_C_FP32:
751   case AMDGPU::OPERAND_REG_INLINE_C_FP64:
752   case AMDGPU::OPERAND_REG_INLINE_C_FP16:
753   case AMDGPU::OPERAND_REG_INLINE_C_V2FP16:
754     return true;
755   default:
756     return false;
757   }
758 }
759 
760 bool isSISrcInlinableOperand(const MCInstrDesc &Desc, unsigned OpNo) {
761   assert(OpNo < Desc.NumOperands);
762   unsigned OpType = Desc.OpInfo[OpNo].OperandType;
763   return OpType >= AMDGPU::OPERAND_REG_INLINE_C_FIRST &&
764          OpType <= AMDGPU::OPERAND_REG_INLINE_C_LAST;
765 }
766 
767 // Avoid using MCRegisterClass::getSize, since that function will go away
768 // (move from MC* level to Target* level). Return size in bits.
769 unsigned getRegBitWidth(unsigned RCID) {
770   switch (RCID) {
771   case AMDGPU::SGPR_32RegClassID:
772   case AMDGPU::VGPR_32RegClassID:
773   case AMDGPU::VS_32RegClassID:
774   case AMDGPU::SReg_32RegClassID:
775   case AMDGPU::SReg_32_XM0RegClassID:
776     return 32;
777   case AMDGPU::SGPR_64RegClassID:
778   case AMDGPU::VS_64RegClassID:
779   case AMDGPU::SReg_64RegClassID:
780   case AMDGPU::VReg_64RegClassID:
781     return 64;
782   case AMDGPU::VReg_96RegClassID:
783     return 96;
784   case AMDGPU::SGPR_128RegClassID:
785   case AMDGPU::SReg_128RegClassID:
786   case AMDGPU::VReg_128RegClassID:
787     return 128;
788   case AMDGPU::SReg_256RegClassID:
789   case AMDGPU::VReg_256RegClassID:
790     return 256;
791   case AMDGPU::SReg_512RegClassID:
792   case AMDGPU::VReg_512RegClassID:
793     return 512;
794   default:
795     llvm_unreachable("Unexpected register class");
796   }
797 }
798 
799 unsigned getRegBitWidth(const MCRegisterClass &RC) {
800   return getRegBitWidth(RC.getID());
801 }
802 
803 unsigned getRegOperandSize(const MCRegisterInfo *MRI, const MCInstrDesc &Desc,
804                            unsigned OpNo) {
805   assert(OpNo < Desc.NumOperands);
806   unsigned RCID = Desc.OpInfo[OpNo].RegClass;
807   return getRegBitWidth(MRI->getRegClass(RCID)) / 8;
808 }
809 
810 bool isInlinableLiteral64(int64_t Literal, bool HasInv2Pi) {
811   if (Literal >= -16 && Literal <= 64)
812     return true;
813 
814   uint64_t Val = static_cast<uint64_t>(Literal);
815   return (Val == DoubleToBits(0.0)) ||
816          (Val == DoubleToBits(1.0)) ||
817          (Val == DoubleToBits(-1.0)) ||
818          (Val == DoubleToBits(0.5)) ||
819          (Val == DoubleToBits(-0.5)) ||
820          (Val == DoubleToBits(2.0)) ||
821          (Val == DoubleToBits(-2.0)) ||
822          (Val == DoubleToBits(4.0)) ||
823          (Val == DoubleToBits(-4.0)) ||
824          (Val == 0x3fc45f306dc9c882 && HasInv2Pi);
825 }
826 
827 bool isInlinableLiteral32(int32_t Literal, bool HasInv2Pi) {
828   if (Literal >= -16 && Literal <= 64)
829     return true;
830 
831   // The actual type of the operand does not seem to matter as long
832   // as the bits match one of the inline immediate values.  For example:
833   //
834   // -nan has the hexadecimal encoding of 0xfffffffe which is -2 in decimal,
835   // so it is a legal inline immediate.
836   //
837   // 1065353216 has the hexadecimal encoding 0x3f800000 which is 1.0f in
838   // floating-point, so it is a legal inline immediate.
839 
840   uint32_t Val = static_cast<uint32_t>(Literal);
841   return (Val == FloatToBits(0.0f)) ||
842          (Val == FloatToBits(1.0f)) ||
843          (Val == FloatToBits(-1.0f)) ||
844          (Val == FloatToBits(0.5f)) ||
845          (Val == FloatToBits(-0.5f)) ||
846          (Val == FloatToBits(2.0f)) ||
847          (Val == FloatToBits(-2.0f)) ||
848          (Val == FloatToBits(4.0f)) ||
849          (Val == FloatToBits(-4.0f)) ||
850          (Val == 0x3e22f983 && HasInv2Pi);
851 }
852 
853 bool isInlinableLiteral16(int16_t Literal, bool HasInv2Pi) {
854   if (!HasInv2Pi)
855     return false;
856 
857   if (Literal >= -16 && Literal <= 64)
858     return true;
859 
860   uint16_t Val = static_cast<uint16_t>(Literal);
861   return Val == 0x3C00 || // 1.0
862          Val == 0xBC00 || // -1.0
863          Val == 0x3800 || // 0.5
864          Val == 0xB800 || // -0.5
865          Val == 0x4000 || // 2.0
866          Val == 0xC000 || // -2.0
867          Val == 0x4400 || // 4.0
868          Val == 0xC400 || // -4.0
869          Val == 0x3118;   // 1/2pi
870 }
871 
872 bool isInlinableLiteralV216(int32_t Literal, bool HasInv2Pi) {
873   assert(HasInv2Pi);
874 
875   if (!EnablePackedInlinableLiterals)
876     return false;
877 
878   int16_t Lo16 = static_cast<int16_t>(Literal);
879   int16_t Hi16 = static_cast<int16_t>(Literal >> 16);
880   return Lo16 == Hi16 && isInlinableLiteral16(Lo16, HasInv2Pi);
881 }
882 
883 bool isArgPassedInSGPR(const Argument *A) {
884   const Function *F = A->getParent();
885 
886   // Arguments to compute shaders are never a source of divergence.
887   CallingConv::ID CC = F->getCallingConv();
888   switch (CC) {
889   case CallingConv::AMDGPU_KERNEL:
890   case CallingConv::SPIR_KERNEL:
891     return true;
892   case CallingConv::AMDGPU_VS:
893   case CallingConv::AMDGPU_LS:
894   case CallingConv::AMDGPU_HS:
895   case CallingConv::AMDGPU_ES:
896   case CallingConv::AMDGPU_GS:
897   case CallingConv::AMDGPU_PS:
898   case CallingConv::AMDGPU_CS:
899     // For non-compute shaders, SGPR inputs are marked with either inreg or byval.
900     // Everything else is in VGPRs.
901     return F->getAttributes().hasParamAttribute(A->getArgNo(), Attribute::InReg) ||
902            F->getAttributes().hasParamAttribute(A->getArgNo(), Attribute::ByVal);
903   default:
904     // TODO: Should calls support inreg for SGPR inputs?
905     return false;
906   }
907 }
908 
909 int64_t getSMRDEncodedOffset(const MCSubtargetInfo &ST, int64_t ByteOffset) {
910   if (isGCN3Encoding(ST))
911     return ByteOffset;
912   return ByteOffset >> 2;
913 }
914 
915 bool isLegalSMRDImmOffset(const MCSubtargetInfo &ST, int64_t ByteOffset) {
916   int64_t EncodedOffset = getSMRDEncodedOffset(ST, ByteOffset);
917   return isGCN3Encoding(ST) ?
918     isUInt<20>(EncodedOffset) : isUInt<8>(EncodedOffset);
919 }
920 
921 } // end namespace AMDGPU
922 
923 } // end namespace llvm
924 
925 namespace llvm {
926 namespace AMDGPU {
927 
928 AMDGPUAS getAMDGPUAS(Triple T) {
929   AMDGPUAS AS;
930   AS.FLAT_ADDRESS = 0;
931   AS.PRIVATE_ADDRESS = 5;
932   AS.REGION_ADDRESS = 2;
933   return AS;
934 }
935 
936 AMDGPUAS getAMDGPUAS(const TargetMachine &M) {
937   return getAMDGPUAS(M.getTargetTriple());
938 }
939 
940 AMDGPUAS getAMDGPUAS(const Module &M) {
941   return getAMDGPUAS(Triple(M.getTargetTriple()));
942 }
943 } // namespace AMDGPU
944 } // namespace llvm
945