1 //===-- AMDGPUBaseInfo.cpp - AMDGPU Base encoding information--------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 #include "AMDGPUBaseInfo.h"
10 #include "AMDGPU.h"
11 #include "SIDefines.h"
12 #include "llvm/IR/LLVMContext.h"
13 #include "llvm/IR/Function.h"
14 #include "llvm/IR/GlobalValue.h"
15 #include "llvm/MC/MCContext.h"
16 #include "llvm/MC/MCInstrInfo.h"
17 #include "llvm/MC/MCRegisterInfo.h"
18 #include "llvm/MC/MCSectionELF.h"
19 #include "llvm/MC/MCSubtargetInfo.h"
20 #include "llvm/MC/SubtargetFeature.h"
21 
22 #define GET_SUBTARGETINFO_ENUM
23 #include "AMDGPUGenSubtargetInfo.inc"
24 #undef GET_SUBTARGETINFO_ENUM
25 
26 #define GET_REGINFO_ENUM
27 #include "AMDGPUGenRegisterInfo.inc"
28 #undef GET_REGINFO_ENUM
29 
30 namespace llvm {
31 namespace AMDGPU {
32 
33 IsaVersion getIsaVersion(const FeatureBitset &Features) {
34 
35   if (Features.test(FeatureISAVersion7_0_0))
36     return {7, 0, 0};
37 
38   if (Features.test(FeatureISAVersion7_0_1))
39     return {7, 0, 1};
40 
41   if (Features.test(FeatureISAVersion8_0_0))
42     return {8, 0, 0};
43 
44   if (Features.test(FeatureISAVersion8_0_1))
45     return {8, 0, 1};
46 
47   if (Features.test(FeatureISAVersion8_0_3))
48     return {8, 0, 3};
49 
50   return {0, 0, 0};
51 }
52 
53 void initDefaultAMDKernelCodeT(amd_kernel_code_t &Header,
54                                const FeatureBitset &Features) {
55 
56   IsaVersion ISA = getIsaVersion(Features);
57 
58   memset(&Header, 0, sizeof(Header));
59 
60   Header.amd_kernel_code_version_major = 1;
61   Header.amd_kernel_code_version_minor = 0;
62   Header.amd_machine_kind = 1; // AMD_MACHINE_KIND_AMDGPU
63   Header.amd_machine_version_major = ISA.Major;
64   Header.amd_machine_version_minor = ISA.Minor;
65   Header.amd_machine_version_stepping = ISA.Stepping;
66   Header.kernel_code_entry_byte_offset = sizeof(Header);
67   // wavefront_size is specified as a power of 2: 2^6 = 64 threads.
68   Header.wavefront_size = 6;
69   // These alignment values are specified in powers of two, so alignment =
70   // 2^n.  The minimum alignment is 2^4 = 16.
71   Header.kernarg_segment_alignment = 4;
72   Header.group_segment_alignment = 4;
73   Header.private_segment_alignment = 4;
74 }
75 
76 MCSection *getHSATextSection(MCContext &Ctx) {
77   return Ctx.getELFSection(".hsatext", ELF::SHT_PROGBITS,
78                            ELF::SHF_ALLOC | ELF::SHF_WRITE |
79                            ELF::SHF_EXECINSTR |
80                            ELF::SHF_AMDGPU_HSA_AGENT |
81                            ELF::SHF_AMDGPU_HSA_CODE);
82 }
83 
84 MCSection *getHSADataGlobalAgentSection(MCContext &Ctx) {
85   return Ctx.getELFSection(".hsadata_global_agent", ELF::SHT_PROGBITS,
86                            ELF::SHF_ALLOC | ELF::SHF_WRITE |
87                            ELF::SHF_AMDGPU_HSA_GLOBAL |
88                            ELF::SHF_AMDGPU_HSA_AGENT);
89 }
90 
91 MCSection *getHSADataGlobalProgramSection(MCContext &Ctx) {
92   return  Ctx.getELFSection(".hsadata_global_program", ELF::SHT_PROGBITS,
93                             ELF::SHF_ALLOC | ELF::SHF_WRITE |
94                             ELF::SHF_AMDGPU_HSA_GLOBAL);
95 }
96 
97 MCSection *getHSARodataReadonlyAgentSection(MCContext &Ctx) {
98   return Ctx.getELFSection(".hsarodata_readonly_agent", ELF::SHT_PROGBITS,
99                            ELF::SHF_ALLOC | ELF::SHF_AMDGPU_HSA_READONLY |
100                            ELF::SHF_AMDGPU_HSA_AGENT);
101 }
102 
103 bool isGroupSegment(const GlobalValue *GV) {
104   return GV->getType()->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS;
105 }
106 
107 bool isGlobalSegment(const GlobalValue *GV) {
108   return GV->getType()->getAddressSpace() == AMDGPUAS::GLOBAL_ADDRESS;
109 }
110 
111 bool isReadOnlySegment(const GlobalValue *GV) {
112   return GV->getType()->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS;
113 }
114 
115 int getIntegerAttribute(const Function &F, StringRef Name, int Default) {
116   Attribute A = F.getFnAttribute(Name);
117   int Result = Default;
118 
119   if (A.isStringAttribute()) {
120     StringRef Str = A.getValueAsString();
121     if (Str.getAsInteger(0, Result)) {
122       LLVMContext &Ctx = F.getContext();
123       Ctx.emitError("can't parse integer attribute " + Name);
124     }
125   }
126 
127   return Result;
128 }
129 
130 std::pair<int, int> getIntegerPairAttribute(const Function &F,
131                                             StringRef Name,
132                                             std::pair<int, int> Default,
133                                             bool OnlyFirstRequired) {
134   Attribute A = F.getFnAttribute(Name);
135   if (!A.isStringAttribute())
136     return Default;
137 
138   LLVMContext &Ctx = F.getContext();
139   std::pair<int, int> Ints = Default;
140   std::pair<StringRef, StringRef> Strs = A.getValueAsString().split(',');
141   if (Strs.first.trim().getAsInteger(0, Ints.first)) {
142     Ctx.emitError("can't parse first integer attribute " + Name);
143     return Default;
144   }
145   if (Strs.second.trim().getAsInteger(0, Ints.second)) {
146     if (!OnlyFirstRequired || Strs.second.trim().size()) {
147       Ctx.emitError("can't parse second integer attribute " + Name);
148       return Default;
149     }
150   }
151 
152   return Ints;
153 }
154 
155 unsigned getInitialPSInputAddr(const Function &F) {
156   return getIntegerAttribute(F, "InitialPSInputAddr", 0);
157 }
158 
159 bool isShader(CallingConv::ID cc) {
160   switch(cc) {
161     case CallingConv::AMDGPU_VS:
162     case CallingConv::AMDGPU_GS:
163     case CallingConv::AMDGPU_PS:
164     case CallingConv::AMDGPU_CS:
165       return true;
166     default:
167       return false;
168   }
169 }
170 
171 bool isCompute(CallingConv::ID cc) {
172   return !isShader(cc) || cc == CallingConv::AMDGPU_CS;
173 }
174 
175 bool isSI(const MCSubtargetInfo &STI) {
176   return STI.getFeatureBits()[AMDGPU::FeatureSouthernIslands];
177 }
178 
179 bool isCI(const MCSubtargetInfo &STI) {
180   return STI.getFeatureBits()[AMDGPU::FeatureSeaIslands];
181 }
182 
183 bool isVI(const MCSubtargetInfo &STI) {
184   return STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands];
185 }
186 
187 unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI) {
188 
189   switch(Reg) {
190   default: break;
191   case AMDGPU::FLAT_SCR:
192     assert(!isSI(STI));
193     return isCI(STI) ? AMDGPU::FLAT_SCR_ci : AMDGPU::FLAT_SCR_vi;
194 
195   case AMDGPU::FLAT_SCR_LO:
196     assert(!isSI(STI));
197     return isCI(STI) ? AMDGPU::FLAT_SCR_LO_ci : AMDGPU::FLAT_SCR_LO_vi;
198 
199   case AMDGPU::FLAT_SCR_HI:
200     assert(!isSI(STI));
201     return isCI(STI) ? AMDGPU::FLAT_SCR_HI_ci : AMDGPU::FLAT_SCR_HI_vi;
202   }
203   return Reg;
204 }
205 
206 bool isSISrcOperand(const MCInstrDesc &Desc, unsigned OpNo) {
207   unsigned OpType = Desc.OpInfo[OpNo].OperandType;
208 
209   return OpType == AMDGPU::OPERAND_REG_IMM32_INT ||
210          OpType == AMDGPU::OPERAND_REG_IMM32_FP ||
211          OpType == AMDGPU::OPERAND_REG_INLINE_C_INT ||
212          OpType == AMDGPU::OPERAND_REG_INLINE_C_FP;
213 }
214 
215 bool isSISrcFPOperand(const MCInstrDesc &Desc, unsigned OpNo) {
216   unsigned OpType = Desc.OpInfo[OpNo].OperandType;
217 
218   return OpType == AMDGPU::OPERAND_REG_IMM32_FP ||
219          OpType == AMDGPU::OPERAND_REG_INLINE_C_FP;
220 }
221 
222 bool isSISrcInlinableOperand(const MCInstrDesc &Desc, unsigned OpNo) {
223   unsigned OpType = Desc.OpInfo[OpNo].OperandType;
224 
225   return OpType == AMDGPU::OPERAND_REG_INLINE_C_INT ||
226          OpType == AMDGPU::OPERAND_REG_INLINE_C_FP;
227 }
228 
229 unsigned getRegOperandSize(const MCRegisterInfo *MRI, const MCInstrDesc &Desc,
230                            unsigned OpNo) {
231   int RCID = Desc.OpInfo[OpNo].RegClass;
232   const MCRegisterClass &RC = MRI->getRegClass(RCID);
233   return RC.getSize();
234 }
235 
236 bool isInlinableLiteral64(int64_t Literal, bool IsVI) {
237   if (Literal >= -16 && Literal <= 64)
238     return true;
239 
240   double D = BitsToDouble(Literal);
241 
242   if (D == 0.5 || D == -0.5 ||
243       D == 1.0 || D == -1.0 ||
244       D == 2.0 || D == -2.0 ||
245       D == 4.0 || D == -4.0)
246     return true;
247 
248   if (IsVI && Literal == 0x3fc45f306dc9c882)
249     return true;
250 
251   return false;
252 }
253 
254 bool isInlinableLiteral32(int32_t Literal, bool IsVI) {
255   if (Literal >= -16 && Literal <= 64)
256     return true;
257 
258   float F = BitsToFloat(Literal);
259 
260   if (F == 0.5 || F == -0.5 ||
261       F == 1.0 || F == -1.0 ||
262       F == 2.0 || F == -2.0 ||
263       F == 4.0 || F == -4.0)
264     return true;
265 
266   if (IsVI && Literal == 0x3e22f983)
267     return true;
268 
269   return false;
270 }
271 
272 
273 } // End namespace AMDGPU
274 } // End namespace llvm
275