1 //===- AMDGPUBaseInfo.cpp - AMDGPU Base encoding information --------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
10 #include "AMDGPUBaseInfo.h"
11 #include "AMDGPUTargetTransformInfo.h"
12 #include "AMDGPU.h"
13 #include "SIDefines.h"
14 #include "llvm/ADT/StringRef.h"
15 #include "llvm/ADT/Triple.h"
16 #include "llvm/BinaryFormat/ELF.h"
17 #include "llvm/CodeGen/MachineMemOperand.h"
18 #include "llvm/IR/Attributes.h"
19 #include "llvm/IR/Constants.h"
20 #include "llvm/IR/Function.h"
21 #include "llvm/IR/GlobalValue.h"
22 #include "llvm/IR/Instruction.h"
23 #include "llvm/IR/LLVMContext.h"
24 #include "llvm/IR/Module.h"
25 #include "llvm/MC/MCContext.h"
26 #include "llvm/MC/MCInstrDesc.h"
27 #include "llvm/MC/MCInstrInfo.h"
28 #include "llvm/MC/MCRegisterInfo.h"
29 #include "llvm/MC/MCSectionELF.h"
30 #include "llvm/MC/MCSubtargetInfo.h"
31 #include "llvm/MC/SubtargetFeature.h"
32 #include "llvm/Support/Casting.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/MathExtras.h"
35 #include <algorithm>
36 #include <cassert>
37 #include <cstdint>
38 #include <cstring>
39 #include <utility>
40 
41 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
42 
43 #define GET_INSTRINFO_NAMED_OPS
44 #define GET_INSTRMAP_INFO
45 #include "AMDGPUGenInstrInfo.inc"
46 #undef GET_INSTRMAP_INFO
47 #undef GET_INSTRINFO_NAMED_OPS
48 
49 namespace {
50 
51 /// \returns Bit mask for given bit \p Shift and bit \p Width.
52 unsigned getBitMask(unsigned Shift, unsigned Width) {
53   return ((1 << Width) - 1) << Shift;
54 }
55 
56 /// Packs \p Src into \p Dst for given bit \p Shift and bit \p Width.
57 ///
58 /// \returns Packed \p Dst.
59 unsigned packBits(unsigned Src, unsigned Dst, unsigned Shift, unsigned Width) {
60   Dst &= ~(1 << Shift) & ~getBitMask(Shift, Width);
61   Dst |= (Src << Shift) & getBitMask(Shift, Width);
62   return Dst;
63 }
64 
65 /// Unpacks bits from \p Src for given bit \p Shift and bit \p Width.
66 ///
67 /// \returns Unpacked bits.
68 unsigned unpackBits(unsigned Src, unsigned Shift, unsigned Width) {
69   return (Src & getBitMask(Shift, Width)) >> Shift;
70 }
71 
72 /// \returns Vmcnt bit shift (lower bits).
73 unsigned getVmcntBitShiftLo() { return 0; }
74 
75 /// \returns Vmcnt bit width (lower bits).
76 unsigned getVmcntBitWidthLo() { return 4; }
77 
78 /// \returns Expcnt bit shift.
79 unsigned getExpcntBitShift() { return 4; }
80 
81 /// \returns Expcnt bit width.
82 unsigned getExpcntBitWidth() { return 3; }
83 
84 /// \returns Lgkmcnt bit shift.
85 unsigned getLgkmcntBitShift() { return 8; }
86 
87 /// \returns Lgkmcnt bit width.
88 unsigned getLgkmcntBitWidth() { return 4; }
89 
90 /// \returns Vmcnt bit shift (higher bits).
91 unsigned getVmcntBitShiftHi() { return 14; }
92 
93 /// \returns Vmcnt bit width (higher bits).
94 unsigned getVmcntBitWidthHi() { return 2; }
95 
96 } // end namespace anonymous
97 
98 namespace llvm {
99 
100 namespace AMDGPU {
101 
102 LLVM_READNONE
103 static inline Channels indexToChannel(unsigned Channel) {
104   switch (Channel) {
105   case 1:
106     return AMDGPU::Channels_1;
107   case 2:
108     return AMDGPU::Channels_2;
109   case 3:
110     return AMDGPU::Channels_3;
111   case 4:
112     return AMDGPU::Channels_4;
113   default:
114     llvm_unreachable("invalid MIMG channel");
115   }
116 }
117 
118 
119 // FIXME: Need to handle d16 images correctly.
120 static unsigned rcToChannels(unsigned RCID) {
121   switch (RCID) {
122   case AMDGPU::VGPR_32RegClassID:
123     return 1;
124   case AMDGPU::VReg_64RegClassID:
125     return 2;
126   case AMDGPU::VReg_96RegClassID:
127     return 3;
128   case AMDGPU::VReg_128RegClassID:
129     return 4;
130   default:
131     llvm_unreachable("invalid MIMG register class");
132   }
133 }
134 
135 int getMaskedMIMGOp(const MCInstrInfo &MII, unsigned Opc, unsigned NewChannels) {
136   AMDGPU::Channels Channel = AMDGPU::indexToChannel(NewChannels);
137   unsigned OrigChannels = rcToChannels(MII.get(Opc).OpInfo[0].RegClass);
138   if (NewChannels == OrigChannels)
139     return Opc;
140 
141   switch (OrigChannels) {
142   case 1:
143     return AMDGPU::getMaskedMIMGOp1(Opc, Channel);
144   case 2:
145     return AMDGPU::getMaskedMIMGOp2(Opc, Channel);
146   case 3:
147     return AMDGPU::getMaskedMIMGOp3(Opc, Channel);
148   case 4:
149     return AMDGPU::getMaskedMIMGOp4(Opc, Channel);
150   default:
151     llvm_unreachable("invalid MIMG channel");
152   }
153 }
154 
155 int getMaskedMIMGAtomicOp(const MCInstrInfo &MII, unsigned Opc, unsigned NewChannels) {
156   assert(AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdst) != -1);
157   assert(NewChannels == 1 || NewChannels == 2 || NewChannels == 4);
158 
159   unsigned OrigChannels = rcToChannels(MII.get(Opc).OpInfo[0].RegClass);
160   assert(OrigChannels == 1 || OrigChannels == 2 || OrigChannels == 4);
161 
162   if (NewChannels == OrigChannels) return Opc;
163 
164   if (OrigChannels <= 2 && NewChannels <= 2) {
165     // This is an ordinary atomic (not an atomic_cmpswap)
166     return (OrigChannels == 1)?
167       AMDGPU::getMIMGAtomicOp1(Opc) : AMDGPU::getMIMGAtomicOp2(Opc);
168   } else if (OrigChannels >= 2 && NewChannels >= 2) {
169     // This is an atomic_cmpswap
170     return (OrigChannels == 2)?
171       AMDGPU::getMIMGAtomicOp1(Opc) : AMDGPU::getMIMGAtomicOp2(Opc);
172   } else { // invalid OrigChannels/NewChannels value
173     return -1;
174   }
175 }
176 
177 // Wrapper for Tablegen'd function.  enum Subtarget is not defined in any
178 // header files, so we need to wrap it in a function that takes unsigned
179 // instead.
180 int getMCOpcode(uint16_t Opcode, unsigned Gen) {
181   return getMCOpcodeGen(Opcode, static_cast<Subtarget>(Gen));
182 }
183 
184 namespace IsaInfo {
185 
186 IsaVersion getIsaVersion(const FeatureBitset &Features) {
187   // GCN GFX6 (Southern Islands (SI)).
188   if (Features.test(FeatureISAVersion6_0_0))
189     return {6, 0, 0};
190   if (Features.test(FeatureISAVersion6_0_1))
191     return {6, 0, 1};
192 
193   // GCN GFX7 (Sea Islands (CI)).
194   if (Features.test(FeatureISAVersion7_0_0))
195     return {7, 0, 0};
196   if (Features.test(FeatureISAVersion7_0_1))
197     return {7, 0, 1};
198   if (Features.test(FeatureISAVersion7_0_2))
199     return {7, 0, 2};
200   if (Features.test(FeatureISAVersion7_0_3))
201     return {7, 0, 3};
202   if (Features.test(FeatureISAVersion7_0_4))
203     return {7, 0, 4};
204   if (Features.test(FeatureSeaIslands))
205     return {7, 0, 0};
206 
207   // GCN GFX8 (Volcanic Islands (VI)).
208   if (Features.test(FeatureISAVersion8_0_1))
209     return {8, 0, 1};
210   if (Features.test(FeatureISAVersion8_0_2))
211     return {8, 0, 2};
212   if (Features.test(FeatureISAVersion8_0_3))
213     return {8, 0, 3};
214   if (Features.test(FeatureISAVersion8_1_0))
215     return {8, 1, 0};
216   if (Features.test(FeatureVolcanicIslands))
217     return {8, 0, 0};
218 
219   // GCN GFX9.
220   if (Features.test(FeatureISAVersion9_0_0))
221     return {9, 0, 0};
222   if (Features.test(FeatureISAVersion9_0_2))
223     return {9, 0, 2};
224   if (Features.test(FeatureISAVersion9_0_4))
225     return {9, 0, 4};
226   if (Features.test(FeatureISAVersion9_0_6))
227     return {9, 0, 6};
228   if (Features.test(FeatureGFX9))
229     return {9, 0, 0};
230 
231   if (!Features.test(FeatureGCN) || Features.test(FeatureSouthernIslands))
232     return {0, 0, 0};
233   return {7, 0, 0};
234 }
235 
236 void streamIsaVersion(const MCSubtargetInfo *STI, raw_ostream &Stream) {
237   auto TargetTriple = STI->getTargetTriple();
238   auto ISAVersion = IsaInfo::getIsaVersion(STI->getFeatureBits());
239 
240   Stream << TargetTriple.getArchName() << '-'
241          << TargetTriple.getVendorName() << '-'
242          << TargetTriple.getOSName() << '-'
243          << TargetTriple.getEnvironmentName() << '-'
244          << "gfx"
245          << ISAVersion.Major
246          << ISAVersion.Minor
247          << ISAVersion.Stepping;
248   Stream.flush();
249 }
250 
251 bool hasCodeObjectV3(const FeatureBitset &Features) {
252   return Features.test(FeatureCodeObjectV3);
253 }
254 
255 unsigned getWavefrontSize(const FeatureBitset &Features) {
256   if (Features.test(FeatureWavefrontSize16))
257     return 16;
258   if (Features.test(FeatureWavefrontSize32))
259     return 32;
260 
261   return 64;
262 }
263 
264 unsigned getLocalMemorySize(const FeatureBitset &Features) {
265   if (Features.test(FeatureLocalMemorySize32768))
266     return 32768;
267   if (Features.test(FeatureLocalMemorySize65536))
268     return 65536;
269 
270   return 0;
271 }
272 
273 unsigned getEUsPerCU(const FeatureBitset &Features) {
274   return 4;
275 }
276 
277 unsigned getMaxWorkGroupsPerCU(const FeatureBitset &Features,
278                                unsigned FlatWorkGroupSize) {
279   if (!Features.test(FeatureGCN))
280     return 8;
281   unsigned N = getWavesPerWorkGroup(Features, FlatWorkGroupSize);
282   if (N == 1)
283     return 40;
284   N = 40 / N;
285   return std::min(N, 16u);
286 }
287 
288 unsigned getMaxWavesPerCU(const FeatureBitset &Features) {
289   return getMaxWavesPerEU(Features) * getEUsPerCU(Features);
290 }
291 
292 unsigned getMaxWavesPerCU(const FeatureBitset &Features,
293                           unsigned FlatWorkGroupSize) {
294   return getWavesPerWorkGroup(Features, FlatWorkGroupSize);
295 }
296 
297 unsigned getMinWavesPerEU(const FeatureBitset &Features) {
298   return 1;
299 }
300 
301 unsigned getMaxWavesPerEU(const FeatureBitset &Features) {
302   if (!Features.test(FeatureGCN))
303     return 8;
304   // FIXME: Need to take scratch memory into account.
305   return 10;
306 }
307 
308 unsigned getMaxWavesPerEU(const FeatureBitset &Features,
309                           unsigned FlatWorkGroupSize) {
310   return alignTo(getMaxWavesPerCU(Features, FlatWorkGroupSize),
311                  getEUsPerCU(Features)) / getEUsPerCU(Features);
312 }
313 
314 unsigned getMinFlatWorkGroupSize(const FeatureBitset &Features) {
315   return 1;
316 }
317 
318 unsigned getMaxFlatWorkGroupSize(const FeatureBitset &Features) {
319   return 2048;
320 }
321 
322 unsigned getWavesPerWorkGroup(const FeatureBitset &Features,
323                               unsigned FlatWorkGroupSize) {
324   return alignTo(FlatWorkGroupSize, getWavefrontSize(Features)) /
325                  getWavefrontSize(Features);
326 }
327 
328 unsigned getSGPRAllocGranule(const FeatureBitset &Features) {
329   IsaVersion Version = getIsaVersion(Features);
330   if (Version.Major >= 8)
331     return 16;
332   return 8;
333 }
334 
335 unsigned getSGPREncodingGranule(const FeatureBitset &Features) {
336   return 8;
337 }
338 
339 unsigned getTotalNumSGPRs(const FeatureBitset &Features) {
340   IsaVersion Version = getIsaVersion(Features);
341   if (Version.Major >= 8)
342     return 800;
343   return 512;
344 }
345 
346 unsigned getAddressableNumSGPRs(const FeatureBitset &Features) {
347   if (Features.test(FeatureSGPRInitBug))
348     return FIXED_NUM_SGPRS_FOR_INIT_BUG;
349 
350   IsaVersion Version = getIsaVersion(Features);
351   if (Version.Major >= 8)
352     return 102;
353   return 104;
354 }
355 
356 unsigned getMinNumSGPRs(const FeatureBitset &Features, unsigned WavesPerEU) {
357   assert(WavesPerEU != 0);
358 
359   if (WavesPerEU >= getMaxWavesPerEU(Features))
360     return 0;
361 
362   unsigned MinNumSGPRs = getTotalNumSGPRs(Features) / (WavesPerEU + 1);
363   if (Features.test(FeatureTrapHandler))
364     MinNumSGPRs -= std::min(MinNumSGPRs, (unsigned)TRAP_NUM_SGPRS);
365   MinNumSGPRs = alignDown(MinNumSGPRs, getSGPRAllocGranule(Features)) + 1;
366   return std::min(MinNumSGPRs, getAddressableNumSGPRs(Features));
367 }
368 
369 unsigned getMaxNumSGPRs(const FeatureBitset &Features, unsigned WavesPerEU,
370                         bool Addressable) {
371   assert(WavesPerEU != 0);
372 
373   IsaVersion Version = getIsaVersion(Features);
374   unsigned AddressableNumSGPRs = getAddressableNumSGPRs(Features);
375   if (Version.Major >= 8 && !Addressable)
376     AddressableNumSGPRs = 112;
377   unsigned MaxNumSGPRs = getTotalNumSGPRs(Features) / WavesPerEU;
378   if (Features.test(FeatureTrapHandler))
379     MaxNumSGPRs -= std::min(MaxNumSGPRs, (unsigned)TRAP_NUM_SGPRS);
380   MaxNumSGPRs = alignDown(MaxNumSGPRs, getSGPRAllocGranule(Features));
381   return std::min(MaxNumSGPRs, AddressableNumSGPRs);
382 }
383 
384 unsigned getVGPRAllocGranule(const FeatureBitset &Features) {
385   return 4;
386 }
387 
388 unsigned getVGPREncodingGranule(const FeatureBitset &Features) {
389   return getVGPRAllocGranule(Features);
390 }
391 
392 unsigned getTotalNumVGPRs(const FeatureBitset &Features) {
393   return 256;
394 }
395 
396 unsigned getAddressableNumVGPRs(const FeatureBitset &Features) {
397   return getTotalNumVGPRs(Features);
398 }
399 
400 unsigned getMinNumVGPRs(const FeatureBitset &Features, unsigned WavesPerEU) {
401   assert(WavesPerEU != 0);
402 
403   if (WavesPerEU >= getMaxWavesPerEU(Features))
404     return 0;
405   unsigned MinNumVGPRs =
406       alignDown(getTotalNumVGPRs(Features) / (WavesPerEU + 1),
407                 getVGPRAllocGranule(Features)) + 1;
408   return std::min(MinNumVGPRs, getAddressableNumVGPRs(Features));
409 }
410 
411 unsigned getMaxNumVGPRs(const FeatureBitset &Features, unsigned WavesPerEU) {
412   assert(WavesPerEU != 0);
413 
414   unsigned MaxNumVGPRs = alignDown(getTotalNumVGPRs(Features) / WavesPerEU,
415                                    getVGPRAllocGranule(Features));
416   unsigned AddressableNumVGPRs = getAddressableNumVGPRs(Features);
417   return std::min(MaxNumVGPRs, AddressableNumVGPRs);
418 }
419 
420 } // end namespace IsaInfo
421 
422 void initDefaultAMDKernelCodeT(amd_kernel_code_t &Header,
423                                const FeatureBitset &Features) {
424   IsaInfo::IsaVersion ISA = IsaInfo::getIsaVersion(Features);
425 
426   memset(&Header, 0, sizeof(Header));
427 
428   Header.amd_kernel_code_version_major = 1;
429   Header.amd_kernel_code_version_minor = 2;
430   Header.amd_machine_kind = 1; // AMD_MACHINE_KIND_AMDGPU
431   Header.amd_machine_version_major = ISA.Major;
432   Header.amd_machine_version_minor = ISA.Minor;
433   Header.amd_machine_version_stepping = ISA.Stepping;
434   Header.kernel_code_entry_byte_offset = sizeof(Header);
435   // wavefront_size is specified as a power of 2: 2^6 = 64 threads.
436   Header.wavefront_size = 6;
437 
438   // If the code object does not support indirect functions, then the value must
439   // be 0xffffffff.
440   Header.call_convention = -1;
441 
442   // These alignment values are specified in powers of two, so alignment =
443   // 2^n.  The minimum alignment is 2^4 = 16.
444   Header.kernarg_segment_alignment = 4;
445   Header.group_segment_alignment = 4;
446   Header.private_segment_alignment = 4;
447 }
448 
449 bool isGroupSegment(const GlobalValue *GV) {
450   return GV->getType()->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS;
451 }
452 
453 bool isGlobalSegment(const GlobalValue *GV) {
454   return GV->getType()->getAddressSpace() == AMDGPUAS::GLOBAL_ADDRESS;
455 }
456 
457 bool isReadOnlySegment(const GlobalValue *GV) {
458   return GV->getType()->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS ||
459          GV->getType()->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS_32BIT;
460 }
461 
462 bool shouldEmitConstantsToTextSection(const Triple &TT) {
463   return TT.getOS() != Triple::AMDHSA;
464 }
465 
466 int getIntegerAttribute(const Function &F, StringRef Name, int Default) {
467   Attribute A = F.getFnAttribute(Name);
468   int Result = Default;
469 
470   if (A.isStringAttribute()) {
471     StringRef Str = A.getValueAsString();
472     if (Str.getAsInteger(0, Result)) {
473       LLVMContext &Ctx = F.getContext();
474       Ctx.emitError("can't parse integer attribute " + Name);
475     }
476   }
477 
478   return Result;
479 }
480 
481 std::pair<int, int> getIntegerPairAttribute(const Function &F,
482                                             StringRef Name,
483                                             std::pair<int, int> Default,
484                                             bool OnlyFirstRequired) {
485   Attribute A = F.getFnAttribute(Name);
486   if (!A.isStringAttribute())
487     return Default;
488 
489   LLVMContext &Ctx = F.getContext();
490   std::pair<int, int> Ints = Default;
491   std::pair<StringRef, StringRef> Strs = A.getValueAsString().split(',');
492   if (Strs.first.trim().getAsInteger(0, Ints.first)) {
493     Ctx.emitError("can't parse first integer attribute " + Name);
494     return Default;
495   }
496   if (Strs.second.trim().getAsInteger(0, Ints.second)) {
497     if (!OnlyFirstRequired || !Strs.second.trim().empty()) {
498       Ctx.emitError("can't parse second integer attribute " + Name);
499       return Default;
500     }
501   }
502 
503   return Ints;
504 }
505 
506 unsigned getVmcntBitMask(const IsaInfo::IsaVersion &Version) {
507   unsigned VmcntLo = (1 << getVmcntBitWidthLo()) - 1;
508   if (Version.Major < 9)
509     return VmcntLo;
510 
511   unsigned VmcntHi = ((1 << getVmcntBitWidthHi()) - 1) << getVmcntBitWidthLo();
512   return VmcntLo | VmcntHi;
513 }
514 
515 unsigned getExpcntBitMask(const IsaInfo::IsaVersion &Version) {
516   return (1 << getExpcntBitWidth()) - 1;
517 }
518 
519 unsigned getLgkmcntBitMask(const IsaInfo::IsaVersion &Version) {
520   return (1 << getLgkmcntBitWidth()) - 1;
521 }
522 
523 unsigned getWaitcntBitMask(const IsaInfo::IsaVersion &Version) {
524   unsigned VmcntLo = getBitMask(getVmcntBitShiftLo(), getVmcntBitWidthLo());
525   unsigned Expcnt = getBitMask(getExpcntBitShift(), getExpcntBitWidth());
526   unsigned Lgkmcnt = getBitMask(getLgkmcntBitShift(), getLgkmcntBitWidth());
527   unsigned Waitcnt = VmcntLo | Expcnt | Lgkmcnt;
528   if (Version.Major < 9)
529     return Waitcnt;
530 
531   unsigned VmcntHi = getBitMask(getVmcntBitShiftHi(), getVmcntBitWidthHi());
532   return Waitcnt | VmcntHi;
533 }
534 
535 unsigned decodeVmcnt(const IsaInfo::IsaVersion &Version, unsigned Waitcnt) {
536   unsigned VmcntLo =
537       unpackBits(Waitcnt, getVmcntBitShiftLo(), getVmcntBitWidthLo());
538   if (Version.Major < 9)
539     return VmcntLo;
540 
541   unsigned VmcntHi =
542       unpackBits(Waitcnt, getVmcntBitShiftHi(), getVmcntBitWidthHi());
543   VmcntHi <<= getVmcntBitWidthLo();
544   return VmcntLo | VmcntHi;
545 }
546 
547 unsigned decodeExpcnt(const IsaInfo::IsaVersion &Version, unsigned Waitcnt) {
548   return unpackBits(Waitcnt, getExpcntBitShift(), getExpcntBitWidth());
549 }
550 
551 unsigned decodeLgkmcnt(const IsaInfo::IsaVersion &Version, unsigned Waitcnt) {
552   return unpackBits(Waitcnt, getLgkmcntBitShift(), getLgkmcntBitWidth());
553 }
554 
555 void decodeWaitcnt(const IsaInfo::IsaVersion &Version, unsigned Waitcnt,
556                    unsigned &Vmcnt, unsigned &Expcnt, unsigned &Lgkmcnt) {
557   Vmcnt = decodeVmcnt(Version, Waitcnt);
558   Expcnt = decodeExpcnt(Version, Waitcnt);
559   Lgkmcnt = decodeLgkmcnt(Version, Waitcnt);
560 }
561 
562 unsigned encodeVmcnt(const IsaInfo::IsaVersion &Version, unsigned Waitcnt,
563                      unsigned Vmcnt) {
564   Waitcnt =
565       packBits(Vmcnt, Waitcnt, getVmcntBitShiftLo(), getVmcntBitWidthLo());
566   if (Version.Major < 9)
567     return Waitcnt;
568 
569   Vmcnt >>= getVmcntBitWidthLo();
570   return packBits(Vmcnt, Waitcnt, getVmcntBitShiftHi(), getVmcntBitWidthHi());
571 }
572 
573 unsigned encodeExpcnt(const IsaInfo::IsaVersion &Version, unsigned Waitcnt,
574                       unsigned Expcnt) {
575   return packBits(Expcnt, Waitcnt, getExpcntBitShift(), getExpcntBitWidth());
576 }
577 
578 unsigned encodeLgkmcnt(const IsaInfo::IsaVersion &Version, unsigned Waitcnt,
579                        unsigned Lgkmcnt) {
580   return packBits(Lgkmcnt, Waitcnt, getLgkmcntBitShift(), getLgkmcntBitWidth());
581 }
582 
583 unsigned encodeWaitcnt(const IsaInfo::IsaVersion &Version,
584                        unsigned Vmcnt, unsigned Expcnt, unsigned Lgkmcnt) {
585   unsigned Waitcnt = getWaitcntBitMask(Version);
586   Waitcnt = encodeVmcnt(Version, Waitcnt, Vmcnt);
587   Waitcnt = encodeExpcnt(Version, Waitcnt, Expcnt);
588   Waitcnt = encodeLgkmcnt(Version, Waitcnt, Lgkmcnt);
589   return Waitcnt;
590 }
591 
592 unsigned getInitialPSInputAddr(const Function &F) {
593   return getIntegerAttribute(F, "InitialPSInputAddr", 0);
594 }
595 
596 bool isShader(CallingConv::ID cc) {
597   switch(cc) {
598     case CallingConv::AMDGPU_VS:
599     case CallingConv::AMDGPU_LS:
600     case CallingConv::AMDGPU_HS:
601     case CallingConv::AMDGPU_ES:
602     case CallingConv::AMDGPU_GS:
603     case CallingConv::AMDGPU_PS:
604     case CallingConv::AMDGPU_CS:
605       return true;
606     default:
607       return false;
608   }
609 }
610 
611 bool isCompute(CallingConv::ID cc) {
612   return !isShader(cc) || cc == CallingConv::AMDGPU_CS;
613 }
614 
615 bool isEntryFunctionCC(CallingConv::ID CC) {
616   switch (CC) {
617   case CallingConv::AMDGPU_KERNEL:
618   case CallingConv::SPIR_KERNEL:
619   case CallingConv::AMDGPU_VS:
620   case CallingConv::AMDGPU_GS:
621   case CallingConv::AMDGPU_PS:
622   case CallingConv::AMDGPU_CS:
623   case CallingConv::AMDGPU_ES:
624   case CallingConv::AMDGPU_HS:
625   case CallingConv::AMDGPU_LS:
626     return true;
627   default:
628     return false;
629   }
630 }
631 
632 bool hasXNACK(const MCSubtargetInfo &STI) {
633   return STI.getFeatureBits()[AMDGPU::FeatureXNACK];
634 }
635 
636 bool hasMIMG_R128(const MCSubtargetInfo &STI) {
637   return STI.getFeatureBits()[AMDGPU::FeatureMIMG_R128];
638 }
639 
640 bool hasPackedD16(const MCSubtargetInfo &STI) {
641   return !STI.getFeatureBits()[AMDGPU::FeatureUnpackedD16VMem];
642 }
643 
644 bool isSI(const MCSubtargetInfo &STI) {
645   return STI.getFeatureBits()[AMDGPU::FeatureSouthernIslands];
646 }
647 
648 bool isCI(const MCSubtargetInfo &STI) {
649   return STI.getFeatureBits()[AMDGPU::FeatureSeaIslands];
650 }
651 
652 bool isVI(const MCSubtargetInfo &STI) {
653   return STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands];
654 }
655 
656 bool isGFX9(const MCSubtargetInfo &STI) {
657   return STI.getFeatureBits()[AMDGPU::FeatureGFX9];
658 }
659 
660 bool isGCN3Encoding(const MCSubtargetInfo &STI) {
661   return STI.getFeatureBits()[AMDGPU::FeatureGCN3Encoding];
662 }
663 
664 bool isSGPR(unsigned Reg, const MCRegisterInfo* TRI) {
665   const MCRegisterClass SGPRClass = TRI->getRegClass(AMDGPU::SReg_32RegClassID);
666   const unsigned FirstSubReg = TRI->getSubReg(Reg, 1);
667   return SGPRClass.contains(FirstSubReg != 0 ? FirstSubReg : Reg) ||
668     Reg == AMDGPU::SCC;
669 }
670 
671 bool isRegIntersect(unsigned Reg0, unsigned Reg1, const MCRegisterInfo* TRI) {
672   for (MCRegAliasIterator R(Reg0, TRI, true); R.isValid(); ++R) {
673     if (*R == Reg1) return true;
674   }
675   return false;
676 }
677 
678 #define MAP_REG2REG \
679   using namespace AMDGPU; \
680   switch(Reg) { \
681   default: return Reg; \
682   CASE_CI_VI(FLAT_SCR) \
683   CASE_CI_VI(FLAT_SCR_LO) \
684   CASE_CI_VI(FLAT_SCR_HI) \
685   CASE_VI_GFX9(TTMP0) \
686   CASE_VI_GFX9(TTMP1) \
687   CASE_VI_GFX9(TTMP2) \
688   CASE_VI_GFX9(TTMP3) \
689   CASE_VI_GFX9(TTMP4) \
690   CASE_VI_GFX9(TTMP5) \
691   CASE_VI_GFX9(TTMP6) \
692   CASE_VI_GFX9(TTMP7) \
693   CASE_VI_GFX9(TTMP8) \
694   CASE_VI_GFX9(TTMP9) \
695   CASE_VI_GFX9(TTMP10) \
696   CASE_VI_GFX9(TTMP11) \
697   CASE_VI_GFX9(TTMP12) \
698   CASE_VI_GFX9(TTMP13) \
699   CASE_VI_GFX9(TTMP14) \
700   CASE_VI_GFX9(TTMP15) \
701   CASE_VI_GFX9(TTMP0_TTMP1) \
702   CASE_VI_GFX9(TTMP2_TTMP3) \
703   CASE_VI_GFX9(TTMP4_TTMP5) \
704   CASE_VI_GFX9(TTMP6_TTMP7) \
705   CASE_VI_GFX9(TTMP8_TTMP9) \
706   CASE_VI_GFX9(TTMP10_TTMP11) \
707   CASE_VI_GFX9(TTMP12_TTMP13) \
708   CASE_VI_GFX9(TTMP14_TTMP15) \
709   CASE_VI_GFX9(TTMP0_TTMP1_TTMP2_TTMP3) \
710   CASE_VI_GFX9(TTMP4_TTMP5_TTMP6_TTMP7) \
711   CASE_VI_GFX9(TTMP8_TTMP9_TTMP10_TTMP11) \
712   CASE_VI_GFX9(TTMP12_TTMP13_TTMP14_TTMP15) \
713   CASE_VI_GFX9(TTMP0_TTMP1_TTMP2_TTMP3_TTMP4_TTMP5_TTMP6_TTMP7) \
714   CASE_VI_GFX9(TTMP4_TTMP5_TTMP6_TTMP7_TTMP8_TTMP9_TTMP10_TTMP11) \
715   CASE_VI_GFX9(TTMP8_TTMP9_TTMP10_TTMP11_TTMP12_TTMP13_TTMP14_TTMP15) \
716   CASE_VI_GFX9(TTMP0_TTMP1_TTMP2_TTMP3_TTMP4_TTMP5_TTMP6_TTMP7_TTMP8_TTMP9_TTMP10_TTMP11_TTMP12_TTMP13_TTMP14_TTMP15) \
717   }
718 
719 #define CASE_CI_VI(node) \
720   assert(!isSI(STI)); \
721   case node: return isCI(STI) ? node##_ci : node##_vi;
722 
723 #define CASE_VI_GFX9(node) \
724   case node: return isGFX9(STI) ? node##_gfx9 : node##_vi;
725 
726 unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI) {
727   MAP_REG2REG
728 }
729 
730 #undef CASE_CI_VI
731 #undef CASE_VI_GFX9
732 
733 #define CASE_CI_VI(node)   case node##_ci: case node##_vi:   return node;
734 #define CASE_VI_GFX9(node) case node##_vi: case node##_gfx9: return node;
735 
736 unsigned mc2PseudoReg(unsigned Reg) {
737   MAP_REG2REG
738 }
739 
740 #undef CASE_CI_VI
741 #undef CASE_VI_GFX9
742 #undef MAP_REG2REG
743 
744 bool isSISrcOperand(const MCInstrDesc &Desc, unsigned OpNo) {
745   assert(OpNo < Desc.NumOperands);
746   unsigned OpType = Desc.OpInfo[OpNo].OperandType;
747   return OpType >= AMDGPU::OPERAND_SRC_FIRST &&
748          OpType <= AMDGPU::OPERAND_SRC_LAST;
749 }
750 
751 bool isSISrcFPOperand(const MCInstrDesc &Desc, unsigned OpNo) {
752   assert(OpNo < Desc.NumOperands);
753   unsigned OpType = Desc.OpInfo[OpNo].OperandType;
754   switch (OpType) {
755   case AMDGPU::OPERAND_REG_IMM_FP32:
756   case AMDGPU::OPERAND_REG_IMM_FP64:
757   case AMDGPU::OPERAND_REG_IMM_FP16:
758   case AMDGPU::OPERAND_REG_INLINE_C_FP32:
759   case AMDGPU::OPERAND_REG_INLINE_C_FP64:
760   case AMDGPU::OPERAND_REG_INLINE_C_FP16:
761   case AMDGPU::OPERAND_REG_INLINE_C_V2FP16:
762     return true;
763   default:
764     return false;
765   }
766 }
767 
768 bool isSISrcInlinableOperand(const MCInstrDesc &Desc, unsigned OpNo) {
769   assert(OpNo < Desc.NumOperands);
770   unsigned OpType = Desc.OpInfo[OpNo].OperandType;
771   return OpType >= AMDGPU::OPERAND_REG_INLINE_C_FIRST &&
772          OpType <= AMDGPU::OPERAND_REG_INLINE_C_LAST;
773 }
774 
775 // Avoid using MCRegisterClass::getSize, since that function will go away
776 // (move from MC* level to Target* level). Return size in bits.
777 unsigned getRegBitWidth(unsigned RCID) {
778   switch (RCID) {
779   case AMDGPU::SGPR_32RegClassID:
780   case AMDGPU::VGPR_32RegClassID:
781   case AMDGPU::VS_32RegClassID:
782   case AMDGPU::SReg_32RegClassID:
783   case AMDGPU::SReg_32_XM0RegClassID:
784     return 32;
785   case AMDGPU::SGPR_64RegClassID:
786   case AMDGPU::VS_64RegClassID:
787   case AMDGPU::SReg_64RegClassID:
788   case AMDGPU::VReg_64RegClassID:
789     return 64;
790   case AMDGPU::VReg_96RegClassID:
791     return 96;
792   case AMDGPU::SGPR_128RegClassID:
793   case AMDGPU::SReg_128RegClassID:
794   case AMDGPU::VReg_128RegClassID:
795     return 128;
796   case AMDGPU::SReg_256RegClassID:
797   case AMDGPU::VReg_256RegClassID:
798     return 256;
799   case AMDGPU::SReg_512RegClassID:
800   case AMDGPU::VReg_512RegClassID:
801     return 512;
802   default:
803     llvm_unreachable("Unexpected register class");
804   }
805 }
806 
807 unsigned getRegBitWidth(const MCRegisterClass &RC) {
808   return getRegBitWidth(RC.getID());
809 }
810 
811 unsigned getRegOperandSize(const MCRegisterInfo *MRI, const MCInstrDesc &Desc,
812                            unsigned OpNo) {
813   assert(OpNo < Desc.NumOperands);
814   unsigned RCID = Desc.OpInfo[OpNo].RegClass;
815   return getRegBitWidth(MRI->getRegClass(RCID)) / 8;
816 }
817 
818 bool isInlinableLiteral64(int64_t Literal, bool HasInv2Pi) {
819   if (Literal >= -16 && Literal <= 64)
820     return true;
821 
822   uint64_t Val = static_cast<uint64_t>(Literal);
823   return (Val == DoubleToBits(0.0)) ||
824          (Val == DoubleToBits(1.0)) ||
825          (Val == DoubleToBits(-1.0)) ||
826          (Val == DoubleToBits(0.5)) ||
827          (Val == DoubleToBits(-0.5)) ||
828          (Val == DoubleToBits(2.0)) ||
829          (Val == DoubleToBits(-2.0)) ||
830          (Val == DoubleToBits(4.0)) ||
831          (Val == DoubleToBits(-4.0)) ||
832          (Val == 0x3fc45f306dc9c882 && HasInv2Pi);
833 }
834 
835 bool isInlinableLiteral32(int32_t Literal, bool HasInv2Pi) {
836   if (Literal >= -16 && Literal <= 64)
837     return true;
838 
839   // The actual type of the operand does not seem to matter as long
840   // as the bits match one of the inline immediate values.  For example:
841   //
842   // -nan has the hexadecimal encoding of 0xfffffffe which is -2 in decimal,
843   // so it is a legal inline immediate.
844   //
845   // 1065353216 has the hexadecimal encoding 0x3f800000 which is 1.0f in
846   // floating-point, so it is a legal inline immediate.
847 
848   uint32_t Val = static_cast<uint32_t>(Literal);
849   return (Val == FloatToBits(0.0f)) ||
850          (Val == FloatToBits(1.0f)) ||
851          (Val == FloatToBits(-1.0f)) ||
852          (Val == FloatToBits(0.5f)) ||
853          (Val == FloatToBits(-0.5f)) ||
854          (Val == FloatToBits(2.0f)) ||
855          (Val == FloatToBits(-2.0f)) ||
856          (Val == FloatToBits(4.0f)) ||
857          (Val == FloatToBits(-4.0f)) ||
858          (Val == 0x3e22f983 && HasInv2Pi);
859 }
860 
861 bool isInlinableLiteral16(int16_t Literal, bool HasInv2Pi) {
862   if (!HasInv2Pi)
863     return false;
864 
865   if (Literal >= -16 && Literal <= 64)
866     return true;
867 
868   uint16_t Val = static_cast<uint16_t>(Literal);
869   return Val == 0x3C00 || // 1.0
870          Val == 0xBC00 || // -1.0
871          Val == 0x3800 || // 0.5
872          Val == 0xB800 || // -0.5
873          Val == 0x4000 || // 2.0
874          Val == 0xC000 || // -2.0
875          Val == 0x4400 || // 4.0
876          Val == 0xC400 || // -4.0
877          Val == 0x3118;   // 1/2pi
878 }
879 
880 bool isInlinableLiteralV216(int32_t Literal, bool HasInv2Pi) {
881   assert(HasInv2Pi);
882 
883   int16_t Lo16 = static_cast<int16_t>(Literal);
884   int16_t Hi16 = static_cast<int16_t>(Literal >> 16);
885   return Lo16 == Hi16 && isInlinableLiteral16(Lo16, HasInv2Pi);
886 }
887 
888 bool isArgPassedInSGPR(const Argument *A) {
889   const Function *F = A->getParent();
890 
891   // Arguments to compute shaders are never a source of divergence.
892   CallingConv::ID CC = F->getCallingConv();
893   switch (CC) {
894   case CallingConv::AMDGPU_KERNEL:
895   case CallingConv::SPIR_KERNEL:
896     return true;
897   case CallingConv::AMDGPU_VS:
898   case CallingConv::AMDGPU_LS:
899   case CallingConv::AMDGPU_HS:
900   case CallingConv::AMDGPU_ES:
901   case CallingConv::AMDGPU_GS:
902   case CallingConv::AMDGPU_PS:
903   case CallingConv::AMDGPU_CS:
904     // For non-compute shaders, SGPR inputs are marked with either inreg or byval.
905     // Everything else is in VGPRs.
906     return F->getAttributes().hasParamAttribute(A->getArgNo(), Attribute::InReg) ||
907            F->getAttributes().hasParamAttribute(A->getArgNo(), Attribute::ByVal);
908   default:
909     // TODO: Should calls support inreg for SGPR inputs?
910     return false;
911   }
912 }
913 
914 int64_t getSMRDEncodedOffset(const MCSubtargetInfo &ST, int64_t ByteOffset) {
915   if (isGCN3Encoding(ST))
916     return ByteOffset;
917   return ByteOffset >> 2;
918 }
919 
920 bool isLegalSMRDImmOffset(const MCSubtargetInfo &ST, int64_t ByteOffset) {
921   int64_t EncodedOffset = getSMRDEncodedOffset(ST, ByteOffset);
922   return isGCN3Encoding(ST) ?
923     isUInt<20>(EncodedOffset) : isUInt<8>(EncodedOffset);
924 }
925 
926 } // end namespace AMDGPU
927 
928 } // end namespace llvm
929 
930 namespace llvm {
931 namespace AMDGPU {
932 
933 AMDGPUAS getAMDGPUAS(Triple T) {
934   AMDGPUAS AS;
935   AS.FLAT_ADDRESS = 0;
936   AS.PRIVATE_ADDRESS = 5;
937   AS.REGION_ADDRESS = 2;
938   return AS;
939 }
940 
941 AMDGPUAS getAMDGPUAS(const TargetMachine &M) {
942   return getAMDGPUAS(M.getTargetTriple());
943 }
944 
945 AMDGPUAS getAMDGPUAS(const Module &M) {
946   return getAMDGPUAS(Triple(M.getTargetTriple()));
947 }
948 
949 namespace {
950 
951 struct SourceOfDivergence {
952   unsigned Intr;
953 };
954 const SourceOfDivergence *lookupSourceOfDivergenceByIntr(unsigned Intr);
955 
956 #define GET_SOURCEOFDIVERGENCE_IMPL
957 #include "AMDGPUGenSearchableTables.inc"
958 
959 } // end anonymous namespace
960 
961 bool isIntrinsicSourceOfDivergence(unsigned IntrID) {
962   return lookupSourceOfDivergenceByIntr(IntrID);
963 }
964 } // namespace AMDGPU
965 } // namespace llvm
966