1 //===-- AMDGPUAsmUtils.cpp - AsmParser/InstPrinter common -----------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 #include "AMDGPUAsmUtils.h" 9 #include "AMDGPUBaseInfo.h" 10 #include "SIDefines.h" 11 12 namespace llvm { 13 namespace AMDGPU { 14 namespace SendMsg { 15 16 // This must be in sync with llvm::AMDGPU::SendMsg::Id enum members, see SIDefines.h. 17 const char *const IdSymbolic[ID_GAPS_LAST_] = { 18 nullptr, 19 "MSG_INTERRUPT", 20 "MSG_GS", 21 "MSG_GS_DONE", 22 "MSG_SAVEWAVE", 23 "MSG_STALL_WAVE_GEN", 24 "MSG_HALT_WAVES", 25 "MSG_ORDERED_PS_DONE", 26 "MSG_EARLY_PRIM_DEALLOC", 27 "MSG_GS_ALLOC_REQ", 28 "MSG_GET_DOORBELL", 29 "MSG_GET_DDID", 30 nullptr, 31 nullptr, 32 nullptr, 33 "MSG_SYSMSG" 34 }; 35 36 // These two must be in sync with llvm::AMDGPU::SendMsg::Op enum members, see SIDefines.h. 37 const char *const OpSysSymbolic[OP_SYS_LAST_] = { 38 nullptr, 39 "SYSMSG_OP_ECC_ERR_INTERRUPT", 40 "SYSMSG_OP_REG_RD", 41 "SYSMSG_OP_HOST_TRAP_ACK", 42 "SYSMSG_OP_TTRACE_PC" 43 }; 44 45 const char *const OpGsSymbolic[OP_GS_LAST_] = { 46 "GS_OP_NOP", 47 "GS_OP_CUT", 48 "GS_OP_EMIT", 49 "GS_OP_EMIT_CUT" 50 }; 51 52 } // namespace SendMsg 53 54 namespace Hwreg { 55 56 // Disable lint checking for this block since it makes the table unreadable. 57 // NOLINTBEGIN 58 const CustomOperand<const MCSubtargetInfo &> Opr[] = { 59 {}, 60 {{"HW_REG_MODE"}, ID_MODE}, 61 {{"HW_REG_STATUS"}, ID_STATUS}, 62 {{"HW_REG_TRAPSTS"}, ID_TRAPSTS}, 63 {{"HW_REG_HW_ID"}, ID_HW_ID, 64 [](const MCSubtargetInfo &STI) { 65 return isSI(STI) || isCI(STI) || 66 isVI(STI) || isGFX9(STI); 67 }}, 68 {{"HW_REG_GPR_ALLOC"}, ID_GPR_ALLOC}, 69 {{"HW_REG_LDS_ALLOC"}, ID_LDS_ALLOC}, 70 {{"HW_REG_IB_STS"}, ID_IB_STS}, 71 {}, 72 {}, 73 {}, 74 {}, 75 {}, 76 {}, 77 {}, 78 {{"HW_REG_SH_MEM_BASES"}, ID_MEM_BASES, isGFX9Plus}, 79 {{"HW_REG_TBA_LO"}, ID_TBA_LO, isGFX9_GFX10}, 80 {{"HW_REG_TBA_HI"}, ID_TBA_HI, isGFX9_GFX10}, 81 {{"HW_REG_TMA_LO"}, ID_TMA_LO, isGFX9_GFX10}, 82 {{"HW_REG_TMA_HI"}, ID_TMA_HI, isGFX9_GFX10}, 83 {{"HW_REG_FLAT_SCR_LO"}, ID_FLAT_SCR_LO, isGFX10Plus}, 84 {{"HW_REG_FLAT_SCR_HI"}, ID_FLAT_SCR_HI, isGFX10Plus}, 85 {{"HW_REG_XNACK_MASK"}, ID_XNACK_MASK, 86 [](const MCSubtargetInfo &STI) { 87 return isGFX10(STI) && 88 !AMDGPU::isGFX10_BEncoding(STI); 89 }}, 90 {{"HW_REG_HW_ID1"}, ID_HW_ID1, isGFX10Plus}, 91 {{"HW_REG_HW_ID2"}, ID_HW_ID2, isGFX10Plus}, 92 {{"HW_REG_POPS_PACKER"}, ID_POPS_PACKER, isGFX10}, 93 {}, 94 {}, 95 {}, 96 {{"HW_REG_SHADER_CYCLES"}, ID_SHADER_CYCLES, isGFX10_BEncoding}, 97 98 // GFX940 specific registers 99 {{"HW_REG_XCC_ID"}, ID_XCC_ID, isGFX940}, 100 {{"HW_REG_SQ_PERF_SNAPSHOT_DATA"}, ID_SQ_PERF_SNAPSHOT_DATA, isGFX940}, 101 {{"HW_REG_SQ_PERF_SNAPSHOT_DATA1"}, ID_SQ_PERF_SNAPSHOT_DATA1, isGFX940}, 102 {{"HW_REG_SQ_PERF_SNAPSHOT_PC_LO"}, ID_SQ_PERF_SNAPSHOT_PC_LO, isGFX940}, 103 {{"HW_REG_SQ_PERF_SNAPSHOT_PC_HI"}, ID_SQ_PERF_SNAPSHOT_PC_HI, isGFX940}, 104 105 // Aliases 106 {{"HW_REG_HW_ID"}, ID_HW_ID1, isGFX10}, 107 }; 108 // NOLINTEND 109 110 const int OPR_SIZE = static_cast<int>( 111 sizeof(Opr) / sizeof(CustomOperand<const MCSubtargetInfo &>)); 112 113 } // namespace Hwreg 114 115 namespace MTBUFFormat { 116 117 StringLiteral const DfmtSymbolic[] = { 118 "BUF_DATA_FORMAT_INVALID", 119 "BUF_DATA_FORMAT_8", 120 "BUF_DATA_FORMAT_16", 121 "BUF_DATA_FORMAT_8_8", 122 "BUF_DATA_FORMAT_32", 123 "BUF_DATA_FORMAT_16_16", 124 "BUF_DATA_FORMAT_10_11_11", 125 "BUF_DATA_FORMAT_11_11_10", 126 "BUF_DATA_FORMAT_10_10_10_2", 127 "BUF_DATA_FORMAT_2_10_10_10", 128 "BUF_DATA_FORMAT_8_8_8_8", 129 "BUF_DATA_FORMAT_32_32", 130 "BUF_DATA_FORMAT_16_16_16_16", 131 "BUF_DATA_FORMAT_32_32_32", 132 "BUF_DATA_FORMAT_32_32_32_32", 133 "BUF_DATA_FORMAT_RESERVED_15" 134 }; 135 136 StringLiteral const NfmtSymbolicGFX10[] = { 137 "BUF_NUM_FORMAT_UNORM", 138 "BUF_NUM_FORMAT_SNORM", 139 "BUF_NUM_FORMAT_USCALED", 140 "BUF_NUM_FORMAT_SSCALED", 141 "BUF_NUM_FORMAT_UINT", 142 "BUF_NUM_FORMAT_SINT", 143 "", 144 "BUF_NUM_FORMAT_FLOAT" 145 }; 146 147 StringLiteral const NfmtSymbolicSICI[] = { 148 "BUF_NUM_FORMAT_UNORM", 149 "BUF_NUM_FORMAT_SNORM", 150 "BUF_NUM_FORMAT_USCALED", 151 "BUF_NUM_FORMAT_SSCALED", 152 "BUF_NUM_FORMAT_UINT", 153 "BUF_NUM_FORMAT_SINT", 154 "BUF_NUM_FORMAT_SNORM_OGL", 155 "BUF_NUM_FORMAT_FLOAT" 156 }; 157 158 StringLiteral const NfmtSymbolicVI[] = { // VI and GFX9 159 "BUF_NUM_FORMAT_UNORM", 160 "BUF_NUM_FORMAT_SNORM", 161 "BUF_NUM_FORMAT_USCALED", 162 "BUF_NUM_FORMAT_SSCALED", 163 "BUF_NUM_FORMAT_UINT", 164 "BUF_NUM_FORMAT_SINT", 165 "BUF_NUM_FORMAT_RESERVED_6", 166 "BUF_NUM_FORMAT_FLOAT" 167 }; 168 169 StringLiteral const UfmtSymbolic[] = { 170 "BUF_FMT_INVALID", 171 172 "BUF_FMT_8_UNORM", 173 "BUF_FMT_8_SNORM", 174 "BUF_FMT_8_USCALED", 175 "BUF_FMT_8_SSCALED", 176 "BUF_FMT_8_UINT", 177 "BUF_FMT_8_SINT", 178 179 "BUF_FMT_16_UNORM", 180 "BUF_FMT_16_SNORM", 181 "BUF_FMT_16_USCALED", 182 "BUF_FMT_16_SSCALED", 183 "BUF_FMT_16_UINT", 184 "BUF_FMT_16_SINT", 185 "BUF_FMT_16_FLOAT", 186 187 "BUF_FMT_8_8_UNORM", 188 "BUF_FMT_8_8_SNORM", 189 "BUF_FMT_8_8_USCALED", 190 "BUF_FMT_8_8_SSCALED", 191 "BUF_FMT_8_8_UINT", 192 "BUF_FMT_8_8_SINT", 193 194 "BUF_FMT_32_UINT", 195 "BUF_FMT_32_SINT", 196 "BUF_FMT_32_FLOAT", 197 198 "BUF_FMT_16_16_UNORM", 199 "BUF_FMT_16_16_SNORM", 200 "BUF_FMT_16_16_USCALED", 201 "BUF_FMT_16_16_SSCALED", 202 "BUF_FMT_16_16_UINT", 203 "BUF_FMT_16_16_SINT", 204 "BUF_FMT_16_16_FLOAT", 205 206 "BUF_FMT_10_11_11_UNORM", 207 "BUF_FMT_10_11_11_SNORM", 208 "BUF_FMT_10_11_11_USCALED", 209 "BUF_FMT_10_11_11_SSCALED", 210 "BUF_FMT_10_11_11_UINT", 211 "BUF_FMT_10_11_11_SINT", 212 "BUF_FMT_10_11_11_FLOAT", 213 214 "BUF_FMT_11_11_10_UNORM", 215 "BUF_FMT_11_11_10_SNORM", 216 "BUF_FMT_11_11_10_USCALED", 217 "BUF_FMT_11_11_10_SSCALED", 218 "BUF_FMT_11_11_10_UINT", 219 "BUF_FMT_11_11_10_SINT", 220 "BUF_FMT_11_11_10_FLOAT", 221 222 "BUF_FMT_10_10_10_2_UNORM", 223 "BUF_FMT_10_10_10_2_SNORM", 224 "BUF_FMT_10_10_10_2_USCALED", 225 "BUF_FMT_10_10_10_2_SSCALED", 226 "BUF_FMT_10_10_10_2_UINT", 227 "BUF_FMT_10_10_10_2_SINT", 228 229 "BUF_FMT_2_10_10_10_UNORM", 230 "BUF_FMT_2_10_10_10_SNORM", 231 "BUF_FMT_2_10_10_10_USCALED", 232 "BUF_FMT_2_10_10_10_SSCALED", 233 "BUF_FMT_2_10_10_10_UINT", 234 "BUF_FMT_2_10_10_10_SINT", 235 236 "BUF_FMT_8_8_8_8_UNORM", 237 "BUF_FMT_8_8_8_8_SNORM", 238 "BUF_FMT_8_8_8_8_USCALED", 239 "BUF_FMT_8_8_8_8_SSCALED", 240 "BUF_FMT_8_8_8_8_UINT", 241 "BUF_FMT_8_8_8_8_SINT", 242 243 "BUF_FMT_32_32_UINT", 244 "BUF_FMT_32_32_SINT", 245 "BUF_FMT_32_32_FLOAT", 246 247 "BUF_FMT_16_16_16_16_UNORM", 248 "BUF_FMT_16_16_16_16_SNORM", 249 "BUF_FMT_16_16_16_16_USCALED", 250 "BUF_FMT_16_16_16_16_SSCALED", 251 "BUF_FMT_16_16_16_16_UINT", 252 "BUF_FMT_16_16_16_16_SINT", 253 "BUF_FMT_16_16_16_16_FLOAT", 254 255 "BUF_FMT_32_32_32_UINT", 256 "BUF_FMT_32_32_32_SINT", 257 "BUF_FMT_32_32_32_FLOAT", 258 "BUF_FMT_32_32_32_32_UINT", 259 "BUF_FMT_32_32_32_32_SINT", 260 "BUF_FMT_32_32_32_32_FLOAT" 261 }; 262 263 unsigned const DfmtNfmt2UFmt[] = { 264 DFMT_INVALID | (NFMT_UNORM << NFMT_SHIFT), 265 266 DFMT_8 | (NFMT_UNORM << NFMT_SHIFT), 267 DFMT_8 | (NFMT_SNORM << NFMT_SHIFT), 268 DFMT_8 | (NFMT_USCALED << NFMT_SHIFT), 269 DFMT_8 | (NFMT_SSCALED << NFMT_SHIFT), 270 DFMT_8 | (NFMT_UINT << NFMT_SHIFT), 271 DFMT_8 | (NFMT_SINT << NFMT_SHIFT), 272 273 DFMT_16 | (NFMT_UNORM << NFMT_SHIFT), 274 DFMT_16 | (NFMT_SNORM << NFMT_SHIFT), 275 DFMT_16 | (NFMT_USCALED << NFMT_SHIFT), 276 DFMT_16 | (NFMT_SSCALED << NFMT_SHIFT), 277 DFMT_16 | (NFMT_UINT << NFMT_SHIFT), 278 DFMT_16 | (NFMT_SINT << NFMT_SHIFT), 279 DFMT_16 | (NFMT_FLOAT << NFMT_SHIFT), 280 281 DFMT_8_8 | (NFMT_UNORM << NFMT_SHIFT), 282 DFMT_8_8 | (NFMT_SNORM << NFMT_SHIFT), 283 DFMT_8_8 | (NFMT_USCALED << NFMT_SHIFT), 284 DFMT_8_8 | (NFMT_SSCALED << NFMT_SHIFT), 285 DFMT_8_8 | (NFMT_UINT << NFMT_SHIFT), 286 DFMT_8_8 | (NFMT_SINT << NFMT_SHIFT), 287 288 DFMT_32 | (NFMT_UINT << NFMT_SHIFT), 289 DFMT_32 | (NFMT_SINT << NFMT_SHIFT), 290 DFMT_32 | (NFMT_FLOAT << NFMT_SHIFT), 291 292 DFMT_16_16 | (NFMT_UNORM << NFMT_SHIFT), 293 DFMT_16_16 | (NFMT_SNORM << NFMT_SHIFT), 294 DFMT_16_16 | (NFMT_USCALED << NFMT_SHIFT), 295 DFMT_16_16 | (NFMT_SSCALED << NFMT_SHIFT), 296 DFMT_16_16 | (NFMT_UINT << NFMT_SHIFT), 297 DFMT_16_16 | (NFMT_SINT << NFMT_SHIFT), 298 DFMT_16_16 | (NFMT_FLOAT << NFMT_SHIFT), 299 300 DFMT_10_11_11 | (NFMT_UNORM << NFMT_SHIFT), 301 DFMT_10_11_11 | (NFMT_SNORM << NFMT_SHIFT), 302 DFMT_10_11_11 | (NFMT_USCALED << NFMT_SHIFT), 303 DFMT_10_11_11 | (NFMT_SSCALED << NFMT_SHIFT), 304 DFMT_10_11_11 | (NFMT_UINT << NFMT_SHIFT), 305 DFMT_10_11_11 | (NFMT_SINT << NFMT_SHIFT), 306 DFMT_10_11_11 | (NFMT_FLOAT << NFMT_SHIFT), 307 308 DFMT_11_11_10 | (NFMT_UNORM << NFMT_SHIFT), 309 DFMT_11_11_10 | (NFMT_SNORM << NFMT_SHIFT), 310 DFMT_11_11_10 | (NFMT_USCALED << NFMT_SHIFT), 311 DFMT_11_11_10 | (NFMT_SSCALED << NFMT_SHIFT), 312 DFMT_11_11_10 | (NFMT_UINT << NFMT_SHIFT), 313 DFMT_11_11_10 | (NFMT_SINT << NFMT_SHIFT), 314 DFMT_11_11_10 | (NFMT_FLOAT << NFMT_SHIFT), 315 316 DFMT_10_10_10_2 | (NFMT_UNORM << NFMT_SHIFT), 317 DFMT_10_10_10_2 | (NFMT_SNORM << NFMT_SHIFT), 318 DFMT_10_10_10_2 | (NFMT_USCALED << NFMT_SHIFT), 319 DFMT_10_10_10_2 | (NFMT_SSCALED << NFMT_SHIFT), 320 DFMT_10_10_10_2 | (NFMT_UINT << NFMT_SHIFT), 321 DFMT_10_10_10_2 | (NFMT_SINT << NFMT_SHIFT), 322 323 DFMT_2_10_10_10 | (NFMT_UNORM << NFMT_SHIFT), 324 DFMT_2_10_10_10 | (NFMT_SNORM << NFMT_SHIFT), 325 DFMT_2_10_10_10 | (NFMT_USCALED << NFMT_SHIFT), 326 DFMT_2_10_10_10 | (NFMT_SSCALED << NFMT_SHIFT), 327 DFMT_2_10_10_10 | (NFMT_UINT << NFMT_SHIFT), 328 DFMT_2_10_10_10 | (NFMT_SINT << NFMT_SHIFT), 329 330 DFMT_8_8_8_8 | (NFMT_UNORM << NFMT_SHIFT), 331 DFMT_8_8_8_8 | (NFMT_SNORM << NFMT_SHIFT), 332 DFMT_8_8_8_8 | (NFMT_USCALED << NFMT_SHIFT), 333 DFMT_8_8_8_8 | (NFMT_SSCALED << NFMT_SHIFT), 334 DFMT_8_8_8_8 | (NFMT_UINT << NFMT_SHIFT), 335 DFMT_8_8_8_8 | (NFMT_SINT << NFMT_SHIFT), 336 337 DFMT_32_32 | (NFMT_UINT << NFMT_SHIFT), 338 DFMT_32_32 | (NFMT_SINT << NFMT_SHIFT), 339 DFMT_32_32 | (NFMT_FLOAT << NFMT_SHIFT), 340 341 DFMT_16_16_16_16 | (NFMT_UNORM << NFMT_SHIFT), 342 DFMT_16_16_16_16 | (NFMT_SNORM << NFMT_SHIFT), 343 DFMT_16_16_16_16 | (NFMT_USCALED << NFMT_SHIFT), 344 DFMT_16_16_16_16 | (NFMT_SSCALED << NFMT_SHIFT), 345 DFMT_16_16_16_16 | (NFMT_UINT << NFMT_SHIFT), 346 DFMT_16_16_16_16 | (NFMT_SINT << NFMT_SHIFT), 347 DFMT_16_16_16_16 | (NFMT_FLOAT << NFMT_SHIFT), 348 349 DFMT_32_32_32 | (NFMT_UINT << NFMT_SHIFT), 350 DFMT_32_32_32 | (NFMT_SINT << NFMT_SHIFT), 351 DFMT_32_32_32 | (NFMT_FLOAT << NFMT_SHIFT), 352 DFMT_32_32_32_32 | (NFMT_UINT << NFMT_SHIFT), 353 DFMT_32_32_32_32 | (NFMT_SINT << NFMT_SHIFT), 354 DFMT_32_32_32_32 | (NFMT_FLOAT << NFMT_SHIFT) 355 }; 356 357 } // namespace MTBUFFormat 358 359 namespace Swizzle { 360 361 // This must be in sync with llvm::AMDGPU::Swizzle::Id enum members, see SIDefines.h. 362 const char* const IdSymbolic[] = { 363 "QUAD_PERM", 364 "BITMASK_PERM", 365 "SWAP", 366 "REVERSE", 367 "BROADCAST", 368 }; 369 370 } // namespace Swizzle 371 372 namespace VGPRIndexMode { 373 374 // This must be in sync with llvm::AMDGPU::VGPRIndexMode::Id enum members, see SIDefines.h. 375 const char* const IdSymbolic[] = { 376 "SRC0", 377 "SRC1", 378 "SRC2", 379 "DST", 380 }; 381 382 } // namespace VGPRIndexMode 383 384 } // namespace AMDGPU 385 } // namespace llvm 386