1 //===-- AMDGPUAsmUtils.cpp - AsmParser/InstPrinter common -----------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 #include "AMDGPUAsmUtils.h" 9 #include "AMDGPUBaseInfo.h" 10 #include "SIDefines.h" 11 12 namespace llvm { 13 namespace AMDGPU { 14 namespace SendMsg { 15 16 // Disable lint checking for this block since it makes the table unreadable. 17 // NOLINTBEGIN 18 const CustomOperand<const MCSubtargetInfo &> Msg[] = { 19 {{""}}, 20 {{"MSG_INTERRUPT"}, ID_INTERRUPT}, 21 {{"MSG_GS"}, ID_GS}, 22 {{"MSG_GS_DONE"}, ID_GS_DONE}, 23 {{"MSG_SAVEWAVE"}, ID_SAVEWAVE, isGFX8Plus}, 24 {{"MSG_STALL_WAVE_GEN"}, ID_STALL_WAVE_GEN, isGFX9Plus}, 25 {{"MSG_HALT_WAVES"}, ID_HALT_WAVES, isGFX9Plus}, 26 {{"MSG_ORDERED_PS_DONE"}, ID_ORDERED_PS_DONE, isGFX9Plus}, 27 {{"MSG_EARLY_PRIM_DEALLOC"}, ID_EARLY_PRIM_DEALLOC, isGFX9}, 28 {{"MSG_GS_ALLOC_REQ"}, ID_GS_ALLOC_REQ, isGFX9Plus}, 29 {{"MSG_GET_DOORBELL"}, ID_GET_DOORBELL, isGFX9Plus}, 30 {{"MSG_GET_DDID"}, ID_GET_DDID, isGFX10Plus}, 31 {{""}}, 32 {{""}}, 33 {{""}}, 34 {{"MSG_SYSMSG"}, ID_SYSMSG}, 35 }; 36 // NOLINTEND 37 38 const int MSG_SIZE = static_cast<int>( 39 sizeof(Msg) / sizeof(CustomOperand<const MCSubtargetInfo &>)); 40 41 // These two must be in sync with llvm::AMDGPU::SendMsg::Op enum members, see SIDefines.h. 42 const char *const OpSysSymbolic[OP_SYS_LAST_] = { 43 nullptr, 44 "SYSMSG_OP_ECC_ERR_INTERRUPT", 45 "SYSMSG_OP_REG_RD", 46 "SYSMSG_OP_HOST_TRAP_ACK", 47 "SYSMSG_OP_TTRACE_PC" 48 }; 49 50 const char *const OpGsSymbolic[OP_GS_LAST_] = { 51 "GS_OP_NOP", 52 "GS_OP_CUT", 53 "GS_OP_EMIT", 54 "GS_OP_EMIT_CUT" 55 }; 56 57 } // namespace SendMsg 58 59 namespace Hwreg { 60 61 // Disable lint checking for this block since it makes the table unreadable. 62 // NOLINTBEGIN 63 const CustomOperand<const MCSubtargetInfo &> Opr[] = { 64 {{""}}, 65 {{"HW_REG_MODE"}, ID_MODE}, 66 {{"HW_REG_STATUS"}, ID_STATUS}, 67 {{"HW_REG_TRAPSTS"}, ID_TRAPSTS}, 68 {{"HW_REG_HW_ID"}, ID_HW_ID, isNotGFX10Plus}, 69 {{"HW_REG_GPR_ALLOC"}, ID_GPR_ALLOC}, 70 {{"HW_REG_LDS_ALLOC"}, ID_LDS_ALLOC}, 71 {{"HW_REG_IB_STS"}, ID_IB_STS}, 72 {{""}}, 73 {{""}}, 74 {{""}}, 75 {{""}}, 76 {{""}}, 77 {{""}}, 78 {{""}}, 79 {{"HW_REG_SH_MEM_BASES"}, ID_MEM_BASES, isGFX9Plus}, 80 {{"HW_REG_TBA_LO"}, ID_TBA_LO, isGFX9_GFX10}, 81 {{"HW_REG_TBA_HI"}, ID_TBA_HI, isGFX9_GFX10}, 82 {{"HW_REG_TMA_LO"}, ID_TMA_LO, isGFX9_GFX10}, 83 {{"HW_REG_TMA_HI"}, ID_TMA_HI, isGFX9_GFX10}, 84 {{"HW_REG_FLAT_SCR_LO"}, ID_FLAT_SCR_LO, isGFX10Plus}, 85 {{"HW_REG_FLAT_SCR_HI"}, ID_FLAT_SCR_HI, isGFX10Plus}, 86 {{"HW_REG_XNACK_MASK"}, ID_XNACK_MASK, isGFX10Before1030}, 87 {{"HW_REG_HW_ID1"}, ID_HW_ID1, isGFX10Plus}, 88 {{"HW_REG_HW_ID2"}, ID_HW_ID2, isGFX10Plus}, 89 {{"HW_REG_POPS_PACKER"}, ID_POPS_PACKER, isGFX10}, 90 {{""}}, 91 {{""}}, 92 {{""}}, 93 {{"HW_REG_SHADER_CYCLES"}, ID_SHADER_CYCLES, isGFX10_BEncoding}, 94 95 // GFX940 specific registers 96 {{"HW_REG_XCC_ID"}, ID_XCC_ID, isGFX940}, 97 {{"HW_REG_SQ_PERF_SNAPSHOT_DATA"}, ID_SQ_PERF_SNAPSHOT_DATA, isGFX940}, 98 {{"HW_REG_SQ_PERF_SNAPSHOT_DATA1"}, ID_SQ_PERF_SNAPSHOT_DATA1, isGFX940}, 99 {{"HW_REG_SQ_PERF_SNAPSHOT_PC_LO"}, ID_SQ_PERF_SNAPSHOT_PC_LO, isGFX940}, 100 {{"HW_REG_SQ_PERF_SNAPSHOT_PC_HI"}, ID_SQ_PERF_SNAPSHOT_PC_HI, isGFX940}, 101 102 // Aliases 103 {{"HW_REG_HW_ID"}, ID_HW_ID1, isGFX10}, 104 }; 105 // NOLINTEND 106 107 const int OPR_SIZE = static_cast<int>( 108 sizeof(Opr) / sizeof(CustomOperand<const MCSubtargetInfo &>)); 109 110 } // namespace Hwreg 111 112 namespace MTBUFFormat { 113 114 StringLiteral const DfmtSymbolic[] = { 115 "BUF_DATA_FORMAT_INVALID", 116 "BUF_DATA_FORMAT_8", 117 "BUF_DATA_FORMAT_16", 118 "BUF_DATA_FORMAT_8_8", 119 "BUF_DATA_FORMAT_32", 120 "BUF_DATA_FORMAT_16_16", 121 "BUF_DATA_FORMAT_10_11_11", 122 "BUF_DATA_FORMAT_11_11_10", 123 "BUF_DATA_FORMAT_10_10_10_2", 124 "BUF_DATA_FORMAT_2_10_10_10", 125 "BUF_DATA_FORMAT_8_8_8_8", 126 "BUF_DATA_FORMAT_32_32", 127 "BUF_DATA_FORMAT_16_16_16_16", 128 "BUF_DATA_FORMAT_32_32_32", 129 "BUF_DATA_FORMAT_32_32_32_32", 130 "BUF_DATA_FORMAT_RESERVED_15" 131 }; 132 133 StringLiteral const NfmtSymbolicGFX10[] = { 134 "BUF_NUM_FORMAT_UNORM", 135 "BUF_NUM_FORMAT_SNORM", 136 "BUF_NUM_FORMAT_USCALED", 137 "BUF_NUM_FORMAT_SSCALED", 138 "BUF_NUM_FORMAT_UINT", 139 "BUF_NUM_FORMAT_SINT", 140 "", 141 "BUF_NUM_FORMAT_FLOAT" 142 }; 143 144 StringLiteral const NfmtSymbolicSICI[] = { 145 "BUF_NUM_FORMAT_UNORM", 146 "BUF_NUM_FORMAT_SNORM", 147 "BUF_NUM_FORMAT_USCALED", 148 "BUF_NUM_FORMAT_SSCALED", 149 "BUF_NUM_FORMAT_UINT", 150 "BUF_NUM_FORMAT_SINT", 151 "BUF_NUM_FORMAT_SNORM_OGL", 152 "BUF_NUM_FORMAT_FLOAT" 153 }; 154 155 StringLiteral const NfmtSymbolicVI[] = { // VI and GFX9 156 "BUF_NUM_FORMAT_UNORM", 157 "BUF_NUM_FORMAT_SNORM", 158 "BUF_NUM_FORMAT_USCALED", 159 "BUF_NUM_FORMAT_SSCALED", 160 "BUF_NUM_FORMAT_UINT", 161 "BUF_NUM_FORMAT_SINT", 162 "BUF_NUM_FORMAT_RESERVED_6", 163 "BUF_NUM_FORMAT_FLOAT" 164 }; 165 166 StringLiteral const UfmtSymbolic[] = { 167 "BUF_FMT_INVALID", 168 169 "BUF_FMT_8_UNORM", 170 "BUF_FMT_8_SNORM", 171 "BUF_FMT_8_USCALED", 172 "BUF_FMT_8_SSCALED", 173 "BUF_FMT_8_UINT", 174 "BUF_FMT_8_SINT", 175 176 "BUF_FMT_16_UNORM", 177 "BUF_FMT_16_SNORM", 178 "BUF_FMT_16_USCALED", 179 "BUF_FMT_16_SSCALED", 180 "BUF_FMT_16_UINT", 181 "BUF_FMT_16_SINT", 182 "BUF_FMT_16_FLOAT", 183 184 "BUF_FMT_8_8_UNORM", 185 "BUF_FMT_8_8_SNORM", 186 "BUF_FMT_8_8_USCALED", 187 "BUF_FMT_8_8_SSCALED", 188 "BUF_FMT_8_8_UINT", 189 "BUF_FMT_8_8_SINT", 190 191 "BUF_FMT_32_UINT", 192 "BUF_FMT_32_SINT", 193 "BUF_FMT_32_FLOAT", 194 195 "BUF_FMT_16_16_UNORM", 196 "BUF_FMT_16_16_SNORM", 197 "BUF_FMT_16_16_USCALED", 198 "BUF_FMT_16_16_SSCALED", 199 "BUF_FMT_16_16_UINT", 200 "BUF_FMT_16_16_SINT", 201 "BUF_FMT_16_16_FLOAT", 202 203 "BUF_FMT_10_11_11_UNORM", 204 "BUF_FMT_10_11_11_SNORM", 205 "BUF_FMT_10_11_11_USCALED", 206 "BUF_FMT_10_11_11_SSCALED", 207 "BUF_FMT_10_11_11_UINT", 208 "BUF_FMT_10_11_11_SINT", 209 "BUF_FMT_10_11_11_FLOAT", 210 211 "BUF_FMT_11_11_10_UNORM", 212 "BUF_FMT_11_11_10_SNORM", 213 "BUF_FMT_11_11_10_USCALED", 214 "BUF_FMT_11_11_10_SSCALED", 215 "BUF_FMT_11_11_10_UINT", 216 "BUF_FMT_11_11_10_SINT", 217 "BUF_FMT_11_11_10_FLOAT", 218 219 "BUF_FMT_10_10_10_2_UNORM", 220 "BUF_FMT_10_10_10_2_SNORM", 221 "BUF_FMT_10_10_10_2_USCALED", 222 "BUF_FMT_10_10_10_2_SSCALED", 223 "BUF_FMT_10_10_10_2_UINT", 224 "BUF_FMT_10_10_10_2_SINT", 225 226 "BUF_FMT_2_10_10_10_UNORM", 227 "BUF_FMT_2_10_10_10_SNORM", 228 "BUF_FMT_2_10_10_10_USCALED", 229 "BUF_FMT_2_10_10_10_SSCALED", 230 "BUF_FMT_2_10_10_10_UINT", 231 "BUF_FMT_2_10_10_10_SINT", 232 233 "BUF_FMT_8_8_8_8_UNORM", 234 "BUF_FMT_8_8_8_8_SNORM", 235 "BUF_FMT_8_8_8_8_USCALED", 236 "BUF_FMT_8_8_8_8_SSCALED", 237 "BUF_FMT_8_8_8_8_UINT", 238 "BUF_FMT_8_8_8_8_SINT", 239 240 "BUF_FMT_32_32_UINT", 241 "BUF_FMT_32_32_SINT", 242 "BUF_FMT_32_32_FLOAT", 243 244 "BUF_FMT_16_16_16_16_UNORM", 245 "BUF_FMT_16_16_16_16_SNORM", 246 "BUF_FMT_16_16_16_16_USCALED", 247 "BUF_FMT_16_16_16_16_SSCALED", 248 "BUF_FMT_16_16_16_16_UINT", 249 "BUF_FMT_16_16_16_16_SINT", 250 "BUF_FMT_16_16_16_16_FLOAT", 251 252 "BUF_FMT_32_32_32_UINT", 253 "BUF_FMT_32_32_32_SINT", 254 "BUF_FMT_32_32_32_FLOAT", 255 "BUF_FMT_32_32_32_32_UINT", 256 "BUF_FMT_32_32_32_32_SINT", 257 "BUF_FMT_32_32_32_32_FLOAT" 258 }; 259 260 unsigned const DfmtNfmt2UFmt[] = { 261 DFMT_INVALID | (NFMT_UNORM << NFMT_SHIFT), 262 263 DFMT_8 | (NFMT_UNORM << NFMT_SHIFT), 264 DFMT_8 | (NFMT_SNORM << NFMT_SHIFT), 265 DFMT_8 | (NFMT_USCALED << NFMT_SHIFT), 266 DFMT_8 | (NFMT_SSCALED << NFMT_SHIFT), 267 DFMT_8 | (NFMT_UINT << NFMT_SHIFT), 268 DFMT_8 | (NFMT_SINT << NFMT_SHIFT), 269 270 DFMT_16 | (NFMT_UNORM << NFMT_SHIFT), 271 DFMT_16 | (NFMT_SNORM << NFMT_SHIFT), 272 DFMT_16 | (NFMT_USCALED << NFMT_SHIFT), 273 DFMT_16 | (NFMT_SSCALED << NFMT_SHIFT), 274 DFMT_16 | (NFMT_UINT << NFMT_SHIFT), 275 DFMT_16 | (NFMT_SINT << NFMT_SHIFT), 276 DFMT_16 | (NFMT_FLOAT << NFMT_SHIFT), 277 278 DFMT_8_8 | (NFMT_UNORM << NFMT_SHIFT), 279 DFMT_8_8 | (NFMT_SNORM << NFMT_SHIFT), 280 DFMT_8_8 | (NFMT_USCALED << NFMT_SHIFT), 281 DFMT_8_8 | (NFMT_SSCALED << NFMT_SHIFT), 282 DFMT_8_8 | (NFMT_UINT << NFMT_SHIFT), 283 DFMT_8_8 | (NFMT_SINT << NFMT_SHIFT), 284 285 DFMT_32 | (NFMT_UINT << NFMT_SHIFT), 286 DFMT_32 | (NFMT_SINT << NFMT_SHIFT), 287 DFMT_32 | (NFMT_FLOAT << NFMT_SHIFT), 288 289 DFMT_16_16 | (NFMT_UNORM << NFMT_SHIFT), 290 DFMT_16_16 | (NFMT_SNORM << NFMT_SHIFT), 291 DFMT_16_16 | (NFMT_USCALED << NFMT_SHIFT), 292 DFMT_16_16 | (NFMT_SSCALED << NFMT_SHIFT), 293 DFMT_16_16 | (NFMT_UINT << NFMT_SHIFT), 294 DFMT_16_16 | (NFMT_SINT << NFMT_SHIFT), 295 DFMT_16_16 | (NFMT_FLOAT << NFMT_SHIFT), 296 297 DFMT_10_11_11 | (NFMT_UNORM << NFMT_SHIFT), 298 DFMT_10_11_11 | (NFMT_SNORM << NFMT_SHIFT), 299 DFMT_10_11_11 | (NFMT_USCALED << NFMT_SHIFT), 300 DFMT_10_11_11 | (NFMT_SSCALED << NFMT_SHIFT), 301 DFMT_10_11_11 | (NFMT_UINT << NFMT_SHIFT), 302 DFMT_10_11_11 | (NFMT_SINT << NFMT_SHIFT), 303 DFMT_10_11_11 | (NFMT_FLOAT << NFMT_SHIFT), 304 305 DFMT_11_11_10 | (NFMT_UNORM << NFMT_SHIFT), 306 DFMT_11_11_10 | (NFMT_SNORM << NFMT_SHIFT), 307 DFMT_11_11_10 | (NFMT_USCALED << NFMT_SHIFT), 308 DFMT_11_11_10 | (NFMT_SSCALED << NFMT_SHIFT), 309 DFMT_11_11_10 | (NFMT_UINT << NFMT_SHIFT), 310 DFMT_11_11_10 | (NFMT_SINT << NFMT_SHIFT), 311 DFMT_11_11_10 | (NFMT_FLOAT << NFMT_SHIFT), 312 313 DFMT_10_10_10_2 | (NFMT_UNORM << NFMT_SHIFT), 314 DFMT_10_10_10_2 | (NFMT_SNORM << NFMT_SHIFT), 315 DFMT_10_10_10_2 | (NFMT_USCALED << NFMT_SHIFT), 316 DFMT_10_10_10_2 | (NFMT_SSCALED << NFMT_SHIFT), 317 DFMT_10_10_10_2 | (NFMT_UINT << NFMT_SHIFT), 318 DFMT_10_10_10_2 | (NFMT_SINT << NFMT_SHIFT), 319 320 DFMT_2_10_10_10 | (NFMT_UNORM << NFMT_SHIFT), 321 DFMT_2_10_10_10 | (NFMT_SNORM << NFMT_SHIFT), 322 DFMT_2_10_10_10 | (NFMT_USCALED << NFMT_SHIFT), 323 DFMT_2_10_10_10 | (NFMT_SSCALED << NFMT_SHIFT), 324 DFMT_2_10_10_10 | (NFMT_UINT << NFMT_SHIFT), 325 DFMT_2_10_10_10 | (NFMT_SINT << NFMT_SHIFT), 326 327 DFMT_8_8_8_8 | (NFMT_UNORM << NFMT_SHIFT), 328 DFMT_8_8_8_8 | (NFMT_SNORM << NFMT_SHIFT), 329 DFMT_8_8_8_8 | (NFMT_USCALED << NFMT_SHIFT), 330 DFMT_8_8_8_8 | (NFMT_SSCALED << NFMT_SHIFT), 331 DFMT_8_8_8_8 | (NFMT_UINT << NFMT_SHIFT), 332 DFMT_8_8_8_8 | (NFMT_SINT << NFMT_SHIFT), 333 334 DFMT_32_32 | (NFMT_UINT << NFMT_SHIFT), 335 DFMT_32_32 | (NFMT_SINT << NFMT_SHIFT), 336 DFMT_32_32 | (NFMT_FLOAT << NFMT_SHIFT), 337 338 DFMT_16_16_16_16 | (NFMT_UNORM << NFMT_SHIFT), 339 DFMT_16_16_16_16 | (NFMT_SNORM << NFMT_SHIFT), 340 DFMT_16_16_16_16 | (NFMT_USCALED << NFMT_SHIFT), 341 DFMT_16_16_16_16 | (NFMT_SSCALED << NFMT_SHIFT), 342 DFMT_16_16_16_16 | (NFMT_UINT << NFMT_SHIFT), 343 DFMT_16_16_16_16 | (NFMT_SINT << NFMT_SHIFT), 344 DFMT_16_16_16_16 | (NFMT_FLOAT << NFMT_SHIFT), 345 346 DFMT_32_32_32 | (NFMT_UINT << NFMT_SHIFT), 347 DFMT_32_32_32 | (NFMT_SINT << NFMT_SHIFT), 348 DFMT_32_32_32 | (NFMT_FLOAT << NFMT_SHIFT), 349 DFMT_32_32_32_32 | (NFMT_UINT << NFMT_SHIFT), 350 DFMT_32_32_32_32 | (NFMT_SINT << NFMT_SHIFT), 351 DFMT_32_32_32_32 | (NFMT_FLOAT << NFMT_SHIFT) 352 }; 353 354 } // namespace MTBUFFormat 355 356 namespace Swizzle { 357 358 // This must be in sync with llvm::AMDGPU::Swizzle::Id enum members, see SIDefines.h. 359 const char* const IdSymbolic[] = { 360 "QUAD_PERM", 361 "BITMASK_PERM", 362 "SWAP", 363 "REVERSE", 364 "BROADCAST", 365 }; 366 367 } // namespace Swizzle 368 369 namespace VGPRIndexMode { 370 371 // This must be in sync with llvm::AMDGPU::VGPRIndexMode::Id enum members, see SIDefines.h. 372 const char* const IdSymbolic[] = { 373 "SRC0", 374 "SRC1", 375 "SRC2", 376 "DST", 377 }; 378 379 } // namespace VGPRIndexMode 380 381 } // namespace AMDGPU 382 } // namespace llvm 383