1//===---- SMInstructions.td - Scalar Memory Instruction Defintions --------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10def smrd_offset_8 : NamedOperandU32<"SMRDOffset8", 11 NamedMatchClass<"SMRDOffset8">> { 12 let OperandType = "OPERAND_IMMEDIATE"; 13} 14 15def smrd_offset_20 : NamedOperandU32<"SMRDOffset20", 16 NamedMatchClass<"SMRDOffset20">> { 17 let OperandType = "OPERAND_IMMEDIATE"; 18} 19 20//===----------------------------------------------------------------------===// 21// Scalar Memory classes 22//===----------------------------------------------------------------------===// 23 24class SM_Pseudo <string opName, dag outs, dag ins, string asmOps, list<dag> pattern=[]> : 25 InstSI <outs, ins, "", pattern>, 26 SIMCInstr<opName, SIEncodingFamily.NONE> { 27 let isPseudo = 1; 28 let isCodeGenOnly = 1; 29 30 let LGKM_CNT = 1; 31 let SMRD = 1; 32 let mayStore = 0; 33 let mayLoad = 1; 34 let hasSideEffects = 0; 35 let UseNamedOperandTable = 1; 36 let SchedRW = [WriteSMEM]; 37 let SubtargetPredicate = isGCN; 38 39 string Mnemonic = opName; 40 string AsmOperands = asmOps; 41 42 bits<1> has_sbase = 1; 43 bits<1> has_sdst = 1; 44 bit has_glc = 0; 45 bits<1> has_offset = 1; 46 bits<1> offset_is_imm = 0; 47} 48 49class SM_Real <SM_Pseudo ps> 50 : InstSI<ps.OutOperandList, ps.InOperandList, ps.Mnemonic # ps.AsmOperands, []> { 51 52 let isPseudo = 0; 53 let isCodeGenOnly = 0; 54 55 // copy relevant pseudo op flags 56 let SubtargetPredicate = ps.SubtargetPredicate; 57 let AsmMatchConverter = ps.AsmMatchConverter; 58 59 // encoding 60 bits<7> sbase; 61 bits<7> sdst; 62 bits<32> offset; 63 bits<1> imm = !if(ps.has_offset, ps.offset_is_imm, 0); 64} 65 66class SM_Load_Pseudo <string opName, dag outs, dag ins, string asmOps, list<dag> pattern=[]> 67 : SM_Pseudo<opName, outs, ins, asmOps, pattern> { 68 RegisterClass BaseClass; 69 let mayLoad = 1; 70 let mayStore = 0; 71 let has_glc = 1; 72} 73 74class SM_Store_Pseudo <string opName, dag ins, string asmOps, list<dag> pattern = []> 75 : SM_Pseudo<opName, (outs), ins, asmOps, pattern> { 76 RegisterClass BaseClass; 77 RegisterClass SrcClass; 78 let mayLoad = 0; 79 let mayStore = 1; 80 let has_glc = 1; 81 let ScalarStore = 1; 82} 83 84multiclass SM_Pseudo_Loads<string opName, 85 RegisterClass baseClass, 86 RegisterClass dstClass> { 87 def _IMM : SM_Load_Pseudo <opName, 88 (outs dstClass:$sdst), 89 (ins baseClass:$sbase, i32imm:$offset, i1imm:$glc), 90 " $sdst, $sbase, $offset$glc", []> { 91 let offset_is_imm = 1; 92 let BaseClass = baseClass; 93 let PseudoInstr = opName # "_IMM"; 94 let has_glc = 1; 95 } 96 97 def _SGPR : SM_Load_Pseudo <opName, 98 (outs dstClass:$sdst), 99 (ins baseClass:$sbase, SReg_32:$soff, i1imm:$glc), 100 " $sdst, $sbase, $offset$glc", []> { 101 let BaseClass = baseClass; 102 let PseudoInstr = opName # "_SGPR"; 103 let has_glc = 1; 104 } 105} 106 107multiclass SM_Pseudo_Stores<string opName, 108 RegisterClass baseClass, 109 RegisterClass srcClass> { 110 def _IMM : SM_Store_Pseudo <opName, 111 (ins srcClass:$sdata, baseClass:$sbase, i32imm:$offset, i1imm:$glc), 112 " $sdata, $sbase, $offset$glc", []> { 113 let offset_is_imm = 1; 114 let BaseClass = baseClass; 115 let SrcClass = srcClass; 116 let PseudoInstr = opName # "_IMM"; 117 } 118 119 def _SGPR : SM_Store_Pseudo <opName, 120 (ins srcClass:$sdata, baseClass:$sbase, SReg_32:$soff, i1imm:$glc), 121 " $sdata, $sbase, $offset$glc", []> { 122 let BaseClass = baseClass; 123 let SrcClass = srcClass; 124 let PseudoInstr = opName # "_SGPR"; 125 } 126} 127 128class SM_Time_Pseudo<string opName, SDPatternOperator node> : SM_Pseudo< 129 opName, (outs SReg_64_XEXEC:$sdst), (ins), 130 " $sdst", [(set i64:$sdst, (node))]> { 131 let hasSideEffects = 1; 132 // FIXME: mayStore = ? is a workaround for tablegen bug for different 133 // inferred mayStore flags for the instruction pattern vs. standalone 134 // Pat. Each considers the other contradictory. 135 let mayStore = ?; 136 let mayLoad = ?; 137 let has_sbase = 0; 138 let has_offset = 0; 139} 140 141class SM_Inval_Pseudo <string opName, SDPatternOperator node> : SM_Pseudo< 142 opName, (outs), (ins), "", [(node)]> { 143 let hasSideEffects = 1; 144 let mayStore = 1; 145 let has_sdst = 0; 146 let has_sbase = 0; 147 let has_offset = 0; 148} 149 150 151//===----------------------------------------------------------------------===// 152// Scalar Memory Instructions 153//===----------------------------------------------------------------------===// 154 155// We are using the SReg_32_XM0 and not the SReg_32 register class for 32-bit 156// SMRD instructions, because the SReg_32_XM0 register class does not include M0 157// and writing to M0 from an SMRD instruction will hang the GPU. 158 159// XXX - SMEM instructions do not allow exec for data operand, but 160// does sdst for SMRD on SI/CI? 161defm S_LOAD_DWORD : SM_Pseudo_Loads <"s_load_dword", SReg_64, SReg_32_XM0_XEXEC>; 162defm S_LOAD_DWORDX2 : SM_Pseudo_Loads <"s_load_dwordx2", SReg_64, SReg_64_XEXEC>; 163defm S_LOAD_DWORDX4 : SM_Pseudo_Loads <"s_load_dwordx4", SReg_64, SReg_128>; 164defm S_LOAD_DWORDX8 : SM_Pseudo_Loads <"s_load_dwordx8", SReg_64, SReg_256>; 165defm S_LOAD_DWORDX16 : SM_Pseudo_Loads <"s_load_dwordx16", SReg_64, SReg_512>; 166 167defm S_BUFFER_LOAD_DWORD : SM_Pseudo_Loads < 168 "s_buffer_load_dword", SReg_128, SReg_32_XM0_XEXEC 169>; 170 171// FIXME: exec_lo/exec_hi appear to be allowed for SMRD loads on 172// SI/CI, bit disallowed for SMEM on VI. 173defm S_BUFFER_LOAD_DWORDX2 : SM_Pseudo_Loads < 174 "s_buffer_load_dwordx2", SReg_128, SReg_64_XEXEC 175>; 176 177defm S_BUFFER_LOAD_DWORDX4 : SM_Pseudo_Loads < 178 "s_buffer_load_dwordx4", SReg_128, SReg_128 179>; 180 181defm S_BUFFER_LOAD_DWORDX8 : SM_Pseudo_Loads < 182 "s_buffer_load_dwordx8", SReg_128, SReg_256 183>; 184 185defm S_BUFFER_LOAD_DWORDX16 : SM_Pseudo_Loads < 186 "s_buffer_load_dwordx16", SReg_128, SReg_512 187>; 188 189defm S_STORE_DWORD : SM_Pseudo_Stores <"s_store_dword", SReg_64, SReg_32_XM0_XEXEC>; 190defm S_STORE_DWORDX2 : SM_Pseudo_Stores <"s_store_dwordx2", SReg_64, SReg_64_XEXEC>; 191defm S_STORE_DWORDX4 : SM_Pseudo_Stores <"s_store_dwordx4", SReg_64, SReg_128>; 192 193defm S_BUFFER_STORE_DWORD : SM_Pseudo_Stores < 194 "s_buffer_store_dword", SReg_128, SReg_32_XM0_XEXEC 195>; 196 197defm S_BUFFER_STORE_DWORDX2 : SM_Pseudo_Stores < 198 "s_buffer_store_dwordx2", SReg_128, SReg_64_XEXEC 199>; 200 201defm S_BUFFER_STORE_DWORDX4 : SM_Pseudo_Stores < 202 "s_buffer_store_dwordx4", SReg_128, SReg_128 203>; 204 205 206def S_MEMTIME : SM_Time_Pseudo <"s_memtime", int_amdgcn_s_memtime>; 207def S_DCACHE_INV : SM_Inval_Pseudo <"s_dcache_inv", int_amdgcn_s_dcache_inv>; 208 209let SubtargetPredicate = isCIVI in { 210def S_DCACHE_INV_VOL : SM_Inval_Pseudo <"s_dcache_inv_vol", int_amdgcn_s_dcache_inv_vol>; 211} // let SubtargetPredicate = isCIVI 212 213let SubtargetPredicate = isVI in { 214def S_DCACHE_WB : SM_Inval_Pseudo <"s_dcache_wb", int_amdgcn_s_dcache_wb>; 215def S_DCACHE_WB_VOL : SM_Inval_Pseudo <"s_dcache_wb_vol", int_amdgcn_s_dcache_wb_vol>; 216def S_MEMREALTIME : SM_Time_Pseudo <"s_memrealtime", int_amdgcn_s_memrealtime>; 217} // SubtargetPredicate = isVI 218 219 220 221//===----------------------------------------------------------------------===// 222// Scalar Memory Patterns 223//===----------------------------------------------------------------------===// 224 225 226def smrd_load : PatFrag <(ops node:$ptr), (load node:$ptr), [{ 227 auto Ld = cast<LoadSDNode>(N); 228 return Ld->getAlignment() >= 4 && 229 ((Ld->getAddressSpace() == AMDGPUASI.CONSTANT_ADDRESS && 230 static_cast<const SITargetLowering *>(getTargetLowering())->isMemOpUniform(N)) || 231 (Subtarget->getScalarizeGlobalBehavior() && Ld->getAddressSpace() == AMDGPUASI.GLOBAL_ADDRESS && 232 !Ld->isVolatile() && 233 static_cast<const SITargetLowering *>(getTargetLowering())->isMemOpUniform(N) && 234 static_cast<const SITargetLowering *>(getTargetLowering())->isMemOpHasNoClobberedMemOperand(N))); 235}]>; 236 237def SMRDImm : ComplexPattern<i64, 2, "SelectSMRDImm">; 238def SMRDImm32 : ComplexPattern<i64, 2, "SelectSMRDImm32">; 239def SMRDSgpr : ComplexPattern<i64, 2, "SelectSMRDSgpr">; 240def SMRDBufferImm : ComplexPattern<i32, 1, "SelectSMRDBufferImm">; 241def SMRDBufferImm32 : ComplexPattern<i32, 1, "SelectSMRDBufferImm32">; 242 243multiclass SMRD_Pattern <string Instr, ValueType vt> { 244 245 // 1. IMM offset 246 def : GCNPat < 247 (smrd_load (SMRDImm i64:$sbase, i32:$offset)), 248 (vt (!cast<SM_Pseudo>(Instr#"_IMM") $sbase, $offset, 0)) 249 >; 250 251 // 2. SGPR offset 252 def : GCNPat < 253 (smrd_load (SMRDSgpr i64:$sbase, i32:$offset)), 254 (vt (!cast<SM_Pseudo>(Instr#"_SGPR") $sbase, $offset, 0)) 255 >; 256} 257 258let OtherPredicates = [isSICI] in { 259def : GCNPat < 260 (i64 (readcyclecounter)), 261 (S_MEMTIME) 262>; 263} 264 265// Global and constant loads can be selected to either MUBUF or SMRD 266// instructions, but SMRD instructions are faster so we want the instruction 267// selector to prefer those. 268let AddedComplexity = 100 in { 269 270defm : SMRD_Pattern <"S_LOAD_DWORD", i32>; 271defm : SMRD_Pattern <"S_LOAD_DWORDX2", v2i32>; 272defm : SMRD_Pattern <"S_LOAD_DWORDX4", v4i32>; 273defm : SMRD_Pattern <"S_LOAD_DWORDX8", v8i32>; 274defm : SMRD_Pattern <"S_LOAD_DWORDX16", v16i32>; 275 276// 1. Offset as an immediate 277def SM_LOAD_PATTERN : GCNPat < // name this pattern to reuse AddedComplexity on CI 278 (SIload_constant v4i32:$sbase, (SMRDBufferImm i32:$offset)), 279 (S_BUFFER_LOAD_DWORD_IMM $sbase, $offset, 0) 280>; 281 282// 2. Offset loaded in an 32bit SGPR 283def : GCNPat < 284 (SIload_constant v4i32:$sbase, i32:$offset), 285 (S_BUFFER_LOAD_DWORD_SGPR $sbase, $offset, 0) 286>; 287 288} // End let AddedComplexity = 100 289 290let OtherPredicates = [isVI] in { 291 292def : GCNPat < 293 (i64 (readcyclecounter)), 294 (S_MEMREALTIME) 295>; 296 297} // let OtherPredicates = [isVI] 298 299 300//===----------------------------------------------------------------------===// 301// Targets 302//===----------------------------------------------------------------------===// 303 304//===----------------------------------------------------------------------===// 305// SI 306//===----------------------------------------------------------------------===// 307 308class SMRD_Real_si <bits<5> op, SM_Pseudo ps> 309 : SM_Real<ps> 310 , SIMCInstr<ps.PseudoInstr, SIEncodingFamily.SI> 311 , Enc32 { 312 313 let AssemblerPredicates = [isSICI]; 314 let DecoderNamespace = "SICI"; 315 316 let Inst{7-0} = !if(ps.has_offset, offset{7-0}, ?); 317 let Inst{8} = imm; 318 let Inst{14-9} = !if(ps.has_sbase, sbase{6-1}, ?); 319 let Inst{21-15} = !if(ps.has_sdst, sdst{6-0}, ?); 320 let Inst{26-22} = op; 321 let Inst{31-27} = 0x18; //encoding 322} 323 324// FIXME: Assembler should reject trying to use glc on SMRD 325// instructions on SI. 326multiclass SM_Real_Loads_si<bits<5> op, string ps, 327 SM_Load_Pseudo immPs = !cast<SM_Load_Pseudo>(ps#_IMM), 328 SM_Load_Pseudo sgprPs = !cast<SM_Load_Pseudo>(ps#_SGPR)> { 329 330 def _IMM_si : SMRD_Real_si <op, immPs> { 331 let InOperandList = (ins immPs.BaseClass:$sbase, smrd_offset_8:$offset, GLC:$glc); 332 } 333 334 // FIXME: The operand name $offset is inconsistent with $soff used 335 // in the pseudo 336 def _SGPR_si : SMRD_Real_si <op, sgprPs> { 337 let InOperandList = (ins sgprPs.BaseClass:$sbase, SReg_32:$offset, GLC:$glc); 338 } 339 340} 341 342defm S_LOAD_DWORD : SM_Real_Loads_si <0x00, "S_LOAD_DWORD">; 343defm S_LOAD_DWORDX2 : SM_Real_Loads_si <0x01, "S_LOAD_DWORDX2">; 344defm S_LOAD_DWORDX4 : SM_Real_Loads_si <0x02, "S_LOAD_DWORDX4">; 345defm S_LOAD_DWORDX8 : SM_Real_Loads_si <0x03, "S_LOAD_DWORDX8">; 346defm S_LOAD_DWORDX16 : SM_Real_Loads_si <0x04, "S_LOAD_DWORDX16">; 347defm S_BUFFER_LOAD_DWORD : SM_Real_Loads_si <0x08, "S_BUFFER_LOAD_DWORD">; 348defm S_BUFFER_LOAD_DWORDX2 : SM_Real_Loads_si <0x09, "S_BUFFER_LOAD_DWORDX2">; 349defm S_BUFFER_LOAD_DWORDX4 : SM_Real_Loads_si <0x0a, "S_BUFFER_LOAD_DWORDX4">; 350defm S_BUFFER_LOAD_DWORDX8 : SM_Real_Loads_si <0x0b, "S_BUFFER_LOAD_DWORDX8">; 351defm S_BUFFER_LOAD_DWORDX16 : SM_Real_Loads_si <0x0c, "S_BUFFER_LOAD_DWORDX16">; 352 353def S_MEMTIME_si : SMRD_Real_si <0x1e, S_MEMTIME>; 354def S_DCACHE_INV_si : SMRD_Real_si <0x1f, S_DCACHE_INV>; 355 356 357//===----------------------------------------------------------------------===// 358// VI 359//===----------------------------------------------------------------------===// 360 361class SMEM_Real_vi <bits<8> op, SM_Pseudo ps> 362 : SM_Real<ps> 363 , SIMCInstr<ps.PseudoInstr, SIEncodingFamily.VI> 364 , Enc64 { 365 bit glc; 366 367 let AssemblerPredicates = [isVI]; 368 let DecoderNamespace = "VI"; 369 370 let Inst{5-0} = !if(ps.has_sbase, sbase{6-1}, ?); 371 let Inst{12-6} = !if(ps.has_sdst, sdst{6-0}, ?); 372 373 let Inst{16} = !if(ps.has_glc, glc, ?); 374 let Inst{17} = imm; 375 let Inst{25-18} = op; 376 let Inst{31-26} = 0x30; //encoding 377 let Inst{51-32} = !if(ps.has_offset, offset{19-0}, ?); 378} 379 380multiclass SM_Real_Loads_vi<bits<8> op, string ps, 381 SM_Load_Pseudo immPs = !cast<SM_Load_Pseudo>(ps#_IMM), 382 SM_Load_Pseudo sgprPs = !cast<SM_Load_Pseudo>(ps#_SGPR)> { 383 def _IMM_vi : SMEM_Real_vi <op, immPs> { 384 let InOperandList = (ins immPs.BaseClass:$sbase, smrd_offset_20:$offset, GLC:$glc); 385 } 386 def _SGPR_vi : SMEM_Real_vi <op, sgprPs> { 387 let InOperandList = (ins sgprPs.BaseClass:$sbase, SReg_32:$offset, GLC:$glc); 388 } 389} 390 391class SMEM_Real_Store_vi <bits<8> op, SM_Pseudo ps> : SMEM_Real_vi <op, ps> { 392 // encoding 393 bits<7> sdata; 394 395 let sdst = ?; 396 let Inst{12-6} = !if(ps.has_sdst, sdata{6-0}, ?); 397} 398 399multiclass SM_Real_Stores_vi<bits<8> op, string ps, 400 SM_Store_Pseudo immPs = !cast<SM_Store_Pseudo>(ps#_IMM), 401 SM_Store_Pseudo sgprPs = !cast<SM_Store_Pseudo>(ps#_SGPR)> { 402 // FIXME: The operand name $offset is inconsistent with $soff used 403 // in the pseudo 404 def _IMM_vi : SMEM_Real_Store_vi <op, immPs> { 405 let InOperandList = (ins immPs.SrcClass:$sdata, immPs.BaseClass:$sbase, smrd_offset_20:$offset, GLC:$glc); 406 } 407 408 def _SGPR_vi : SMEM_Real_Store_vi <op, sgprPs> { 409 let InOperandList = (ins sgprPs.SrcClass:$sdata, sgprPs.BaseClass:$sbase, SReg_32:$offset, GLC:$glc); 410 } 411} 412 413defm S_LOAD_DWORD : SM_Real_Loads_vi <0x00, "S_LOAD_DWORD">; 414defm S_LOAD_DWORDX2 : SM_Real_Loads_vi <0x01, "S_LOAD_DWORDX2">; 415defm S_LOAD_DWORDX4 : SM_Real_Loads_vi <0x02, "S_LOAD_DWORDX4">; 416defm S_LOAD_DWORDX8 : SM_Real_Loads_vi <0x03, "S_LOAD_DWORDX8">; 417defm S_LOAD_DWORDX16 : SM_Real_Loads_vi <0x04, "S_LOAD_DWORDX16">; 418defm S_BUFFER_LOAD_DWORD : SM_Real_Loads_vi <0x08, "S_BUFFER_LOAD_DWORD">; 419defm S_BUFFER_LOAD_DWORDX2 : SM_Real_Loads_vi <0x09, "S_BUFFER_LOAD_DWORDX2">; 420defm S_BUFFER_LOAD_DWORDX4 : SM_Real_Loads_vi <0x0a, "S_BUFFER_LOAD_DWORDX4">; 421defm S_BUFFER_LOAD_DWORDX8 : SM_Real_Loads_vi <0x0b, "S_BUFFER_LOAD_DWORDX8">; 422defm S_BUFFER_LOAD_DWORDX16 : SM_Real_Loads_vi <0x0c, "S_BUFFER_LOAD_DWORDX16">; 423 424defm S_STORE_DWORD : SM_Real_Stores_vi <0x10, "S_STORE_DWORD">; 425defm S_STORE_DWORDX2 : SM_Real_Stores_vi <0x11, "S_STORE_DWORDX2">; 426defm S_STORE_DWORDX4 : SM_Real_Stores_vi <0x12, "S_STORE_DWORDX4">; 427 428defm S_BUFFER_STORE_DWORD : SM_Real_Stores_vi <0x18, "S_BUFFER_STORE_DWORD">; 429defm S_BUFFER_STORE_DWORDX2 : SM_Real_Stores_vi <0x19, "S_BUFFER_STORE_DWORDX2">; 430defm S_BUFFER_STORE_DWORDX4 : SM_Real_Stores_vi <0x1a, "S_BUFFER_STORE_DWORDX4">; 431 432// These instructions use same encoding 433def S_DCACHE_INV_vi : SMEM_Real_vi <0x20, S_DCACHE_INV>; 434def S_DCACHE_WB_vi : SMEM_Real_vi <0x21, S_DCACHE_WB>; 435def S_DCACHE_INV_VOL_vi : SMEM_Real_vi <0x22, S_DCACHE_INV_VOL>; 436def S_DCACHE_WB_VOL_vi : SMEM_Real_vi <0x23, S_DCACHE_WB_VOL>; 437def S_MEMTIME_vi : SMEM_Real_vi <0x24, S_MEMTIME>; 438def S_MEMREALTIME_vi : SMEM_Real_vi <0x25, S_MEMREALTIME>; 439 440 441//===----------------------------------------------------------------------===// 442// CI 443//===----------------------------------------------------------------------===// 444 445def smrd_literal_offset : NamedOperandU32<"SMRDLiteralOffset", 446 NamedMatchClass<"SMRDLiteralOffset">> { 447 let OperandType = "OPERAND_IMMEDIATE"; 448} 449 450class SMRD_Real_Load_IMM_ci <bits<5> op, SM_Load_Pseudo ps> : 451 SM_Real<ps>, 452 Enc64 { 453 454 let AssemblerPredicates = [isCIOnly]; 455 let DecoderNamespace = "CI"; 456 let InOperandList = (ins ps.BaseClass:$sbase, smrd_literal_offset:$offset, GLC:$glc); 457 458 let LGKM_CNT = ps.LGKM_CNT; 459 let SMRD = ps.SMRD; 460 let mayLoad = ps.mayLoad; 461 let mayStore = ps.mayStore; 462 let hasSideEffects = ps.hasSideEffects; 463 let SchedRW = ps.SchedRW; 464 let UseNamedOperandTable = ps.UseNamedOperandTable; 465 466 let Inst{7-0} = 0xff; 467 let Inst{8} = 0; 468 let Inst{14-9} = sbase{6-1}; 469 let Inst{21-15} = sdst{6-0}; 470 let Inst{26-22} = op; 471 let Inst{31-27} = 0x18; //encoding 472 let Inst{63-32} = offset{31-0}; 473} 474 475def S_LOAD_DWORD_IMM_ci : SMRD_Real_Load_IMM_ci <0x00, S_LOAD_DWORD_IMM>; 476def S_LOAD_DWORDX2_IMM_ci : SMRD_Real_Load_IMM_ci <0x01, S_LOAD_DWORDX2_IMM>; 477def S_LOAD_DWORDX4_IMM_ci : SMRD_Real_Load_IMM_ci <0x02, S_LOAD_DWORDX4_IMM>; 478def S_LOAD_DWORDX8_IMM_ci : SMRD_Real_Load_IMM_ci <0x03, S_LOAD_DWORDX8_IMM>; 479def S_LOAD_DWORDX16_IMM_ci : SMRD_Real_Load_IMM_ci <0x04, S_LOAD_DWORDX16_IMM>; 480def S_BUFFER_LOAD_DWORD_IMM_ci : SMRD_Real_Load_IMM_ci <0x08, S_BUFFER_LOAD_DWORD_IMM>; 481def S_BUFFER_LOAD_DWORDX2_IMM_ci : SMRD_Real_Load_IMM_ci <0x09, S_BUFFER_LOAD_DWORDX2_IMM>; 482def S_BUFFER_LOAD_DWORDX4_IMM_ci : SMRD_Real_Load_IMM_ci <0x0a, S_BUFFER_LOAD_DWORDX4_IMM>; 483def S_BUFFER_LOAD_DWORDX8_IMM_ci : SMRD_Real_Load_IMM_ci <0x0b, S_BUFFER_LOAD_DWORDX8_IMM>; 484def S_BUFFER_LOAD_DWORDX16_IMM_ci : SMRD_Real_Load_IMM_ci <0x0c, S_BUFFER_LOAD_DWORDX16_IMM>; 485 486class SMRD_Real_ci <bits<5> op, SM_Pseudo ps> 487 : SM_Real<ps> 488 , SIMCInstr<ps.PseudoInstr, SIEncodingFamily.SI> 489 , Enc32 { 490 491 let AssemblerPredicates = [isCIOnly]; 492 let DecoderNamespace = "CI"; 493 494 let Inst{7-0} = !if(ps.has_offset, offset{7-0}, ?); 495 let Inst{8} = imm; 496 let Inst{14-9} = !if(ps.has_sbase, sbase{6-1}, ?); 497 let Inst{21-15} = !if(ps.has_sdst, sdst{6-0}, ?); 498 let Inst{26-22} = op; 499 let Inst{31-27} = 0x18; //encoding 500} 501 502def S_DCACHE_INV_VOL_ci : SMRD_Real_ci <0x1d, S_DCACHE_INV_VOL>; 503 504let AddedComplexity = SM_LOAD_PATTERN.AddedComplexity in { 505 506class SMRD_Pattern_ci <string Instr, ValueType vt> : GCNPat < 507 (smrd_load (SMRDImm32 i64:$sbase, i32:$offset)), 508 (vt (!cast<SM_Pseudo>(Instr#"_IMM_ci") $sbase, $offset, 0))> { 509 let OtherPredicates = [isCIOnly]; 510} 511 512def : SMRD_Pattern_ci <"S_LOAD_DWORD", i32>; 513def : SMRD_Pattern_ci <"S_LOAD_DWORDX2", v2i32>; 514def : SMRD_Pattern_ci <"S_LOAD_DWORDX4", v4i32>; 515def : SMRD_Pattern_ci <"S_LOAD_DWORDX8", v8i32>; 516def : SMRD_Pattern_ci <"S_LOAD_DWORDX16", v16i32>; 517 518def : GCNPat < 519 (SIload_constant v4i32:$sbase, (SMRDBufferImm32 i32:$offset)), 520 (S_BUFFER_LOAD_DWORD_IMM_ci $sbase, $offset, 0)> { 521 let OtherPredicates = [isCI]; // should this be isCIOnly? 522} 523 524} // End let AddedComplexity = SM_LOAD_PATTERN.AddedComplexity 525 526