1 //===-- SIShrinkInstructions.cpp - Shrink Instructions --------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 /// The pass tries to use the 32-bit encoding for instructions when possible.
9 //===----------------------------------------------------------------------===//
10 //
11 
12 #include "AMDGPU.h"
13 #include "AMDGPUMCInstLower.h"
14 #include "AMDGPUSubtarget.h"
15 #include "SIInstrInfo.h"
16 #include "llvm/ADT/Statistic.h"
17 #include "llvm/CodeGen/MachineFunctionPass.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/MachineRegisterInfo.h"
20 #include "llvm/IR/Constants.h"
21 #include "llvm/IR/Function.h"
22 #include "llvm/IR/LLVMContext.h"
23 #include "llvm/Support/Debug.h"
24 #include "llvm/Support/raw_ostream.h"
25 #include "llvm/Target/TargetMachine.h"
26 
27 #define DEBUG_TYPE "si-shrink-instructions"
28 
29 STATISTIC(NumInstructionsShrunk,
30           "Number of 64-bit instruction reduced to 32-bit.");
31 STATISTIC(NumLiteralConstantsFolded,
32           "Number of literal constants folded into 32-bit instructions.");
33 
34 namespace llvm {
35   void initializeSIShrinkInstructionsPass(PassRegistry&);
36 }
37 
38 using namespace llvm;
39 
40 namespace {
41 
42 class SIShrinkInstructions : public MachineFunctionPass {
43 public:
44   static char ID;
45 
46 public:
47   SIShrinkInstructions() : MachineFunctionPass(ID) {
48   }
49 
50   bool runOnMachineFunction(MachineFunction &MF) override;
51 
52   const char *getPassName() const override {
53     return "SI Shrink Instructions";
54   }
55 
56   void getAnalysisUsage(AnalysisUsage &AU) const override {
57     AU.setPreservesCFG();
58     MachineFunctionPass::getAnalysisUsage(AU);
59   }
60 };
61 
62 } // End anonymous namespace.
63 
64 INITIALIZE_PASS_BEGIN(SIShrinkInstructions, DEBUG_TYPE,
65                       "SI Lower il Copies", false, false)
66 INITIALIZE_PASS_END(SIShrinkInstructions, DEBUG_TYPE,
67                     "SI Lower il Copies", false, false)
68 
69 char SIShrinkInstructions::ID = 0;
70 
71 FunctionPass *llvm::createSIShrinkInstructionsPass() {
72   return new SIShrinkInstructions();
73 }
74 
75 static bool isVGPR(const MachineOperand *MO, const SIRegisterInfo &TRI,
76                    const MachineRegisterInfo &MRI) {
77   if (!MO->isReg())
78     return false;
79 
80   if (TargetRegisterInfo::isVirtualRegister(MO->getReg()))
81     return TRI.hasVGPRs(MRI.getRegClass(MO->getReg()));
82 
83   return TRI.hasVGPRs(TRI.getPhysRegClass(MO->getReg()));
84 }
85 
86 static bool canShrink(MachineInstr &MI, const SIInstrInfo *TII,
87                       const SIRegisterInfo &TRI,
88                       const MachineRegisterInfo &MRI) {
89 
90   const MachineOperand *Src2 = TII->getNamedOperand(MI, AMDGPU::OpName::src2);
91   // Can't shrink instruction with three operands.
92   // FIXME: v_cndmask_b32 has 3 operands and is shrinkable, but we need to add
93   // a special case for it.  It can only be shrunk if the third operand
94   // is vcc.  We should handle this the same way we handle vopc, by addding
95   // a register allocation hint pre-regalloc and then do the shrining
96   // post-regalloc.
97   if (Src2) {
98     switch (MI.getOpcode()) {
99       default: return false;
100 
101       case AMDGPU::V_MAC_F32_e64:
102         if (!isVGPR(Src2, TRI, MRI) ||
103             TII->hasModifiersSet(MI, AMDGPU::OpName::src2_modifiers))
104           return false;
105         break;
106 
107       case AMDGPU::V_CNDMASK_B32_e64:
108         break;
109     }
110   }
111 
112   const MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1);
113   const MachineOperand *Src1Mod =
114       TII->getNamedOperand(MI, AMDGPU::OpName::src1_modifiers);
115 
116   if (Src1 && (!isVGPR(Src1, TRI, MRI) || (Src1Mod && Src1Mod->getImm() != 0)))
117     return false;
118 
119   // We don't need to check src0, all input types are legal, so just make sure
120   // src0 isn't using any modifiers.
121   if (TII->hasModifiersSet(MI, AMDGPU::OpName::src0_modifiers))
122     return false;
123 
124   // Check output modifiers
125   if (TII->hasModifiersSet(MI, AMDGPU::OpName::omod))
126     return false;
127 
128   return !TII->hasModifiersSet(MI, AMDGPU::OpName::clamp);
129 }
130 
131 /// \brief This function checks \p MI for operands defined by a move immediate
132 /// instruction and then folds the literal constant into the instruction if it
133 /// can.  This function assumes that \p MI is a VOP1, VOP2, or VOPC instruction
134 /// and will only fold literal constants if we are still in SSA.
135 static void foldImmediates(MachineInstr &MI, const SIInstrInfo *TII,
136                            MachineRegisterInfo &MRI, bool TryToCommute = true) {
137 
138   if (!MRI.isSSA())
139     return;
140 
141   assert(TII->isVOP1(MI) || TII->isVOP2(MI) || TII->isVOPC(MI));
142 
143   const SIRegisterInfo &TRI = TII->getRegisterInfo();
144   int Src0Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::src0);
145   MachineOperand &Src0 = MI.getOperand(Src0Idx);
146 
147   // Only one literal constant is allowed per instruction, so if src0 is a
148   // literal constant then we can't do any folding.
149   if (Src0.isImm() &&
150       TII->isLiteralConstant(Src0, TII->getOpSize(MI, Src0Idx)))
151     return;
152 
153   // Literal constants and SGPRs can only be used in Src0, so if Src0 is an
154   // SGPR, we cannot commute the instruction, so we can't fold any literal
155   // constants.
156   if (Src0.isReg() && !isVGPR(&Src0, TRI, MRI))
157     return;
158 
159   // Try to fold Src0
160   if (Src0.isReg() && MRI.hasOneUse(Src0.getReg())) {
161     unsigned Reg = Src0.getReg();
162     MachineInstr *Def = MRI.getUniqueVRegDef(Reg);
163     if (Def && Def->isMoveImmediate()) {
164       MachineOperand &MovSrc = Def->getOperand(1);
165       bool ConstantFolded = false;
166 
167       if (MovSrc.isImm() && isUInt<32>(MovSrc.getImm())) {
168         Src0.ChangeToImmediate(MovSrc.getImm());
169         ConstantFolded = true;
170       }
171       if (ConstantFolded) {
172         if (MRI.use_empty(Reg))
173           Def->eraseFromParent();
174         ++NumLiteralConstantsFolded;
175         return;
176       }
177     }
178   }
179 
180   // We have failed to fold src0, so commute the instruction and try again.
181   if (TryToCommute && MI.isCommutable() && TII->commuteInstruction(&MI))
182     foldImmediates(MI, TII, MRI, false);
183 
184 }
185 
186 // Copy MachineOperand with all flags except setting it as implicit.
187 static MachineOperand copyRegOperandAsImplicit(const MachineOperand &Orig) {
188   assert(!Orig.isImplicit());
189   return MachineOperand::CreateReg(Orig.getReg(),
190                                    Orig.isDef(),
191                                    true,
192                                    Orig.isKill(),
193                                    Orig.isDead(),
194                                    Orig.isUndef(),
195                                    Orig.isEarlyClobber(),
196                                    Orig.getSubReg(),
197                                    Orig.isDebug(),
198                                    Orig.isInternalRead());
199 }
200 
201 bool SIShrinkInstructions::runOnMachineFunction(MachineFunction &MF) {
202   MachineRegisterInfo &MRI = MF.getRegInfo();
203   const SIInstrInfo *TII =
204       static_cast<const SIInstrInfo *>(MF.getSubtarget().getInstrInfo());
205   const SIRegisterInfo &TRI = TII->getRegisterInfo();
206   std::vector<unsigned> I1Defs;
207 
208   for (MachineFunction::iterator BI = MF.begin(), BE = MF.end();
209                                                   BI != BE; ++BI) {
210 
211     MachineBasicBlock &MBB = *BI;
212     MachineBasicBlock::iterator I, Next;
213     for (I = MBB.begin(); I != MBB.end(); I = Next) {
214       Next = std::next(I);
215       MachineInstr &MI = *I;
216 
217       // Try to use S_MOVK_I32, which will save 4 bytes for small immediates.
218       if (MI.getOpcode() == AMDGPU::S_MOV_B32) {
219         const MachineOperand &Src = MI.getOperand(1);
220 
221         if (Src.isImm()) {
222           if (isInt<16>(Src.getImm()) && !TII->isInlineConstant(Src, 4))
223             MI.setDesc(TII->get(AMDGPU::S_MOVK_I32));
224         }
225 
226         continue;
227       }
228 
229       if (MI.getOpcode() == AMDGPU::V_MOV_B32_e32) {
230         // If this has a literal constant source that is the same as the
231         // reversed bits of an inline immediate, replace with a bitreverse of
232         // that constant. This saves 4 bytes in the common case of materializing
233         // sign bits.
234 
235         // Test if we are after regalloc. We only want to do this after any
236         // optimizations happen because this will confuse them.
237         // XXX - not exactly a check for post-regalloc run.
238         MachineOperand &Src = MI.getOperand(1);
239         if (Src.isImm() &&
240             TargetRegisterInfo::isPhysicalRegister(MI.getOperand(0).getReg())) {
241           int64_t Imm = Src.getImm();
242           if (isInt<32>(Imm) && !TII->isInlineConstant(Src, 4)) {
243             int32_t ReverseImm = reverseBits<int32_t>(static_cast<int32_t>(Imm));
244             if (ReverseImm >= -16 && ReverseImm <= 64) {
245               MI.setDesc(TII->get(AMDGPU::V_BFREV_B32_e32));
246               Src.setImm(ReverseImm);
247               continue;
248             }
249           }
250         }
251       }
252 
253       if (!TII->hasVALU32BitEncoding(MI.getOpcode()))
254         continue;
255 
256       if (!canShrink(MI, TII, TRI, MRI)) {
257         // Try commuting the instruction and see if that enables us to shrink
258         // it.
259         if (!MI.isCommutable() || !TII->commuteInstruction(&MI) ||
260             !canShrink(MI, TII, TRI, MRI))
261           continue;
262       }
263 
264       // getVOPe32 could be -1 here if we started with an instruction that had
265       // a 32-bit encoding and then commuted it to an instruction that did not.
266       if (!TII->hasVALU32BitEncoding(MI.getOpcode()))
267         continue;
268 
269       int Op32 = AMDGPU::getVOPe32(MI.getOpcode());
270 
271       if (TII->isVOPC(Op32)) {
272         unsigned DstReg = MI.getOperand(0).getReg();
273         if (TargetRegisterInfo::isVirtualRegister(DstReg)) {
274           // VOPC instructions can only write to the VCC register. We can't
275           // force them to use VCC here, because this is only one register and
276           // cannot deal with sequences which would require multiple copies of
277           // VCC, e.g. S_AND_B64 (vcc = V_CMP_...), (vcc = V_CMP_...)
278           //
279           // So, instead of forcing the instruction to write to VCC, we provide
280           // a hint to the register allocator to use VCC and then we we will run
281           // this pass again after RA and shrink it if it outputs to VCC.
282           MRI.setRegAllocationHint(MI.getOperand(0).getReg(), 0, AMDGPU::VCC);
283           continue;
284         }
285         if (DstReg != AMDGPU::VCC)
286           continue;
287       }
288 
289       if (Op32 == AMDGPU::V_CNDMASK_B32_e32) {
290         // We shrink V_CNDMASK_B32_e64 using regalloc hints like we do for VOPC
291         // instructions.
292         const MachineOperand *Src2 =
293             TII->getNamedOperand(MI, AMDGPU::OpName::src2);
294         if (!Src2->isReg())
295           continue;
296         unsigned SReg = Src2->getReg();
297         if (TargetRegisterInfo::isVirtualRegister(SReg)) {
298           MRI.setRegAllocationHint(SReg, 0, AMDGPU::VCC);
299           continue;
300         }
301         if (SReg != AMDGPU::VCC)
302           continue;
303       }
304 
305       // We can shrink this instruction
306       DEBUG(dbgs() << "Shrinking " << MI);
307 
308       MachineInstrBuilder Inst32 =
309           BuildMI(MBB, I, MI.getDebugLoc(), TII->get(Op32));
310 
311       // Add the dst operand if the 32-bit encoding also has an explicit $vdst.
312       // For VOPC instructions, this is replaced by an implicit def of vcc.
313       int Op32DstIdx = AMDGPU::getNamedOperandIdx(Op32, AMDGPU::OpName::vdst);
314       if (Op32DstIdx != -1) {
315         // dst
316         Inst32.addOperand(MI.getOperand(0));
317       } else {
318         assert(MI.getOperand(0).getReg() == AMDGPU::VCC &&
319                "Unexpected case");
320       }
321 
322 
323       Inst32.addOperand(*TII->getNamedOperand(MI, AMDGPU::OpName::src0));
324 
325       const MachineOperand *Src1 =
326           TII->getNamedOperand(MI, AMDGPU::OpName::src1);
327       if (Src1)
328         Inst32.addOperand(*Src1);
329 
330       const MachineOperand *Src2 =
331         TII->getNamedOperand(MI, AMDGPU::OpName::src2);
332       if (Src2) {
333         int Op32Src2Idx = AMDGPU::getNamedOperandIdx(Op32, AMDGPU::OpName::src2);
334         if (Op32Src2Idx != -1) {
335           Inst32.addOperand(*Src2);
336         } else {
337           // In the case of V_CNDMASK_B32_e32, the explicit operand src2 is
338           // replaced with an implicit read of vcc.
339           assert(Src2->getReg() == AMDGPU::VCC &&
340                  "Unexpected missing register operand");
341           Inst32.addOperand(copyRegOperandAsImplicit(*Src2));
342         }
343       }
344 
345       ++NumInstructionsShrunk;
346       MI.eraseFromParent();
347 
348       foldImmediates(*Inst32, TII, MRI);
349       DEBUG(dbgs() << "e32 MI = " << *Inst32 << '\n');
350 
351 
352     }
353   }
354   return false;
355 }
356