1//===-- SISchedule.td - SI Scheduling definitons -------------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// MachineModel definitions for Southern Islands (SI)
11//
12//===----------------------------------------------------------------------===//
13
14def : PredicateProlog<[{
15  const SIInstrInfo *TII =
16    static_cast<const SIInstrInfo*>(SchedModel->getInstrInfo());
17  (void)TII;
18}]>;
19
20def WriteBranch : SchedWrite;
21def WriteExport : SchedWrite;
22def WriteLDS    : SchedWrite;
23def WriteSALU   : SchedWrite;
24def WriteSMEM   : SchedWrite;
25def WriteVMEM   : SchedWrite;
26def WriteBarrier : SchedWrite;
27
28// Vector ALU instructions
29def Write32Bit         : SchedWrite;
30def WriteQuarterRate32 : SchedWrite;
31def WriteFullOrQuarterRate32 : SchedWrite;
32
33def WriteFloatFMA   : SchedWrite;
34
35// Slow quarter rate f64 instruction.
36def WriteDouble : SchedWrite;
37
38// half rate f64 instruction (same as v_add_f64)
39def WriteDoubleAdd  : SchedWrite;
40
41// Half rate 64-bit instructions.
42def Write64Bit : SchedWrite;
43
44// FIXME: Should there be a class for instructions which are VALU
45// instructions and have VALU rates, but write to the SALU (i.e. VOPC
46// instructions)
47
48class SISchedMachineModel : SchedMachineModel {
49  let CompleteModel = 1;
50  // MicroOpBufferSize = 1 means that instructions will always be added
51  // the ready queue when they become available.  This exposes them
52  // to the register pressure analysis.
53  let MicroOpBufferSize = 1;
54  let IssueWidth = 1;
55  let PostRAScheduler = 1;
56}
57
58def SIFullSpeedModel : SISchedMachineModel;
59def SIQuarterSpeedModel : SISchedMachineModel;
60
61// XXX: Are the resource counts correct?
62def HWBranch : ProcResource<1> {
63  let BufferSize = 1;
64}
65def HWExport : ProcResource<1> {
66  let BufferSize = 7; // Taken from S_WAITCNT
67}
68def HWLGKM   : ProcResource<1> {
69  let BufferSize = 31;  // Taken from S_WAITCNT
70}
71def HWSALU   : ProcResource<1> {
72  let BufferSize = 1;
73}
74def HWVMEM   : ProcResource<1> {
75  let BufferSize = 15;  // Taken from S_WAITCNT
76}
77def HWVALU   : ProcResource<1> {
78  let BufferSize = 1;
79}
80
81class HWWriteRes<SchedWrite write, list<ProcResourceKind> resources,
82                 int latency> : WriteRes<write, resources> {
83  let Latency = latency;
84}
85
86class HWVALUWriteRes<SchedWrite write, int latency> :
87  HWWriteRes<write, [HWVALU], latency>;
88
89
90// The latency numbers are taken from AMD Accelerated Parallel Processing
91// guide. They may not be accurate.
92
93// The latency values are 1 / (operations / cycle) / 4.
94multiclass SICommonWriteRes {
95
96  def : HWWriteRes<WriteBranch,  [HWBranch], 8>;
97  def : HWWriteRes<WriteExport,  [HWExport], 4>;
98  def : HWWriteRes<WriteLDS,     [HWLGKM],   5>; // Can be between 2 and 64
99  def : HWWriteRes<WriteSALU,    [HWSALU],   1>;
100  def : HWWriteRes<WriteSMEM,    [HWLGKM],   5>;
101  def : HWWriteRes<WriteVMEM,    [HWVMEM],   80>;
102  def : HWWriteRes<WriteBarrier, [HWBranch], 500>; // XXX: Guessed ???
103
104  def : HWVALUWriteRes<Write32Bit,         1>;
105  def : HWVALUWriteRes<Write64Bit,         2>;
106  def : HWVALUWriteRes<WriteQuarterRate32, 4>;
107}
108
109def PredIsVGPR32Copy : SchedPredicate<[{TII->isVGPRCopy(*MI) && TII->getOpSize(*MI, 0) <= 32}]>;
110def PredIsVGPR64Copy : SchedPredicate<[{TII->isVGPRCopy(*MI) && TII->getOpSize(*MI, 0) > 32}]>;
111def WriteCopy : SchedWriteVariant<[
112    SchedVar<PredIsVGPR32Copy, [Write32Bit]>,
113    SchedVar<PredIsVGPR64Copy, [Write64Bit]>,
114    SchedVar<NoSchedPred, [WriteSALU]>]>;
115
116let SchedModel = SIFullSpeedModel in {
117
118defm : SICommonWriteRes;
119
120def : HWVALUWriteRes<WriteFloatFMA,   1>;
121def : HWVALUWriteRes<WriteDouble,     4>;
122def : HWVALUWriteRes<WriteDoubleAdd,  2>;
123
124def : InstRW<[WriteCopy], (instrs COPY)>;
125
126} // End SchedModel = SIFullSpeedModel
127
128let SchedModel = SIQuarterSpeedModel in {
129
130defm : SICommonWriteRes;
131
132def : HWVALUWriteRes<WriteFloatFMA, 16>;
133def : HWVALUWriteRes<WriteDouble,   16>;
134def : HWVALUWriteRes<WriteDoubleAdd, 8>;
135
136def : InstRW<[WriteCopy], (instrs COPY)>;
137
138}  // End SchedModel = SIQuarterSpeedModel
139