1 //===-- SIOptimizeExecMaskingPreRA.cpp ------------------------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 /// This pass removes redundant S_OR_B64 instructions enabling lanes in
12 /// the exec. If two SI_END_CF (lowered as S_OR_B64) come together without any
13 /// vector instructions between them we can only keep outer SI_END_CF, given
14 /// that CFG is structured and exec bits of the outer end statement are always
15 /// not less than exec bit of the inner one.
16 ///
17 /// This needs to be done before the RA to eliminate saved exec bits registers
18 /// but after register coalescer to have no vector registers copies in between
19 /// of different end cf statements.
20 ///
21 //===----------------------------------------------------------------------===//
22 
23 #include "AMDGPU.h"
24 #include "AMDGPUSubtarget.h"
25 #include "SIInstrInfo.h"
26 #include "llvm/CodeGen/LiveIntervals.h"
27 #include "llvm/CodeGen/MachineFunctionPass.h"
28 
29 using namespace llvm;
30 
31 #define DEBUG_TYPE "si-optimize-exec-masking-pre-ra"
32 
33 namespace {
34 
35 class SIOptimizeExecMaskingPreRA : public MachineFunctionPass {
36 public:
37   static char ID;
38 
39 public:
40   SIOptimizeExecMaskingPreRA() : MachineFunctionPass(ID) {
41     initializeSIOptimizeExecMaskingPreRAPass(*PassRegistry::getPassRegistry());
42   }
43 
44   bool runOnMachineFunction(MachineFunction &MF) override;
45 
46   StringRef getPassName() const override {
47     return "SI optimize exec mask operations pre-RA";
48   }
49 
50   void getAnalysisUsage(AnalysisUsage &AU) const override {
51     AU.addRequired<LiveIntervals>();
52     AU.setPreservesAll();
53     MachineFunctionPass::getAnalysisUsage(AU);
54   }
55 };
56 
57 } // End anonymous namespace.
58 
59 INITIALIZE_PASS_BEGIN(SIOptimizeExecMaskingPreRA, DEBUG_TYPE,
60                       "SI optimize exec mask operations pre-RA", false, false)
61 INITIALIZE_PASS_DEPENDENCY(LiveIntervals)
62 INITIALIZE_PASS_END(SIOptimizeExecMaskingPreRA, DEBUG_TYPE,
63                     "SI optimize exec mask operations pre-RA", false, false)
64 
65 char SIOptimizeExecMaskingPreRA::ID = 0;
66 
67 char &llvm::SIOptimizeExecMaskingPreRAID = SIOptimizeExecMaskingPreRA::ID;
68 
69 FunctionPass *llvm::createSIOptimizeExecMaskingPreRAPass() {
70   return new SIOptimizeExecMaskingPreRA();
71 }
72 
73 static bool isEndCF(const MachineInstr& MI, const SIRegisterInfo* TRI) {
74   return MI.getOpcode() == AMDGPU::S_OR_B64 &&
75          MI.modifiesRegister(AMDGPU::EXEC, TRI);
76 }
77 
78 static bool isFullExecCopy(const MachineInstr& MI) {
79   return MI.isFullCopy() && MI.getOperand(1).getReg() == AMDGPU::EXEC;
80 }
81 
82 static unsigned getOrNonExecReg(const MachineInstr &MI,
83                                 const SIInstrInfo &TII) {
84   auto Op = TII.getNamedOperand(MI, AMDGPU::OpName::src1);
85   if (Op->isReg() && Op->getReg() != AMDGPU::EXEC)
86      return Op->getReg();
87   Op = TII.getNamedOperand(MI, AMDGPU::OpName::src0);
88   if (Op->isReg() && Op->getReg() != AMDGPU::EXEC)
89      return Op->getReg();
90   return AMDGPU::NoRegister;
91 }
92 
93 static MachineInstr* getOrExecSource(const MachineInstr &MI,
94                                      const SIInstrInfo &TII,
95                                      const MachineRegisterInfo &MRI) {
96   auto SavedExec = getOrNonExecReg(MI, TII);
97   if (SavedExec == AMDGPU::NoRegister)
98     return nullptr;
99   auto SaveExecInst = MRI.getUniqueVRegDef(SavedExec);
100   if (!SaveExecInst || !isFullExecCopy(*SaveExecInst))
101     return nullptr;
102   return SaveExecInst;
103 }
104 
105 bool SIOptimizeExecMaskingPreRA::runOnMachineFunction(MachineFunction &MF) {
106   if (skipFunction(MF.getFunction()))
107     return false;
108 
109   const SISubtarget &ST = MF.getSubtarget<SISubtarget>();
110   const SIRegisterInfo *TRI = ST.getRegisterInfo();
111   const SIInstrInfo *TII = ST.getInstrInfo();
112   MachineRegisterInfo &MRI = MF.getRegInfo();
113   LiveIntervals *LIS = &getAnalysis<LiveIntervals>();
114   DenseSet<unsigned> RecalcRegs({AMDGPU::EXEC_LO, AMDGPU::EXEC_HI});
115   bool Changed = false;
116 
117   for (MachineBasicBlock &MBB : MF) {
118 
119     // Try to remove unneeded instructions before s_endpgm.
120     if (MBB.succ_empty()) {
121       if (MBB.empty() || MBB.back().getOpcode() != AMDGPU::S_ENDPGM)
122         continue;
123 
124       SmallVector<MachineBasicBlock*, 4> Blocks({&MBB});
125 
126       while (!Blocks.empty()) {
127         auto CurBB = Blocks.pop_back_val();
128         auto I = CurBB->rbegin(), E = CurBB->rend();
129         if (I != E) {
130           if (I->isUnconditionalBranch() || I->getOpcode() == AMDGPU::S_ENDPGM)
131             ++I;
132           else if (I->isBranch())
133             continue;
134         }
135 
136         while (I != E) {
137           if (I->isDebugInstr()) {
138             I = std::next(I);
139             continue;
140           }
141 
142           if (I->mayStore() || I->isBarrier() || I->isCall() ||
143               I->hasUnmodeledSideEffects() || I->hasOrderedMemoryRef())
144             break;
145 
146           LLVM_DEBUG(dbgs()
147                      << "Removing no effect instruction: " << *I << '\n');
148 
149           for (auto &Op : I->operands()) {
150             if (Op.isReg())
151               RecalcRegs.insert(Op.getReg());
152           }
153 
154           auto Next = std::next(I);
155           LIS->RemoveMachineInstrFromMaps(*I);
156           I->eraseFromParent();
157           I = Next;
158 
159           Changed = true;
160         }
161 
162         if (I != E)
163           continue;
164 
165         // Try to ascend predecessors.
166         for (auto *Pred : CurBB->predecessors()) {
167           if (Pred->succ_size() == 1)
168             Blocks.push_back(Pred);
169         }
170       }
171       continue;
172     }
173 
174     // Try to collapse adjacent endifs.
175     auto Lead = MBB.begin(), E = MBB.end();
176     if (MBB.succ_size() != 1 || Lead == E || !isEndCF(*Lead, TRI))
177       continue;
178 
179     const MachineBasicBlock* Succ = *MBB.succ_begin();
180     if (!MBB.isLayoutSuccessor(Succ))
181       continue;
182 
183     auto I = std::next(Lead);
184 
185     for ( ; I != E; ++I)
186       if (!TII->isSALU(*I) || I->readsRegister(AMDGPU::EXEC, TRI))
187         break;
188 
189     if (I != E)
190       continue;
191 
192     const auto NextLead = Succ->begin();
193     if (NextLead == Succ->end() || !isEndCF(*NextLead, TRI) ||
194         !getOrExecSource(*NextLead, *TII, MRI))
195       continue;
196 
197     LLVM_DEBUG(dbgs() << "Redundant EXEC = S_OR_B64 found: " << *Lead << '\n');
198 
199     auto SaveExec = getOrExecSource(*Lead, *TII, MRI);
200     unsigned SaveExecReg = getOrNonExecReg(*Lead, *TII);
201     for (auto &Op : Lead->operands()) {
202       if (Op.isReg())
203         RecalcRegs.insert(Op.getReg());
204     }
205 
206     LIS->RemoveMachineInstrFromMaps(*Lead);
207     Lead->eraseFromParent();
208     if (SaveExecReg) {
209       LIS->removeInterval(SaveExecReg);
210       LIS->createAndComputeVirtRegInterval(SaveExecReg);
211     }
212 
213     Changed = true;
214 
215     // If the only use of saved exec in the removed instruction is S_AND_B64
216     // fold the copy now.
217     if (!SaveExec || !SaveExec->isFullCopy())
218       continue;
219 
220     unsigned SavedExec = SaveExec->getOperand(0).getReg();
221     bool SafeToReplace = true;
222     for (auto& U : MRI.use_nodbg_instructions(SavedExec)) {
223       if (U.getParent() != SaveExec->getParent()) {
224         SafeToReplace = false;
225         break;
226       }
227 
228       LLVM_DEBUG(dbgs() << "Redundant EXEC COPY: " << *SaveExec << '\n');
229     }
230 
231     if (SafeToReplace) {
232       LIS->RemoveMachineInstrFromMaps(*SaveExec);
233       SaveExec->eraseFromParent();
234       MRI.replaceRegWith(SavedExec, AMDGPU::EXEC);
235       LIS->removeInterval(SavedExec);
236     }
237   }
238 
239   if (Changed) {
240     for (auto Reg : RecalcRegs) {
241       if (TargetRegisterInfo::isVirtualRegister(Reg)) {
242         LIS->removeInterval(Reg);
243         if (!MRI.reg_empty(Reg))
244           LIS->createAndComputeVirtRegInterval(Reg);
245       } else {
246         for (MCRegUnitIterator U(Reg, TRI); U.isValid(); ++U)
247           LIS->removeRegUnit(*U);
248       }
249     }
250   }
251 
252   return Changed;
253 }
254