1 //===-- SIOptimizeExecMasking.cpp -----------------------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #include "AMDGPU.h"
10 #include "AMDGPUSubtarget.h"
11 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
12 #include "SIInstrInfo.h"
13 #include "llvm/ADT/SmallSet.h"
14 #include "llvm/CodeGen/MachineFunctionPass.h"
15 #include "llvm/CodeGen/MachineInstrBuilder.h"
16 #include "llvm/CodeGen/MachineRegisterInfo.h"
17 #include "llvm/InitializePasses.h"
18 #include "llvm/Support/Debug.h"
19 
20 using namespace llvm;
21 
22 #define DEBUG_TYPE "si-optimize-exec-masking"
23 
24 namespace {
25 
26 class SIOptimizeExecMasking : public MachineFunctionPass {
27 public:
28   static char ID;
29 
30 public:
31   SIOptimizeExecMasking() : MachineFunctionPass(ID) {
32     initializeSIOptimizeExecMaskingPass(*PassRegistry::getPassRegistry());
33   }
34 
35   bool runOnMachineFunction(MachineFunction &MF) override;
36 
37   StringRef getPassName() const override {
38     return "SI optimize exec mask operations";
39   }
40 
41   void getAnalysisUsage(AnalysisUsage &AU) const override {
42     AU.setPreservesCFG();
43     MachineFunctionPass::getAnalysisUsage(AU);
44   }
45 };
46 
47 } // End anonymous namespace.
48 
49 INITIALIZE_PASS_BEGIN(SIOptimizeExecMasking, DEBUG_TYPE,
50                       "SI optimize exec mask operations", false, false)
51 INITIALIZE_PASS_DEPENDENCY(LiveIntervals)
52 INITIALIZE_PASS_END(SIOptimizeExecMasking, DEBUG_TYPE,
53                     "SI optimize exec mask operations", false, false)
54 
55 char SIOptimizeExecMasking::ID = 0;
56 
57 char &llvm::SIOptimizeExecMaskingID = SIOptimizeExecMasking::ID;
58 
59 /// If \p MI is a copy from exec, return the register copied to.
60 static Register isCopyFromExec(const MachineInstr &MI, const GCNSubtarget &ST) {
61   switch (MI.getOpcode()) {
62   case AMDGPU::COPY:
63   case AMDGPU::S_MOV_B64:
64   case AMDGPU::S_MOV_B64_term:
65   case AMDGPU::S_MOV_B32:
66   case AMDGPU::S_MOV_B32_term: {
67     const MachineOperand &Src = MI.getOperand(1);
68     if (Src.isReg() &&
69         Src.getReg() == (ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC))
70       return MI.getOperand(0).getReg();
71   }
72   }
73 
74   return AMDGPU::NoRegister;
75 }
76 
77 /// If \p MI is a copy to exec, return the register copied from.
78 static Register isCopyToExec(const MachineInstr &MI, const GCNSubtarget &ST) {
79   switch (MI.getOpcode()) {
80   case AMDGPU::COPY:
81   case AMDGPU::S_MOV_B64:
82   case AMDGPU::S_MOV_B32: {
83     const MachineOperand &Dst = MI.getOperand(0);
84     if (Dst.isReg() &&
85         Dst.getReg() == (ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC) &&
86         MI.getOperand(1).isReg())
87       return MI.getOperand(1).getReg();
88     break;
89   }
90   case AMDGPU::S_MOV_B64_term:
91   case AMDGPU::S_MOV_B32_term:
92     llvm_unreachable("should have been replaced");
93   }
94 
95   return Register();
96 }
97 
98 /// If \p MI is a logical operation on an exec value,
99 /// return the register copied to.
100 static Register isLogicalOpOnExec(const MachineInstr &MI) {
101   switch (MI.getOpcode()) {
102   case AMDGPU::S_AND_B64:
103   case AMDGPU::S_OR_B64:
104   case AMDGPU::S_XOR_B64:
105   case AMDGPU::S_ANDN2_B64:
106   case AMDGPU::S_ORN2_B64:
107   case AMDGPU::S_NAND_B64:
108   case AMDGPU::S_NOR_B64:
109   case AMDGPU::S_XNOR_B64: {
110     const MachineOperand &Src1 = MI.getOperand(1);
111     if (Src1.isReg() && Src1.getReg() == AMDGPU::EXEC)
112       return MI.getOperand(0).getReg();
113     const MachineOperand &Src2 = MI.getOperand(2);
114     if (Src2.isReg() && Src2.getReg() == AMDGPU::EXEC)
115       return MI.getOperand(0).getReg();
116     break;
117   }
118   case AMDGPU::S_AND_B32:
119   case AMDGPU::S_OR_B32:
120   case AMDGPU::S_XOR_B32:
121   case AMDGPU::S_ANDN2_B32:
122   case AMDGPU::S_ORN2_B32:
123   case AMDGPU::S_NAND_B32:
124   case AMDGPU::S_NOR_B32:
125   case AMDGPU::S_XNOR_B32: {
126     const MachineOperand &Src1 = MI.getOperand(1);
127     if (Src1.isReg() && Src1.getReg() == AMDGPU::EXEC_LO)
128       return MI.getOperand(0).getReg();
129     const MachineOperand &Src2 = MI.getOperand(2);
130     if (Src2.isReg() && Src2.getReg() == AMDGPU::EXEC_LO)
131       return MI.getOperand(0).getReg();
132     break;
133   }
134   }
135 
136   return AMDGPU::NoRegister;
137 }
138 
139 static unsigned getSaveExecOp(unsigned Opc) {
140   switch (Opc) {
141   case AMDGPU::S_AND_B64:
142     return AMDGPU::S_AND_SAVEEXEC_B64;
143   case AMDGPU::S_OR_B64:
144     return AMDGPU::S_OR_SAVEEXEC_B64;
145   case AMDGPU::S_XOR_B64:
146     return AMDGPU::S_XOR_SAVEEXEC_B64;
147   case AMDGPU::S_ANDN2_B64:
148     return AMDGPU::S_ANDN2_SAVEEXEC_B64;
149   case AMDGPU::S_ORN2_B64:
150     return AMDGPU::S_ORN2_SAVEEXEC_B64;
151   case AMDGPU::S_NAND_B64:
152     return AMDGPU::S_NAND_SAVEEXEC_B64;
153   case AMDGPU::S_NOR_B64:
154     return AMDGPU::S_NOR_SAVEEXEC_B64;
155   case AMDGPU::S_XNOR_B64:
156     return AMDGPU::S_XNOR_SAVEEXEC_B64;
157   case AMDGPU::S_AND_B32:
158     return AMDGPU::S_AND_SAVEEXEC_B32;
159   case AMDGPU::S_OR_B32:
160     return AMDGPU::S_OR_SAVEEXEC_B32;
161   case AMDGPU::S_XOR_B32:
162     return AMDGPU::S_XOR_SAVEEXEC_B32;
163   case AMDGPU::S_ANDN2_B32:
164     return AMDGPU::S_ANDN2_SAVEEXEC_B32;
165   case AMDGPU::S_ORN2_B32:
166     return AMDGPU::S_ORN2_SAVEEXEC_B32;
167   case AMDGPU::S_NAND_B32:
168     return AMDGPU::S_NAND_SAVEEXEC_B32;
169   case AMDGPU::S_NOR_B32:
170     return AMDGPU::S_NOR_SAVEEXEC_B32;
171   case AMDGPU::S_XNOR_B32:
172     return AMDGPU::S_XNOR_SAVEEXEC_B32;
173   default:
174     return AMDGPU::INSTRUCTION_LIST_END;
175   }
176 }
177 
178 // These are only terminators to get correct spill code placement during
179 // register allocation, so turn them back into normal instructions.
180 static bool removeTerminatorBit(const SIInstrInfo &TII, MachineInstr &MI) {
181   switch (MI.getOpcode()) {
182   case AMDGPU::S_MOV_B64_term:
183   case AMDGPU::S_MOV_B32_term: {
184     MI.setDesc(TII.get(AMDGPU::COPY));
185     return true;
186   }
187   case AMDGPU::S_XOR_B64_term: {
188     // This is only a terminator to get the correct spill code placement during
189     // register allocation.
190     MI.setDesc(TII.get(AMDGPU::S_XOR_B64));
191     return true;
192   }
193   case AMDGPU::S_XOR_B32_term: {
194     // This is only a terminator to get the correct spill code placement during
195     // register allocation.
196     MI.setDesc(TII.get(AMDGPU::S_XOR_B32));
197     return true;
198   }
199   case AMDGPU::S_OR_B32_term: {
200     // This is only a terminator to get the correct spill code placement during
201     // register allocation.
202     MI.setDesc(TII.get(AMDGPU::S_OR_B32));
203     return true;
204   }
205   case AMDGPU::S_ANDN2_B64_term: {
206     // This is only a terminator to get the correct spill code placement during
207     // register allocation.
208     MI.setDesc(TII.get(AMDGPU::S_ANDN2_B64));
209     return true;
210   }
211   case AMDGPU::S_ANDN2_B32_term: {
212     // This is only a terminator to get the correct spill code placement during
213     // register allocation.
214     MI.setDesc(TII.get(AMDGPU::S_ANDN2_B32));
215     return true;
216   }
217   default:
218     return false;
219   }
220 }
221 
222 // Turn all pseudoterminators in the block into their equivalent non-terminator
223 // instructions. Returns the reverse iterator to the first non-terminator
224 // instruction in the block.
225 static MachineBasicBlock::reverse_iterator fixTerminators(
226   const SIInstrInfo &TII,
227   MachineBasicBlock &MBB) {
228   MachineBasicBlock::reverse_iterator I = MBB.rbegin(), E = MBB.rend();
229 
230   bool Seen = false;
231   MachineBasicBlock::reverse_iterator FirstNonTerm = I;
232   for (; I != E; ++I) {
233     if (!I->isTerminator())
234       return Seen ? FirstNonTerm : I;
235 
236     if (removeTerminatorBit(TII, *I)) {
237       if (!Seen) {
238         FirstNonTerm = I;
239         Seen = true;
240       }
241     }
242   }
243 
244   return FirstNonTerm;
245 }
246 
247 static MachineBasicBlock::reverse_iterator findExecCopy(
248   const SIInstrInfo &TII,
249   const GCNSubtarget &ST,
250   MachineBasicBlock &MBB,
251   MachineBasicBlock::reverse_iterator I,
252   unsigned CopyToExec) {
253   const unsigned InstLimit = 25;
254 
255   auto E = MBB.rend();
256   for (unsigned N = 0; N <= InstLimit && I != E; ++I, ++N) {
257     Register CopyFromExec = isCopyFromExec(*I, ST);
258     if (CopyFromExec.isValid())
259       return I;
260   }
261 
262   return E;
263 }
264 
265 // XXX - Seems LivePhysRegs doesn't work correctly since it will incorrectly
266 // report the register as unavailable because a super-register with a lane mask
267 // is unavailable.
268 static bool isLiveOut(const MachineBasicBlock &MBB, unsigned Reg) {
269   for (MachineBasicBlock *Succ : MBB.successors()) {
270     if (Succ->isLiveIn(Reg))
271       return true;
272   }
273 
274   return false;
275 }
276 
277 bool SIOptimizeExecMasking::runOnMachineFunction(MachineFunction &MF) {
278   if (skipFunction(MF.getFunction()))
279     return false;
280 
281   const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
282   const SIRegisterInfo *TRI = ST.getRegisterInfo();
283   const SIInstrInfo *TII = ST.getInstrInfo();
284   MCRegister Exec = ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC;
285 
286   // Optimize sequences emitted for control flow lowering. They are originally
287   // emitted as the separate operations because spill code may need to be
288   // inserted for the saved copy of exec.
289   //
290   //     x = copy exec
291   //     z = s_<op>_b64 x, y
292   //     exec = copy z
293   // =>
294   //     x = s_<op>_saveexec_b64 y
295   //
296 
297   for (MachineBasicBlock &MBB : MF) {
298     MachineBasicBlock::reverse_iterator I = fixTerminators(*TII, MBB);
299     MachineBasicBlock::reverse_iterator E = MBB.rend();
300     if (I == E)
301       continue;
302 
303     // It's possible to see other terminator copies after the exec copy. This
304     // can happen if control flow pseudos had their outputs used by phis.
305     Register CopyToExec;
306 
307     unsigned SearchCount = 0;
308     const unsigned SearchLimit = 5;
309     while (I != E && SearchCount++ < SearchLimit) {
310       CopyToExec = isCopyToExec(*I, ST);
311       if (CopyToExec)
312         break;
313       ++I;
314     }
315 
316     if (!CopyToExec)
317       continue;
318 
319     // Scan backwards to find the def.
320     auto CopyToExecInst = &*I;
321     auto CopyFromExecInst = findExecCopy(*TII, ST, MBB, I, CopyToExec);
322     if (CopyFromExecInst == E) {
323       auto PrepareExecInst = std::next(I);
324       if (PrepareExecInst == E)
325         continue;
326       // Fold exec = COPY (S_AND_B64 reg, exec) -> exec = S_AND_B64 reg, exec
327       if (CopyToExecInst->getOperand(1).isKill() &&
328           isLogicalOpOnExec(*PrepareExecInst) == CopyToExec) {
329         LLVM_DEBUG(dbgs() << "Fold exec copy: " << *PrepareExecInst);
330 
331         PrepareExecInst->getOperand(0).setReg(Exec);
332 
333         LLVM_DEBUG(dbgs() << "into: " << *PrepareExecInst << '\n');
334 
335         CopyToExecInst->eraseFromParent();
336       }
337 
338       continue;
339     }
340 
341     if (isLiveOut(MBB, CopyToExec)) {
342       // The copied register is live out and has a second use in another block.
343       LLVM_DEBUG(dbgs() << "Exec copy source register is live out\n");
344       continue;
345     }
346 
347     Register CopyFromExec = CopyFromExecInst->getOperand(0).getReg();
348     MachineInstr *SaveExecInst = nullptr;
349     SmallVector<MachineInstr *, 4> OtherUseInsts;
350 
351     for (MachineBasicBlock::iterator J
352            = std::next(CopyFromExecInst->getIterator()), JE = I->getIterator();
353          J != JE; ++J) {
354       if (SaveExecInst && J->readsRegister(Exec, TRI)) {
355         LLVM_DEBUG(dbgs() << "exec read prevents saveexec: " << *J << '\n');
356         // Make sure this is inserted after any VALU ops that may have been
357         // scheduled in between.
358         SaveExecInst = nullptr;
359         break;
360       }
361 
362       bool ReadsCopyFromExec = J->readsRegister(CopyFromExec, TRI);
363 
364       if (J->modifiesRegister(CopyToExec, TRI)) {
365         if (SaveExecInst) {
366           LLVM_DEBUG(dbgs() << "Multiple instructions modify "
367                             << printReg(CopyToExec, TRI) << '\n');
368           SaveExecInst = nullptr;
369           break;
370         }
371 
372         unsigned SaveExecOp = getSaveExecOp(J->getOpcode());
373         if (SaveExecOp == AMDGPU::INSTRUCTION_LIST_END)
374           break;
375 
376         if (ReadsCopyFromExec) {
377           SaveExecInst = &*J;
378           LLVM_DEBUG(dbgs() << "Found save exec op: " << *SaveExecInst << '\n');
379           continue;
380         } else {
381           LLVM_DEBUG(dbgs()
382                      << "Instruction does not read exec copy: " << *J << '\n');
383           break;
384         }
385       } else if (ReadsCopyFromExec && !SaveExecInst) {
386         // Make sure no other instruction is trying to use this copy, before it
387         // will be rewritten by the saveexec, i.e. hasOneUse. There may have
388         // been another use, such as an inserted spill. For example:
389         //
390         // %sgpr0_sgpr1 = COPY %exec
391         // spill %sgpr0_sgpr1
392         // %sgpr2_sgpr3 = S_AND_B64 %sgpr0_sgpr1
393         //
394         LLVM_DEBUG(dbgs() << "Found second use of save inst candidate: " << *J
395                           << '\n');
396         break;
397       }
398 
399       if (SaveExecInst && J->readsRegister(CopyToExec, TRI)) {
400         assert(SaveExecInst != &*J);
401         OtherUseInsts.push_back(&*J);
402       }
403     }
404 
405     if (!SaveExecInst)
406       continue;
407 
408     LLVM_DEBUG(dbgs() << "Insert save exec op: " << *SaveExecInst << '\n');
409 
410     MachineOperand &Src0 = SaveExecInst->getOperand(1);
411     MachineOperand &Src1 = SaveExecInst->getOperand(2);
412 
413     MachineOperand *OtherOp = nullptr;
414 
415     if (Src0.isReg() && Src0.getReg() == CopyFromExec) {
416       OtherOp = &Src1;
417     } else if (Src1.isReg() && Src1.getReg() == CopyFromExec) {
418       if (!SaveExecInst->isCommutable())
419         break;
420 
421       OtherOp = &Src0;
422     } else
423       llvm_unreachable("unexpected");
424 
425     CopyFromExecInst->eraseFromParent();
426 
427     auto InsPt = SaveExecInst->getIterator();
428     const DebugLoc &DL = SaveExecInst->getDebugLoc();
429 
430     BuildMI(MBB, InsPt, DL, TII->get(getSaveExecOp(SaveExecInst->getOpcode())),
431             CopyFromExec)
432       .addReg(OtherOp->getReg());
433     SaveExecInst->eraseFromParent();
434 
435     CopyToExecInst->eraseFromParent();
436 
437     for (MachineInstr *OtherInst : OtherUseInsts) {
438       OtherInst->substituteRegister(CopyToExec, Exec,
439                                     AMDGPU::NoSubRegister, *TRI);
440     }
441   }
442 
443   return true;
444 
445 }
446