1 //==- SIMachineFunctionInfo.h - SIMachineFunctionInfo interface --*- C++ -*-==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_AMDGPU_SIMACHINEFUNCTIONINFO_H
14 #define LLVM_LIB_TARGET_AMDGPU_SIMACHINEFUNCTIONINFO_H
15 
16 #include "AMDGPUArgumentUsageInfo.h"
17 #include "AMDGPUMachineFunction.h"
18 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
19 #include "SIInstrInfo.h"
20 #include "SIRegisterInfo.h"
21 #include "llvm/ADT/ArrayRef.h"
22 #include "llvm/ADT/DenseMap.h"
23 #include "llvm/ADT/Optional.h"
24 #include "llvm/ADT/STLExtras.h"
25 #include "llvm/ADT/SmallVector.h"
26 #include "llvm/ADT/SparseBitVector.h"
27 #include "llvm/CodeGen/MIRYamlMapping.h"
28 #include "llvm/CodeGen/PseudoSourceValue.h"
29 #include "llvm/CodeGen/TargetInstrInfo.h"
30 #include "llvm/MC/MCRegisterInfo.h"
31 #include "llvm/Support/ErrorHandling.h"
32 #include <array>
33 #include <cassert>
34 #include <utility>
35 #include <vector>
36 
37 namespace llvm {
38 
39 class MachineFrameInfo;
40 class MachineFunction;
41 class TargetRegisterClass;
42 
43 class AMDGPUPseudoSourceValue : public PseudoSourceValue {
44 public:
45   enum AMDGPUPSVKind : unsigned {
46     PSVBuffer = PseudoSourceValue::TargetCustom,
47     PSVImage,
48     GWSResource
49   };
50 
51 protected:
52   AMDGPUPseudoSourceValue(unsigned Kind, const TargetInstrInfo &TII)
53       : PseudoSourceValue(Kind, TII) {}
54 
55 public:
56   bool isConstant(const MachineFrameInfo *) const override {
57     // This should probably be true for most images, but we will start by being
58     // conservative.
59     return false;
60   }
61 
62   bool isAliased(const MachineFrameInfo *) const override {
63     return true;
64   }
65 
66   bool mayAlias(const MachineFrameInfo *) const override {
67     return true;
68   }
69 };
70 
71 class AMDGPUBufferPseudoSourceValue final : public AMDGPUPseudoSourceValue {
72 public:
73   explicit AMDGPUBufferPseudoSourceValue(const TargetInstrInfo &TII)
74       : AMDGPUPseudoSourceValue(PSVBuffer, TII) {}
75 
76   static bool classof(const PseudoSourceValue *V) {
77     return V->kind() == PSVBuffer;
78   }
79 };
80 
81 class AMDGPUImagePseudoSourceValue final : public AMDGPUPseudoSourceValue {
82 public:
83   // TODO: Is the img rsrc useful?
84   explicit AMDGPUImagePseudoSourceValue(const TargetInstrInfo &TII)
85       : AMDGPUPseudoSourceValue(PSVImage, TII) {}
86 
87   static bool classof(const PseudoSourceValue *V) {
88     return V->kind() == PSVImage;
89   }
90 };
91 
92 class AMDGPUGWSResourcePseudoSourceValue final : public AMDGPUPseudoSourceValue {
93 public:
94   explicit AMDGPUGWSResourcePseudoSourceValue(const TargetInstrInfo &TII)
95       : AMDGPUPseudoSourceValue(GWSResource, TII) {}
96 
97   static bool classof(const PseudoSourceValue *V) {
98     return V->kind() == GWSResource;
99   }
100 
101   // These are inaccessible memory from IR.
102   bool isAliased(const MachineFrameInfo *) const override {
103     return false;
104   }
105 
106   // These are inaccessible memory from IR.
107   bool mayAlias(const MachineFrameInfo *) const override {
108     return false;
109   }
110 
111   void printCustom(raw_ostream &OS) const override {
112     OS << "GWSResource";
113   }
114 };
115 
116 namespace yaml {
117 
118 struct SIArgument {
119   bool IsRegister;
120   union {
121     StringValue RegisterName;
122     unsigned StackOffset;
123   };
124   Optional<unsigned> Mask;
125 
126   // Default constructor, which creates a stack argument.
127   SIArgument() : IsRegister(false), StackOffset(0) {}
128   SIArgument(const SIArgument &Other) {
129     IsRegister = Other.IsRegister;
130     if (IsRegister) {
131       ::new ((void *)std::addressof(RegisterName))
132           StringValue(Other.RegisterName);
133     } else
134       StackOffset = Other.StackOffset;
135     Mask = Other.Mask;
136   }
137   SIArgument &operator=(const SIArgument &Other) {
138     IsRegister = Other.IsRegister;
139     if (IsRegister) {
140       ::new ((void *)std::addressof(RegisterName))
141           StringValue(Other.RegisterName);
142     } else
143       StackOffset = Other.StackOffset;
144     Mask = Other.Mask;
145     return *this;
146   }
147   ~SIArgument() {
148     if (IsRegister)
149       RegisterName.~StringValue();
150   }
151 
152   // Helper to create a register or stack argument.
153   static inline SIArgument createArgument(bool IsReg) {
154     if (IsReg)
155       return SIArgument(IsReg);
156     return SIArgument();
157   }
158 
159 private:
160   // Construct a register argument.
161   SIArgument(bool) : IsRegister(true), RegisterName() {}
162 };
163 
164 template <> struct MappingTraits<SIArgument> {
165   static void mapping(IO &YamlIO, SIArgument &A) {
166     if (YamlIO.outputting()) {
167       if (A.IsRegister)
168         YamlIO.mapRequired("reg", A.RegisterName);
169       else
170         YamlIO.mapRequired("offset", A.StackOffset);
171     } else {
172       auto Keys = YamlIO.keys();
173       if (is_contained(Keys, "reg")) {
174         A = SIArgument::createArgument(true);
175         YamlIO.mapRequired("reg", A.RegisterName);
176       } else if (is_contained(Keys, "offset"))
177         YamlIO.mapRequired("offset", A.StackOffset);
178       else
179         YamlIO.setError("missing required key 'reg' or 'offset'");
180     }
181     YamlIO.mapOptional("mask", A.Mask);
182   }
183   static const bool flow = true;
184 };
185 
186 struct SIArgumentInfo {
187   Optional<SIArgument> PrivateSegmentBuffer;
188   Optional<SIArgument> DispatchPtr;
189   Optional<SIArgument> QueuePtr;
190   Optional<SIArgument> KernargSegmentPtr;
191   Optional<SIArgument> DispatchID;
192   Optional<SIArgument> FlatScratchInit;
193   Optional<SIArgument> PrivateSegmentSize;
194 
195   Optional<SIArgument> WorkGroupIDX;
196   Optional<SIArgument> WorkGroupIDY;
197   Optional<SIArgument> WorkGroupIDZ;
198   Optional<SIArgument> WorkGroupInfo;
199   Optional<SIArgument> PrivateSegmentWaveByteOffset;
200 
201   Optional<SIArgument> ImplicitArgPtr;
202   Optional<SIArgument> ImplicitBufferPtr;
203 
204   Optional<SIArgument> WorkItemIDX;
205   Optional<SIArgument> WorkItemIDY;
206   Optional<SIArgument> WorkItemIDZ;
207 };
208 
209 template <> struct MappingTraits<SIArgumentInfo> {
210   static void mapping(IO &YamlIO, SIArgumentInfo &AI) {
211     YamlIO.mapOptional("privateSegmentBuffer", AI.PrivateSegmentBuffer);
212     YamlIO.mapOptional("dispatchPtr", AI.DispatchPtr);
213     YamlIO.mapOptional("queuePtr", AI.QueuePtr);
214     YamlIO.mapOptional("kernargSegmentPtr", AI.KernargSegmentPtr);
215     YamlIO.mapOptional("dispatchID", AI.DispatchID);
216     YamlIO.mapOptional("flatScratchInit", AI.FlatScratchInit);
217     YamlIO.mapOptional("privateSegmentSize", AI.PrivateSegmentSize);
218 
219     YamlIO.mapOptional("workGroupIDX", AI.WorkGroupIDX);
220     YamlIO.mapOptional("workGroupIDY", AI.WorkGroupIDY);
221     YamlIO.mapOptional("workGroupIDZ", AI.WorkGroupIDZ);
222     YamlIO.mapOptional("workGroupInfo", AI.WorkGroupInfo);
223     YamlIO.mapOptional("privateSegmentWaveByteOffset",
224                        AI.PrivateSegmentWaveByteOffset);
225 
226     YamlIO.mapOptional("implicitArgPtr", AI.ImplicitArgPtr);
227     YamlIO.mapOptional("implicitBufferPtr", AI.ImplicitBufferPtr);
228 
229     YamlIO.mapOptional("workItemIDX", AI.WorkItemIDX);
230     YamlIO.mapOptional("workItemIDY", AI.WorkItemIDY);
231     YamlIO.mapOptional("workItemIDZ", AI.WorkItemIDZ);
232   }
233 };
234 
235 // Default to default mode for default calling convention.
236 struct SIMode {
237   bool IEEE = true;
238   bool DX10Clamp = true;
239   bool FP32InputDenormals = true;
240   bool FP32OutputDenormals = true;
241   bool FP64FP16InputDenormals = true;
242   bool FP64FP16OutputDenormals = true;
243 
244   SIMode() = default;
245 
246   SIMode(const AMDGPU::SIModeRegisterDefaults &Mode) {
247     IEEE = Mode.IEEE;
248     DX10Clamp = Mode.DX10Clamp;
249     FP32InputDenormals = Mode.FP32InputDenormals;
250     FP32OutputDenormals = Mode.FP32OutputDenormals;
251     FP64FP16InputDenormals = Mode.FP64FP16InputDenormals;
252     FP64FP16OutputDenormals = Mode.FP64FP16OutputDenormals;
253   }
254 
255   bool operator ==(const SIMode Other) const {
256     return IEEE == Other.IEEE &&
257            DX10Clamp == Other.DX10Clamp &&
258            FP32InputDenormals == Other.FP32InputDenormals &&
259            FP32OutputDenormals == Other.FP32OutputDenormals &&
260            FP64FP16InputDenormals == Other.FP64FP16InputDenormals &&
261            FP64FP16OutputDenormals == Other.FP64FP16OutputDenormals;
262   }
263 };
264 
265 template <> struct MappingTraits<SIMode> {
266   static void mapping(IO &YamlIO, SIMode &Mode) {
267     YamlIO.mapOptional("ieee", Mode.IEEE, true);
268     YamlIO.mapOptional("dx10-clamp", Mode.DX10Clamp, true);
269     YamlIO.mapOptional("fp32-input-denormals", Mode.FP32InputDenormals, true);
270     YamlIO.mapOptional("fp32-output-denormals", Mode.FP32OutputDenormals, true);
271     YamlIO.mapOptional("fp64-fp16-input-denormals", Mode.FP64FP16InputDenormals, true);
272     YamlIO.mapOptional("fp64-fp16-output-denormals", Mode.FP64FP16OutputDenormals, true);
273   }
274 };
275 
276 struct SIMachineFunctionInfo final : public yaml::MachineFunctionInfo {
277   uint64_t ExplicitKernArgSize = 0;
278   unsigned MaxKernArgAlign = 0;
279   unsigned LDSSize = 0;
280   bool IsEntryFunction = false;
281   bool NoSignedZerosFPMath = false;
282   bool MemoryBound = false;
283   bool WaveLimiter = false;
284   bool HasSpilledSGPRs = false;
285   bool HasSpilledVGPRs = false;
286   uint32_t HighBitsOf32BitAddress = 0;
287 
288   StringValue ScratchRSrcReg = "$private_rsrc_reg";
289   StringValue FrameOffsetReg = "$fp_reg";
290   StringValue StackPtrOffsetReg = "$sp_reg";
291 
292   Optional<SIArgumentInfo> ArgInfo;
293   SIMode Mode;
294 
295   SIMachineFunctionInfo() = default;
296   SIMachineFunctionInfo(const llvm::SIMachineFunctionInfo &,
297                         const TargetRegisterInfo &TRI);
298 
299   void mappingImpl(yaml::IO &YamlIO) override;
300   ~SIMachineFunctionInfo() = default;
301 };
302 
303 template <> struct MappingTraits<SIMachineFunctionInfo> {
304   static void mapping(IO &YamlIO, SIMachineFunctionInfo &MFI) {
305     YamlIO.mapOptional("explicitKernArgSize", MFI.ExplicitKernArgSize,
306                        UINT64_C(0));
307     YamlIO.mapOptional("maxKernArgAlign", MFI.MaxKernArgAlign, 0u);
308     YamlIO.mapOptional("ldsSize", MFI.LDSSize, 0u);
309     YamlIO.mapOptional("isEntryFunction", MFI.IsEntryFunction, false);
310     YamlIO.mapOptional("noSignedZerosFPMath", MFI.NoSignedZerosFPMath, false);
311     YamlIO.mapOptional("memoryBound", MFI.MemoryBound, false);
312     YamlIO.mapOptional("waveLimiter", MFI.WaveLimiter, false);
313     YamlIO.mapOptional("hasSpilledSGPRs", MFI.HasSpilledSGPRs, false);
314     YamlIO.mapOptional("hasSpilledVGPRs", MFI.HasSpilledVGPRs, false);
315     YamlIO.mapOptional("scratchRSrcReg", MFI.ScratchRSrcReg,
316                        StringValue("$private_rsrc_reg"));
317     YamlIO.mapOptional("frameOffsetReg", MFI.FrameOffsetReg,
318                        StringValue("$fp_reg"));
319     YamlIO.mapOptional("stackPtrOffsetReg", MFI.StackPtrOffsetReg,
320                        StringValue("$sp_reg"));
321     YamlIO.mapOptional("argumentInfo", MFI.ArgInfo);
322     YamlIO.mapOptional("mode", MFI.Mode, SIMode());
323     YamlIO.mapOptional("highBitsOf32BitAddress",
324                        MFI.HighBitsOf32BitAddress, 0u);
325   }
326 };
327 
328 } // end namespace yaml
329 
330 /// This class keeps track of the SPI_SP_INPUT_ADDR config register, which
331 /// tells the hardware which interpolation parameters to load.
332 class SIMachineFunctionInfo final : public AMDGPUMachineFunction {
333   friend class GCNTargetMachine;
334 
335   Register TIDReg = AMDGPU::NoRegister;
336 
337   // Registers that may be reserved for spilling purposes. These may be the same
338   // as the input registers.
339   Register ScratchRSrcReg = AMDGPU::PRIVATE_RSRC_REG;
340 
341   // This is the the unswizzled offset from the current dispatch's scratch wave
342   // base to the beginning of the current function's frame.
343   Register FrameOffsetReg = AMDGPU::FP_REG;
344 
345   // This is an ABI register used in the non-entry calling convention to
346   // communicate the unswizzled offset from the current dispatch's scratch wave
347   // base to the beginning of the new function's frame.
348   Register StackPtrOffsetReg = AMDGPU::SP_REG;
349 
350   AMDGPUFunctionArgInfo ArgInfo;
351 
352   // Graphics info.
353   unsigned PSInputAddr = 0;
354   unsigned PSInputEnable = 0;
355 
356   /// Number of bytes of arguments this function has on the stack. If the callee
357   /// is expected to restore the argument stack this should be a multiple of 16,
358   /// all usable during a tail call.
359   ///
360   /// The alternative would forbid tail call optimisation in some cases: if we
361   /// want to transfer control from a function with 8-bytes of stack-argument
362   /// space to a function with 16-bytes then misalignment of this value would
363   /// make a stack adjustment necessary, which could not be undone by the
364   /// callee.
365   unsigned BytesInStackArgArea = 0;
366 
367   bool ReturnsVoid = true;
368 
369   // A pair of default/requested minimum/maximum flat work group sizes.
370   // Minimum - first, maximum - second.
371   std::pair<unsigned, unsigned> FlatWorkGroupSizes = {0, 0};
372 
373   // A pair of default/requested minimum/maximum number of waves per execution
374   // unit. Minimum - first, maximum - second.
375   std::pair<unsigned, unsigned> WavesPerEU = {0, 0};
376 
377   DenseMap<const Value *,
378            std::unique_ptr<const AMDGPUBufferPseudoSourceValue>> BufferPSVs;
379   DenseMap<const Value *,
380            std::unique_ptr<const AMDGPUImagePseudoSourceValue>> ImagePSVs;
381   std::unique_ptr<const AMDGPUGWSResourcePseudoSourceValue> GWSResourcePSV;
382 
383 private:
384   unsigned LDSWaveSpillSize = 0;
385   unsigned NumUserSGPRs = 0;
386   unsigned NumSystemSGPRs = 0;
387 
388   bool HasSpilledSGPRs = false;
389   bool HasSpilledVGPRs = false;
390   bool HasNonSpillStackObjects = false;
391   bool IsStackRealigned = false;
392 
393   unsigned NumSpilledSGPRs = 0;
394   unsigned NumSpilledVGPRs = 0;
395 
396   // Feature bits required for inputs passed in user SGPRs.
397   bool PrivateSegmentBuffer : 1;
398   bool DispatchPtr : 1;
399   bool QueuePtr : 1;
400   bool KernargSegmentPtr : 1;
401   bool DispatchID : 1;
402   bool FlatScratchInit : 1;
403 
404   // Feature bits required for inputs passed in system SGPRs.
405   bool WorkGroupIDX : 1; // Always initialized.
406   bool WorkGroupIDY : 1;
407   bool WorkGroupIDZ : 1;
408   bool WorkGroupInfo : 1;
409   bool PrivateSegmentWaveByteOffset : 1;
410 
411   bool WorkItemIDX : 1; // Always initialized.
412   bool WorkItemIDY : 1;
413   bool WorkItemIDZ : 1;
414 
415   // Private memory buffer
416   // Compute directly in sgpr[0:1]
417   // Other shaders indirect 64-bits at sgpr[0:1]
418   bool ImplicitBufferPtr : 1;
419 
420   // Pointer to where the ABI inserts special kernel arguments separate from the
421   // user arguments. This is an offset from the KernargSegmentPtr.
422   bool ImplicitArgPtr : 1;
423 
424   // The hard-wired high half of the address of the global information table
425   // for AMDPAL OS type. 0xffffffff represents no hard-wired high half, since
426   // current hardware only allows a 16 bit value.
427   unsigned GITPtrHigh;
428 
429   unsigned HighBitsOf32BitAddress;
430   unsigned GDSSize;
431 
432   // Current recorded maximum possible occupancy.
433   unsigned Occupancy;
434 
435   MCPhysReg getNextUserSGPR() const;
436 
437   MCPhysReg getNextSystemSGPR() const;
438 
439 public:
440   struct SpilledReg {
441     Register VGPR;
442     int Lane = -1;
443 
444     SpilledReg() = default;
445     SpilledReg(Register R, int L) : VGPR (R), Lane (L) {}
446 
447     bool hasLane() { return Lane != -1;}
448     bool hasReg() { return VGPR != 0;}
449   };
450 
451   struct SGPRSpillVGPRCSR {
452     // VGPR used for SGPR spills
453     Register VGPR;
454 
455     // If the VGPR is a CSR, the stack slot used to save/restore it in the
456     // prolog/epilog.
457     Optional<int> FI;
458 
459     SGPRSpillVGPRCSR(Register V, Optional<int> F) : VGPR(V), FI(F) {}
460   };
461 
462   struct VGPRSpillToAGPR {
463     SmallVector<MCPhysReg, 32> Lanes;
464     bool FullyAllocated = false;
465   };
466 
467   SparseBitVector<> WWMReservedRegs;
468 
469   void ReserveWWMRegister(Register Reg) { WWMReservedRegs.set(Reg); }
470 
471 private:
472   // Track VGPR + wave index for each subregister of the SGPR spilled to
473   // frameindex key.
474   DenseMap<int, std::vector<SpilledReg>> SGPRToVGPRSpills;
475   unsigned NumVGPRSpillLanes = 0;
476   SmallVector<SGPRSpillVGPRCSR, 2> SpillVGPRs;
477 
478   DenseMap<int, VGPRSpillToAGPR> VGPRToAGPRSpills;
479 
480   // AGPRs used for VGPR spills.
481   SmallVector<MCPhysReg, 32> SpillAGPR;
482 
483   // VGPRs used for AGPR spills.
484   SmallVector<MCPhysReg, 32> SpillVGPR;
485 
486 public: // FIXME
487   /// If this is set, an SGPR used for save/restore of the register used for the
488   /// frame pointer.
489   Register SGPRForFPSaveRestoreCopy;
490   Optional<int> FramePointerSaveIndex;
491 
492   /// If this is set, an SGPR used for save/restore of the register used for the
493   /// base pointer.
494   Register SGPRForBPSaveRestoreCopy;
495   Optional<int> BasePointerSaveIndex;
496 
497   Register VGPRReservedForSGPRSpill;
498   bool isCalleeSavedReg(const MCPhysReg *CSRegs, MCPhysReg Reg);
499 
500 public:
501   SIMachineFunctionInfo(const MachineFunction &MF);
502 
503   bool initializeBaseYamlFields(const yaml::SIMachineFunctionInfo &YamlMFI);
504 
505   ArrayRef<SpilledReg> getSGPRToVGPRSpills(int FrameIndex) const {
506     auto I = SGPRToVGPRSpills.find(FrameIndex);
507     return (I == SGPRToVGPRSpills.end()) ?
508       ArrayRef<SpilledReg>() : makeArrayRef(I->second);
509   }
510 
511   ArrayRef<SGPRSpillVGPRCSR> getSGPRSpillVGPRs() const {
512     return SpillVGPRs;
513   }
514 
515   void setSGPRSpillVGPRs(Register NewVGPR, Optional<int> newFI, int Index) {
516     SpillVGPRs[Index].VGPR = NewVGPR;
517     SpillVGPRs[Index].FI = newFI;
518     VGPRReservedForSGPRSpill = NewVGPR;
519   }
520 
521   bool removeVGPRForSGPRSpill(Register ReservedVGPR, MachineFunction &MF);
522 
523   ArrayRef<MCPhysReg> getAGPRSpillVGPRs() const {
524     return SpillAGPR;
525   }
526 
527   ArrayRef<MCPhysReg> getVGPRSpillAGPRs() const {
528     return SpillVGPR;
529   }
530 
531   MCPhysReg getVGPRToAGPRSpill(int FrameIndex, unsigned Lane) const {
532     auto I = VGPRToAGPRSpills.find(FrameIndex);
533     return (I == VGPRToAGPRSpills.end()) ? (MCPhysReg)AMDGPU::NoRegister
534                                          : I->second.Lanes[Lane];
535   }
536 
537   bool haveFreeLanesForSGPRSpill(const MachineFunction &MF,
538                                  unsigned NumLane) const;
539   bool allocateSGPRSpillToVGPR(MachineFunction &MF, int FI);
540   bool reserveVGPRforSGPRSpills(MachineFunction &MF);
541   bool allocateVGPRSpillToAGPR(MachineFunction &MF, int FI, bool isAGPRtoVGPR);
542   void removeDeadFrameIndices(MachineFrameInfo &MFI);
543 
544   bool hasCalculatedTID() const { return TIDReg != 0; };
545   Register getTIDReg() const { return TIDReg; };
546   void setTIDReg(Register Reg) { TIDReg = Reg; }
547 
548   unsigned getBytesInStackArgArea() const {
549     return BytesInStackArgArea;
550   }
551 
552   void setBytesInStackArgArea(unsigned Bytes) {
553     BytesInStackArgArea = Bytes;
554   }
555 
556   // Add user SGPRs.
557   Register addPrivateSegmentBuffer(const SIRegisterInfo &TRI);
558   Register addDispatchPtr(const SIRegisterInfo &TRI);
559   Register addQueuePtr(const SIRegisterInfo &TRI);
560   Register addKernargSegmentPtr(const SIRegisterInfo &TRI);
561   Register addDispatchID(const SIRegisterInfo &TRI);
562   Register addFlatScratchInit(const SIRegisterInfo &TRI);
563   Register addImplicitBufferPtr(const SIRegisterInfo &TRI);
564 
565   // Add system SGPRs.
566   Register addWorkGroupIDX() {
567     ArgInfo.WorkGroupIDX = ArgDescriptor::createRegister(getNextSystemSGPR());
568     NumSystemSGPRs += 1;
569     return ArgInfo.WorkGroupIDX.getRegister();
570   }
571 
572   Register addWorkGroupIDY() {
573     ArgInfo.WorkGroupIDY = ArgDescriptor::createRegister(getNextSystemSGPR());
574     NumSystemSGPRs += 1;
575     return ArgInfo.WorkGroupIDY.getRegister();
576   }
577 
578   Register addWorkGroupIDZ() {
579     ArgInfo.WorkGroupIDZ = ArgDescriptor::createRegister(getNextSystemSGPR());
580     NumSystemSGPRs += 1;
581     return ArgInfo.WorkGroupIDZ.getRegister();
582   }
583 
584   Register addWorkGroupInfo() {
585     ArgInfo.WorkGroupInfo = ArgDescriptor::createRegister(getNextSystemSGPR());
586     NumSystemSGPRs += 1;
587     return ArgInfo.WorkGroupInfo.getRegister();
588   }
589 
590   // Add special VGPR inputs
591   void setWorkItemIDX(ArgDescriptor Arg) {
592     ArgInfo.WorkItemIDX = Arg;
593   }
594 
595   void setWorkItemIDY(ArgDescriptor Arg) {
596     ArgInfo.WorkItemIDY = Arg;
597   }
598 
599   void setWorkItemIDZ(ArgDescriptor Arg) {
600     ArgInfo.WorkItemIDZ = Arg;
601   }
602 
603   Register addPrivateSegmentWaveByteOffset() {
604     ArgInfo.PrivateSegmentWaveByteOffset
605       = ArgDescriptor::createRegister(getNextSystemSGPR());
606     NumSystemSGPRs += 1;
607     return ArgInfo.PrivateSegmentWaveByteOffset.getRegister();
608   }
609 
610   void setPrivateSegmentWaveByteOffset(Register Reg) {
611     ArgInfo.PrivateSegmentWaveByteOffset = ArgDescriptor::createRegister(Reg);
612   }
613 
614   bool hasPrivateSegmentBuffer() const {
615     return PrivateSegmentBuffer;
616   }
617 
618   bool hasDispatchPtr() const {
619     return DispatchPtr;
620   }
621 
622   bool hasQueuePtr() const {
623     return QueuePtr;
624   }
625 
626   bool hasKernargSegmentPtr() const {
627     return KernargSegmentPtr;
628   }
629 
630   bool hasDispatchID() const {
631     return DispatchID;
632   }
633 
634   bool hasFlatScratchInit() const {
635     return FlatScratchInit;
636   }
637 
638   bool hasWorkGroupIDX() const {
639     return WorkGroupIDX;
640   }
641 
642   bool hasWorkGroupIDY() const {
643     return WorkGroupIDY;
644   }
645 
646   bool hasWorkGroupIDZ() const {
647     return WorkGroupIDZ;
648   }
649 
650   bool hasWorkGroupInfo() const {
651     return WorkGroupInfo;
652   }
653 
654   bool hasPrivateSegmentWaveByteOffset() const {
655     return PrivateSegmentWaveByteOffset;
656   }
657 
658   bool hasWorkItemIDX() const {
659     return WorkItemIDX;
660   }
661 
662   bool hasWorkItemIDY() const {
663     return WorkItemIDY;
664   }
665 
666   bool hasWorkItemIDZ() const {
667     return WorkItemIDZ;
668   }
669 
670   bool hasImplicitArgPtr() const {
671     return ImplicitArgPtr;
672   }
673 
674   bool hasImplicitBufferPtr() const {
675     return ImplicitBufferPtr;
676   }
677 
678   AMDGPUFunctionArgInfo &getArgInfo() {
679     return ArgInfo;
680   }
681 
682   const AMDGPUFunctionArgInfo &getArgInfo() const {
683     return ArgInfo;
684   }
685 
686   std::tuple<const ArgDescriptor *, const TargetRegisterClass *, LLT>
687   getPreloadedValue(AMDGPUFunctionArgInfo::PreloadedValue Value) const {
688     return ArgInfo.getPreloadedValue(Value);
689   }
690 
691   MCRegister getPreloadedReg(AMDGPUFunctionArgInfo::PreloadedValue Value) const {
692     auto Arg = std::get<0>(ArgInfo.getPreloadedValue(Value));
693     return Arg ? Arg->getRegister() : MCRegister();
694   }
695 
696   unsigned getGITPtrHigh() const {
697     return GITPtrHigh;
698   }
699 
700   Register getGITPtrLoReg(const MachineFunction &MF) const;
701 
702   uint32_t get32BitAddressHighBits() const {
703     return HighBitsOf32BitAddress;
704   }
705 
706   unsigned getGDSSize() const {
707     return GDSSize;
708   }
709 
710   unsigned getNumUserSGPRs() const {
711     return NumUserSGPRs;
712   }
713 
714   unsigned getNumPreloadedSGPRs() const {
715     return NumUserSGPRs + NumSystemSGPRs;
716   }
717 
718   Register getPrivateSegmentWaveByteOffsetSystemSGPR() const {
719     return ArgInfo.PrivateSegmentWaveByteOffset.getRegister();
720   }
721 
722   /// Returns the physical register reserved for use as the resource
723   /// descriptor for scratch accesses.
724   Register getScratchRSrcReg() const {
725     return ScratchRSrcReg;
726   }
727 
728   void setScratchRSrcReg(Register Reg) {
729     assert(Reg != 0 && "Should never be unset");
730     ScratchRSrcReg = Reg;
731   }
732 
733   Register getFrameOffsetReg() const {
734     return FrameOffsetReg;
735   }
736 
737   void setFrameOffsetReg(Register Reg) {
738     assert(Reg != 0 && "Should never be unset");
739     FrameOffsetReg = Reg;
740   }
741 
742   void setStackPtrOffsetReg(Register Reg) {
743     assert(Reg != 0 && "Should never be unset");
744     StackPtrOffsetReg = Reg;
745   }
746 
747   // Note the unset value for this is AMDGPU::SP_REG rather than
748   // NoRegister. This is mostly a workaround for MIR tests where state that
749   // can't be directly computed from the function is not preserved in serialized
750   // MIR.
751   Register getStackPtrOffsetReg() const {
752     return StackPtrOffsetReg;
753   }
754 
755   Register getQueuePtrUserSGPR() const {
756     return ArgInfo.QueuePtr.getRegister();
757   }
758 
759   Register getImplicitBufferPtrUserSGPR() const {
760     return ArgInfo.ImplicitBufferPtr.getRegister();
761   }
762 
763   bool hasSpilledSGPRs() const {
764     return HasSpilledSGPRs;
765   }
766 
767   void setHasSpilledSGPRs(bool Spill = true) {
768     HasSpilledSGPRs = Spill;
769   }
770 
771   bool hasSpilledVGPRs() const {
772     return HasSpilledVGPRs;
773   }
774 
775   void setHasSpilledVGPRs(bool Spill = true) {
776     HasSpilledVGPRs = Spill;
777   }
778 
779   bool hasNonSpillStackObjects() const {
780     return HasNonSpillStackObjects;
781   }
782 
783   void setHasNonSpillStackObjects(bool StackObject = true) {
784     HasNonSpillStackObjects = StackObject;
785   }
786 
787   bool isStackRealigned() const {
788     return IsStackRealigned;
789   }
790 
791   void setIsStackRealigned(bool Realigned = true) {
792     IsStackRealigned = Realigned;
793   }
794 
795   unsigned getNumSpilledSGPRs() const {
796     return NumSpilledSGPRs;
797   }
798 
799   unsigned getNumSpilledVGPRs() const {
800     return NumSpilledVGPRs;
801   }
802 
803   void addToSpilledSGPRs(unsigned num) {
804     NumSpilledSGPRs += num;
805   }
806 
807   void addToSpilledVGPRs(unsigned num) {
808     NumSpilledVGPRs += num;
809   }
810 
811   unsigned getPSInputAddr() const {
812     return PSInputAddr;
813   }
814 
815   unsigned getPSInputEnable() const {
816     return PSInputEnable;
817   }
818 
819   bool isPSInputAllocated(unsigned Index) const {
820     return PSInputAddr & (1 << Index);
821   }
822 
823   void markPSInputAllocated(unsigned Index) {
824     PSInputAddr |= 1 << Index;
825   }
826 
827   void markPSInputEnabled(unsigned Index) {
828     PSInputEnable |= 1 << Index;
829   }
830 
831   bool returnsVoid() const {
832     return ReturnsVoid;
833   }
834 
835   void setIfReturnsVoid(bool Value) {
836     ReturnsVoid = Value;
837   }
838 
839   /// \returns A pair of default/requested minimum/maximum flat work group sizes
840   /// for this function.
841   std::pair<unsigned, unsigned> getFlatWorkGroupSizes() const {
842     return FlatWorkGroupSizes;
843   }
844 
845   /// \returns Default/requested minimum flat work group size for this function.
846   unsigned getMinFlatWorkGroupSize() const {
847     return FlatWorkGroupSizes.first;
848   }
849 
850   /// \returns Default/requested maximum flat work group size for this function.
851   unsigned getMaxFlatWorkGroupSize() const {
852     return FlatWorkGroupSizes.second;
853   }
854 
855   /// \returns A pair of default/requested minimum/maximum number of waves per
856   /// execution unit.
857   std::pair<unsigned, unsigned> getWavesPerEU() const {
858     return WavesPerEU;
859   }
860 
861   /// \returns Default/requested minimum number of waves per execution unit.
862   unsigned getMinWavesPerEU() const {
863     return WavesPerEU.first;
864   }
865 
866   /// \returns Default/requested maximum number of waves per execution unit.
867   unsigned getMaxWavesPerEU() const {
868     return WavesPerEU.second;
869   }
870 
871   /// \returns SGPR used for \p Dim's work group ID.
872   Register getWorkGroupIDSGPR(unsigned Dim) const {
873     switch (Dim) {
874     case 0:
875       assert(hasWorkGroupIDX());
876       return ArgInfo.WorkGroupIDX.getRegister();
877     case 1:
878       assert(hasWorkGroupIDY());
879       return ArgInfo.WorkGroupIDY.getRegister();
880     case 2:
881       assert(hasWorkGroupIDZ());
882       return ArgInfo.WorkGroupIDZ.getRegister();
883     }
884     llvm_unreachable("unexpected dimension");
885   }
886 
887   unsigned getLDSWaveSpillSize() const {
888     return LDSWaveSpillSize;
889   }
890 
891   const AMDGPUBufferPseudoSourceValue *getBufferPSV(const SIInstrInfo &TII,
892                                                     const Value *BufferRsrc) {
893     assert(BufferRsrc);
894     auto PSV = BufferPSVs.try_emplace(
895       BufferRsrc,
896       std::make_unique<AMDGPUBufferPseudoSourceValue>(TII));
897     return PSV.first->second.get();
898   }
899 
900   const AMDGPUImagePseudoSourceValue *getImagePSV(const SIInstrInfo &TII,
901                                                   const Value *ImgRsrc) {
902     assert(ImgRsrc);
903     auto PSV = ImagePSVs.try_emplace(
904       ImgRsrc,
905       std::make_unique<AMDGPUImagePseudoSourceValue>(TII));
906     return PSV.first->second.get();
907   }
908 
909   const AMDGPUGWSResourcePseudoSourceValue *getGWSPSV(const SIInstrInfo &TII) {
910     if (!GWSResourcePSV) {
911       GWSResourcePSV =
912           std::make_unique<AMDGPUGWSResourcePseudoSourceValue>(TII);
913     }
914 
915     return GWSResourcePSV.get();
916   }
917 
918   unsigned getOccupancy() const {
919     return Occupancy;
920   }
921 
922   unsigned getMinAllowedOccupancy() const {
923     if (!isMemoryBound() && !needsWaveLimiter())
924       return Occupancy;
925     return (Occupancy < 4) ? Occupancy : 4;
926   }
927 
928   void limitOccupancy(const MachineFunction &MF);
929 
930   void limitOccupancy(unsigned Limit) {
931     if (Occupancy > Limit)
932       Occupancy = Limit;
933   }
934 
935   void increaseOccupancy(const MachineFunction &MF, unsigned Limit) {
936     if (Occupancy < Limit)
937       Occupancy = Limit;
938     limitOccupancy(MF);
939   }
940 };
941 
942 } // end namespace llvm
943 
944 #endif // LLVM_LIB_TARGET_AMDGPU_SIMACHINEFUNCTIONINFO_H
945