1 //==- SIMachineFunctionInfo.h - SIMachineFunctionInfo interface --*- C++ -*-==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_AMDGPU_SIMACHINEFUNCTIONINFO_H
14 #define LLVM_LIB_TARGET_AMDGPU_SIMACHINEFUNCTIONINFO_H
15 
16 #include "AMDGPUArgumentUsageInfo.h"
17 #include "AMDGPUMachineFunction.h"
18 #include "AMDGPUTargetMachine.h"
19 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
20 #include "SIInstrInfo.h"
21 #include "llvm/ADT/SetVector.h"
22 #include "llvm/CodeGen/MIRYamlMapping.h"
23 #include "llvm/CodeGen/PseudoSourceValue.h"
24 #include "llvm/Support/raw_ostream.h"
25 
26 namespace llvm {
27 
28 class MachineFrameInfo;
29 class MachineFunction;
30 class SIMachineFunctionInfo;
31 class SIRegisterInfo;
32 class TargetRegisterClass;
33 
34 class AMDGPUPseudoSourceValue : public PseudoSourceValue {
35 public:
36   enum AMDGPUPSVKind : unsigned {
37     PSVBuffer = PseudoSourceValue::TargetCustom,
38     PSVImage,
39     GWSResource
40   };
41 
42 protected:
43   AMDGPUPseudoSourceValue(unsigned Kind, const AMDGPUTargetMachine &TM)
44       : PseudoSourceValue(Kind, TM) {}
45 
46 public:
47   bool isConstant(const MachineFrameInfo *) const override {
48     // This should probably be true for most images, but we will start by being
49     // conservative.
50     return false;
51   }
52 
53   bool isAliased(const MachineFrameInfo *) const override {
54     return true;
55   }
56 
57   bool mayAlias(const MachineFrameInfo *) const override {
58     return true;
59   }
60 };
61 
62 class AMDGPUBufferPseudoSourceValue final : public AMDGPUPseudoSourceValue {
63 public:
64   explicit AMDGPUBufferPseudoSourceValue(const AMDGPUTargetMachine &TM)
65       : AMDGPUPseudoSourceValue(PSVBuffer, TM) {}
66 
67   static bool classof(const PseudoSourceValue *V) {
68     return V->kind() == PSVBuffer;
69   }
70 
71   void printCustom(raw_ostream &OS) const override { OS << "BufferResource"; }
72 };
73 
74 class AMDGPUImagePseudoSourceValue final : public AMDGPUPseudoSourceValue {
75 public:
76   // TODO: Is the img rsrc useful?
77   explicit AMDGPUImagePseudoSourceValue(const AMDGPUTargetMachine &TM)
78       : AMDGPUPseudoSourceValue(PSVImage, TM) {}
79 
80   static bool classof(const PseudoSourceValue *V) {
81     return V->kind() == PSVImage;
82   }
83 
84   void printCustom(raw_ostream &OS) const override { OS << "ImageResource"; }
85 };
86 
87 class AMDGPUGWSResourcePseudoSourceValue final : public AMDGPUPseudoSourceValue {
88 public:
89   explicit AMDGPUGWSResourcePseudoSourceValue(const AMDGPUTargetMachine &TM)
90       : AMDGPUPseudoSourceValue(GWSResource, TM) {}
91 
92   static bool classof(const PseudoSourceValue *V) {
93     return V->kind() == GWSResource;
94   }
95 
96   // These are inaccessible memory from IR.
97   bool isAliased(const MachineFrameInfo *) const override {
98     return false;
99   }
100 
101   // These are inaccessible memory from IR.
102   bool mayAlias(const MachineFrameInfo *) const override {
103     return false;
104   }
105 
106   void printCustom(raw_ostream &OS) const override {
107     OS << "GWSResource";
108   }
109 };
110 
111 namespace yaml {
112 
113 struct SIArgument {
114   bool IsRegister;
115   union {
116     StringValue RegisterName;
117     unsigned StackOffset;
118   };
119   Optional<unsigned> Mask;
120 
121   // Default constructor, which creates a stack argument.
122   SIArgument() : IsRegister(false), StackOffset(0) {}
123   SIArgument(const SIArgument &Other) {
124     IsRegister = Other.IsRegister;
125     if (IsRegister) {
126       ::new ((void *)std::addressof(RegisterName))
127           StringValue(Other.RegisterName);
128     } else
129       StackOffset = Other.StackOffset;
130     Mask = Other.Mask;
131   }
132   SIArgument &operator=(const SIArgument &Other) {
133     IsRegister = Other.IsRegister;
134     if (IsRegister) {
135       ::new ((void *)std::addressof(RegisterName))
136           StringValue(Other.RegisterName);
137     } else
138       StackOffset = Other.StackOffset;
139     Mask = Other.Mask;
140     return *this;
141   }
142   ~SIArgument() {
143     if (IsRegister)
144       RegisterName.~StringValue();
145   }
146 
147   // Helper to create a register or stack argument.
148   static inline SIArgument createArgument(bool IsReg) {
149     if (IsReg)
150       return SIArgument(IsReg);
151     return SIArgument();
152   }
153 
154 private:
155   // Construct a register argument.
156   SIArgument(bool) : IsRegister(true), RegisterName() {}
157 };
158 
159 template <> struct MappingTraits<SIArgument> {
160   static void mapping(IO &YamlIO, SIArgument &A) {
161     if (YamlIO.outputting()) {
162       if (A.IsRegister)
163         YamlIO.mapRequired("reg", A.RegisterName);
164       else
165         YamlIO.mapRequired("offset", A.StackOffset);
166     } else {
167       auto Keys = YamlIO.keys();
168       if (is_contained(Keys, "reg")) {
169         A = SIArgument::createArgument(true);
170         YamlIO.mapRequired("reg", A.RegisterName);
171       } else if (is_contained(Keys, "offset"))
172         YamlIO.mapRequired("offset", A.StackOffset);
173       else
174         YamlIO.setError("missing required key 'reg' or 'offset'");
175     }
176     YamlIO.mapOptional("mask", A.Mask);
177   }
178   static const bool flow = true;
179 };
180 
181 struct SIArgumentInfo {
182   Optional<SIArgument> PrivateSegmentBuffer;
183   Optional<SIArgument> DispatchPtr;
184   Optional<SIArgument> QueuePtr;
185   Optional<SIArgument> KernargSegmentPtr;
186   Optional<SIArgument> DispatchID;
187   Optional<SIArgument> FlatScratchInit;
188   Optional<SIArgument> PrivateSegmentSize;
189 
190   Optional<SIArgument> WorkGroupIDX;
191   Optional<SIArgument> WorkGroupIDY;
192   Optional<SIArgument> WorkGroupIDZ;
193   Optional<SIArgument> WorkGroupInfo;
194   Optional<SIArgument> PrivateSegmentWaveByteOffset;
195 
196   Optional<SIArgument> ImplicitArgPtr;
197   Optional<SIArgument> ImplicitBufferPtr;
198 
199   Optional<SIArgument> WorkItemIDX;
200   Optional<SIArgument> WorkItemIDY;
201   Optional<SIArgument> WorkItemIDZ;
202 };
203 
204 template <> struct MappingTraits<SIArgumentInfo> {
205   static void mapping(IO &YamlIO, SIArgumentInfo &AI) {
206     YamlIO.mapOptional("privateSegmentBuffer", AI.PrivateSegmentBuffer);
207     YamlIO.mapOptional("dispatchPtr", AI.DispatchPtr);
208     YamlIO.mapOptional("queuePtr", AI.QueuePtr);
209     YamlIO.mapOptional("kernargSegmentPtr", AI.KernargSegmentPtr);
210     YamlIO.mapOptional("dispatchID", AI.DispatchID);
211     YamlIO.mapOptional("flatScratchInit", AI.FlatScratchInit);
212     YamlIO.mapOptional("privateSegmentSize", AI.PrivateSegmentSize);
213 
214     YamlIO.mapOptional("workGroupIDX", AI.WorkGroupIDX);
215     YamlIO.mapOptional("workGroupIDY", AI.WorkGroupIDY);
216     YamlIO.mapOptional("workGroupIDZ", AI.WorkGroupIDZ);
217     YamlIO.mapOptional("workGroupInfo", AI.WorkGroupInfo);
218     YamlIO.mapOptional("privateSegmentWaveByteOffset",
219                        AI.PrivateSegmentWaveByteOffset);
220 
221     YamlIO.mapOptional("implicitArgPtr", AI.ImplicitArgPtr);
222     YamlIO.mapOptional("implicitBufferPtr", AI.ImplicitBufferPtr);
223 
224     YamlIO.mapOptional("workItemIDX", AI.WorkItemIDX);
225     YamlIO.mapOptional("workItemIDY", AI.WorkItemIDY);
226     YamlIO.mapOptional("workItemIDZ", AI.WorkItemIDZ);
227   }
228 };
229 
230 // Default to default mode for default calling convention.
231 struct SIMode {
232   bool IEEE = true;
233   bool DX10Clamp = true;
234   bool FP32InputDenormals = true;
235   bool FP32OutputDenormals = true;
236   bool FP64FP16InputDenormals = true;
237   bool FP64FP16OutputDenormals = true;
238 
239   SIMode() = default;
240 
241   SIMode(const AMDGPU::SIModeRegisterDefaults &Mode) {
242     IEEE = Mode.IEEE;
243     DX10Clamp = Mode.DX10Clamp;
244     FP32InputDenormals = Mode.FP32InputDenormals;
245     FP32OutputDenormals = Mode.FP32OutputDenormals;
246     FP64FP16InputDenormals = Mode.FP64FP16InputDenormals;
247     FP64FP16OutputDenormals = Mode.FP64FP16OutputDenormals;
248   }
249 
250   bool operator ==(const SIMode Other) const {
251     return IEEE == Other.IEEE &&
252            DX10Clamp == Other.DX10Clamp &&
253            FP32InputDenormals == Other.FP32InputDenormals &&
254            FP32OutputDenormals == Other.FP32OutputDenormals &&
255            FP64FP16InputDenormals == Other.FP64FP16InputDenormals &&
256            FP64FP16OutputDenormals == Other.FP64FP16OutputDenormals;
257   }
258 };
259 
260 template <> struct MappingTraits<SIMode> {
261   static void mapping(IO &YamlIO, SIMode &Mode) {
262     YamlIO.mapOptional("ieee", Mode.IEEE, true);
263     YamlIO.mapOptional("dx10-clamp", Mode.DX10Clamp, true);
264     YamlIO.mapOptional("fp32-input-denormals", Mode.FP32InputDenormals, true);
265     YamlIO.mapOptional("fp32-output-denormals", Mode.FP32OutputDenormals, true);
266     YamlIO.mapOptional("fp64-fp16-input-denormals", Mode.FP64FP16InputDenormals, true);
267     YamlIO.mapOptional("fp64-fp16-output-denormals", Mode.FP64FP16OutputDenormals, true);
268   }
269 };
270 
271 struct SIMachineFunctionInfo final : public yaml::MachineFunctionInfo {
272   uint64_t ExplicitKernArgSize = 0;
273   Align MaxKernArgAlign;
274   uint32_t LDSSize = 0;
275   uint32_t GDSSize = 0;
276   Align DynLDSAlign;
277   bool IsEntryFunction = false;
278   bool NoSignedZerosFPMath = false;
279   bool MemoryBound = false;
280   bool WaveLimiter = false;
281   bool HasSpilledSGPRs = false;
282   bool HasSpilledVGPRs = false;
283   uint32_t HighBitsOf32BitAddress = 0;
284 
285   // TODO: 10 may be a better default since it's the maximum.
286   unsigned Occupancy = 0;
287 
288   SmallVector<StringValue> WWMReservedRegs;
289 
290   StringValue ScratchRSrcReg = "$private_rsrc_reg";
291   StringValue FrameOffsetReg = "$fp_reg";
292   StringValue StackPtrOffsetReg = "$sp_reg";
293 
294   unsigned BytesInStackArgArea = 0;
295   bool ReturnsVoid = true;
296 
297   Optional<SIArgumentInfo> ArgInfo;
298   SIMode Mode;
299   Optional<FrameIndex> ScavengeFI;
300   StringValue VGPRForAGPRCopy;
301 
302   SIMachineFunctionInfo() = default;
303   SIMachineFunctionInfo(const llvm::SIMachineFunctionInfo &,
304                         const TargetRegisterInfo &TRI,
305                         const llvm::MachineFunction &MF);
306 
307   void mappingImpl(yaml::IO &YamlIO) override;
308   ~SIMachineFunctionInfo() = default;
309 };
310 
311 template <> struct MappingTraits<SIMachineFunctionInfo> {
312   static void mapping(IO &YamlIO, SIMachineFunctionInfo &MFI) {
313     YamlIO.mapOptional("explicitKernArgSize", MFI.ExplicitKernArgSize,
314                        UINT64_C(0));
315     YamlIO.mapOptional("maxKernArgAlign", MFI.MaxKernArgAlign);
316     YamlIO.mapOptional("ldsSize", MFI.LDSSize, 0u);
317     YamlIO.mapOptional("gdsSize", MFI.GDSSize, 0u);
318     YamlIO.mapOptional("dynLDSAlign", MFI.DynLDSAlign, Align());
319     YamlIO.mapOptional("isEntryFunction", MFI.IsEntryFunction, false);
320     YamlIO.mapOptional("noSignedZerosFPMath", MFI.NoSignedZerosFPMath, false);
321     YamlIO.mapOptional("memoryBound", MFI.MemoryBound, false);
322     YamlIO.mapOptional("waveLimiter", MFI.WaveLimiter, false);
323     YamlIO.mapOptional("hasSpilledSGPRs", MFI.HasSpilledSGPRs, false);
324     YamlIO.mapOptional("hasSpilledVGPRs", MFI.HasSpilledVGPRs, false);
325     YamlIO.mapOptional("scratchRSrcReg", MFI.ScratchRSrcReg,
326                        StringValue("$private_rsrc_reg"));
327     YamlIO.mapOptional("frameOffsetReg", MFI.FrameOffsetReg,
328                        StringValue("$fp_reg"));
329     YamlIO.mapOptional("stackPtrOffsetReg", MFI.StackPtrOffsetReg,
330                        StringValue("$sp_reg"));
331     YamlIO.mapOptional("bytesInStackArgArea", MFI.BytesInStackArgArea, 0u);
332     YamlIO.mapOptional("returnsVoid", MFI.ReturnsVoid, true);
333     YamlIO.mapOptional("argumentInfo", MFI.ArgInfo);
334     YamlIO.mapOptional("mode", MFI.Mode, SIMode());
335     YamlIO.mapOptional("highBitsOf32BitAddress",
336                        MFI.HighBitsOf32BitAddress, 0u);
337     YamlIO.mapOptional("occupancy", MFI.Occupancy, 0);
338     YamlIO.mapOptional("wwmReservedRegs", MFI.WWMReservedRegs);
339     YamlIO.mapOptional("scavengeFI", MFI.ScavengeFI);
340     YamlIO.mapOptional("vgprForAGPRCopy", MFI.VGPRForAGPRCopy,
341                        StringValue()); // Don't print out when it's empty.
342   }
343 };
344 
345 } // end namespace yaml
346 
347 /// This class keeps track of the SPI_SP_INPUT_ADDR config register, which
348 /// tells the hardware which interpolation parameters to load.
349 class SIMachineFunctionInfo final : public AMDGPUMachineFunction {
350   friend class GCNTargetMachine;
351 
352   // Registers that may be reserved for spilling purposes. These may be the same
353   // as the input registers.
354   Register ScratchRSrcReg = AMDGPU::PRIVATE_RSRC_REG;
355 
356   // This is the the unswizzled offset from the current dispatch's scratch wave
357   // base to the beginning of the current function's frame.
358   Register FrameOffsetReg = AMDGPU::FP_REG;
359 
360   // This is an ABI register used in the non-entry calling convention to
361   // communicate the unswizzled offset from the current dispatch's scratch wave
362   // base to the beginning of the new function's frame.
363   Register StackPtrOffsetReg = AMDGPU::SP_REG;
364 
365   AMDGPUFunctionArgInfo ArgInfo;
366 
367   // Graphics info.
368   unsigned PSInputAddr = 0;
369   unsigned PSInputEnable = 0;
370 
371   /// Number of bytes of arguments this function has on the stack. If the callee
372   /// is expected to restore the argument stack this should be a multiple of 16,
373   /// all usable during a tail call.
374   ///
375   /// The alternative would forbid tail call optimisation in some cases: if we
376   /// want to transfer control from a function with 8-bytes of stack-argument
377   /// space to a function with 16-bytes then misalignment of this value would
378   /// make a stack adjustment necessary, which could not be undone by the
379   /// callee.
380   unsigned BytesInStackArgArea = 0;
381 
382   bool ReturnsVoid = true;
383 
384   // A pair of default/requested minimum/maximum flat work group sizes.
385   // Minimum - first, maximum - second.
386   std::pair<unsigned, unsigned> FlatWorkGroupSizes = {0, 0};
387 
388   // A pair of default/requested minimum/maximum number of waves per execution
389   // unit. Minimum - first, maximum - second.
390   std::pair<unsigned, unsigned> WavesPerEU = {0, 0};
391 
392   const AMDGPUBufferPseudoSourceValue BufferPSV;
393   const AMDGPUImagePseudoSourceValue ImagePSV;
394   const AMDGPUGWSResourcePseudoSourceValue GWSResourcePSV;
395 
396 private:
397   unsigned NumUserSGPRs = 0;
398   unsigned NumSystemSGPRs = 0;
399 
400   bool HasSpilledSGPRs = false;
401   bool HasSpilledVGPRs = false;
402   bool HasNonSpillStackObjects = false;
403   bool IsStackRealigned = false;
404 
405   unsigned NumSpilledSGPRs = 0;
406   unsigned NumSpilledVGPRs = 0;
407 
408   // Feature bits required for inputs passed in user SGPRs.
409   bool PrivateSegmentBuffer : 1;
410   bool DispatchPtr : 1;
411   bool QueuePtr : 1;
412   bool KernargSegmentPtr : 1;
413   bool DispatchID : 1;
414   bool FlatScratchInit : 1;
415 
416   // Feature bits required for inputs passed in system SGPRs.
417   bool WorkGroupIDX : 1; // Always initialized.
418   bool WorkGroupIDY : 1;
419   bool WorkGroupIDZ : 1;
420   bool WorkGroupInfo : 1;
421   bool PrivateSegmentWaveByteOffset : 1;
422 
423   bool WorkItemIDX : 1; // Always initialized.
424   bool WorkItemIDY : 1;
425   bool WorkItemIDZ : 1;
426 
427   // Private memory buffer
428   // Compute directly in sgpr[0:1]
429   // Other shaders indirect 64-bits at sgpr[0:1]
430   bool ImplicitBufferPtr : 1;
431 
432   // Pointer to where the ABI inserts special kernel arguments separate from the
433   // user arguments. This is an offset from the KernargSegmentPtr.
434   bool ImplicitArgPtr : 1;
435 
436   bool MayNeedAGPRs : 1;
437 
438   // The hard-wired high half of the address of the global information table
439   // for AMDPAL OS type. 0xffffffff represents no hard-wired high half, since
440   // current hardware only allows a 16 bit value.
441   unsigned GITPtrHigh;
442 
443   unsigned HighBitsOf32BitAddress;
444 
445   // Current recorded maximum possible occupancy.
446   unsigned Occupancy;
447 
448   mutable Optional<bool> UsesAGPRs;
449 
450   MCPhysReg getNextUserSGPR() const;
451 
452   MCPhysReg getNextSystemSGPR() const;
453 
454 public:
455   struct SGPRSpillVGPR {
456     // VGPR used for SGPR spills
457     Register VGPR;
458 
459     // If the VGPR is is used for SGPR spills in a non-entrypoint function, the
460     // stack slot used to save/restore it in the prolog/epilog.
461     Optional<int> FI;
462 
463     SGPRSpillVGPR(Register V, Optional<int> F) : VGPR(V), FI(F) {}
464   };
465 
466   struct VGPRSpillToAGPR {
467     SmallVector<MCPhysReg, 32> Lanes;
468     bool FullyAllocated = false;
469     bool IsDead = false;
470   };
471 
472   // Track VGPRs reserved for WWM.
473   SmallSetVector<Register, 8> WWMReservedRegs;
474 
475   /// Track stack slots used for save/restore of reserved WWM VGPRs in the
476   /// prolog/epilog.
477 
478   /// FIXME: This is temporary state only needed in PrologEpilogInserter, and
479   /// doesn't really belong here. It does not require serialization
480   SmallVector<int, 8> WWMReservedFrameIndexes;
481 
482   void allocateWWMReservedSpillSlots(MachineFrameInfo &MFI,
483                                      const SIRegisterInfo &TRI);
484 
485   auto wwmAllocation() const {
486     assert(WWMReservedRegs.size() == WWMReservedFrameIndexes.size());
487     return zip(WWMReservedRegs, WWMReservedFrameIndexes);
488   }
489 
490 private:
491   // Track VGPR + wave index for each subregister of the SGPR spilled to
492   // frameindex key.
493   DenseMap<int, std::vector<SIRegisterInfo::SpilledReg>> SGPRToVGPRSpills;
494   unsigned NumVGPRSpillLanes = 0;
495   SmallVector<SGPRSpillVGPR, 2> SpillVGPRs;
496 
497   DenseMap<int, VGPRSpillToAGPR> VGPRToAGPRSpills;
498 
499   // AGPRs used for VGPR spills.
500   SmallVector<MCPhysReg, 32> SpillAGPR;
501 
502   // VGPRs used for AGPR spills.
503   SmallVector<MCPhysReg, 32> SpillVGPR;
504 
505   // Emergency stack slot. Sometimes, we create this before finalizing the stack
506   // frame, so save it here and add it to the RegScavenger later.
507   Optional<int> ScavengeFI;
508 
509 private:
510   Register VGPRForAGPRCopy;
511 
512 public:
513   Register getVGPRForAGPRCopy() const {
514     return VGPRForAGPRCopy;
515   }
516 
517   void setVGPRForAGPRCopy(Register NewVGPRForAGPRCopy) {
518     VGPRForAGPRCopy = NewVGPRForAGPRCopy;
519   }
520 
521 public: // FIXME
522   /// If this is set, an SGPR used for save/restore of the register used for the
523   /// frame pointer.
524   Register SGPRForFPSaveRestoreCopy;
525   Optional<int> FramePointerSaveIndex;
526 
527   /// If this is set, an SGPR used for save/restore of the register used for the
528   /// base pointer.
529   Register SGPRForBPSaveRestoreCopy;
530   Optional<int> BasePointerSaveIndex;
531 
532   bool isCalleeSavedReg(const MCPhysReg *CSRegs, MCPhysReg Reg);
533 
534 public:
535   SIMachineFunctionInfo(const MachineFunction &MF);
536   SIMachineFunctionInfo(const SIMachineFunctionInfo &MFI) = default;
537 
538   MachineFunctionInfo *
539   clone(BumpPtrAllocator &Allocator, MachineFunction &DestMF,
540         const DenseMap<MachineBasicBlock *, MachineBasicBlock *> &Src2DstMBB)
541       const override;
542 
543   bool initializeBaseYamlFields(const yaml::SIMachineFunctionInfo &YamlMFI,
544                                 const MachineFunction &MF,
545                                 PerFunctionMIParsingState &PFS,
546                                 SMDiagnostic &Error, SMRange &SourceRange);
547 
548   void reserveWWMRegister(Register Reg) {
549     WWMReservedRegs.insert(Reg);
550   }
551 
552   ArrayRef<SIRegisterInfo::SpilledReg>
553   getSGPRToVGPRSpills(int FrameIndex) const {
554     auto I = SGPRToVGPRSpills.find(FrameIndex);
555     return (I == SGPRToVGPRSpills.end())
556                ? ArrayRef<SIRegisterInfo::SpilledReg>()
557                : makeArrayRef(I->second);
558   }
559 
560   ArrayRef<SGPRSpillVGPR> getSGPRSpillVGPRs() const { return SpillVGPRs; }
561 
562   ArrayRef<MCPhysReg> getAGPRSpillVGPRs() const {
563     return SpillAGPR;
564   }
565 
566   ArrayRef<MCPhysReg> getVGPRSpillAGPRs() const {
567     return SpillVGPR;
568   }
569 
570   MCPhysReg getVGPRToAGPRSpill(int FrameIndex, unsigned Lane) const {
571     auto I = VGPRToAGPRSpills.find(FrameIndex);
572     return (I == VGPRToAGPRSpills.end()) ? (MCPhysReg)AMDGPU::NoRegister
573                                          : I->second.Lanes[Lane];
574   }
575 
576   void setVGPRToAGPRSpillDead(int FrameIndex) {
577     auto I = VGPRToAGPRSpills.find(FrameIndex);
578     if (I != VGPRToAGPRSpills.end())
579       I->second.IsDead = true;
580   }
581 
582   bool haveFreeLanesForSGPRSpill(const MachineFunction &MF,
583                                  unsigned NumLane) const;
584   bool allocateSGPRSpillToVGPR(MachineFunction &MF, int FI);
585   bool allocateVGPRSpillToAGPR(MachineFunction &MF, int FI, bool isAGPRtoVGPR);
586 
587   /// If \p ResetSGPRSpillStackIDs is true, reset the stack ID from sgpr-spill
588   /// to the default stack.
589   bool removeDeadFrameIndices(MachineFrameInfo &MFI,
590                               bool ResetSGPRSpillStackIDs);
591 
592   int getScavengeFI(MachineFrameInfo &MFI, const SIRegisterInfo &TRI);
593   Optional<int> getOptionalScavengeFI() const { return ScavengeFI; }
594 
595   unsigned getBytesInStackArgArea() const {
596     return BytesInStackArgArea;
597   }
598 
599   void setBytesInStackArgArea(unsigned Bytes) {
600     BytesInStackArgArea = Bytes;
601   }
602 
603   // Add user SGPRs.
604   Register addPrivateSegmentBuffer(const SIRegisterInfo &TRI);
605   Register addDispatchPtr(const SIRegisterInfo &TRI);
606   Register addQueuePtr(const SIRegisterInfo &TRI);
607   Register addKernargSegmentPtr(const SIRegisterInfo &TRI);
608   Register addDispatchID(const SIRegisterInfo &TRI);
609   Register addFlatScratchInit(const SIRegisterInfo &TRI);
610   Register addImplicitBufferPtr(const SIRegisterInfo &TRI);
611 
612   /// Increment user SGPRs used for padding the argument list only.
613   Register addReservedUserSGPR() {
614     Register Next = getNextUserSGPR();
615     ++NumUserSGPRs;
616     return Next;
617   }
618 
619   // Add system SGPRs.
620   Register addWorkGroupIDX() {
621     ArgInfo.WorkGroupIDX = ArgDescriptor::createRegister(getNextSystemSGPR());
622     NumSystemSGPRs += 1;
623     return ArgInfo.WorkGroupIDX.getRegister();
624   }
625 
626   Register addWorkGroupIDY() {
627     ArgInfo.WorkGroupIDY = ArgDescriptor::createRegister(getNextSystemSGPR());
628     NumSystemSGPRs += 1;
629     return ArgInfo.WorkGroupIDY.getRegister();
630   }
631 
632   Register addWorkGroupIDZ() {
633     ArgInfo.WorkGroupIDZ = ArgDescriptor::createRegister(getNextSystemSGPR());
634     NumSystemSGPRs += 1;
635     return ArgInfo.WorkGroupIDZ.getRegister();
636   }
637 
638   Register addWorkGroupInfo() {
639     ArgInfo.WorkGroupInfo = ArgDescriptor::createRegister(getNextSystemSGPR());
640     NumSystemSGPRs += 1;
641     return ArgInfo.WorkGroupInfo.getRegister();
642   }
643 
644   // Add special VGPR inputs
645   void setWorkItemIDX(ArgDescriptor Arg) {
646     ArgInfo.WorkItemIDX = Arg;
647   }
648 
649   void setWorkItemIDY(ArgDescriptor Arg) {
650     ArgInfo.WorkItemIDY = Arg;
651   }
652 
653   void setWorkItemIDZ(ArgDescriptor Arg) {
654     ArgInfo.WorkItemIDZ = Arg;
655   }
656 
657   Register addPrivateSegmentWaveByteOffset() {
658     ArgInfo.PrivateSegmentWaveByteOffset
659       = ArgDescriptor::createRegister(getNextSystemSGPR());
660     NumSystemSGPRs += 1;
661     return ArgInfo.PrivateSegmentWaveByteOffset.getRegister();
662   }
663 
664   void setPrivateSegmentWaveByteOffset(Register Reg) {
665     ArgInfo.PrivateSegmentWaveByteOffset = ArgDescriptor::createRegister(Reg);
666   }
667 
668   bool hasPrivateSegmentBuffer() const {
669     return PrivateSegmentBuffer;
670   }
671 
672   bool hasDispatchPtr() const {
673     return DispatchPtr;
674   }
675 
676   bool hasQueuePtr() const {
677     return QueuePtr;
678   }
679 
680   bool hasKernargSegmentPtr() const {
681     return KernargSegmentPtr;
682   }
683 
684   bool hasDispatchID() const {
685     return DispatchID;
686   }
687 
688   bool hasFlatScratchInit() const {
689     return FlatScratchInit;
690   }
691 
692   bool hasWorkGroupIDX() const {
693     return WorkGroupIDX;
694   }
695 
696   bool hasWorkGroupIDY() const {
697     return WorkGroupIDY;
698   }
699 
700   bool hasWorkGroupIDZ() const {
701     return WorkGroupIDZ;
702   }
703 
704   bool hasWorkGroupInfo() const {
705     return WorkGroupInfo;
706   }
707 
708   bool hasPrivateSegmentWaveByteOffset() const {
709     return PrivateSegmentWaveByteOffset;
710   }
711 
712   bool hasWorkItemIDX() const {
713     return WorkItemIDX;
714   }
715 
716   bool hasWorkItemIDY() const {
717     return WorkItemIDY;
718   }
719 
720   bool hasWorkItemIDZ() const {
721     return WorkItemIDZ;
722   }
723 
724   bool hasImplicitArgPtr() const {
725     return ImplicitArgPtr;
726   }
727 
728   bool hasImplicitBufferPtr() const {
729     return ImplicitBufferPtr;
730   }
731 
732   AMDGPUFunctionArgInfo &getArgInfo() {
733     return ArgInfo;
734   }
735 
736   const AMDGPUFunctionArgInfo &getArgInfo() const {
737     return ArgInfo;
738   }
739 
740   std::tuple<const ArgDescriptor *, const TargetRegisterClass *, LLT>
741   getPreloadedValue(AMDGPUFunctionArgInfo::PreloadedValue Value) const {
742     return ArgInfo.getPreloadedValue(Value);
743   }
744 
745   MCRegister getPreloadedReg(AMDGPUFunctionArgInfo::PreloadedValue Value) const {
746     auto Arg = std::get<0>(ArgInfo.getPreloadedValue(Value));
747     return Arg ? Arg->getRegister() : MCRegister();
748   }
749 
750   unsigned getGITPtrHigh() const {
751     return GITPtrHigh;
752   }
753 
754   Register getGITPtrLoReg(const MachineFunction &MF) const;
755 
756   uint32_t get32BitAddressHighBits() const {
757     return HighBitsOf32BitAddress;
758   }
759 
760   unsigned getNumUserSGPRs() const {
761     return NumUserSGPRs;
762   }
763 
764   unsigned getNumPreloadedSGPRs() const {
765     return NumUserSGPRs + NumSystemSGPRs;
766   }
767 
768   Register getPrivateSegmentWaveByteOffsetSystemSGPR() const {
769     return ArgInfo.PrivateSegmentWaveByteOffset.getRegister();
770   }
771 
772   /// Returns the physical register reserved for use as the resource
773   /// descriptor for scratch accesses.
774   Register getScratchRSrcReg() const {
775     return ScratchRSrcReg;
776   }
777 
778   void setScratchRSrcReg(Register Reg) {
779     assert(Reg != 0 && "Should never be unset");
780     ScratchRSrcReg = Reg;
781   }
782 
783   Register getFrameOffsetReg() const {
784     return FrameOffsetReg;
785   }
786 
787   void setFrameOffsetReg(Register Reg) {
788     assert(Reg != 0 && "Should never be unset");
789     FrameOffsetReg = Reg;
790   }
791 
792   void setStackPtrOffsetReg(Register Reg) {
793     assert(Reg != 0 && "Should never be unset");
794     StackPtrOffsetReg = Reg;
795   }
796 
797   // Note the unset value for this is AMDGPU::SP_REG rather than
798   // NoRegister. This is mostly a workaround for MIR tests where state that
799   // can't be directly computed from the function is not preserved in serialized
800   // MIR.
801   Register getStackPtrOffsetReg() const {
802     return StackPtrOffsetReg;
803   }
804 
805   Register getQueuePtrUserSGPR() const {
806     return ArgInfo.QueuePtr.getRegister();
807   }
808 
809   Register getImplicitBufferPtrUserSGPR() const {
810     return ArgInfo.ImplicitBufferPtr.getRegister();
811   }
812 
813   bool hasSpilledSGPRs() const {
814     return HasSpilledSGPRs;
815   }
816 
817   void setHasSpilledSGPRs(bool Spill = true) {
818     HasSpilledSGPRs = Spill;
819   }
820 
821   bool hasSpilledVGPRs() const {
822     return HasSpilledVGPRs;
823   }
824 
825   void setHasSpilledVGPRs(bool Spill = true) {
826     HasSpilledVGPRs = Spill;
827   }
828 
829   bool hasNonSpillStackObjects() const {
830     return HasNonSpillStackObjects;
831   }
832 
833   void setHasNonSpillStackObjects(bool StackObject = true) {
834     HasNonSpillStackObjects = StackObject;
835   }
836 
837   bool isStackRealigned() const {
838     return IsStackRealigned;
839   }
840 
841   void setIsStackRealigned(bool Realigned = true) {
842     IsStackRealigned = Realigned;
843   }
844 
845   unsigned getNumSpilledSGPRs() const {
846     return NumSpilledSGPRs;
847   }
848 
849   unsigned getNumSpilledVGPRs() const {
850     return NumSpilledVGPRs;
851   }
852 
853   void addToSpilledSGPRs(unsigned num) {
854     NumSpilledSGPRs += num;
855   }
856 
857   void addToSpilledVGPRs(unsigned num) {
858     NumSpilledVGPRs += num;
859   }
860 
861   unsigned getPSInputAddr() const {
862     return PSInputAddr;
863   }
864 
865   unsigned getPSInputEnable() const {
866     return PSInputEnable;
867   }
868 
869   bool isPSInputAllocated(unsigned Index) const {
870     return PSInputAddr & (1 << Index);
871   }
872 
873   void markPSInputAllocated(unsigned Index) {
874     PSInputAddr |= 1 << Index;
875   }
876 
877   void markPSInputEnabled(unsigned Index) {
878     PSInputEnable |= 1 << Index;
879   }
880 
881   bool returnsVoid() const {
882     return ReturnsVoid;
883   }
884 
885   void setIfReturnsVoid(bool Value) {
886     ReturnsVoid = Value;
887   }
888 
889   /// \returns A pair of default/requested minimum/maximum flat work group sizes
890   /// for this function.
891   std::pair<unsigned, unsigned> getFlatWorkGroupSizes() const {
892     return FlatWorkGroupSizes;
893   }
894 
895   /// \returns Default/requested minimum flat work group size for this function.
896   unsigned getMinFlatWorkGroupSize() const {
897     return FlatWorkGroupSizes.first;
898   }
899 
900   /// \returns Default/requested maximum flat work group size for this function.
901   unsigned getMaxFlatWorkGroupSize() const {
902     return FlatWorkGroupSizes.second;
903   }
904 
905   /// \returns A pair of default/requested minimum/maximum number of waves per
906   /// execution unit.
907   std::pair<unsigned, unsigned> getWavesPerEU() const {
908     return WavesPerEU;
909   }
910 
911   /// \returns Default/requested minimum number of waves per execution unit.
912   unsigned getMinWavesPerEU() const {
913     return WavesPerEU.first;
914   }
915 
916   /// \returns Default/requested maximum number of waves per execution unit.
917   unsigned getMaxWavesPerEU() const {
918     return WavesPerEU.second;
919   }
920 
921   /// \returns SGPR used for \p Dim's work group ID.
922   Register getWorkGroupIDSGPR(unsigned Dim) const {
923     switch (Dim) {
924     case 0:
925       assert(hasWorkGroupIDX());
926       return ArgInfo.WorkGroupIDX.getRegister();
927     case 1:
928       assert(hasWorkGroupIDY());
929       return ArgInfo.WorkGroupIDY.getRegister();
930     case 2:
931       assert(hasWorkGroupIDZ());
932       return ArgInfo.WorkGroupIDZ.getRegister();
933     }
934     llvm_unreachable("unexpected dimension");
935   }
936 
937   const AMDGPUBufferPseudoSourceValue *
938   getBufferPSV(const AMDGPUTargetMachine &TM) {
939     return &BufferPSV;
940   }
941 
942   const AMDGPUImagePseudoSourceValue *
943   getImagePSV(const AMDGPUTargetMachine &TM) {
944     return &ImagePSV;
945   }
946 
947   const AMDGPUGWSResourcePseudoSourceValue *
948   getGWSPSV(const AMDGPUTargetMachine &TM) {
949     return &GWSResourcePSV;
950   }
951 
952   unsigned getOccupancy() const {
953     return Occupancy;
954   }
955 
956   unsigned getMinAllowedOccupancy() const {
957     if (!isMemoryBound() && !needsWaveLimiter())
958       return Occupancy;
959     return (Occupancy < 4) ? Occupancy : 4;
960   }
961 
962   void limitOccupancy(const MachineFunction &MF);
963 
964   void limitOccupancy(unsigned Limit) {
965     if (Occupancy > Limit)
966       Occupancy = Limit;
967   }
968 
969   void increaseOccupancy(const MachineFunction &MF, unsigned Limit) {
970     if (Occupancy < Limit)
971       Occupancy = Limit;
972     limitOccupancy(MF);
973   }
974 
975   bool mayNeedAGPRs() const {
976     return MayNeedAGPRs;
977   }
978 
979   // \returns true if a function has a use of AGPRs via inline asm or
980   // has a call which may use it.
981   bool mayUseAGPRs(const MachineFunction &MF) const;
982 
983   // \returns true if a function needs or may need AGPRs.
984   bool usesAGPRs(const MachineFunction &MF) const;
985 };
986 
987 } // end namespace llvm
988 
989 #endif // LLVM_LIB_TARGET_AMDGPU_SIMACHINEFUNCTIONINFO_H
990