1 //===- SIMachineFunctionInfo.h - SIMachineFunctionInfo interface -*- C++ -*-==//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 //
12 //===----------------------------------------------------------------------===//
13 
14 
15 #ifndef LLVM_LIB_TARGET_R600_SIMACHINEFUNCTIONINFO_H
16 #define LLVM_LIB_TARGET_R600_SIMACHINEFUNCTIONINFO_H
17 
18 #include "AMDGPUMachineFunction.h"
19 #include "SIRegisterInfo.h"
20 #include <map>
21 
22 namespace llvm {
23 
24 class MachineRegisterInfo;
25 
26 /// This class keeps track of the SPI_SP_INPUT_ADDR config register, which
27 /// tells the hardware which interpolation parameters to load.
28 class SIMachineFunctionInfo : public AMDGPUMachineFunction {
29   void anchor() override;
30 
31   unsigned TIDReg;
32   bool HasSpilledSGPRs;
33   bool HasSpilledVGPRs;
34 
35 public:
36 
37   struct SpilledReg {
38     unsigned VGPR;
39     int Lane;
40     SpilledReg(unsigned R, int L) : VGPR (R), Lane (L) { }
41     SpilledReg() : VGPR(0), Lane(-1) { }
42     bool hasLane() { return Lane != -1;}
43   };
44 
45   // SIMachineFunctionInfo definition
46 
47   SIMachineFunctionInfo(const MachineFunction &MF);
48   SpilledReg getSpilledReg(MachineFunction *MF, unsigned FrameIndex,
49                            unsigned SubIdx);
50   unsigned PSInputAddr;
51   unsigned NumUserSGPRs;
52   std::map<unsigned, unsigned> LaneVGPRs;
53   unsigned LDSWaveSpillSize;
54   unsigned ScratchOffsetReg;
55   bool hasCalculatedTID() const { return TIDReg != AMDGPU::NoRegister; };
56   unsigned getTIDReg() const { return TIDReg; };
57   void setTIDReg(unsigned Reg) { TIDReg = Reg; }
58 
59   bool hasSpilledSGPRs() const {
60     return HasSpilledSGPRs;
61   }
62 
63   void setHasSpilledSGPRs(bool Spill = true) {
64     HasSpilledSGPRs = Spill;
65   }
66 
67   bool hasSpilledVGPRs() const {
68     return HasSpilledVGPRs;
69   }
70 
71   void setHasSpilledVGPRs(bool Spill = true) {
72     HasSpilledVGPRs = Spill;
73   }
74 
75   unsigned getMaximumWorkGroupSize(const MachineFunction &MF) const;
76 };
77 
78 } // End namespace llvm
79 
80 
81 #endif
82