1 //==- SIMachineFunctionInfo.h - SIMachineFunctionInfo interface --*- C++ -*-==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_AMDGPU_SIMACHINEFUNCTIONINFO_H
14 #define LLVM_LIB_TARGET_AMDGPU_SIMACHINEFUNCTIONINFO_H
15 
16 #include "AMDGPUArgumentUsageInfo.h"
17 #include "AMDGPUMachineFunction.h"
18 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
19 #include "SIInstrInfo.h"
20 #include "SIRegisterInfo.h"
21 #include "llvm/ADT/ArrayRef.h"
22 #include "llvm/ADT/DenseMap.h"
23 #include "llvm/ADT/Optional.h"
24 #include "llvm/ADT/STLExtras.h"
25 #include "llvm/ADT/SmallVector.h"
26 #include "llvm/ADT/SparseBitVector.h"
27 #include "llvm/CodeGen/MIRYamlMapping.h"
28 #include "llvm/CodeGen/PseudoSourceValue.h"
29 #include "llvm/CodeGen/TargetInstrInfo.h"
30 #include "llvm/MC/MCRegisterInfo.h"
31 #include "llvm/Support/ErrorHandling.h"
32 #include <array>
33 #include <cassert>
34 #include <utility>
35 #include <vector>
36 
37 namespace llvm {
38 
39 class MachineFrameInfo;
40 class MachineFunction;
41 class TargetRegisterClass;
42 
43 class AMDGPUPseudoSourceValue : public PseudoSourceValue {
44 public:
45   enum AMDGPUPSVKind : unsigned {
46     PSVBuffer = PseudoSourceValue::TargetCustom,
47     PSVImage,
48     GWSResource
49   };
50 
51 protected:
52   AMDGPUPseudoSourceValue(unsigned Kind, const TargetInstrInfo &TII)
53       : PseudoSourceValue(Kind, TII) {}
54 
55 public:
56   bool isConstant(const MachineFrameInfo *) const override {
57     // This should probably be true for most images, but we will start by being
58     // conservative.
59     return false;
60   }
61 
62   bool isAliased(const MachineFrameInfo *) const override {
63     return true;
64   }
65 
66   bool mayAlias(const MachineFrameInfo *) const override {
67     return true;
68   }
69 };
70 
71 class AMDGPUBufferPseudoSourceValue final : public AMDGPUPseudoSourceValue {
72 public:
73   explicit AMDGPUBufferPseudoSourceValue(const TargetInstrInfo &TII)
74       : AMDGPUPseudoSourceValue(PSVBuffer, TII) {}
75 
76   static bool classof(const PseudoSourceValue *V) {
77     return V->kind() == PSVBuffer;
78   }
79 };
80 
81 class AMDGPUImagePseudoSourceValue final : public AMDGPUPseudoSourceValue {
82 public:
83   // TODO: Is the img rsrc useful?
84   explicit AMDGPUImagePseudoSourceValue(const TargetInstrInfo &TII)
85       : AMDGPUPseudoSourceValue(PSVImage, TII) {}
86 
87   static bool classof(const PseudoSourceValue *V) {
88     return V->kind() == PSVImage;
89   }
90 };
91 
92 class AMDGPUGWSResourcePseudoSourceValue final : public AMDGPUPseudoSourceValue {
93 public:
94   explicit AMDGPUGWSResourcePseudoSourceValue(const TargetInstrInfo &TII)
95       : AMDGPUPseudoSourceValue(GWSResource, TII) {}
96 
97   static bool classof(const PseudoSourceValue *V) {
98     return V->kind() == GWSResource;
99   }
100 
101   // These are inaccessible memory from IR.
102   bool isAliased(const MachineFrameInfo *) const override {
103     return false;
104   }
105 
106   // These are inaccessible memory from IR.
107   bool mayAlias(const MachineFrameInfo *) const override {
108     return false;
109   }
110 
111   void printCustom(raw_ostream &OS) const override {
112     OS << "GWSResource";
113   }
114 };
115 
116 namespace yaml {
117 
118 struct SIArgument {
119   bool IsRegister;
120   union {
121     StringValue RegisterName;
122     unsigned StackOffset;
123   };
124   Optional<unsigned> Mask;
125 
126   // Default constructor, which creates a stack argument.
127   SIArgument() : IsRegister(false), StackOffset(0) {}
128   SIArgument(const SIArgument &Other) {
129     IsRegister = Other.IsRegister;
130     if (IsRegister) {
131       ::new ((void *)std::addressof(RegisterName))
132           StringValue(Other.RegisterName);
133     } else
134       StackOffset = Other.StackOffset;
135     Mask = Other.Mask;
136   }
137   SIArgument &operator=(const SIArgument &Other) {
138     IsRegister = Other.IsRegister;
139     if (IsRegister) {
140       ::new ((void *)std::addressof(RegisterName))
141           StringValue(Other.RegisterName);
142     } else
143       StackOffset = Other.StackOffset;
144     Mask = Other.Mask;
145     return *this;
146   }
147   ~SIArgument() {
148     if (IsRegister)
149       RegisterName.~StringValue();
150   }
151 
152   // Helper to create a register or stack argument.
153   static inline SIArgument createArgument(bool IsReg) {
154     if (IsReg)
155       return SIArgument(IsReg);
156     return SIArgument();
157   }
158 
159 private:
160   // Construct a register argument.
161   SIArgument(bool) : IsRegister(true), RegisterName() {}
162 };
163 
164 template <> struct MappingTraits<SIArgument> {
165   static void mapping(IO &YamlIO, SIArgument &A) {
166     if (YamlIO.outputting()) {
167       if (A.IsRegister)
168         YamlIO.mapRequired("reg", A.RegisterName);
169       else
170         YamlIO.mapRequired("offset", A.StackOffset);
171     } else {
172       auto Keys = YamlIO.keys();
173       if (is_contained(Keys, "reg")) {
174         A = SIArgument::createArgument(true);
175         YamlIO.mapRequired("reg", A.RegisterName);
176       } else if (is_contained(Keys, "offset"))
177         YamlIO.mapRequired("offset", A.StackOffset);
178       else
179         YamlIO.setError("missing required key 'reg' or 'offset'");
180     }
181     YamlIO.mapOptional("mask", A.Mask);
182   }
183   static const bool flow = true;
184 };
185 
186 struct SIArgumentInfo {
187   Optional<SIArgument> PrivateSegmentBuffer;
188   Optional<SIArgument> DispatchPtr;
189   Optional<SIArgument> QueuePtr;
190   Optional<SIArgument> KernargSegmentPtr;
191   Optional<SIArgument> DispatchID;
192   Optional<SIArgument> FlatScratchInit;
193   Optional<SIArgument> PrivateSegmentSize;
194 
195   Optional<SIArgument> WorkGroupIDX;
196   Optional<SIArgument> WorkGroupIDY;
197   Optional<SIArgument> WorkGroupIDZ;
198   Optional<SIArgument> WorkGroupInfo;
199   Optional<SIArgument> PrivateSegmentWaveByteOffset;
200 
201   Optional<SIArgument> ImplicitArgPtr;
202   Optional<SIArgument> ImplicitBufferPtr;
203 
204   Optional<SIArgument> WorkItemIDX;
205   Optional<SIArgument> WorkItemIDY;
206   Optional<SIArgument> WorkItemIDZ;
207 };
208 
209 template <> struct MappingTraits<SIArgumentInfo> {
210   static void mapping(IO &YamlIO, SIArgumentInfo &AI) {
211     YamlIO.mapOptional("privateSegmentBuffer", AI.PrivateSegmentBuffer);
212     YamlIO.mapOptional("dispatchPtr", AI.DispatchPtr);
213     YamlIO.mapOptional("queuePtr", AI.QueuePtr);
214     YamlIO.mapOptional("kernargSegmentPtr", AI.KernargSegmentPtr);
215     YamlIO.mapOptional("dispatchID", AI.DispatchID);
216     YamlIO.mapOptional("flatScratchInit", AI.FlatScratchInit);
217     YamlIO.mapOptional("privateSegmentSize", AI.PrivateSegmentSize);
218 
219     YamlIO.mapOptional("workGroupIDX", AI.WorkGroupIDX);
220     YamlIO.mapOptional("workGroupIDY", AI.WorkGroupIDY);
221     YamlIO.mapOptional("workGroupIDZ", AI.WorkGroupIDZ);
222     YamlIO.mapOptional("workGroupInfo", AI.WorkGroupInfo);
223     YamlIO.mapOptional("privateSegmentWaveByteOffset",
224                        AI.PrivateSegmentWaveByteOffset);
225 
226     YamlIO.mapOptional("implicitArgPtr", AI.ImplicitArgPtr);
227     YamlIO.mapOptional("implicitBufferPtr", AI.ImplicitBufferPtr);
228 
229     YamlIO.mapOptional("workItemIDX", AI.WorkItemIDX);
230     YamlIO.mapOptional("workItemIDY", AI.WorkItemIDY);
231     YamlIO.mapOptional("workItemIDZ", AI.WorkItemIDZ);
232   }
233 };
234 
235 // Default to default mode for default calling convention.
236 struct SIMode {
237   bool IEEE = true;
238   bool DX10Clamp = true;
239   bool FP32Denormals = true;
240   bool FP64FP16Denormals = true;
241 
242   SIMode() = default;
243 
244   SIMode(const AMDGPU::SIModeRegisterDefaults &Mode) {
245     IEEE = Mode.IEEE;
246     DX10Clamp = Mode.DX10Clamp;
247     FP32Denormals = Mode.FP32Denormals;
248     FP64FP16Denormals = Mode.FP64FP16Denormals;
249   }
250 
251   bool operator ==(const SIMode Other) const {
252     return IEEE == Other.IEEE &&
253            DX10Clamp == Other.DX10Clamp &&
254            FP32Denormals == Other.FP32Denormals &&
255            FP64FP16Denormals == Other.FP64FP16Denormals;
256   }
257 };
258 
259 template <> struct MappingTraits<SIMode> {
260   static void mapping(IO &YamlIO, SIMode &Mode) {
261     YamlIO.mapOptional("ieee", Mode.IEEE, true);
262     YamlIO.mapOptional("dx10-clamp", Mode.DX10Clamp, true);
263     YamlIO.mapOptional("fp32-denormals", Mode.FP32Denormals, true);
264     YamlIO.mapOptional("fp64-fp16-denormals", Mode.FP64FP16Denormals, true);
265   }
266 };
267 
268 struct SIMachineFunctionInfo final : public yaml::MachineFunctionInfo {
269   uint64_t ExplicitKernArgSize = 0;
270   unsigned MaxKernArgAlign = 0;
271   unsigned LDSSize = 0;
272   bool IsEntryFunction = false;
273   bool NoSignedZerosFPMath = false;
274   bool MemoryBound = false;
275   bool WaveLimiter = false;
276   uint32_t HighBitsOf32BitAddress = 0;
277 
278   StringValue ScratchRSrcReg = "$private_rsrc_reg";
279   StringValue ScratchWaveOffsetReg = "$scratch_wave_offset_reg";
280   StringValue FrameOffsetReg = "$fp_reg";
281   StringValue StackPtrOffsetReg = "$sp_reg";
282 
283   Optional<SIArgumentInfo> ArgInfo;
284   SIMode Mode;
285 
286   SIMachineFunctionInfo() = default;
287   SIMachineFunctionInfo(const llvm::SIMachineFunctionInfo &,
288                         const TargetRegisterInfo &TRI);
289 
290   void mappingImpl(yaml::IO &YamlIO) override;
291   ~SIMachineFunctionInfo() = default;
292 };
293 
294 template <> struct MappingTraits<SIMachineFunctionInfo> {
295   static void mapping(IO &YamlIO, SIMachineFunctionInfo &MFI) {
296     YamlIO.mapOptional("explicitKernArgSize", MFI.ExplicitKernArgSize,
297                        UINT64_C(0));
298     YamlIO.mapOptional("maxKernArgAlign", MFI.MaxKernArgAlign, 0u);
299     YamlIO.mapOptional("ldsSize", MFI.LDSSize, 0u);
300     YamlIO.mapOptional("isEntryFunction", MFI.IsEntryFunction, false);
301     YamlIO.mapOptional("noSignedZerosFPMath", MFI.NoSignedZerosFPMath, false);
302     YamlIO.mapOptional("memoryBound", MFI.MemoryBound, false);
303     YamlIO.mapOptional("waveLimiter", MFI.WaveLimiter, false);
304     YamlIO.mapOptional("scratchRSrcReg", MFI.ScratchRSrcReg,
305                        StringValue("$private_rsrc_reg"));
306     YamlIO.mapOptional("scratchWaveOffsetReg", MFI.ScratchWaveOffsetReg,
307                        StringValue("$scratch_wave_offset_reg"));
308     YamlIO.mapOptional("frameOffsetReg", MFI.FrameOffsetReg,
309                        StringValue("$fp_reg"));
310     YamlIO.mapOptional("stackPtrOffsetReg", MFI.StackPtrOffsetReg,
311                        StringValue("$sp_reg"));
312     YamlIO.mapOptional("argumentInfo", MFI.ArgInfo);
313     YamlIO.mapOptional("mode", MFI.Mode, SIMode());
314     YamlIO.mapOptional("highBitsOf32BitAddress",
315                        MFI.HighBitsOf32BitAddress, 0u);
316   }
317 };
318 
319 } // end namespace yaml
320 
321 /// This class keeps track of the SPI_SP_INPUT_ADDR config register, which
322 /// tells the hardware which interpolation parameters to load.
323 class SIMachineFunctionInfo final : public AMDGPUMachineFunction {
324   friend class GCNTargetMachine;
325 
326   unsigned TIDReg = AMDGPU::NoRegister;
327 
328   // Registers that may be reserved for spilling purposes. These may be the same
329   // as the input registers.
330   unsigned ScratchRSrcReg = AMDGPU::PRIVATE_RSRC_REG;
331   unsigned ScratchWaveOffsetReg = AMDGPU::SCRATCH_WAVE_OFFSET_REG;
332 
333   // This is the current function's incremented size from the kernel's scratch
334   // wave offset register. For an entry function, this is exactly the same as
335   // the ScratchWaveOffsetReg.
336   unsigned FrameOffsetReg = AMDGPU::FP_REG;
337 
338   // Top of the stack SGPR offset derived from the ScratchWaveOffsetReg.
339   unsigned StackPtrOffsetReg = AMDGPU::SP_REG;
340 
341   AMDGPUFunctionArgInfo ArgInfo;
342 
343   // State of MODE register, assumed FP mode.
344   AMDGPU::SIModeRegisterDefaults Mode;
345 
346   // Graphics info.
347   unsigned PSInputAddr = 0;
348   unsigned PSInputEnable = 0;
349 
350   /// Number of bytes of arguments this function has on the stack. If the callee
351   /// is expected to restore the argument stack this should be a multiple of 16,
352   /// all usable during a tail call.
353   ///
354   /// The alternative would forbid tail call optimisation in some cases: if we
355   /// want to transfer control from a function with 8-bytes of stack-argument
356   /// space to a function with 16-bytes then misalignment of this value would
357   /// make a stack adjustment necessary, which could not be undone by the
358   /// callee.
359   unsigned BytesInStackArgArea = 0;
360 
361   bool ReturnsVoid = true;
362 
363   // A pair of default/requested minimum/maximum flat work group sizes.
364   // Minimum - first, maximum - second.
365   std::pair<unsigned, unsigned> FlatWorkGroupSizes = {0, 0};
366 
367   // A pair of default/requested minimum/maximum number of waves per execution
368   // unit. Minimum - first, maximum - second.
369   std::pair<unsigned, unsigned> WavesPerEU = {0, 0};
370 
371   DenseMap<const Value *,
372            std::unique_ptr<const AMDGPUBufferPseudoSourceValue>> BufferPSVs;
373   DenseMap<const Value *,
374            std::unique_ptr<const AMDGPUImagePseudoSourceValue>> ImagePSVs;
375   std::unique_ptr<const AMDGPUGWSResourcePseudoSourceValue> GWSResourcePSV;
376 
377 private:
378   unsigned LDSWaveSpillSize = 0;
379   unsigned NumUserSGPRs = 0;
380   unsigned NumSystemSGPRs = 0;
381 
382   bool HasSpilledSGPRs = false;
383   bool HasSpilledVGPRs = false;
384   bool HasNonSpillStackObjects = false;
385   bool IsStackRealigned = false;
386 
387   unsigned NumSpilledSGPRs = 0;
388   unsigned NumSpilledVGPRs = 0;
389 
390   // Feature bits required for inputs passed in user SGPRs.
391   bool PrivateSegmentBuffer : 1;
392   bool DispatchPtr : 1;
393   bool QueuePtr : 1;
394   bool KernargSegmentPtr : 1;
395   bool DispatchID : 1;
396   bool FlatScratchInit : 1;
397 
398   // Feature bits required for inputs passed in system SGPRs.
399   bool WorkGroupIDX : 1; // Always initialized.
400   bool WorkGroupIDY : 1;
401   bool WorkGroupIDZ : 1;
402   bool WorkGroupInfo : 1;
403   bool PrivateSegmentWaveByteOffset : 1;
404 
405   bool WorkItemIDX : 1; // Always initialized.
406   bool WorkItemIDY : 1;
407   bool WorkItemIDZ : 1;
408 
409   // Private memory buffer
410   // Compute directly in sgpr[0:1]
411   // Other shaders indirect 64-bits at sgpr[0:1]
412   bool ImplicitBufferPtr : 1;
413 
414   // Pointer to where the ABI inserts special kernel arguments separate from the
415   // user arguments. This is an offset from the KernargSegmentPtr.
416   bool ImplicitArgPtr : 1;
417 
418   // The hard-wired high half of the address of the global information table
419   // for AMDPAL OS type. 0xffffffff represents no hard-wired high half, since
420   // current hardware only allows a 16 bit value.
421   unsigned GITPtrHigh;
422 
423   unsigned HighBitsOf32BitAddress;
424   unsigned GDSSize;
425 
426   // Current recorded maximum possible occupancy.
427   unsigned Occupancy;
428 
429   MCPhysReg getNextUserSGPR() const;
430 
431   MCPhysReg getNextSystemSGPR() const;
432 
433 public:
434   struct SpilledReg {
435     unsigned VGPR = 0;
436     int Lane = -1;
437 
438     SpilledReg() = default;
439     SpilledReg(unsigned R, int L) : VGPR (R), Lane (L) {}
440 
441     bool hasLane() { return Lane != -1;}
442     bool hasReg() { return VGPR != 0;}
443   };
444 
445   struct SGPRSpillVGPRCSR {
446     // VGPR used for SGPR spills
447     unsigned VGPR;
448 
449     // If the VGPR is a CSR, the stack slot used to save/restore it in the
450     // prolog/epilog.
451     Optional<int> FI;
452 
453     SGPRSpillVGPRCSR(unsigned V, Optional<int> F) : VGPR(V), FI(F) {}
454   };
455 
456   struct VGPRSpillToAGPR {
457     SmallVector<MCPhysReg, 32> Lanes;
458     bool FullyAllocated = false;
459   };
460 
461   SparseBitVector<> WWMReservedRegs;
462 
463   void ReserveWWMRegister(unsigned reg) { WWMReservedRegs.set(reg); }
464 
465 private:
466   // SGPR->VGPR spilling support.
467   using SpillRegMask = std::pair<unsigned, unsigned>;
468 
469   // Track VGPR + wave index for each subregister of the SGPR spilled to
470   // frameindex key.
471   DenseMap<int, std::vector<SpilledReg>> SGPRToVGPRSpills;
472   unsigned NumVGPRSpillLanes = 0;
473   SmallVector<SGPRSpillVGPRCSR, 2> SpillVGPRs;
474 
475   DenseMap<int, VGPRSpillToAGPR> VGPRToAGPRSpills;
476 
477   // AGPRs used for VGPR spills.
478   SmallVector<MCPhysReg, 32> SpillAGPR;
479 
480   // VGPRs used for AGPR spills.
481   SmallVector<MCPhysReg, 32> SpillVGPR;
482 
483 public: // FIXME
484   /// If this is set, an SGPR used for save/restore of the register used for the
485   /// frame pointer.
486   unsigned SGPRForFPSaveRestoreCopy = 0;
487   Optional<int> FramePointerSaveIndex;
488 
489 public:
490   SIMachineFunctionInfo(const MachineFunction &MF);
491 
492   bool initializeBaseYamlFields(const yaml::SIMachineFunctionInfo &YamlMFI);
493 
494   ArrayRef<SpilledReg> getSGPRToVGPRSpills(int FrameIndex) const {
495     auto I = SGPRToVGPRSpills.find(FrameIndex);
496     return (I == SGPRToVGPRSpills.end()) ?
497       ArrayRef<SpilledReg>() : makeArrayRef(I->second);
498   }
499 
500   ArrayRef<SGPRSpillVGPRCSR> getSGPRSpillVGPRs() const {
501     return SpillVGPRs;
502   }
503 
504   ArrayRef<MCPhysReg> getAGPRSpillVGPRs() const {
505     return SpillAGPR;
506   }
507 
508   ArrayRef<MCPhysReg> getVGPRSpillAGPRs() const {
509     return SpillVGPR;
510   }
511 
512   MCPhysReg getVGPRToAGPRSpill(int FrameIndex, unsigned Lane) const {
513     auto I = VGPRToAGPRSpills.find(FrameIndex);
514     return (I == VGPRToAGPRSpills.end()) ? (MCPhysReg)AMDGPU::NoRegister
515                                          : I->second.Lanes[Lane];
516   }
517 
518   AMDGPU::SIModeRegisterDefaults getMode() const {
519     return Mode;
520   }
521 
522   bool haveFreeLanesForSGPRSpill(const MachineFunction &MF,
523                                  unsigned NumLane) const;
524   bool allocateSGPRSpillToVGPR(MachineFunction &MF, int FI);
525   bool allocateVGPRSpillToAGPR(MachineFunction &MF, int FI, bool isAGPRtoVGPR);
526   void removeDeadFrameIndices(MachineFrameInfo &MFI);
527 
528   bool hasCalculatedTID() const { return TIDReg != 0; };
529   unsigned getTIDReg() const { return TIDReg; };
530   void setTIDReg(unsigned Reg) { TIDReg = Reg; }
531 
532   unsigned getBytesInStackArgArea() const {
533     return BytesInStackArgArea;
534   }
535 
536   void setBytesInStackArgArea(unsigned Bytes) {
537     BytesInStackArgArea = Bytes;
538   }
539 
540   // Add user SGPRs.
541   unsigned addPrivateSegmentBuffer(const SIRegisterInfo &TRI);
542   unsigned addDispatchPtr(const SIRegisterInfo &TRI);
543   unsigned addQueuePtr(const SIRegisterInfo &TRI);
544   unsigned addKernargSegmentPtr(const SIRegisterInfo &TRI);
545   unsigned addDispatchID(const SIRegisterInfo &TRI);
546   unsigned addFlatScratchInit(const SIRegisterInfo &TRI);
547   unsigned addImplicitBufferPtr(const SIRegisterInfo &TRI);
548 
549   // Add system SGPRs.
550   unsigned addWorkGroupIDX() {
551     ArgInfo.WorkGroupIDX = ArgDescriptor::createRegister(getNextSystemSGPR());
552     NumSystemSGPRs += 1;
553     return ArgInfo.WorkGroupIDX.getRegister();
554   }
555 
556   unsigned addWorkGroupIDY() {
557     ArgInfo.WorkGroupIDY = ArgDescriptor::createRegister(getNextSystemSGPR());
558     NumSystemSGPRs += 1;
559     return ArgInfo.WorkGroupIDY.getRegister();
560   }
561 
562   unsigned addWorkGroupIDZ() {
563     ArgInfo.WorkGroupIDZ = ArgDescriptor::createRegister(getNextSystemSGPR());
564     NumSystemSGPRs += 1;
565     return ArgInfo.WorkGroupIDZ.getRegister();
566   }
567 
568   unsigned addWorkGroupInfo() {
569     ArgInfo.WorkGroupInfo = ArgDescriptor::createRegister(getNextSystemSGPR());
570     NumSystemSGPRs += 1;
571     return ArgInfo.WorkGroupInfo.getRegister();
572   }
573 
574   // Add special VGPR inputs
575   void setWorkItemIDX(ArgDescriptor Arg) {
576     ArgInfo.WorkItemIDX = Arg;
577   }
578 
579   void setWorkItemIDY(ArgDescriptor Arg) {
580     ArgInfo.WorkItemIDY = Arg;
581   }
582 
583   void setWorkItemIDZ(ArgDescriptor Arg) {
584     ArgInfo.WorkItemIDZ = Arg;
585   }
586 
587   unsigned addPrivateSegmentWaveByteOffset() {
588     ArgInfo.PrivateSegmentWaveByteOffset
589       = ArgDescriptor::createRegister(getNextSystemSGPR());
590     NumSystemSGPRs += 1;
591     return ArgInfo.PrivateSegmentWaveByteOffset.getRegister();
592   }
593 
594   void setPrivateSegmentWaveByteOffset(unsigned Reg) {
595     ArgInfo.PrivateSegmentWaveByteOffset = ArgDescriptor::createRegister(Reg);
596   }
597 
598   bool hasPrivateSegmentBuffer() const {
599     return PrivateSegmentBuffer;
600   }
601 
602   bool hasDispatchPtr() const {
603     return DispatchPtr;
604   }
605 
606   bool hasQueuePtr() const {
607     return QueuePtr;
608   }
609 
610   bool hasKernargSegmentPtr() const {
611     return KernargSegmentPtr;
612   }
613 
614   bool hasDispatchID() const {
615     return DispatchID;
616   }
617 
618   bool hasFlatScratchInit() const {
619     return FlatScratchInit;
620   }
621 
622   bool hasWorkGroupIDX() const {
623     return WorkGroupIDX;
624   }
625 
626   bool hasWorkGroupIDY() const {
627     return WorkGroupIDY;
628   }
629 
630   bool hasWorkGroupIDZ() const {
631     return WorkGroupIDZ;
632   }
633 
634   bool hasWorkGroupInfo() const {
635     return WorkGroupInfo;
636   }
637 
638   bool hasPrivateSegmentWaveByteOffset() const {
639     return PrivateSegmentWaveByteOffset;
640   }
641 
642   bool hasWorkItemIDX() const {
643     return WorkItemIDX;
644   }
645 
646   bool hasWorkItemIDY() const {
647     return WorkItemIDY;
648   }
649 
650   bool hasWorkItemIDZ() const {
651     return WorkItemIDZ;
652   }
653 
654   bool hasImplicitArgPtr() const {
655     return ImplicitArgPtr;
656   }
657 
658   bool hasImplicitBufferPtr() const {
659     return ImplicitBufferPtr;
660   }
661 
662   AMDGPUFunctionArgInfo &getArgInfo() {
663     return ArgInfo;
664   }
665 
666   const AMDGPUFunctionArgInfo &getArgInfo() const {
667     return ArgInfo;
668   }
669 
670   std::pair<const ArgDescriptor *, const TargetRegisterClass *>
671   getPreloadedValue(AMDGPUFunctionArgInfo::PreloadedValue Value) const {
672     return ArgInfo.getPreloadedValue(Value);
673   }
674 
675   Register getPreloadedReg(AMDGPUFunctionArgInfo::PreloadedValue Value) const {
676     auto Arg = ArgInfo.getPreloadedValue(Value).first;
677     return Arg ? Arg->getRegister() : Register();
678   }
679 
680   unsigned getGITPtrHigh() const {
681     return GITPtrHigh;
682   }
683 
684   uint32_t get32BitAddressHighBits() const {
685     return HighBitsOf32BitAddress;
686   }
687 
688   unsigned getGDSSize() const {
689     return GDSSize;
690   }
691 
692   unsigned getNumUserSGPRs() const {
693     return NumUserSGPRs;
694   }
695 
696   unsigned getNumPreloadedSGPRs() const {
697     return NumUserSGPRs + NumSystemSGPRs;
698   }
699 
700   unsigned getPrivateSegmentWaveByteOffsetSystemSGPR() const {
701     return ArgInfo.PrivateSegmentWaveByteOffset.getRegister();
702   }
703 
704   /// Returns the physical register reserved for use as the resource
705   /// descriptor for scratch accesses.
706   unsigned getScratchRSrcReg() const {
707     return ScratchRSrcReg;
708   }
709 
710   void setScratchRSrcReg(unsigned Reg) {
711     assert(Reg != 0 && "Should never be unset");
712     ScratchRSrcReg = Reg;
713   }
714 
715   unsigned getScratchWaveOffsetReg() const {
716     return ScratchWaveOffsetReg;
717   }
718 
719   unsigned getFrameOffsetReg() const {
720     return FrameOffsetReg;
721   }
722 
723   void setFrameOffsetReg(unsigned Reg) {
724     assert(Reg != 0 && "Should never be unset");
725     FrameOffsetReg = Reg;
726   }
727 
728   void setStackPtrOffsetReg(unsigned Reg) {
729     assert(Reg != 0 && "Should never be unset");
730     StackPtrOffsetReg = Reg;
731   }
732 
733   // Note the unset value for this is AMDGPU::SP_REG rather than
734   // NoRegister. This is mostly a workaround for MIR tests where state that
735   // can't be directly computed from the function is not preserved in serialized
736   // MIR.
737   unsigned getStackPtrOffsetReg() const {
738     return StackPtrOffsetReg;
739   }
740 
741   void setScratchWaveOffsetReg(unsigned Reg) {
742     assert(Reg != 0 && "Should never be unset");
743     ScratchWaveOffsetReg = Reg;
744   }
745 
746   unsigned getQueuePtrUserSGPR() const {
747     return ArgInfo.QueuePtr.getRegister();
748   }
749 
750   unsigned getImplicitBufferPtrUserSGPR() const {
751     return ArgInfo.ImplicitBufferPtr.getRegister();
752   }
753 
754   bool hasSpilledSGPRs() const {
755     return HasSpilledSGPRs;
756   }
757 
758   void setHasSpilledSGPRs(bool Spill = true) {
759     HasSpilledSGPRs = Spill;
760   }
761 
762   bool hasSpilledVGPRs() const {
763     return HasSpilledVGPRs;
764   }
765 
766   void setHasSpilledVGPRs(bool Spill = true) {
767     HasSpilledVGPRs = Spill;
768   }
769 
770   bool hasNonSpillStackObjects() const {
771     return HasNonSpillStackObjects;
772   }
773 
774   void setHasNonSpillStackObjects(bool StackObject = true) {
775     HasNonSpillStackObjects = StackObject;
776   }
777 
778   bool isStackRealigned() const {
779     return IsStackRealigned;
780   }
781 
782   void setIsStackRealigned(bool Realigned = true) {
783     IsStackRealigned = Realigned;
784   }
785 
786   unsigned getNumSpilledSGPRs() const {
787     return NumSpilledSGPRs;
788   }
789 
790   unsigned getNumSpilledVGPRs() const {
791     return NumSpilledVGPRs;
792   }
793 
794   void addToSpilledSGPRs(unsigned num) {
795     NumSpilledSGPRs += num;
796   }
797 
798   void addToSpilledVGPRs(unsigned num) {
799     NumSpilledVGPRs += num;
800   }
801 
802   unsigned getPSInputAddr() const {
803     return PSInputAddr;
804   }
805 
806   unsigned getPSInputEnable() const {
807     return PSInputEnable;
808   }
809 
810   bool isPSInputAllocated(unsigned Index) const {
811     return PSInputAddr & (1 << Index);
812   }
813 
814   void markPSInputAllocated(unsigned Index) {
815     PSInputAddr |= 1 << Index;
816   }
817 
818   void markPSInputEnabled(unsigned Index) {
819     PSInputEnable |= 1 << Index;
820   }
821 
822   bool returnsVoid() const {
823     return ReturnsVoid;
824   }
825 
826   void setIfReturnsVoid(bool Value) {
827     ReturnsVoid = Value;
828   }
829 
830   /// \returns A pair of default/requested minimum/maximum flat work group sizes
831   /// for this function.
832   std::pair<unsigned, unsigned> getFlatWorkGroupSizes() const {
833     return FlatWorkGroupSizes;
834   }
835 
836   /// \returns Default/requested minimum flat work group size for this function.
837   unsigned getMinFlatWorkGroupSize() const {
838     return FlatWorkGroupSizes.first;
839   }
840 
841   /// \returns Default/requested maximum flat work group size for this function.
842   unsigned getMaxFlatWorkGroupSize() const {
843     return FlatWorkGroupSizes.second;
844   }
845 
846   /// \returns A pair of default/requested minimum/maximum number of waves per
847   /// execution unit.
848   std::pair<unsigned, unsigned> getWavesPerEU() const {
849     return WavesPerEU;
850   }
851 
852   /// \returns Default/requested minimum number of waves per execution unit.
853   unsigned getMinWavesPerEU() const {
854     return WavesPerEU.first;
855   }
856 
857   /// \returns Default/requested maximum number of waves per execution unit.
858   unsigned getMaxWavesPerEU() const {
859     return WavesPerEU.second;
860   }
861 
862   /// \returns SGPR used for \p Dim's work group ID.
863   unsigned getWorkGroupIDSGPR(unsigned Dim) const {
864     switch (Dim) {
865     case 0:
866       assert(hasWorkGroupIDX());
867       return ArgInfo.WorkGroupIDX.getRegister();
868     case 1:
869       assert(hasWorkGroupIDY());
870       return ArgInfo.WorkGroupIDY.getRegister();
871     case 2:
872       assert(hasWorkGroupIDZ());
873       return ArgInfo.WorkGroupIDZ.getRegister();
874     }
875     llvm_unreachable("unexpected dimension");
876   }
877 
878   unsigned getLDSWaveSpillSize() const {
879     return LDSWaveSpillSize;
880   }
881 
882   const AMDGPUBufferPseudoSourceValue *getBufferPSV(const SIInstrInfo &TII,
883                                                     const Value *BufferRsrc) {
884     assert(BufferRsrc);
885     auto PSV = BufferPSVs.try_emplace(
886       BufferRsrc,
887       std::make_unique<AMDGPUBufferPseudoSourceValue>(TII));
888     return PSV.first->second.get();
889   }
890 
891   const AMDGPUImagePseudoSourceValue *getImagePSV(const SIInstrInfo &TII,
892                                                   const Value *ImgRsrc) {
893     assert(ImgRsrc);
894     auto PSV = ImagePSVs.try_emplace(
895       ImgRsrc,
896       std::make_unique<AMDGPUImagePseudoSourceValue>(TII));
897     return PSV.first->second.get();
898   }
899 
900   const AMDGPUGWSResourcePseudoSourceValue *getGWSPSV(const SIInstrInfo &TII) {
901     if (!GWSResourcePSV) {
902       GWSResourcePSV =
903           std::make_unique<AMDGPUGWSResourcePseudoSourceValue>(TII);
904     }
905 
906     return GWSResourcePSV.get();
907   }
908 
909   unsigned getOccupancy() const {
910     return Occupancy;
911   }
912 
913   unsigned getMinAllowedOccupancy() const {
914     if (!isMemoryBound() && !needsWaveLimiter())
915       return Occupancy;
916     return (Occupancy < 4) ? Occupancy : 4;
917   }
918 
919   void limitOccupancy(const MachineFunction &MF);
920 
921   void limitOccupancy(unsigned Limit) {
922     if (Occupancy > Limit)
923       Occupancy = Limit;
924   }
925 
926   void increaseOccupancy(const MachineFunction &MF, unsigned Limit) {
927     if (Occupancy < Limit)
928       Occupancy = Limit;
929     limitOccupancy(MF);
930   }
931 };
932 
933 } // end namespace llvm
934 
935 #endif // LLVM_LIB_TARGET_AMDGPU_SIMACHINEFUNCTIONINFO_H
936