1 //==- SIMachineFunctionInfo.h - SIMachineFunctionInfo interface --*- C++ -*-==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_AMDGPU_SIMACHINEFUNCTIONINFO_H
14 #define LLVM_LIB_TARGET_AMDGPU_SIMACHINEFUNCTIONINFO_H
15 
16 #include "AMDGPUArgumentUsageInfo.h"
17 #include "AMDGPUMachineFunction.h"
18 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
19 #include "SIInstrInfo.h"
20 #include "llvm/CodeGen/MIRYamlMapping.h"
21 #include "llvm/CodeGen/PseudoSourceValue.h"
22 #include "llvm/Support/raw_ostream.h"
23 
24 namespace llvm {
25 
26 class MachineFrameInfo;
27 class MachineFunction;
28 class TargetRegisterClass;
29 class SIMachineFunctionInfo;
30 class SIRegisterInfo;
31 
32 class AMDGPUPseudoSourceValue : public PseudoSourceValue {
33 public:
34   enum AMDGPUPSVKind : unsigned {
35     PSVBuffer = PseudoSourceValue::TargetCustom,
36     PSVImage,
37     GWSResource
38   };
39 
40 protected:
41   AMDGPUPseudoSourceValue(unsigned Kind, const TargetInstrInfo &TII)
42       : PseudoSourceValue(Kind, TII) {}
43 
44 public:
45   bool isConstant(const MachineFrameInfo *) const override {
46     // This should probably be true for most images, but we will start by being
47     // conservative.
48     return false;
49   }
50 
51   bool isAliased(const MachineFrameInfo *) const override {
52     return true;
53   }
54 
55   bool mayAlias(const MachineFrameInfo *) const override {
56     return true;
57   }
58 };
59 
60 class AMDGPUBufferPseudoSourceValue final : public AMDGPUPseudoSourceValue {
61 public:
62   explicit AMDGPUBufferPseudoSourceValue(const TargetInstrInfo &TII)
63       : AMDGPUPseudoSourceValue(PSVBuffer, TII) {}
64 
65   static bool classof(const PseudoSourceValue *V) {
66     return V->kind() == PSVBuffer;
67   }
68 
69   void printCustom(raw_ostream &OS) const override { OS << "BufferResource"; }
70 };
71 
72 class AMDGPUImagePseudoSourceValue final : public AMDGPUPseudoSourceValue {
73 public:
74   // TODO: Is the img rsrc useful?
75   explicit AMDGPUImagePseudoSourceValue(const TargetInstrInfo &TII)
76       : AMDGPUPseudoSourceValue(PSVImage, TII) {}
77 
78   static bool classof(const PseudoSourceValue *V) {
79     return V->kind() == PSVImage;
80   }
81 
82   void printCustom(raw_ostream &OS) const override { OS << "ImageResource"; }
83 };
84 
85 class AMDGPUGWSResourcePseudoSourceValue final : public AMDGPUPseudoSourceValue {
86 public:
87   explicit AMDGPUGWSResourcePseudoSourceValue(const TargetInstrInfo &TII)
88       : AMDGPUPseudoSourceValue(GWSResource, TII) {}
89 
90   static bool classof(const PseudoSourceValue *V) {
91     return V->kind() == GWSResource;
92   }
93 
94   // These are inaccessible memory from IR.
95   bool isAliased(const MachineFrameInfo *) const override {
96     return false;
97   }
98 
99   // These are inaccessible memory from IR.
100   bool mayAlias(const MachineFrameInfo *) const override {
101     return false;
102   }
103 
104   void printCustom(raw_ostream &OS) const override {
105     OS << "GWSResource";
106   }
107 };
108 
109 namespace yaml {
110 
111 struct SIArgument {
112   bool IsRegister;
113   union {
114     StringValue RegisterName;
115     unsigned StackOffset;
116   };
117   Optional<unsigned> Mask;
118 
119   // Default constructor, which creates a stack argument.
120   SIArgument() : IsRegister(false), StackOffset(0) {}
121   SIArgument(const SIArgument &Other) {
122     IsRegister = Other.IsRegister;
123     if (IsRegister) {
124       ::new ((void *)std::addressof(RegisterName))
125           StringValue(Other.RegisterName);
126     } else
127       StackOffset = Other.StackOffset;
128     Mask = Other.Mask;
129   }
130   SIArgument &operator=(const SIArgument &Other) {
131     IsRegister = Other.IsRegister;
132     if (IsRegister) {
133       ::new ((void *)std::addressof(RegisterName))
134           StringValue(Other.RegisterName);
135     } else
136       StackOffset = Other.StackOffset;
137     Mask = Other.Mask;
138     return *this;
139   }
140   ~SIArgument() {
141     if (IsRegister)
142       RegisterName.~StringValue();
143   }
144 
145   // Helper to create a register or stack argument.
146   static inline SIArgument createArgument(bool IsReg) {
147     if (IsReg)
148       return SIArgument(IsReg);
149     return SIArgument();
150   }
151 
152 private:
153   // Construct a register argument.
154   SIArgument(bool) : IsRegister(true), RegisterName() {}
155 };
156 
157 template <> struct MappingTraits<SIArgument> {
158   static void mapping(IO &YamlIO, SIArgument &A) {
159     if (YamlIO.outputting()) {
160       if (A.IsRegister)
161         YamlIO.mapRequired("reg", A.RegisterName);
162       else
163         YamlIO.mapRequired("offset", A.StackOffset);
164     } else {
165       auto Keys = YamlIO.keys();
166       if (is_contained(Keys, "reg")) {
167         A = SIArgument::createArgument(true);
168         YamlIO.mapRequired("reg", A.RegisterName);
169       } else if (is_contained(Keys, "offset"))
170         YamlIO.mapRequired("offset", A.StackOffset);
171       else
172         YamlIO.setError("missing required key 'reg' or 'offset'");
173     }
174     YamlIO.mapOptional("mask", A.Mask);
175   }
176   static const bool flow = true;
177 };
178 
179 struct SIArgumentInfo {
180   Optional<SIArgument> PrivateSegmentBuffer;
181   Optional<SIArgument> DispatchPtr;
182   Optional<SIArgument> QueuePtr;
183   Optional<SIArgument> KernargSegmentPtr;
184   Optional<SIArgument> DispatchID;
185   Optional<SIArgument> FlatScratchInit;
186   Optional<SIArgument> PrivateSegmentSize;
187 
188   Optional<SIArgument> WorkGroupIDX;
189   Optional<SIArgument> WorkGroupIDY;
190   Optional<SIArgument> WorkGroupIDZ;
191   Optional<SIArgument> WorkGroupInfo;
192   Optional<SIArgument> PrivateSegmentWaveByteOffset;
193 
194   Optional<SIArgument> ImplicitArgPtr;
195   Optional<SIArgument> ImplicitBufferPtr;
196 
197   Optional<SIArgument> WorkItemIDX;
198   Optional<SIArgument> WorkItemIDY;
199   Optional<SIArgument> WorkItemIDZ;
200 };
201 
202 template <> struct MappingTraits<SIArgumentInfo> {
203   static void mapping(IO &YamlIO, SIArgumentInfo &AI) {
204     YamlIO.mapOptional("privateSegmentBuffer", AI.PrivateSegmentBuffer);
205     YamlIO.mapOptional("dispatchPtr", AI.DispatchPtr);
206     YamlIO.mapOptional("queuePtr", AI.QueuePtr);
207     YamlIO.mapOptional("kernargSegmentPtr", AI.KernargSegmentPtr);
208     YamlIO.mapOptional("dispatchID", AI.DispatchID);
209     YamlIO.mapOptional("flatScratchInit", AI.FlatScratchInit);
210     YamlIO.mapOptional("privateSegmentSize", AI.PrivateSegmentSize);
211 
212     YamlIO.mapOptional("workGroupIDX", AI.WorkGroupIDX);
213     YamlIO.mapOptional("workGroupIDY", AI.WorkGroupIDY);
214     YamlIO.mapOptional("workGroupIDZ", AI.WorkGroupIDZ);
215     YamlIO.mapOptional("workGroupInfo", AI.WorkGroupInfo);
216     YamlIO.mapOptional("privateSegmentWaveByteOffset",
217                        AI.PrivateSegmentWaveByteOffset);
218 
219     YamlIO.mapOptional("implicitArgPtr", AI.ImplicitArgPtr);
220     YamlIO.mapOptional("implicitBufferPtr", AI.ImplicitBufferPtr);
221 
222     YamlIO.mapOptional("workItemIDX", AI.WorkItemIDX);
223     YamlIO.mapOptional("workItemIDY", AI.WorkItemIDY);
224     YamlIO.mapOptional("workItemIDZ", AI.WorkItemIDZ);
225   }
226 };
227 
228 // Default to default mode for default calling convention.
229 struct SIMode {
230   bool IEEE = true;
231   bool DX10Clamp = true;
232   bool FP32InputDenormals = true;
233   bool FP32OutputDenormals = true;
234   bool FP64FP16InputDenormals = true;
235   bool FP64FP16OutputDenormals = true;
236 
237   SIMode() = default;
238 
239   SIMode(const AMDGPU::SIModeRegisterDefaults &Mode) {
240     IEEE = Mode.IEEE;
241     DX10Clamp = Mode.DX10Clamp;
242     FP32InputDenormals = Mode.FP32InputDenormals;
243     FP32OutputDenormals = Mode.FP32OutputDenormals;
244     FP64FP16InputDenormals = Mode.FP64FP16InputDenormals;
245     FP64FP16OutputDenormals = Mode.FP64FP16OutputDenormals;
246   }
247 
248   bool operator ==(const SIMode Other) const {
249     return IEEE == Other.IEEE &&
250            DX10Clamp == Other.DX10Clamp &&
251            FP32InputDenormals == Other.FP32InputDenormals &&
252            FP32OutputDenormals == Other.FP32OutputDenormals &&
253            FP64FP16InputDenormals == Other.FP64FP16InputDenormals &&
254            FP64FP16OutputDenormals == Other.FP64FP16OutputDenormals;
255   }
256 };
257 
258 template <> struct MappingTraits<SIMode> {
259   static void mapping(IO &YamlIO, SIMode &Mode) {
260     YamlIO.mapOptional("ieee", Mode.IEEE, true);
261     YamlIO.mapOptional("dx10-clamp", Mode.DX10Clamp, true);
262     YamlIO.mapOptional("fp32-input-denormals", Mode.FP32InputDenormals, true);
263     YamlIO.mapOptional("fp32-output-denormals", Mode.FP32OutputDenormals, true);
264     YamlIO.mapOptional("fp64-fp16-input-denormals", Mode.FP64FP16InputDenormals, true);
265     YamlIO.mapOptional("fp64-fp16-output-denormals", Mode.FP64FP16OutputDenormals, true);
266   }
267 };
268 
269 struct SIMachineFunctionInfo final : public yaml::MachineFunctionInfo {
270   uint64_t ExplicitKernArgSize = 0;
271   unsigned MaxKernArgAlign = 0;
272   unsigned LDSSize = 0;
273   Align DynLDSAlign;
274   bool IsEntryFunction = false;
275   bool NoSignedZerosFPMath = false;
276   bool MemoryBound = false;
277   bool WaveLimiter = false;
278   bool HasSpilledSGPRs = false;
279   bool HasSpilledVGPRs = false;
280   uint32_t HighBitsOf32BitAddress = 0;
281 
282   // TODO: 10 may be a better default since it's the maximum.
283   unsigned Occupancy = 0;
284 
285   StringValue ScratchRSrcReg = "$private_rsrc_reg";
286   StringValue FrameOffsetReg = "$fp_reg";
287   StringValue StackPtrOffsetReg = "$sp_reg";
288 
289   Optional<SIArgumentInfo> ArgInfo;
290   SIMode Mode;
291 
292   SIMachineFunctionInfo() = default;
293   SIMachineFunctionInfo(const llvm::SIMachineFunctionInfo &,
294                         const TargetRegisterInfo &TRI);
295 
296   void mappingImpl(yaml::IO &YamlIO) override;
297   ~SIMachineFunctionInfo() = default;
298 };
299 
300 template <> struct MappingTraits<SIMachineFunctionInfo> {
301   static void mapping(IO &YamlIO, SIMachineFunctionInfo &MFI) {
302     YamlIO.mapOptional("explicitKernArgSize", MFI.ExplicitKernArgSize,
303                        UINT64_C(0));
304     YamlIO.mapOptional("maxKernArgAlign", MFI.MaxKernArgAlign, 0u);
305     YamlIO.mapOptional("ldsSize", MFI.LDSSize, 0u);
306     YamlIO.mapOptional("dynLDSAlign", MFI.DynLDSAlign, Align());
307     YamlIO.mapOptional("isEntryFunction", MFI.IsEntryFunction, false);
308     YamlIO.mapOptional("noSignedZerosFPMath", MFI.NoSignedZerosFPMath, false);
309     YamlIO.mapOptional("memoryBound", MFI.MemoryBound, false);
310     YamlIO.mapOptional("waveLimiter", MFI.WaveLimiter, false);
311     YamlIO.mapOptional("hasSpilledSGPRs", MFI.HasSpilledSGPRs, false);
312     YamlIO.mapOptional("hasSpilledVGPRs", MFI.HasSpilledVGPRs, false);
313     YamlIO.mapOptional("scratchRSrcReg", MFI.ScratchRSrcReg,
314                        StringValue("$private_rsrc_reg"));
315     YamlIO.mapOptional("frameOffsetReg", MFI.FrameOffsetReg,
316                        StringValue("$fp_reg"));
317     YamlIO.mapOptional("stackPtrOffsetReg", MFI.StackPtrOffsetReg,
318                        StringValue("$sp_reg"));
319     YamlIO.mapOptional("argumentInfo", MFI.ArgInfo);
320     YamlIO.mapOptional("mode", MFI.Mode, SIMode());
321     YamlIO.mapOptional("highBitsOf32BitAddress",
322                        MFI.HighBitsOf32BitAddress, 0u);
323     YamlIO.mapOptional("occupancy", MFI.Occupancy, 0);
324   }
325 };
326 
327 } // end namespace yaml
328 
329 /// This class keeps track of the SPI_SP_INPUT_ADDR config register, which
330 /// tells the hardware which interpolation parameters to load.
331 class SIMachineFunctionInfo final : public AMDGPUMachineFunction {
332   friend class GCNTargetMachine;
333 
334   Register TIDReg = AMDGPU::NoRegister;
335 
336   // Registers that may be reserved for spilling purposes. These may be the same
337   // as the input registers.
338   Register ScratchRSrcReg = AMDGPU::PRIVATE_RSRC_REG;
339 
340   // This is the the unswizzled offset from the current dispatch's scratch wave
341   // base to the beginning of the current function's frame.
342   Register FrameOffsetReg = AMDGPU::FP_REG;
343 
344   // This is an ABI register used in the non-entry calling convention to
345   // communicate the unswizzled offset from the current dispatch's scratch wave
346   // base to the beginning of the new function's frame.
347   Register StackPtrOffsetReg = AMDGPU::SP_REG;
348 
349   AMDGPUFunctionArgInfo ArgInfo;
350 
351   // Graphics info.
352   unsigned PSInputAddr = 0;
353   unsigned PSInputEnable = 0;
354 
355   /// Number of bytes of arguments this function has on the stack. If the callee
356   /// is expected to restore the argument stack this should be a multiple of 16,
357   /// all usable during a tail call.
358   ///
359   /// The alternative would forbid tail call optimisation in some cases: if we
360   /// want to transfer control from a function with 8-bytes of stack-argument
361   /// space to a function with 16-bytes then misalignment of this value would
362   /// make a stack adjustment necessary, which could not be undone by the
363   /// callee.
364   unsigned BytesInStackArgArea = 0;
365 
366   bool ReturnsVoid = true;
367 
368   // A pair of default/requested minimum/maximum flat work group sizes.
369   // Minimum - first, maximum - second.
370   std::pair<unsigned, unsigned> FlatWorkGroupSizes = {0, 0};
371 
372   // A pair of default/requested minimum/maximum number of waves per execution
373   // unit. Minimum - first, maximum - second.
374   std::pair<unsigned, unsigned> WavesPerEU = {0, 0};
375 
376   std::unique_ptr<const AMDGPUBufferPseudoSourceValue> BufferPSV;
377   std::unique_ptr<const AMDGPUImagePseudoSourceValue> ImagePSV;
378   std::unique_ptr<const AMDGPUGWSResourcePseudoSourceValue> GWSResourcePSV;
379 
380 private:
381   unsigned LDSWaveSpillSize = 0;
382   unsigned NumUserSGPRs = 0;
383   unsigned NumSystemSGPRs = 0;
384 
385   bool HasSpilledSGPRs = false;
386   bool HasSpilledVGPRs = false;
387   bool HasNonSpillStackObjects = false;
388   bool IsStackRealigned = false;
389 
390   unsigned NumSpilledSGPRs = 0;
391   unsigned NumSpilledVGPRs = 0;
392 
393   // Feature bits required for inputs passed in user SGPRs.
394   bool PrivateSegmentBuffer : 1;
395   bool DispatchPtr : 1;
396   bool QueuePtr : 1;
397   bool KernargSegmentPtr : 1;
398   bool DispatchID : 1;
399   bool FlatScratchInit : 1;
400 
401   // Feature bits required for inputs passed in system SGPRs.
402   bool WorkGroupIDX : 1; // Always initialized.
403   bool WorkGroupIDY : 1;
404   bool WorkGroupIDZ : 1;
405   bool WorkGroupInfo : 1;
406   bool PrivateSegmentWaveByteOffset : 1;
407 
408   bool WorkItemIDX : 1; // Always initialized.
409   bool WorkItemIDY : 1;
410   bool WorkItemIDZ : 1;
411 
412   // Private memory buffer
413   // Compute directly in sgpr[0:1]
414   // Other shaders indirect 64-bits at sgpr[0:1]
415   bool ImplicitBufferPtr : 1;
416 
417   // Pointer to where the ABI inserts special kernel arguments separate from the
418   // user arguments. This is an offset from the KernargSegmentPtr.
419   bool ImplicitArgPtr : 1;
420 
421   // The hard-wired high half of the address of the global information table
422   // for AMDPAL OS type. 0xffffffff represents no hard-wired high half, since
423   // current hardware only allows a 16 bit value.
424   unsigned GITPtrHigh;
425 
426   unsigned HighBitsOf32BitAddress;
427   unsigned GDSSize;
428 
429   // Current recorded maximum possible occupancy.
430   unsigned Occupancy;
431 
432   MCPhysReg getNextUserSGPR() const;
433 
434   MCPhysReg getNextSystemSGPR() const;
435 
436 public:
437   struct SpilledReg {
438     Register VGPR;
439     int Lane = -1;
440 
441     SpilledReg() = default;
442     SpilledReg(Register R, int L) : VGPR (R), Lane (L) {}
443 
444     bool hasLane() { return Lane != -1;}
445     bool hasReg() { return VGPR != 0;}
446   };
447 
448   struct SGPRSpillVGPR {
449     // VGPR used for SGPR spills
450     Register VGPR;
451 
452     // If the VGPR is is used for SGPR spills in a non-entrypoint function, the
453     // stack slot used to save/restore it in the prolog/epilog.
454     Optional<int> FI;
455 
456     SGPRSpillVGPR(Register V, Optional<int> F) : VGPR(V), FI(F) {}
457   };
458 
459   struct VGPRSpillToAGPR {
460     SmallVector<MCPhysReg, 32> Lanes;
461     bool FullyAllocated = false;
462   };
463 
464   SparseBitVector<> WWMReservedRegs;
465 
466   void ReserveWWMRegister(Register Reg) { WWMReservedRegs.set(Reg); }
467 
468 private:
469   // Track VGPR + wave index for each subregister of the SGPR spilled to
470   // frameindex key.
471   DenseMap<int, std::vector<SpilledReg>> SGPRToVGPRSpills;
472   unsigned NumVGPRSpillLanes = 0;
473   SmallVector<SGPRSpillVGPR, 2> SpillVGPRs;
474 
475   DenseMap<int, VGPRSpillToAGPR> VGPRToAGPRSpills;
476 
477   // AGPRs used for VGPR spills.
478   SmallVector<MCPhysReg, 32> SpillAGPR;
479 
480   // VGPRs used for AGPR spills.
481   SmallVector<MCPhysReg, 32> SpillVGPR;
482 
483 public: // FIXME
484   /// If this is set, an SGPR used for save/restore of the register used for the
485   /// frame pointer.
486   Register SGPRForFPSaveRestoreCopy;
487   Optional<int> FramePointerSaveIndex;
488 
489   /// If this is set, an SGPR used for save/restore of the register used for the
490   /// base pointer.
491   Register SGPRForBPSaveRestoreCopy;
492   Optional<int> BasePointerSaveIndex;
493 
494   Register VGPRReservedForSGPRSpill;
495   bool isCalleeSavedReg(const MCPhysReg *CSRegs, MCPhysReg Reg);
496 
497 public:
498   SIMachineFunctionInfo(const MachineFunction &MF);
499 
500   bool initializeBaseYamlFields(const yaml::SIMachineFunctionInfo &YamlMFI);
501 
502   ArrayRef<SpilledReg> getSGPRToVGPRSpills(int FrameIndex) const {
503     auto I = SGPRToVGPRSpills.find(FrameIndex);
504     return (I == SGPRToVGPRSpills.end()) ?
505       ArrayRef<SpilledReg>() : makeArrayRef(I->second);
506   }
507 
508   ArrayRef<SGPRSpillVGPR> getSGPRSpillVGPRs() const { return SpillVGPRs; }
509 
510   void setSGPRSpillVGPRs(Register NewVGPR, Optional<int> newFI, int Index) {
511     SpillVGPRs[Index].VGPR = NewVGPR;
512     SpillVGPRs[Index].FI = newFI;
513     VGPRReservedForSGPRSpill = NewVGPR;
514   }
515 
516   bool removeVGPRForSGPRSpill(Register ReservedVGPR, MachineFunction &MF);
517 
518   ArrayRef<MCPhysReg> getAGPRSpillVGPRs() const {
519     return SpillAGPR;
520   }
521 
522   ArrayRef<MCPhysReg> getVGPRSpillAGPRs() const {
523     return SpillVGPR;
524   }
525 
526   MCPhysReg getVGPRToAGPRSpill(int FrameIndex, unsigned Lane) const {
527     auto I = VGPRToAGPRSpills.find(FrameIndex);
528     return (I == VGPRToAGPRSpills.end()) ? (MCPhysReg)AMDGPU::NoRegister
529                                          : I->second.Lanes[Lane];
530   }
531 
532   bool haveFreeLanesForSGPRSpill(const MachineFunction &MF,
533                                  unsigned NumLane) const;
534   bool allocateSGPRSpillToVGPR(MachineFunction &MF, int FI);
535   bool reserveVGPRforSGPRSpills(MachineFunction &MF);
536   bool allocateVGPRSpillToAGPR(MachineFunction &MF, int FI, bool isAGPRtoVGPR);
537   void removeDeadFrameIndices(MachineFrameInfo &MFI);
538 
539   bool hasCalculatedTID() const { return TIDReg != 0; };
540   Register getTIDReg() const { return TIDReg; };
541   void setTIDReg(Register Reg) { TIDReg = Reg; }
542 
543   unsigned getBytesInStackArgArea() const {
544     return BytesInStackArgArea;
545   }
546 
547   void setBytesInStackArgArea(unsigned Bytes) {
548     BytesInStackArgArea = Bytes;
549   }
550 
551   // Add user SGPRs.
552   Register addPrivateSegmentBuffer(const SIRegisterInfo &TRI);
553   Register addDispatchPtr(const SIRegisterInfo &TRI);
554   Register addQueuePtr(const SIRegisterInfo &TRI);
555   Register addKernargSegmentPtr(const SIRegisterInfo &TRI);
556   Register addDispatchID(const SIRegisterInfo &TRI);
557   Register addFlatScratchInit(const SIRegisterInfo &TRI);
558   Register addImplicitBufferPtr(const SIRegisterInfo &TRI);
559 
560   // Add system SGPRs.
561   Register addWorkGroupIDX() {
562     ArgInfo.WorkGroupIDX = ArgDescriptor::createRegister(getNextSystemSGPR());
563     NumSystemSGPRs += 1;
564     return ArgInfo.WorkGroupIDX.getRegister();
565   }
566 
567   Register addWorkGroupIDY() {
568     ArgInfo.WorkGroupIDY = ArgDescriptor::createRegister(getNextSystemSGPR());
569     NumSystemSGPRs += 1;
570     return ArgInfo.WorkGroupIDY.getRegister();
571   }
572 
573   Register addWorkGroupIDZ() {
574     ArgInfo.WorkGroupIDZ = ArgDescriptor::createRegister(getNextSystemSGPR());
575     NumSystemSGPRs += 1;
576     return ArgInfo.WorkGroupIDZ.getRegister();
577   }
578 
579   Register addWorkGroupInfo() {
580     ArgInfo.WorkGroupInfo = ArgDescriptor::createRegister(getNextSystemSGPR());
581     NumSystemSGPRs += 1;
582     return ArgInfo.WorkGroupInfo.getRegister();
583   }
584 
585   // Add special VGPR inputs
586   void setWorkItemIDX(ArgDescriptor Arg) {
587     ArgInfo.WorkItemIDX = Arg;
588   }
589 
590   void setWorkItemIDY(ArgDescriptor Arg) {
591     ArgInfo.WorkItemIDY = Arg;
592   }
593 
594   void setWorkItemIDZ(ArgDescriptor Arg) {
595     ArgInfo.WorkItemIDZ = Arg;
596   }
597 
598   Register addPrivateSegmentWaveByteOffset() {
599     ArgInfo.PrivateSegmentWaveByteOffset
600       = ArgDescriptor::createRegister(getNextSystemSGPR());
601     NumSystemSGPRs += 1;
602     return ArgInfo.PrivateSegmentWaveByteOffset.getRegister();
603   }
604 
605   void setPrivateSegmentWaveByteOffset(Register Reg) {
606     ArgInfo.PrivateSegmentWaveByteOffset = ArgDescriptor::createRegister(Reg);
607   }
608 
609   bool hasPrivateSegmentBuffer() const {
610     return PrivateSegmentBuffer;
611   }
612 
613   bool hasDispatchPtr() const {
614     return DispatchPtr;
615   }
616 
617   bool hasQueuePtr() const {
618     return QueuePtr;
619   }
620 
621   bool hasKernargSegmentPtr() const {
622     return KernargSegmentPtr;
623   }
624 
625   bool hasDispatchID() const {
626     return DispatchID;
627   }
628 
629   bool hasFlatScratchInit() const {
630     return FlatScratchInit;
631   }
632 
633   bool hasWorkGroupIDX() const {
634     return WorkGroupIDX;
635   }
636 
637   bool hasWorkGroupIDY() const {
638     return WorkGroupIDY;
639   }
640 
641   bool hasWorkGroupIDZ() const {
642     return WorkGroupIDZ;
643   }
644 
645   bool hasWorkGroupInfo() const {
646     return WorkGroupInfo;
647   }
648 
649   bool hasPrivateSegmentWaveByteOffset() const {
650     return PrivateSegmentWaveByteOffset;
651   }
652 
653   bool hasWorkItemIDX() const {
654     return WorkItemIDX;
655   }
656 
657   bool hasWorkItemIDY() const {
658     return WorkItemIDY;
659   }
660 
661   bool hasWorkItemIDZ() const {
662     return WorkItemIDZ;
663   }
664 
665   bool hasImplicitArgPtr() const {
666     return ImplicitArgPtr;
667   }
668 
669   bool hasImplicitBufferPtr() const {
670     return ImplicitBufferPtr;
671   }
672 
673   AMDGPUFunctionArgInfo &getArgInfo() {
674     return ArgInfo;
675   }
676 
677   const AMDGPUFunctionArgInfo &getArgInfo() const {
678     return ArgInfo;
679   }
680 
681   std::tuple<const ArgDescriptor *, const TargetRegisterClass *, LLT>
682   getPreloadedValue(AMDGPUFunctionArgInfo::PreloadedValue Value) const {
683     return ArgInfo.getPreloadedValue(Value);
684   }
685 
686   MCRegister getPreloadedReg(AMDGPUFunctionArgInfo::PreloadedValue Value) const {
687     auto Arg = std::get<0>(ArgInfo.getPreloadedValue(Value));
688     return Arg ? Arg->getRegister() : MCRegister();
689   }
690 
691   unsigned getGITPtrHigh() const {
692     return GITPtrHigh;
693   }
694 
695   Register getGITPtrLoReg(const MachineFunction &MF) const;
696 
697   uint32_t get32BitAddressHighBits() const {
698     return HighBitsOf32BitAddress;
699   }
700 
701   unsigned getGDSSize() const {
702     return GDSSize;
703   }
704 
705   unsigned getNumUserSGPRs() const {
706     return NumUserSGPRs;
707   }
708 
709   unsigned getNumPreloadedSGPRs() const {
710     return NumUserSGPRs + NumSystemSGPRs;
711   }
712 
713   Register getPrivateSegmentWaveByteOffsetSystemSGPR() const {
714     return ArgInfo.PrivateSegmentWaveByteOffset.getRegister();
715   }
716 
717   /// Returns the physical register reserved for use as the resource
718   /// descriptor for scratch accesses.
719   Register getScratchRSrcReg() const {
720     return ScratchRSrcReg;
721   }
722 
723   void setScratchRSrcReg(Register Reg) {
724     assert(Reg != 0 && "Should never be unset");
725     ScratchRSrcReg = Reg;
726   }
727 
728   Register getFrameOffsetReg() const {
729     return FrameOffsetReg;
730   }
731 
732   void setFrameOffsetReg(Register Reg) {
733     assert(Reg != 0 && "Should never be unset");
734     FrameOffsetReg = Reg;
735   }
736 
737   void setStackPtrOffsetReg(Register Reg) {
738     assert(Reg != 0 && "Should never be unset");
739     StackPtrOffsetReg = Reg;
740   }
741 
742   // Note the unset value for this is AMDGPU::SP_REG rather than
743   // NoRegister. This is mostly a workaround for MIR tests where state that
744   // can't be directly computed from the function is not preserved in serialized
745   // MIR.
746   Register getStackPtrOffsetReg() const {
747     return StackPtrOffsetReg;
748   }
749 
750   Register getQueuePtrUserSGPR() const {
751     return ArgInfo.QueuePtr.getRegister();
752   }
753 
754   Register getImplicitBufferPtrUserSGPR() const {
755     return ArgInfo.ImplicitBufferPtr.getRegister();
756   }
757 
758   bool hasSpilledSGPRs() const {
759     return HasSpilledSGPRs;
760   }
761 
762   void setHasSpilledSGPRs(bool Spill = true) {
763     HasSpilledSGPRs = Spill;
764   }
765 
766   bool hasSpilledVGPRs() const {
767     return HasSpilledVGPRs;
768   }
769 
770   void setHasSpilledVGPRs(bool Spill = true) {
771     HasSpilledVGPRs = Spill;
772   }
773 
774   bool hasNonSpillStackObjects() const {
775     return HasNonSpillStackObjects;
776   }
777 
778   void setHasNonSpillStackObjects(bool StackObject = true) {
779     HasNonSpillStackObjects = StackObject;
780   }
781 
782   bool isStackRealigned() const {
783     return IsStackRealigned;
784   }
785 
786   void setIsStackRealigned(bool Realigned = true) {
787     IsStackRealigned = Realigned;
788   }
789 
790   unsigned getNumSpilledSGPRs() const {
791     return NumSpilledSGPRs;
792   }
793 
794   unsigned getNumSpilledVGPRs() const {
795     return NumSpilledVGPRs;
796   }
797 
798   void addToSpilledSGPRs(unsigned num) {
799     NumSpilledSGPRs += num;
800   }
801 
802   void addToSpilledVGPRs(unsigned num) {
803     NumSpilledVGPRs += num;
804   }
805 
806   unsigned getPSInputAddr() const {
807     return PSInputAddr;
808   }
809 
810   unsigned getPSInputEnable() const {
811     return PSInputEnable;
812   }
813 
814   bool isPSInputAllocated(unsigned Index) const {
815     return PSInputAddr & (1 << Index);
816   }
817 
818   void markPSInputAllocated(unsigned Index) {
819     PSInputAddr |= 1 << Index;
820   }
821 
822   void markPSInputEnabled(unsigned Index) {
823     PSInputEnable |= 1 << Index;
824   }
825 
826   bool returnsVoid() const {
827     return ReturnsVoid;
828   }
829 
830   void setIfReturnsVoid(bool Value) {
831     ReturnsVoid = Value;
832   }
833 
834   /// \returns A pair of default/requested minimum/maximum flat work group sizes
835   /// for this function.
836   std::pair<unsigned, unsigned> getFlatWorkGroupSizes() const {
837     return FlatWorkGroupSizes;
838   }
839 
840   /// \returns Default/requested minimum flat work group size for this function.
841   unsigned getMinFlatWorkGroupSize() const {
842     return FlatWorkGroupSizes.first;
843   }
844 
845   /// \returns Default/requested maximum flat work group size for this function.
846   unsigned getMaxFlatWorkGroupSize() const {
847     return FlatWorkGroupSizes.second;
848   }
849 
850   /// \returns A pair of default/requested minimum/maximum number of waves per
851   /// execution unit.
852   std::pair<unsigned, unsigned> getWavesPerEU() const {
853     return WavesPerEU;
854   }
855 
856   /// \returns Default/requested minimum number of waves per execution unit.
857   unsigned getMinWavesPerEU() const {
858     return WavesPerEU.first;
859   }
860 
861   /// \returns Default/requested maximum number of waves per execution unit.
862   unsigned getMaxWavesPerEU() const {
863     return WavesPerEU.second;
864   }
865 
866   /// \returns SGPR used for \p Dim's work group ID.
867   Register getWorkGroupIDSGPR(unsigned Dim) const {
868     switch (Dim) {
869     case 0:
870       assert(hasWorkGroupIDX());
871       return ArgInfo.WorkGroupIDX.getRegister();
872     case 1:
873       assert(hasWorkGroupIDY());
874       return ArgInfo.WorkGroupIDY.getRegister();
875     case 2:
876       assert(hasWorkGroupIDZ());
877       return ArgInfo.WorkGroupIDZ.getRegister();
878     }
879     llvm_unreachable("unexpected dimension");
880   }
881 
882   unsigned getLDSWaveSpillSize() const {
883     return LDSWaveSpillSize;
884   }
885 
886   const AMDGPUBufferPseudoSourceValue *getBufferPSV(const SIInstrInfo &TII) {
887     if (!BufferPSV)
888       BufferPSV = std::make_unique<AMDGPUBufferPseudoSourceValue>(TII);
889 
890     return BufferPSV.get();
891   }
892 
893   const AMDGPUImagePseudoSourceValue *getImagePSV(const SIInstrInfo &TII) {
894     if (!ImagePSV)
895       ImagePSV = std::make_unique<AMDGPUImagePseudoSourceValue>(TII);
896 
897     return ImagePSV.get();
898   }
899 
900   const AMDGPUGWSResourcePseudoSourceValue *getGWSPSV(const SIInstrInfo &TII) {
901     if (!GWSResourcePSV) {
902       GWSResourcePSV =
903           std::make_unique<AMDGPUGWSResourcePseudoSourceValue>(TII);
904     }
905 
906     return GWSResourcePSV.get();
907   }
908 
909   unsigned getOccupancy() const {
910     return Occupancy;
911   }
912 
913   unsigned getMinAllowedOccupancy() const {
914     if (!isMemoryBound() && !needsWaveLimiter())
915       return Occupancy;
916     return (Occupancy < 4) ? Occupancy : 4;
917   }
918 
919   void limitOccupancy(const MachineFunction &MF);
920 
921   void limitOccupancy(unsigned Limit) {
922     if (Occupancy > Limit)
923       Occupancy = Limit;
924   }
925 
926   void increaseOccupancy(const MachineFunction &MF, unsigned Limit) {
927     if (Occupancy < Limit)
928       Occupancy = Limit;
929     limitOccupancy(MF);
930   }
931 };
932 
933 } // end namespace llvm
934 
935 #endif // LLVM_LIB_TARGET_AMDGPU_SIMACHINEFUNCTIONINFO_H
936