1 //===- SIMachineFunctionInfo.cpp - SI Machine Function Info ---------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #include "SIMachineFunctionInfo.h"
10 #include "AMDGPUArgumentUsageInfo.h"
11 #include "AMDGPUTargetMachine.h"
12 #include "AMDGPUSubtarget.h"
13 #include "SIRegisterInfo.h"
14 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
15 #include "Utils/AMDGPUBaseInfo.h"
16 #include "llvm/ADT/Optional.h"
17 #include "llvm/CodeGen/MachineBasicBlock.h"
18 #include "llvm/CodeGen/MachineFrameInfo.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/MachineRegisterInfo.h"
21 #include "llvm/IR/CallingConv.h"
22 #include "llvm/IR/Function.h"
23 #include <cassert>
24 #include <vector>
25 
26 #define MAX_LANES 64
27 
28 using namespace llvm;
29 
30 SIMachineFunctionInfo::SIMachineFunctionInfo(const MachineFunction &MF)
31   : AMDGPUMachineFunction(MF),
32     PrivateSegmentBuffer(false),
33     DispatchPtr(false),
34     QueuePtr(false),
35     KernargSegmentPtr(false),
36     DispatchID(false),
37     FlatScratchInit(false),
38     WorkGroupIDX(false),
39     WorkGroupIDY(false),
40     WorkGroupIDZ(false),
41     WorkGroupInfo(false),
42     PrivateSegmentWaveByteOffset(false),
43     WorkItemIDX(false),
44     WorkItemIDY(false),
45     WorkItemIDZ(false),
46     ImplicitBufferPtr(false),
47     ImplicitArgPtr(false),
48     GITPtrHigh(0xffffffff),
49     HighBitsOf32BitAddress(0),
50     GDSSize(0) {
51   const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
52   const Function &F = MF.getFunction();
53   FlatWorkGroupSizes = ST.getFlatWorkGroupSizes(F);
54   WavesPerEU = ST.getWavesPerEU(F);
55 
56   Occupancy = ST.computeOccupancy(MF, getLDSSize());
57   CallingConv::ID CC = F.getCallingConv();
58 
59   // FIXME: Should have analysis or something rather than attribute to detect
60   // calls.
61   const bool HasCalls = F.hasFnAttribute("amdgpu-calls");
62 
63   // Enable all kernel inputs if we have the fixed ABI. Don't bother if we don't
64   // have any calls.
65   const bool UseFixedABI = AMDGPUTargetMachine::EnableFixedFunctionABI &&
66                            (!isEntryFunction() || HasCalls);
67 
68   if (CC == CallingConv::AMDGPU_KERNEL || CC == CallingConv::SPIR_KERNEL) {
69     if (!F.arg_empty())
70       KernargSegmentPtr = true;
71     WorkGroupIDX = true;
72     WorkItemIDX = true;
73   } else if (CC == CallingConv::AMDGPU_PS) {
74     PSInputAddr = AMDGPU::getInitialPSInputAddr(F);
75   }
76 
77   if (!isEntryFunction()) {
78     // Non-entry functions have no special inputs for now, other registers
79     // required for scratch access.
80     ScratchRSrcReg = AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3;
81 
82     // TODO: Pick a high register, and shift down, similar to a kernel.
83     FrameOffsetReg = AMDGPU::SGPR33;
84     StackPtrOffsetReg = AMDGPU::SGPR32;
85 
86     ArgInfo.PrivateSegmentBuffer =
87       ArgDescriptor::createRegister(ScratchRSrcReg);
88 
89     if (F.hasFnAttribute("amdgpu-implicitarg-ptr"))
90       ImplicitArgPtr = true;
91   } else {
92     if (F.hasFnAttribute("amdgpu-implicitarg-ptr")) {
93       KernargSegmentPtr = true;
94       MaxKernArgAlign = std::max(ST.getAlignmentForImplicitArgPtr(),
95                                  MaxKernArgAlign);
96     }
97   }
98 
99   if (UseFixedABI) {
100     WorkGroupIDX = true;
101     WorkGroupIDY = true;
102     WorkGroupIDZ = true;
103     WorkItemIDX = true;
104     WorkItemIDY = true;
105     WorkItemIDZ = true;
106     ImplicitArgPtr = true;
107   } else {
108     if (F.hasFnAttribute("amdgpu-work-group-id-x"))
109       WorkGroupIDX = true;
110 
111     if (F.hasFnAttribute("amdgpu-work-group-id-y"))
112       WorkGroupIDY = true;
113 
114     if (F.hasFnAttribute("amdgpu-work-group-id-z"))
115       WorkGroupIDZ = true;
116 
117     if (F.hasFnAttribute("amdgpu-work-item-id-x"))
118       WorkItemIDX = true;
119 
120     if (F.hasFnAttribute("amdgpu-work-item-id-y"))
121       WorkItemIDY = true;
122 
123     if (F.hasFnAttribute("amdgpu-work-item-id-z"))
124       WorkItemIDZ = true;
125   }
126 
127   bool HasStackObjects = F.hasFnAttribute("amdgpu-stack-objects");
128   if (isEntryFunction()) {
129     // X, XY, and XYZ are the only supported combinations, so make sure Y is
130     // enabled if Z is.
131     if (WorkItemIDZ)
132       WorkItemIDY = true;
133 
134     PrivateSegmentWaveByteOffset = true;
135 
136     // HS and GS always have the scratch wave offset in SGPR5 on GFX9.
137     if (ST.getGeneration() >= AMDGPUSubtarget::GFX9 &&
138         (CC == CallingConv::AMDGPU_HS || CC == CallingConv::AMDGPU_GS))
139       ArgInfo.PrivateSegmentWaveByteOffset =
140           ArgDescriptor::createRegister(AMDGPU::SGPR5);
141   }
142 
143   bool isAmdHsaOrMesa = ST.isAmdHsaOrMesa(F);
144   if (isAmdHsaOrMesa) {
145     PrivateSegmentBuffer = true;
146 
147     if (UseFixedABI) {
148       DispatchPtr = true;
149       QueuePtr = true;
150 
151       // FIXME: We don't need this?
152       DispatchID = true;
153     } else {
154       if (F.hasFnAttribute("amdgpu-dispatch-ptr"))
155         DispatchPtr = true;
156 
157       if (F.hasFnAttribute("amdgpu-queue-ptr"))
158         QueuePtr = true;
159 
160       if (F.hasFnAttribute("amdgpu-dispatch-id"))
161         DispatchID = true;
162     }
163   } else if (ST.isMesaGfxShader(F)) {
164     ImplicitBufferPtr = true;
165   }
166 
167   if (UseFixedABI || F.hasFnAttribute("amdgpu-kernarg-segment-ptr"))
168     KernargSegmentPtr = true;
169 
170   if (ST.hasFlatAddressSpace() && isEntryFunction() && isAmdHsaOrMesa) {
171     // TODO: This could be refined a lot. The attribute is a poor way of
172     // detecting calls or stack objects that may require it before argument
173     // lowering.
174     if (HasCalls || HasStackObjects)
175       FlatScratchInit = true;
176   }
177 
178   Attribute A = F.getFnAttribute("amdgpu-git-ptr-high");
179   StringRef S = A.getValueAsString();
180   if (!S.empty())
181     S.consumeInteger(0, GITPtrHigh);
182 
183   A = F.getFnAttribute("amdgpu-32bit-address-high-bits");
184   S = A.getValueAsString();
185   if (!S.empty())
186     S.consumeInteger(0, HighBitsOf32BitAddress);
187 
188   S = F.getFnAttribute("amdgpu-gds-size").getValueAsString();
189   if (!S.empty())
190     S.consumeInteger(0, GDSSize);
191 }
192 
193 void SIMachineFunctionInfo::limitOccupancy(const MachineFunction &MF) {
194   limitOccupancy(getMaxWavesPerEU());
195   const GCNSubtarget& ST = MF.getSubtarget<GCNSubtarget>();
196   limitOccupancy(ST.getOccupancyWithLocalMemSize(getLDSSize(),
197                  MF.getFunction()));
198 }
199 
200 Register SIMachineFunctionInfo::addPrivateSegmentBuffer(
201   const SIRegisterInfo &TRI) {
202   ArgInfo.PrivateSegmentBuffer =
203     ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
204     getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SGPR_128RegClass));
205   NumUserSGPRs += 4;
206   return ArgInfo.PrivateSegmentBuffer.getRegister();
207 }
208 
209 Register SIMachineFunctionInfo::addDispatchPtr(const SIRegisterInfo &TRI) {
210   ArgInfo.DispatchPtr = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
211     getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
212   NumUserSGPRs += 2;
213   return ArgInfo.DispatchPtr.getRegister();
214 }
215 
216 Register SIMachineFunctionInfo::addQueuePtr(const SIRegisterInfo &TRI) {
217   ArgInfo.QueuePtr = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
218     getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
219   NumUserSGPRs += 2;
220   return ArgInfo.QueuePtr.getRegister();
221 }
222 
223 Register SIMachineFunctionInfo::addKernargSegmentPtr(const SIRegisterInfo &TRI) {
224   ArgInfo.KernargSegmentPtr
225     = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
226     getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
227   NumUserSGPRs += 2;
228   return ArgInfo.KernargSegmentPtr.getRegister();
229 }
230 
231 Register SIMachineFunctionInfo::addDispatchID(const SIRegisterInfo &TRI) {
232   ArgInfo.DispatchID = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
233     getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
234   NumUserSGPRs += 2;
235   return ArgInfo.DispatchID.getRegister();
236 }
237 
238 Register SIMachineFunctionInfo::addFlatScratchInit(const SIRegisterInfo &TRI) {
239   ArgInfo.FlatScratchInit = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
240     getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
241   NumUserSGPRs += 2;
242   return ArgInfo.FlatScratchInit.getRegister();
243 }
244 
245 Register SIMachineFunctionInfo::addImplicitBufferPtr(const SIRegisterInfo &TRI) {
246   ArgInfo.ImplicitBufferPtr = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
247     getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
248   NumUserSGPRs += 2;
249   return ArgInfo.ImplicitBufferPtr.getRegister();
250 }
251 
252 bool SIMachineFunctionInfo::isCalleeSavedReg(const MCPhysReg *CSRegs,
253                                              MCPhysReg Reg) {
254   for (unsigned I = 0; CSRegs[I]; ++I) {
255     if (CSRegs[I] == Reg)
256       return true;
257   }
258 
259   return false;
260 }
261 
262 /// \p returns true if \p NumLanes slots are available in VGPRs already used for
263 /// SGPR spilling.
264 //
265 // FIXME: This only works after processFunctionBeforeFrameFinalized
266 bool SIMachineFunctionInfo::haveFreeLanesForSGPRSpill(const MachineFunction &MF,
267                                                       unsigned NumNeed) const {
268   const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
269   unsigned WaveSize = ST.getWavefrontSize();
270   return NumVGPRSpillLanes + NumNeed <= WaveSize * SpillVGPRs.size();
271 }
272 
273 /// Reserve a slice of a VGPR to support spilling for FrameIndex \p FI.
274 bool SIMachineFunctionInfo::allocateSGPRSpillToVGPR(MachineFunction &MF,
275                                                     int FI) {
276   std::vector<SpilledReg> &SpillLanes = SGPRToVGPRSpills[FI];
277 
278   // This has already been allocated.
279   if (!SpillLanes.empty())
280     return true;
281 
282   const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
283   const SIRegisterInfo *TRI = ST.getRegisterInfo();
284   MachineFrameInfo &FrameInfo = MF.getFrameInfo();
285   MachineRegisterInfo &MRI = MF.getRegInfo();
286   unsigned WaveSize = ST.getWavefrontSize();
287   SIMachineFunctionInfo *FuncInfo = MF.getInfo<SIMachineFunctionInfo>();
288 
289   unsigned Size = FrameInfo.getObjectSize(FI);
290   unsigned NumLanes = Size / 4;
291 
292   if (NumLanes > WaveSize)
293     return false;
294 
295   assert(Size >= 4 && "invalid sgpr spill size");
296   assert(TRI->spillSGPRToVGPR() && "not spilling SGPRs to VGPRs");
297 
298   const MCPhysReg *CSRegs = MRI.getCalleeSavedRegs();
299 
300   // Make sure to handle the case where a wide SGPR spill may span between two
301   // VGPRs.
302   for (unsigned I = 0; I < NumLanes; ++I, ++NumVGPRSpillLanes) {
303     Register LaneVGPR;
304     unsigned VGPRIndex = (NumVGPRSpillLanes % WaveSize);
305 
306     if (VGPRIndex == 0 && !FuncInfo->VGPRReservedForSGPRSpill) {
307       LaneVGPR = TRI->findUnusedRegister(MRI, &AMDGPU::VGPR_32RegClass, MF);
308       if (LaneVGPR == AMDGPU::NoRegister) {
309         // We have no VGPRs left for spilling SGPRs. Reset because we will not
310         // partially spill the SGPR to VGPRs.
311         SGPRToVGPRSpills.erase(FI);
312         NumVGPRSpillLanes -= I;
313         return false;
314       }
315 
316       Optional<int> CSRSpillFI;
317       if ((FrameInfo.hasCalls() || !isEntryFunction()) && CSRegs &&
318           isCalleeSavedReg(CSRegs, LaneVGPR)) {
319         CSRSpillFI = FrameInfo.CreateSpillStackObject(4, Align(4));
320       }
321 
322       SpillVGPRs.push_back(SGPRSpillVGPRCSR(LaneVGPR, CSRSpillFI));
323 
324       // Add this register as live-in to all blocks to avoid machine verifer
325       // complaining about use of an undefined physical register.
326       for (MachineBasicBlock &BB : MF)
327         BB.addLiveIn(LaneVGPR);
328     } else {
329       LaneVGPR = SpillVGPRs.back().VGPR;
330     }
331 
332     SpillLanes.push_back(SpilledReg(LaneVGPR, VGPRIndex));
333   }
334 
335   return true;
336 }
337 
338 /// Reserve a VGPR for spilling of SGPRs
339 bool SIMachineFunctionInfo::reserveVGPRforSGPRSpills(MachineFunction &MF) {
340   const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
341   const SIRegisterInfo *TRI = ST.getRegisterInfo();
342   SIMachineFunctionInfo *FuncInfo = MF.getInfo<SIMachineFunctionInfo>();
343 
344   Register LaneVGPR = TRI->findUnusedRegister(
345       MF.getRegInfo(), &AMDGPU::VGPR_32RegClass, MF, true);
346   SpillVGPRs.push_back(SGPRSpillVGPRCSR(LaneVGPR, None));
347   FuncInfo->VGPRReservedForSGPRSpill = LaneVGPR;
348   return true;
349 }
350 
351 /// Reserve AGPRs or VGPRs to support spilling for FrameIndex \p FI.
352 /// Either AGPR is spilled to VGPR to vice versa.
353 /// Returns true if a \p FI can be eliminated completely.
354 bool SIMachineFunctionInfo::allocateVGPRSpillToAGPR(MachineFunction &MF,
355                                                     int FI,
356                                                     bool isAGPRtoVGPR) {
357   MachineRegisterInfo &MRI = MF.getRegInfo();
358   MachineFrameInfo &FrameInfo = MF.getFrameInfo();
359   const GCNSubtarget &ST =  MF.getSubtarget<GCNSubtarget>();
360 
361   assert(ST.hasMAIInsts() && FrameInfo.isSpillSlotObjectIndex(FI));
362 
363   auto &Spill = VGPRToAGPRSpills[FI];
364 
365   // This has already been allocated.
366   if (!Spill.Lanes.empty())
367     return Spill.FullyAllocated;
368 
369   unsigned Size = FrameInfo.getObjectSize(FI);
370   unsigned NumLanes = Size / 4;
371   Spill.Lanes.resize(NumLanes, AMDGPU::NoRegister);
372 
373   const TargetRegisterClass &RC =
374       isAGPRtoVGPR ? AMDGPU::VGPR_32RegClass : AMDGPU::AGPR_32RegClass;
375   auto Regs = RC.getRegisters();
376 
377   auto &SpillRegs = isAGPRtoVGPR ? SpillAGPR : SpillVGPR;
378   const SIRegisterInfo *TRI = ST.getRegisterInfo();
379   Spill.FullyAllocated = true;
380 
381   // FIXME: Move allocation logic out of MachineFunctionInfo and initialize
382   // once.
383   BitVector OtherUsedRegs;
384   OtherUsedRegs.resize(TRI->getNumRegs());
385 
386   const uint32_t *CSRMask =
387       TRI->getCallPreservedMask(MF, MF.getFunction().getCallingConv());
388   if (CSRMask)
389     OtherUsedRegs.setBitsInMask(CSRMask);
390 
391   // TODO: Should include register tuples, but doesn't matter with current
392   // usage.
393   for (MCPhysReg Reg : SpillAGPR)
394     OtherUsedRegs.set(Reg);
395   for (MCPhysReg Reg : SpillVGPR)
396     OtherUsedRegs.set(Reg);
397 
398   SmallVectorImpl<MCPhysReg>::const_iterator NextSpillReg = Regs.begin();
399   for (unsigned I = 0; I < NumLanes; ++I) {
400     NextSpillReg = std::find_if(
401         NextSpillReg, Regs.end(), [&MRI, &OtherUsedRegs](MCPhysReg Reg) {
402           return MRI.isAllocatable(Reg) && !MRI.isPhysRegUsed(Reg) &&
403                  !OtherUsedRegs[Reg];
404         });
405 
406     if (NextSpillReg == Regs.end()) { // Registers exhausted
407       Spill.FullyAllocated = false;
408       break;
409     }
410 
411     OtherUsedRegs.set(*NextSpillReg);
412     SpillRegs.push_back(*NextSpillReg);
413     Spill.Lanes[I] = *NextSpillReg++;
414   }
415 
416   return Spill.FullyAllocated;
417 }
418 
419 void SIMachineFunctionInfo::removeDeadFrameIndices(MachineFrameInfo &MFI) {
420   // The FP & BP spills haven't been inserted yet, so keep them around.
421   for (auto &R : SGPRToVGPRSpills) {
422     if (R.first != FramePointerSaveIndex && R.first != BasePointerSaveIndex)
423       MFI.RemoveStackObject(R.first);
424   }
425 
426   // All other SPGRs must be allocated on the default stack, so reset the stack
427   // ID.
428   for (int i = MFI.getObjectIndexBegin(), e = MFI.getObjectIndexEnd(); i != e;
429        ++i)
430     if (i != FramePointerSaveIndex && i != BasePointerSaveIndex)
431       MFI.setStackID(i, TargetStackID::Default);
432 
433   for (auto &R : VGPRToAGPRSpills) {
434     if (R.second.FullyAllocated)
435       MFI.RemoveStackObject(R.first);
436   }
437 }
438 
439 MCPhysReg SIMachineFunctionInfo::getNextUserSGPR() const {
440   assert(NumSystemSGPRs == 0 && "System SGPRs must be added after user SGPRs");
441   return AMDGPU::SGPR0 + NumUserSGPRs;
442 }
443 
444 MCPhysReg SIMachineFunctionInfo::getNextSystemSGPR() const {
445   return AMDGPU::SGPR0 + NumUserSGPRs + NumSystemSGPRs;
446 }
447 
448 Register
449 SIMachineFunctionInfo::getGITPtrLoReg(const MachineFunction &MF) const {
450   const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
451   if (!ST.isAmdPalOS())
452     return Register();
453   Register GitPtrLo = AMDGPU::SGPR0; // Low GIT address passed in
454   if (ST.hasMergedShaders()) {
455     switch (MF.getFunction().getCallingConv()) {
456     case CallingConv::AMDGPU_HS:
457     case CallingConv::AMDGPU_GS:
458       // Low GIT address is passed in s8 rather than s0 for an LS+HS or
459       // ES+GS merged shader on gfx9+.
460       GitPtrLo = AMDGPU::SGPR8;
461       return GitPtrLo;
462     default:
463       return GitPtrLo;
464     }
465   }
466   return GitPtrLo;
467 }
468 
469 static yaml::StringValue regToString(Register Reg,
470                                      const TargetRegisterInfo &TRI) {
471   yaml::StringValue Dest;
472   {
473     raw_string_ostream OS(Dest.Value);
474     OS << printReg(Reg, &TRI);
475   }
476   return Dest;
477 }
478 
479 static Optional<yaml::SIArgumentInfo>
480 convertArgumentInfo(const AMDGPUFunctionArgInfo &ArgInfo,
481                     const TargetRegisterInfo &TRI) {
482   yaml::SIArgumentInfo AI;
483 
484   auto convertArg = [&](Optional<yaml::SIArgument> &A,
485                         const ArgDescriptor &Arg) {
486     if (!Arg)
487       return false;
488 
489     // Create a register or stack argument.
490     yaml::SIArgument SA = yaml::SIArgument::createArgument(Arg.isRegister());
491     if (Arg.isRegister()) {
492       raw_string_ostream OS(SA.RegisterName.Value);
493       OS << printReg(Arg.getRegister(), &TRI);
494     } else
495       SA.StackOffset = Arg.getStackOffset();
496     // Check and update the optional mask.
497     if (Arg.isMasked())
498       SA.Mask = Arg.getMask();
499 
500     A = SA;
501     return true;
502   };
503 
504   bool Any = false;
505   Any |= convertArg(AI.PrivateSegmentBuffer, ArgInfo.PrivateSegmentBuffer);
506   Any |= convertArg(AI.DispatchPtr, ArgInfo.DispatchPtr);
507   Any |= convertArg(AI.QueuePtr, ArgInfo.QueuePtr);
508   Any |= convertArg(AI.KernargSegmentPtr, ArgInfo.KernargSegmentPtr);
509   Any |= convertArg(AI.DispatchID, ArgInfo.DispatchID);
510   Any |= convertArg(AI.FlatScratchInit, ArgInfo.FlatScratchInit);
511   Any |= convertArg(AI.PrivateSegmentSize, ArgInfo.PrivateSegmentSize);
512   Any |= convertArg(AI.WorkGroupIDX, ArgInfo.WorkGroupIDX);
513   Any |= convertArg(AI.WorkGroupIDY, ArgInfo.WorkGroupIDY);
514   Any |= convertArg(AI.WorkGroupIDZ, ArgInfo.WorkGroupIDZ);
515   Any |= convertArg(AI.WorkGroupInfo, ArgInfo.WorkGroupInfo);
516   Any |= convertArg(AI.PrivateSegmentWaveByteOffset,
517                     ArgInfo.PrivateSegmentWaveByteOffset);
518   Any |= convertArg(AI.ImplicitArgPtr, ArgInfo.ImplicitArgPtr);
519   Any |= convertArg(AI.ImplicitBufferPtr, ArgInfo.ImplicitBufferPtr);
520   Any |= convertArg(AI.WorkItemIDX, ArgInfo.WorkItemIDX);
521   Any |= convertArg(AI.WorkItemIDY, ArgInfo.WorkItemIDY);
522   Any |= convertArg(AI.WorkItemIDZ, ArgInfo.WorkItemIDZ);
523 
524   if (Any)
525     return AI;
526 
527   return None;
528 }
529 
530 yaml::SIMachineFunctionInfo::SIMachineFunctionInfo(
531   const llvm::SIMachineFunctionInfo& MFI,
532   const TargetRegisterInfo &TRI)
533   : ExplicitKernArgSize(MFI.getExplicitKernArgSize()),
534     MaxKernArgAlign(MFI.getMaxKernArgAlign()),
535     LDSSize(MFI.getLDSSize()),
536     IsEntryFunction(MFI.isEntryFunction()),
537     NoSignedZerosFPMath(MFI.hasNoSignedZerosFPMath()),
538     MemoryBound(MFI.isMemoryBound()),
539     WaveLimiter(MFI.needsWaveLimiter()),
540     HighBitsOf32BitAddress(MFI.get32BitAddressHighBits()),
541     ScratchRSrcReg(regToString(MFI.getScratchRSrcReg(), TRI)),
542     FrameOffsetReg(regToString(MFI.getFrameOffsetReg(), TRI)),
543     StackPtrOffsetReg(regToString(MFI.getStackPtrOffsetReg(), TRI)),
544     ArgInfo(convertArgumentInfo(MFI.getArgInfo(), TRI)),
545     Mode(MFI.getMode()) {}
546 
547 void yaml::SIMachineFunctionInfo::mappingImpl(yaml::IO &YamlIO) {
548   MappingTraits<SIMachineFunctionInfo>::mapping(YamlIO, *this);
549 }
550 
551 bool SIMachineFunctionInfo::initializeBaseYamlFields(
552   const yaml::SIMachineFunctionInfo &YamlMFI) {
553   ExplicitKernArgSize = YamlMFI.ExplicitKernArgSize;
554   MaxKernArgAlign = assumeAligned(YamlMFI.MaxKernArgAlign);
555   LDSSize = YamlMFI.LDSSize;
556   HighBitsOf32BitAddress = YamlMFI.HighBitsOf32BitAddress;
557   IsEntryFunction = YamlMFI.IsEntryFunction;
558   NoSignedZerosFPMath = YamlMFI.NoSignedZerosFPMath;
559   MemoryBound = YamlMFI.MemoryBound;
560   WaveLimiter = YamlMFI.WaveLimiter;
561   return false;
562 }
563 
564 // Remove VGPR which was reserved for SGPR spills if there are no spilled SGPRs
565 bool SIMachineFunctionInfo::removeVGPRForSGPRSpill(Register ReservedVGPR,
566                                                    MachineFunction &MF) {
567   for (auto *i = SpillVGPRs.begin(); i < SpillVGPRs.end(); i++) {
568     if (i->VGPR == ReservedVGPR) {
569       SpillVGPRs.erase(i);
570 
571       for (MachineBasicBlock &MBB : MF) {
572         MBB.removeLiveIn(ReservedVGPR);
573         MBB.sortUniqueLiveIns();
574       }
575       this->VGPRReservedForSGPRSpill = AMDGPU::NoRegister;
576       return true;
577     }
578   }
579   return false;
580 }
581