1 //===- SIMachineFunctionInfo.cpp - SI Machine Function Info ---------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #include "SIMachineFunctionInfo.h"
10 #include "AMDGPUArgumentUsageInfo.h"
11 #include "AMDGPUSubtarget.h"
12 #include "SIRegisterInfo.h"
13 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
14 #include "Utils/AMDGPUBaseInfo.h"
15 #include "llvm/ADT/Optional.h"
16 #include "llvm/CodeGen/MachineBasicBlock.h"
17 #include "llvm/CodeGen/MachineFrameInfo.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/CodeGen/MachineRegisterInfo.h"
20 #include "llvm/IR/CallingConv.h"
21 #include "llvm/IR/Function.h"
22 #include <cassert>
23 #include <vector>
24 
25 #define MAX_LANES 64
26 
27 using namespace llvm;
28 
29 SIMachineFunctionInfo::SIMachineFunctionInfo(const MachineFunction &MF)
30   : AMDGPUMachineFunction(MF),
31     PrivateSegmentBuffer(false),
32     DispatchPtr(false),
33     QueuePtr(false),
34     KernargSegmentPtr(false),
35     DispatchID(false),
36     FlatScratchInit(false),
37     WorkGroupIDX(false),
38     WorkGroupIDY(false),
39     WorkGroupIDZ(false),
40     WorkGroupInfo(false),
41     PrivateSegmentWaveByteOffset(false),
42     WorkItemIDX(false),
43     WorkItemIDY(false),
44     WorkItemIDZ(false),
45     ImplicitBufferPtr(false),
46     ImplicitArgPtr(false),
47     GITPtrHigh(0xffffffff),
48     HighBitsOf32BitAddress(0),
49     GDSSize(0) {
50   const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
51   const Function &F = MF.getFunction();
52   FlatWorkGroupSizes = ST.getFlatWorkGroupSizes(F);
53   WavesPerEU = ST.getWavesPerEU(F);
54 
55   Occupancy = ST.computeOccupancy(MF, getLDSSize());
56   CallingConv::ID CC = F.getCallingConv();
57   const MachineFrameInfo &FrameInfo = MF.getFrameInfo();
58 
59   // FIXME: Should have analysis or something rather than attribute to detect
60   // calls.
61   const bool HasCalls = FrameInfo.hasCalls() || F.hasFnAttribute("amdgpu-calls");
62 
63   if (CC == CallingConv::AMDGPU_KERNEL || CC == CallingConv::SPIR_KERNEL) {
64     if (!F.arg_empty())
65       KernargSegmentPtr = true;
66     WorkGroupIDX = true;
67     WorkItemIDX = true;
68   } else if (CC == CallingConv::AMDGPU_PS) {
69     PSInputAddr = AMDGPU::getInitialPSInputAddr(F);
70   }
71 
72   if (!isEntryFunction()) {
73     // Non-entry functions have no special inputs for now, other registers
74     // required for scratch access.
75     ScratchRSrcReg = AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3;
76     ScratchWaveOffsetReg = AMDGPU::SGPR33;
77 
78     // TODO: Pick a high register, and shift down, similar to a kernel.
79     FrameOffsetReg = AMDGPU::SGPR34;
80     StackPtrOffsetReg = AMDGPU::SGPR32;
81 
82     ArgInfo.PrivateSegmentBuffer =
83       ArgDescriptor::createRegister(ScratchRSrcReg);
84     ArgInfo.PrivateSegmentWaveByteOffset =
85       ArgDescriptor::createRegister(ScratchWaveOffsetReg);
86 
87     if (F.hasFnAttribute("amdgpu-implicitarg-ptr"))
88       ImplicitArgPtr = true;
89   } else {
90     if (F.hasFnAttribute("amdgpu-implicitarg-ptr")) {
91       KernargSegmentPtr = true;
92       MaxKernArgAlign = std::max(ST.getAlignmentForImplicitArgPtr(),
93                                  MaxKernArgAlign);
94     }
95   }
96 
97   if (F.hasFnAttribute("amdgpu-work-group-id-x"))
98     WorkGroupIDX = true;
99 
100   if (F.hasFnAttribute("amdgpu-work-group-id-y"))
101     WorkGroupIDY = true;
102 
103   if (F.hasFnAttribute("amdgpu-work-group-id-z"))
104     WorkGroupIDZ = true;
105 
106   if (F.hasFnAttribute("amdgpu-work-item-id-x"))
107     WorkItemIDX = true;
108 
109   if (F.hasFnAttribute("amdgpu-work-item-id-y"))
110     WorkItemIDY = true;
111 
112   if (F.hasFnAttribute("amdgpu-work-item-id-z"))
113     WorkItemIDZ = true;
114 
115   bool HasStackObjects = FrameInfo.hasStackObjects();
116 
117   if (isEntryFunction()) {
118     // X, XY, and XYZ are the only supported combinations, so make sure Y is
119     // enabled if Z is.
120     if (WorkItemIDZ)
121       WorkItemIDY = true;
122 
123     PrivateSegmentWaveByteOffset = true;
124 
125     // HS and GS always have the scratch wave offset in SGPR5 on GFX9.
126     if (ST.getGeneration() >= AMDGPUSubtarget::GFX9 &&
127         (CC == CallingConv::AMDGPU_HS || CC == CallingConv::AMDGPU_GS))
128       ArgInfo.PrivateSegmentWaveByteOffset =
129           ArgDescriptor::createRegister(AMDGPU::SGPR5);
130   }
131 
132   bool isAmdHsaOrMesa = ST.isAmdHsaOrMesa(F);
133   if (isAmdHsaOrMesa) {
134     PrivateSegmentBuffer = true;
135 
136     if (F.hasFnAttribute("amdgpu-dispatch-ptr"))
137       DispatchPtr = true;
138 
139     if (F.hasFnAttribute("amdgpu-queue-ptr"))
140       QueuePtr = true;
141 
142     if (F.hasFnAttribute("amdgpu-dispatch-id"))
143       DispatchID = true;
144   } else if (ST.isMesaGfxShader(F)) {
145     ImplicitBufferPtr = true;
146   }
147 
148   if (F.hasFnAttribute("amdgpu-kernarg-segment-ptr"))
149     KernargSegmentPtr = true;
150 
151   if (ST.hasFlatAddressSpace() && isEntryFunction() && isAmdHsaOrMesa) {
152     auto hasNonSpillStackObjects = [&]() {
153       // Avoid expensive checking if there's no stack objects.
154       if (!HasStackObjects)
155         return false;
156       for (auto OI = FrameInfo.getObjectIndexBegin(),
157                 OE = FrameInfo.getObjectIndexEnd(); OI != OE; ++OI)
158         if (!FrameInfo.isSpillSlotObjectIndex(OI))
159           return true;
160       // All stack objects are spill slots.
161       return false;
162     };
163     // TODO: This could be refined a lot. The attribute is a poor way of
164     // detecting calls that may require it before argument lowering.
165     if (HasCalls || hasNonSpillStackObjects())
166       FlatScratchInit = true;
167   }
168 
169   Attribute A = F.getFnAttribute("amdgpu-git-ptr-high");
170   StringRef S = A.getValueAsString();
171   if (!S.empty())
172     S.consumeInteger(0, GITPtrHigh);
173 
174   A = F.getFnAttribute("amdgpu-32bit-address-high-bits");
175   S = A.getValueAsString();
176   if (!S.empty())
177     S.consumeInteger(0, HighBitsOf32BitAddress);
178 
179   S = F.getFnAttribute("amdgpu-gds-size").getValueAsString();
180   if (!S.empty())
181     S.consumeInteger(0, GDSSize);
182 }
183 
184 void SIMachineFunctionInfo::limitOccupancy(const MachineFunction &MF) {
185   limitOccupancy(getMaxWavesPerEU());
186   const GCNSubtarget& ST = MF.getSubtarget<GCNSubtarget>();
187   limitOccupancy(ST.getOccupancyWithLocalMemSize(getLDSSize(),
188                  MF.getFunction()));
189 }
190 
191 unsigned SIMachineFunctionInfo::addPrivateSegmentBuffer(
192   const SIRegisterInfo &TRI) {
193   ArgInfo.PrivateSegmentBuffer =
194     ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
195     getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SGPR_128RegClass));
196   NumUserSGPRs += 4;
197   return ArgInfo.PrivateSegmentBuffer.getRegister();
198 }
199 
200 unsigned SIMachineFunctionInfo::addDispatchPtr(const SIRegisterInfo &TRI) {
201   ArgInfo.DispatchPtr = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
202     getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
203   NumUserSGPRs += 2;
204   return ArgInfo.DispatchPtr.getRegister();
205 }
206 
207 unsigned SIMachineFunctionInfo::addQueuePtr(const SIRegisterInfo &TRI) {
208   ArgInfo.QueuePtr = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
209     getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
210   NumUserSGPRs += 2;
211   return ArgInfo.QueuePtr.getRegister();
212 }
213 
214 unsigned SIMachineFunctionInfo::addKernargSegmentPtr(const SIRegisterInfo &TRI) {
215   ArgInfo.KernargSegmentPtr
216     = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
217     getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
218   NumUserSGPRs += 2;
219   return ArgInfo.KernargSegmentPtr.getRegister();
220 }
221 
222 unsigned SIMachineFunctionInfo::addDispatchID(const SIRegisterInfo &TRI) {
223   ArgInfo.DispatchID = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
224     getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
225   NumUserSGPRs += 2;
226   return ArgInfo.DispatchID.getRegister();
227 }
228 
229 unsigned SIMachineFunctionInfo::addFlatScratchInit(const SIRegisterInfo &TRI) {
230   ArgInfo.FlatScratchInit = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
231     getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
232   NumUserSGPRs += 2;
233   return ArgInfo.FlatScratchInit.getRegister();
234 }
235 
236 unsigned SIMachineFunctionInfo::addImplicitBufferPtr(const SIRegisterInfo &TRI) {
237   ArgInfo.ImplicitBufferPtr = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
238     getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
239   NumUserSGPRs += 2;
240   return ArgInfo.ImplicitBufferPtr.getRegister();
241 }
242 
243 static bool isCalleeSavedReg(const MCPhysReg *CSRegs, MCPhysReg Reg) {
244   for (unsigned I = 0; CSRegs[I]; ++I) {
245     if (CSRegs[I] == Reg)
246       return true;
247   }
248 
249   return false;
250 }
251 
252 /// \p returns true if \p NumLanes slots are available in VGPRs already used for
253 /// SGPR spilling.
254 //
255 // FIXME: This only works after processFunctionBeforeFrameFinalized
256 bool SIMachineFunctionInfo::haveFreeLanesForSGPRSpill(const MachineFunction &MF,
257                                                       unsigned NumNeed) const {
258   const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
259   unsigned WaveSize = ST.getWavefrontSize();
260   return NumVGPRSpillLanes + NumNeed <= WaveSize * SpillVGPRs.size();
261 }
262 
263 /// Reserve a slice of a VGPR to support spilling for FrameIndex \p FI.
264 bool SIMachineFunctionInfo::allocateSGPRSpillToVGPR(MachineFunction &MF,
265                                                     int FI) {
266   std::vector<SpilledReg> &SpillLanes = SGPRToVGPRSpills[FI];
267 
268   // This has already been allocated.
269   if (!SpillLanes.empty())
270     return true;
271 
272   const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
273   const SIRegisterInfo *TRI = ST.getRegisterInfo();
274   MachineFrameInfo &FrameInfo = MF.getFrameInfo();
275   MachineRegisterInfo &MRI = MF.getRegInfo();
276   unsigned WaveSize = ST.getWavefrontSize();
277 
278   unsigned Size = FrameInfo.getObjectSize(FI);
279   assert(Size >= 4 && Size <= 64 && "invalid sgpr spill size");
280   assert(TRI->spillSGPRToVGPR() && "not spilling SGPRs to VGPRs");
281 
282   int NumLanes = Size / 4;
283 
284   const MCPhysReg *CSRegs = MRI.getCalleeSavedRegs();
285 
286   // Make sure to handle the case where a wide SGPR spill may span between two
287   // VGPRs.
288   for (int I = 0; I < NumLanes; ++I, ++NumVGPRSpillLanes) {
289     unsigned LaneVGPR;
290     unsigned VGPRIndex = (NumVGPRSpillLanes % WaveSize);
291 
292     if (VGPRIndex == 0) {
293       LaneVGPR = TRI->findUnusedRegister(MRI, &AMDGPU::VGPR_32RegClass, MF);
294       if (LaneVGPR == AMDGPU::NoRegister) {
295         // We have no VGPRs left for spilling SGPRs. Reset because we will not
296         // partially spill the SGPR to VGPRs.
297         SGPRToVGPRSpills.erase(FI);
298         NumVGPRSpillLanes -= I;
299         return false;
300       }
301 
302       Optional<int> CSRSpillFI;
303       if ((FrameInfo.hasCalls() || !isEntryFunction()) && CSRegs &&
304           isCalleeSavedReg(CSRegs, LaneVGPR)) {
305         CSRSpillFI = FrameInfo.CreateSpillStackObject(4, 4);
306       }
307 
308       SpillVGPRs.push_back(SGPRSpillVGPRCSR(LaneVGPR, CSRSpillFI));
309 
310       // Add this register as live-in to all blocks to avoid machine verifer
311       // complaining about use of an undefined physical register.
312       for (MachineBasicBlock &BB : MF)
313         BB.addLiveIn(LaneVGPR);
314     } else {
315       LaneVGPR = SpillVGPRs.back().VGPR;
316     }
317 
318     SpillLanes.push_back(SpilledReg(LaneVGPR, VGPRIndex));
319   }
320 
321   return true;
322 }
323 
324 /// Reserve AGPRs or VGPRs to support spilling for FrameIndex \p FI.
325 /// Either AGPR is spilled to VGPR to vice versa.
326 /// Returns true if a \p FI can be eliminated completely.
327 bool SIMachineFunctionInfo::allocateVGPRSpillToAGPR(MachineFunction &MF,
328                                                     int FI,
329                                                     bool isAGPRtoVGPR) {
330   MachineRegisterInfo &MRI = MF.getRegInfo();
331   MachineFrameInfo &FrameInfo = MF.getFrameInfo();
332   const GCNSubtarget &ST =  MF.getSubtarget<GCNSubtarget>();
333 
334   assert(ST.hasMAIInsts() && FrameInfo.isSpillSlotObjectIndex(FI));
335 
336   auto &Spill = VGPRToAGPRSpills[FI];
337 
338   // This has already been allocated.
339   if (!Spill.Lanes.empty())
340     return Spill.FullyAllocated;
341 
342   unsigned Size = FrameInfo.getObjectSize(FI);
343   unsigned NumLanes = Size / 4;
344   Spill.Lanes.resize(NumLanes, AMDGPU::NoRegister);
345 
346   const TargetRegisterClass &RC =
347       isAGPRtoVGPR ? AMDGPU::VGPR_32RegClass : AMDGPU::AGPR_32RegClass;
348   auto Regs = RC.getRegisters();
349 
350   auto &SpillRegs = isAGPRtoVGPR ? SpillAGPR : SpillVGPR;
351   const SIRegisterInfo *TRI = ST.getRegisterInfo();
352   Spill.FullyAllocated = true;
353 
354   // FIXME: Move allocation logic out of MachineFunctionInfo and initialize
355   // once.
356   BitVector OtherUsedRegs;
357   OtherUsedRegs.resize(TRI->getNumRegs());
358 
359   const uint32_t *CSRMask =
360       TRI->getCallPreservedMask(MF, MF.getFunction().getCallingConv());
361   if (CSRMask)
362     OtherUsedRegs.setBitsInMask(CSRMask);
363 
364   // TODO: Should include register tuples, but doesn't matter with current
365   // usage.
366   for (MCPhysReg Reg : SpillAGPR)
367     OtherUsedRegs.set(Reg);
368   for (MCPhysReg Reg : SpillVGPR)
369     OtherUsedRegs.set(Reg);
370 
371   SmallVectorImpl<MCPhysReg>::const_iterator NextSpillReg = Regs.begin();
372   for (unsigned I = 0; I < NumLanes; ++I) {
373     NextSpillReg = std::find_if(
374         NextSpillReg, Regs.end(), [&MRI, &OtherUsedRegs](MCPhysReg Reg) {
375           return MRI.isAllocatable(Reg) && !MRI.isPhysRegUsed(Reg) &&
376                  !OtherUsedRegs[Reg];
377         });
378 
379     if (NextSpillReg == Regs.end()) { // Registers exhausted
380       Spill.FullyAllocated = false;
381       break;
382     }
383 
384     OtherUsedRegs.set(*NextSpillReg);
385     SpillRegs.push_back(*NextSpillReg);
386     Spill.Lanes[I] = *NextSpillReg++;
387   }
388 
389   return Spill.FullyAllocated;
390 }
391 
392 void SIMachineFunctionInfo::removeDeadFrameIndices(MachineFrameInfo &MFI) {
393   // The FP spill hasn't been inserted yet, so keep it around.
394   for (auto &R : SGPRToVGPRSpills) {
395     if (R.first != FramePointerSaveIndex)
396       MFI.RemoveStackObject(R.first);
397   }
398 
399   // All other SPGRs must be allocated on the default stack, so reset the stack
400   // ID.
401   for (int i = MFI.getObjectIndexBegin(), e = MFI.getObjectIndexEnd(); i != e;
402        ++i)
403     if (i != FramePointerSaveIndex)
404       MFI.setStackID(i, TargetStackID::Default);
405 
406   for (auto &R : VGPRToAGPRSpills) {
407     if (R.second.FullyAllocated)
408       MFI.RemoveStackObject(R.first);
409   }
410 }
411 
412 MCPhysReg SIMachineFunctionInfo::getNextUserSGPR() const {
413   assert(NumSystemSGPRs == 0 && "System SGPRs must be added after user SGPRs");
414   return AMDGPU::SGPR0 + NumUserSGPRs;
415 }
416 
417 MCPhysReg SIMachineFunctionInfo::getNextSystemSGPR() const {
418   return AMDGPU::SGPR0 + NumUserSGPRs + NumSystemSGPRs;
419 }
420 
421 static yaml::StringValue regToString(unsigned Reg,
422                                      const TargetRegisterInfo &TRI) {
423   yaml::StringValue Dest;
424   {
425     raw_string_ostream OS(Dest.Value);
426     OS << printReg(Reg, &TRI);
427   }
428   return Dest;
429 }
430 
431 static Optional<yaml::SIArgumentInfo>
432 convertArgumentInfo(const AMDGPUFunctionArgInfo &ArgInfo,
433                     const TargetRegisterInfo &TRI) {
434   yaml::SIArgumentInfo AI;
435 
436   auto convertArg = [&](Optional<yaml::SIArgument> &A,
437                         const ArgDescriptor &Arg) {
438     if (!Arg)
439       return false;
440 
441     // Create a register or stack argument.
442     yaml::SIArgument SA = yaml::SIArgument::createArgument(Arg.isRegister());
443     if (Arg.isRegister()) {
444       raw_string_ostream OS(SA.RegisterName.Value);
445       OS << printReg(Arg.getRegister(), &TRI);
446     } else
447       SA.StackOffset = Arg.getStackOffset();
448     // Check and update the optional mask.
449     if (Arg.isMasked())
450       SA.Mask = Arg.getMask();
451 
452     A = SA;
453     return true;
454   };
455 
456   bool Any = false;
457   Any |= convertArg(AI.PrivateSegmentBuffer, ArgInfo.PrivateSegmentBuffer);
458   Any |= convertArg(AI.DispatchPtr, ArgInfo.DispatchPtr);
459   Any |= convertArg(AI.QueuePtr, ArgInfo.QueuePtr);
460   Any |= convertArg(AI.KernargSegmentPtr, ArgInfo.KernargSegmentPtr);
461   Any |= convertArg(AI.DispatchID, ArgInfo.DispatchID);
462   Any |= convertArg(AI.FlatScratchInit, ArgInfo.FlatScratchInit);
463   Any |= convertArg(AI.PrivateSegmentSize, ArgInfo.PrivateSegmentSize);
464   Any |= convertArg(AI.WorkGroupIDX, ArgInfo.WorkGroupIDX);
465   Any |= convertArg(AI.WorkGroupIDY, ArgInfo.WorkGroupIDY);
466   Any |= convertArg(AI.WorkGroupIDZ, ArgInfo.WorkGroupIDZ);
467   Any |= convertArg(AI.WorkGroupInfo, ArgInfo.WorkGroupInfo);
468   Any |= convertArg(AI.PrivateSegmentWaveByteOffset,
469                     ArgInfo.PrivateSegmentWaveByteOffset);
470   Any |= convertArg(AI.ImplicitArgPtr, ArgInfo.ImplicitArgPtr);
471   Any |= convertArg(AI.ImplicitBufferPtr, ArgInfo.ImplicitBufferPtr);
472   Any |= convertArg(AI.WorkItemIDX, ArgInfo.WorkItemIDX);
473   Any |= convertArg(AI.WorkItemIDY, ArgInfo.WorkItemIDY);
474   Any |= convertArg(AI.WorkItemIDZ, ArgInfo.WorkItemIDZ);
475 
476   if (Any)
477     return AI;
478 
479   return None;
480 }
481 
482 yaml::SIMachineFunctionInfo::SIMachineFunctionInfo(
483   const llvm::SIMachineFunctionInfo& MFI,
484   const TargetRegisterInfo &TRI)
485   : ExplicitKernArgSize(MFI.getExplicitKernArgSize()),
486     MaxKernArgAlign(MFI.getMaxKernArgAlign()),
487     LDSSize(MFI.getLDSSize()),
488     IsEntryFunction(MFI.isEntryFunction()),
489     NoSignedZerosFPMath(MFI.hasNoSignedZerosFPMath()),
490     MemoryBound(MFI.isMemoryBound()),
491     WaveLimiter(MFI.needsWaveLimiter()),
492     HighBitsOf32BitAddress(MFI.get32BitAddressHighBits()),
493     ScratchRSrcReg(regToString(MFI.getScratchRSrcReg(), TRI)),
494     ScratchWaveOffsetReg(regToString(MFI.getScratchWaveOffsetReg(), TRI)),
495     FrameOffsetReg(regToString(MFI.getFrameOffsetReg(), TRI)),
496     StackPtrOffsetReg(regToString(MFI.getStackPtrOffsetReg(), TRI)),
497     ArgInfo(convertArgumentInfo(MFI.getArgInfo(), TRI)),
498     Mode(MFI.getMode()) {}
499 
500 void yaml::SIMachineFunctionInfo::mappingImpl(yaml::IO &YamlIO) {
501   MappingTraits<SIMachineFunctionInfo>::mapping(YamlIO, *this);
502 }
503 
504 bool SIMachineFunctionInfo::initializeBaseYamlFields(
505   const yaml::SIMachineFunctionInfo &YamlMFI) {
506   ExplicitKernArgSize = YamlMFI.ExplicitKernArgSize;
507   MaxKernArgAlign = assumeAligned(YamlMFI.MaxKernArgAlign);
508   LDSSize = YamlMFI.LDSSize;
509   HighBitsOf32BitAddress = YamlMFI.HighBitsOf32BitAddress;
510   IsEntryFunction = YamlMFI.IsEntryFunction;
511   NoSignedZerosFPMath = YamlMFI.NoSignedZerosFPMath;
512   MemoryBound = YamlMFI.MemoryBound;
513   WaveLimiter = YamlMFI.WaveLimiter;
514   return false;
515 }
516