1 //===- SIMachineFunctionInfo.cpp - SI Machine Function Info ---------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #include "SIMachineFunctionInfo.h"
10 #include "AMDGPUTargetMachine.h"
11 #include "llvm/CodeGen/MIRParser/MIParser.h"
12 
13 #define MAX_LANES 64
14 
15 using namespace llvm;
16 
17 SIMachineFunctionInfo::SIMachineFunctionInfo(const MachineFunction &MF)
18   : AMDGPUMachineFunction(MF),
19     PrivateSegmentBuffer(false),
20     DispatchPtr(false),
21     QueuePtr(false),
22     KernargSegmentPtr(false),
23     DispatchID(false),
24     FlatScratchInit(false),
25     WorkGroupIDX(false),
26     WorkGroupIDY(false),
27     WorkGroupIDZ(false),
28     WorkGroupInfo(false),
29     PrivateSegmentWaveByteOffset(false),
30     WorkItemIDX(false),
31     WorkItemIDY(false),
32     WorkItemIDZ(false),
33     ImplicitBufferPtr(false),
34     ImplicitArgPtr(false),
35     GITPtrHigh(0xffffffff),
36     HighBitsOf32BitAddress(0),
37     GDSSize(0) {
38   const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
39   const Function &F = MF.getFunction();
40   FlatWorkGroupSizes = ST.getFlatWorkGroupSizes(F);
41   WavesPerEU = ST.getWavesPerEU(F);
42 
43   Occupancy = ST.computeOccupancy(F, getLDSSize());
44   CallingConv::ID CC = F.getCallingConv();
45 
46   // FIXME: Should have analysis or something rather than attribute to detect
47   // calls.
48   const bool HasCalls = F.hasFnAttribute("amdgpu-calls");
49 
50   // Enable all kernel inputs if we have the fixed ABI. Don't bother if we don't
51   // have any calls.
52   const bool UseFixedABI = AMDGPUTargetMachine::EnableFixedFunctionABI &&
53                            CC != CallingConv::AMDGPU_Gfx &&
54                            (!isEntryFunction() || HasCalls);
55 
56   if (CC == CallingConv::AMDGPU_KERNEL || CC == CallingConv::SPIR_KERNEL) {
57     if (!F.arg_empty())
58       KernargSegmentPtr = true;
59     WorkGroupIDX = true;
60     WorkItemIDX = true;
61   } else if (CC == CallingConv::AMDGPU_PS) {
62     PSInputAddr = AMDGPU::getInitialPSInputAddr(F);
63   }
64 
65   if (!isEntryFunction()) {
66     if (UseFixedABI)
67       ArgInfo = AMDGPUArgumentUsageInfo::FixedABIFunctionInfo;
68 
69     // TODO: Pick a high register, and shift down, similar to a kernel.
70     FrameOffsetReg = AMDGPU::SGPR33;
71     StackPtrOffsetReg = AMDGPU::SGPR32;
72 
73     if (!ST.enableFlatScratch()) {
74       // Non-entry functions have no special inputs for now, other registers
75       // required for scratch access.
76       ScratchRSrcReg = AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3;
77 
78       ArgInfo.PrivateSegmentBuffer =
79         ArgDescriptor::createRegister(ScratchRSrcReg);
80     }
81 
82     if (F.hasFnAttribute("amdgpu-implicitarg-ptr"))
83       ImplicitArgPtr = true;
84   } else {
85     if (F.hasFnAttribute("amdgpu-implicitarg-ptr")) {
86       KernargSegmentPtr = true;
87       MaxKernArgAlign = std::max(ST.getAlignmentForImplicitArgPtr(),
88                                  MaxKernArgAlign);
89     }
90   }
91 
92   if (UseFixedABI) {
93     WorkGroupIDX = true;
94     WorkGroupIDY = true;
95     WorkGroupIDZ = true;
96     WorkItemIDX = true;
97     WorkItemIDY = true;
98     WorkItemIDZ = true;
99     ImplicitArgPtr = true;
100   } else {
101     if (F.hasFnAttribute("amdgpu-work-group-id-x"))
102       WorkGroupIDX = true;
103 
104     if (F.hasFnAttribute("amdgpu-work-group-id-y"))
105       WorkGroupIDY = true;
106 
107     if (F.hasFnAttribute("amdgpu-work-group-id-z"))
108       WorkGroupIDZ = true;
109 
110     if (F.hasFnAttribute("amdgpu-work-item-id-x"))
111       WorkItemIDX = true;
112 
113     if (F.hasFnAttribute("amdgpu-work-item-id-y"))
114       WorkItemIDY = true;
115 
116     if (F.hasFnAttribute("amdgpu-work-item-id-z"))
117       WorkItemIDZ = true;
118   }
119 
120   bool HasStackObjects = F.hasFnAttribute("amdgpu-stack-objects");
121   if (isEntryFunction()) {
122     // X, XY, and XYZ are the only supported combinations, so make sure Y is
123     // enabled if Z is.
124     if (WorkItemIDZ)
125       WorkItemIDY = true;
126 
127     PrivateSegmentWaveByteOffset = true;
128 
129     // HS and GS always have the scratch wave offset in SGPR5 on GFX9.
130     if (ST.getGeneration() >= AMDGPUSubtarget::GFX9 &&
131         (CC == CallingConv::AMDGPU_HS || CC == CallingConv::AMDGPU_GS))
132       ArgInfo.PrivateSegmentWaveByteOffset =
133           ArgDescriptor::createRegister(AMDGPU::SGPR5);
134   }
135 
136   bool isAmdHsaOrMesa = ST.isAmdHsaOrMesa(F);
137   if (isAmdHsaOrMesa) {
138     if (!ST.enableFlatScratch())
139       PrivateSegmentBuffer = true;
140 
141     if (UseFixedABI) {
142       DispatchPtr = true;
143       QueuePtr = true;
144 
145       // FIXME: We don't need this?
146       DispatchID = true;
147     } else {
148       if (F.hasFnAttribute("amdgpu-dispatch-ptr"))
149         DispatchPtr = true;
150 
151       if (F.hasFnAttribute("amdgpu-queue-ptr"))
152         QueuePtr = true;
153 
154       if (F.hasFnAttribute("amdgpu-dispatch-id"))
155         DispatchID = true;
156     }
157   } else if (ST.isMesaGfxShader(F)) {
158     ImplicitBufferPtr = true;
159   }
160 
161   if (UseFixedABI || F.hasFnAttribute("amdgpu-kernarg-segment-ptr"))
162     KernargSegmentPtr = true;
163 
164   if (ST.hasFlatAddressSpace() && isEntryFunction() &&
165       (isAmdHsaOrMesa || ST.enableFlatScratch())) {
166     // TODO: This could be refined a lot. The attribute is a poor way of
167     // detecting calls or stack objects that may require it before argument
168     // lowering.
169     if (HasCalls || HasStackObjects || ST.enableFlatScratch())
170       FlatScratchInit = true;
171   }
172 
173   Attribute A = F.getFnAttribute("amdgpu-git-ptr-high");
174   StringRef S = A.getValueAsString();
175   if (!S.empty())
176     S.consumeInteger(0, GITPtrHigh);
177 
178   A = F.getFnAttribute("amdgpu-32bit-address-high-bits");
179   S = A.getValueAsString();
180   if (!S.empty())
181     S.consumeInteger(0, HighBitsOf32BitAddress);
182 
183   S = F.getFnAttribute("amdgpu-gds-size").getValueAsString();
184   if (!S.empty())
185     S.consumeInteger(0, GDSSize);
186 }
187 
188 void SIMachineFunctionInfo::limitOccupancy(const MachineFunction &MF) {
189   limitOccupancy(getMaxWavesPerEU());
190   const GCNSubtarget& ST = MF.getSubtarget<GCNSubtarget>();
191   limitOccupancy(ST.getOccupancyWithLocalMemSize(getLDSSize(),
192                  MF.getFunction()));
193 }
194 
195 Register SIMachineFunctionInfo::addPrivateSegmentBuffer(
196   const SIRegisterInfo &TRI) {
197   ArgInfo.PrivateSegmentBuffer =
198     ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
199     getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SGPR_128RegClass));
200   NumUserSGPRs += 4;
201   return ArgInfo.PrivateSegmentBuffer.getRegister();
202 }
203 
204 Register SIMachineFunctionInfo::addDispatchPtr(const SIRegisterInfo &TRI) {
205   ArgInfo.DispatchPtr = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
206     getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
207   NumUserSGPRs += 2;
208   return ArgInfo.DispatchPtr.getRegister();
209 }
210 
211 Register SIMachineFunctionInfo::addQueuePtr(const SIRegisterInfo &TRI) {
212   ArgInfo.QueuePtr = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
213     getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
214   NumUserSGPRs += 2;
215   return ArgInfo.QueuePtr.getRegister();
216 }
217 
218 Register SIMachineFunctionInfo::addKernargSegmentPtr(const SIRegisterInfo &TRI) {
219   ArgInfo.KernargSegmentPtr
220     = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
221     getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
222   NumUserSGPRs += 2;
223   return ArgInfo.KernargSegmentPtr.getRegister();
224 }
225 
226 Register SIMachineFunctionInfo::addDispatchID(const SIRegisterInfo &TRI) {
227   ArgInfo.DispatchID = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
228     getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
229   NumUserSGPRs += 2;
230   return ArgInfo.DispatchID.getRegister();
231 }
232 
233 Register SIMachineFunctionInfo::addFlatScratchInit(const SIRegisterInfo &TRI) {
234   ArgInfo.FlatScratchInit = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
235     getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
236   NumUserSGPRs += 2;
237   return ArgInfo.FlatScratchInit.getRegister();
238 }
239 
240 Register SIMachineFunctionInfo::addImplicitBufferPtr(const SIRegisterInfo &TRI) {
241   ArgInfo.ImplicitBufferPtr = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
242     getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
243   NumUserSGPRs += 2;
244   return ArgInfo.ImplicitBufferPtr.getRegister();
245 }
246 
247 bool SIMachineFunctionInfo::isCalleeSavedReg(const MCPhysReg *CSRegs,
248                                              MCPhysReg Reg) {
249   for (unsigned I = 0; CSRegs[I]; ++I) {
250     if (CSRegs[I] == Reg)
251       return true;
252   }
253 
254   return false;
255 }
256 
257 /// \p returns true if \p NumLanes slots are available in VGPRs already used for
258 /// SGPR spilling.
259 //
260 // FIXME: This only works after processFunctionBeforeFrameFinalized
261 bool SIMachineFunctionInfo::haveFreeLanesForSGPRSpill(const MachineFunction &MF,
262                                                       unsigned NumNeed) const {
263   const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
264   unsigned WaveSize = ST.getWavefrontSize();
265   return NumVGPRSpillLanes + NumNeed <= WaveSize * SpillVGPRs.size();
266 }
267 
268 /// Reserve a slice of a VGPR to support spilling for FrameIndex \p FI.
269 bool SIMachineFunctionInfo::allocateSGPRSpillToVGPR(MachineFunction &MF,
270                                                     int FI) {
271   std::vector<SpilledReg> &SpillLanes = SGPRToVGPRSpills[FI];
272 
273   // This has already been allocated.
274   if (!SpillLanes.empty())
275     return true;
276 
277   const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
278   const SIRegisterInfo *TRI = ST.getRegisterInfo();
279   MachineFrameInfo &FrameInfo = MF.getFrameInfo();
280   MachineRegisterInfo &MRI = MF.getRegInfo();
281   unsigned WaveSize = ST.getWavefrontSize();
282   SIMachineFunctionInfo *FuncInfo = MF.getInfo<SIMachineFunctionInfo>();
283 
284   unsigned Size = FrameInfo.getObjectSize(FI);
285   unsigned NumLanes = Size / 4;
286 
287   if (NumLanes > WaveSize)
288     return false;
289 
290   assert(Size >= 4 && "invalid sgpr spill size");
291   assert(TRI->spillSGPRToVGPR() && "not spilling SGPRs to VGPRs");
292 
293   // Make sure to handle the case where a wide SGPR spill may span between two
294   // VGPRs.
295   for (unsigned I = 0; I < NumLanes; ++I, ++NumVGPRSpillLanes) {
296     Register LaneVGPR;
297     unsigned VGPRIndex = (NumVGPRSpillLanes % WaveSize);
298 
299     // Reserve a VGPR (when NumVGPRSpillLanes = 0, WaveSize, 2*WaveSize, ..) and
300     // when one of the two conditions is true:
301     // 1. One reserved VGPR being tracked by VGPRReservedForSGPRSpill is not yet
302     // reserved.
303     // 2. All spill lanes of reserved VGPR(s) are full and another spill lane is
304     // required.
305     if (FuncInfo->VGPRReservedForSGPRSpill && NumVGPRSpillLanes < WaveSize) {
306       assert(FuncInfo->VGPRReservedForSGPRSpill == SpillVGPRs.back().VGPR);
307       LaneVGPR = FuncInfo->VGPRReservedForSGPRSpill;
308     } else if (VGPRIndex == 0) {
309       LaneVGPR = TRI->findUnusedRegister(MRI, &AMDGPU::VGPR_32RegClass, MF);
310       if (LaneVGPR == AMDGPU::NoRegister) {
311         // We have no VGPRs left for spilling SGPRs. Reset because we will not
312         // partially spill the SGPR to VGPRs.
313         SGPRToVGPRSpills.erase(FI);
314         NumVGPRSpillLanes -= I;
315         return false;
316       }
317 
318       Optional<int> SpillFI;
319       // We need to preserve inactive lanes, so always save, even caller-save
320       // registers.
321       if (!isEntryFunction()) {
322         SpillFI = FrameInfo.CreateSpillStackObject(4, Align(4));
323       }
324 
325       SpillVGPRs.push_back(SGPRSpillVGPR(LaneVGPR, SpillFI));
326 
327       // Add this register as live-in to all blocks to avoid machine verifer
328       // complaining about use of an undefined physical register.
329       for (MachineBasicBlock &BB : MF)
330         BB.addLiveIn(LaneVGPR);
331     } else {
332       LaneVGPR = SpillVGPRs.back().VGPR;
333     }
334 
335     SpillLanes.push_back(SpilledReg(LaneVGPR, VGPRIndex));
336   }
337 
338   return true;
339 }
340 
341 /// Reserve a VGPR for spilling of SGPRs
342 bool SIMachineFunctionInfo::reserveVGPRforSGPRSpills(MachineFunction &MF) {
343   const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
344   const SIRegisterInfo *TRI = ST.getRegisterInfo();
345   SIMachineFunctionInfo *FuncInfo = MF.getInfo<SIMachineFunctionInfo>();
346 
347   Register LaneVGPR = TRI->findUnusedRegister(
348       MF.getRegInfo(), &AMDGPU::VGPR_32RegClass, MF, true);
349   if (LaneVGPR == Register())
350     return false;
351   SpillVGPRs.push_back(SGPRSpillVGPR(LaneVGPR, None));
352   FuncInfo->VGPRReservedForSGPRSpill = LaneVGPR;
353   return true;
354 }
355 
356 /// Reserve AGPRs or VGPRs to support spilling for FrameIndex \p FI.
357 /// Either AGPR is spilled to VGPR to vice versa.
358 /// Returns true if a \p FI can be eliminated completely.
359 bool SIMachineFunctionInfo::allocateVGPRSpillToAGPR(MachineFunction &MF,
360                                                     int FI,
361                                                     bool isAGPRtoVGPR) {
362   MachineRegisterInfo &MRI = MF.getRegInfo();
363   MachineFrameInfo &FrameInfo = MF.getFrameInfo();
364   const GCNSubtarget &ST =  MF.getSubtarget<GCNSubtarget>();
365 
366   assert(ST.hasMAIInsts() && FrameInfo.isSpillSlotObjectIndex(FI));
367 
368   auto &Spill = VGPRToAGPRSpills[FI];
369 
370   // This has already been allocated.
371   if (!Spill.Lanes.empty())
372     return Spill.FullyAllocated;
373 
374   unsigned Size = FrameInfo.getObjectSize(FI);
375   unsigned NumLanes = Size / 4;
376   Spill.Lanes.resize(NumLanes, AMDGPU::NoRegister);
377 
378   const TargetRegisterClass &RC =
379       isAGPRtoVGPR ? AMDGPU::VGPR_32RegClass : AMDGPU::AGPR_32RegClass;
380   auto Regs = RC.getRegisters();
381 
382   auto &SpillRegs = isAGPRtoVGPR ? SpillAGPR : SpillVGPR;
383   const SIRegisterInfo *TRI = ST.getRegisterInfo();
384   Spill.FullyAllocated = true;
385 
386   // FIXME: Move allocation logic out of MachineFunctionInfo and initialize
387   // once.
388   BitVector OtherUsedRegs;
389   OtherUsedRegs.resize(TRI->getNumRegs());
390 
391   const uint32_t *CSRMask =
392       TRI->getCallPreservedMask(MF, MF.getFunction().getCallingConv());
393   if (CSRMask)
394     OtherUsedRegs.setBitsInMask(CSRMask);
395 
396   // TODO: Should include register tuples, but doesn't matter with current
397   // usage.
398   for (MCPhysReg Reg : SpillAGPR)
399     OtherUsedRegs.set(Reg);
400   for (MCPhysReg Reg : SpillVGPR)
401     OtherUsedRegs.set(Reg);
402 
403   SmallVectorImpl<MCPhysReg>::const_iterator NextSpillReg = Regs.begin();
404   for (unsigned I = 0; I < NumLanes; ++I) {
405     NextSpillReg = std::find_if(
406         NextSpillReg, Regs.end(), [&MRI, &OtherUsedRegs](MCPhysReg Reg) {
407           return MRI.isAllocatable(Reg) && !MRI.isPhysRegUsed(Reg) &&
408                  !OtherUsedRegs[Reg];
409         });
410 
411     if (NextSpillReg == Regs.end()) { // Registers exhausted
412       Spill.FullyAllocated = false;
413       break;
414     }
415 
416     OtherUsedRegs.set(*NextSpillReg);
417     SpillRegs.push_back(*NextSpillReg);
418     Spill.Lanes[I] = *NextSpillReg++;
419   }
420 
421   return Spill.FullyAllocated;
422 }
423 
424 void SIMachineFunctionInfo::removeDeadFrameIndices(MachineFrameInfo &MFI) {
425   // The FP & BP spills haven't been inserted yet, so keep them around.
426   for (auto &R : SGPRToVGPRSpills) {
427     if (R.first != FramePointerSaveIndex && R.first != BasePointerSaveIndex)
428       MFI.RemoveStackObject(R.first);
429   }
430 
431   // All other SPGRs must be allocated on the default stack, so reset the stack
432   // ID.
433   for (int i = MFI.getObjectIndexBegin(), e = MFI.getObjectIndexEnd(); i != e;
434        ++i)
435     if (i != FramePointerSaveIndex && i != BasePointerSaveIndex)
436       MFI.setStackID(i, TargetStackID::Default);
437 
438   for (auto &R : VGPRToAGPRSpills) {
439     if (R.second.FullyAllocated)
440       MFI.RemoveStackObject(R.first);
441   }
442 }
443 
444 int SIMachineFunctionInfo::getScavengeFI(MachineFrameInfo &MFI,
445                                          const SIRegisterInfo &TRI) {
446   if (ScavengeFI)
447     return *ScavengeFI;
448   if (isEntryFunction()) {
449     ScavengeFI = MFI.CreateFixedObject(
450         TRI.getSpillSize(AMDGPU::SGPR_32RegClass), 0, false);
451   } else {
452     ScavengeFI = MFI.CreateStackObject(
453         TRI.getSpillSize(AMDGPU::SGPR_32RegClass),
454         TRI.getSpillAlign(AMDGPU::SGPR_32RegClass), false);
455   }
456   return *ScavengeFI;
457 }
458 
459 MCPhysReg SIMachineFunctionInfo::getNextUserSGPR() const {
460   assert(NumSystemSGPRs == 0 && "System SGPRs must be added after user SGPRs");
461   return AMDGPU::SGPR0 + NumUserSGPRs;
462 }
463 
464 MCPhysReg SIMachineFunctionInfo::getNextSystemSGPR() const {
465   return AMDGPU::SGPR0 + NumUserSGPRs + NumSystemSGPRs;
466 }
467 
468 Register
469 SIMachineFunctionInfo::getGITPtrLoReg(const MachineFunction &MF) const {
470   const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
471   if (!ST.isAmdPalOS())
472     return Register();
473   Register GitPtrLo = AMDGPU::SGPR0; // Low GIT address passed in
474   if (ST.hasMergedShaders()) {
475     switch (MF.getFunction().getCallingConv()) {
476     case CallingConv::AMDGPU_HS:
477     case CallingConv::AMDGPU_GS:
478       // Low GIT address is passed in s8 rather than s0 for an LS+HS or
479       // ES+GS merged shader on gfx9+.
480       GitPtrLo = AMDGPU::SGPR8;
481       return GitPtrLo;
482     default:
483       return GitPtrLo;
484     }
485   }
486   return GitPtrLo;
487 }
488 
489 static yaml::StringValue regToString(Register Reg,
490                                      const TargetRegisterInfo &TRI) {
491   yaml::StringValue Dest;
492   {
493     raw_string_ostream OS(Dest.Value);
494     OS << printReg(Reg, &TRI);
495   }
496   return Dest;
497 }
498 
499 static Optional<yaml::SIArgumentInfo>
500 convertArgumentInfo(const AMDGPUFunctionArgInfo &ArgInfo,
501                     const TargetRegisterInfo &TRI) {
502   yaml::SIArgumentInfo AI;
503 
504   auto convertArg = [&](Optional<yaml::SIArgument> &A,
505                         const ArgDescriptor &Arg) {
506     if (!Arg)
507       return false;
508 
509     // Create a register or stack argument.
510     yaml::SIArgument SA = yaml::SIArgument::createArgument(Arg.isRegister());
511     if (Arg.isRegister()) {
512       raw_string_ostream OS(SA.RegisterName.Value);
513       OS << printReg(Arg.getRegister(), &TRI);
514     } else
515       SA.StackOffset = Arg.getStackOffset();
516     // Check and update the optional mask.
517     if (Arg.isMasked())
518       SA.Mask = Arg.getMask();
519 
520     A = SA;
521     return true;
522   };
523 
524   bool Any = false;
525   Any |= convertArg(AI.PrivateSegmentBuffer, ArgInfo.PrivateSegmentBuffer);
526   Any |= convertArg(AI.DispatchPtr, ArgInfo.DispatchPtr);
527   Any |= convertArg(AI.QueuePtr, ArgInfo.QueuePtr);
528   Any |= convertArg(AI.KernargSegmentPtr, ArgInfo.KernargSegmentPtr);
529   Any |= convertArg(AI.DispatchID, ArgInfo.DispatchID);
530   Any |= convertArg(AI.FlatScratchInit, ArgInfo.FlatScratchInit);
531   Any |= convertArg(AI.PrivateSegmentSize, ArgInfo.PrivateSegmentSize);
532   Any |= convertArg(AI.WorkGroupIDX, ArgInfo.WorkGroupIDX);
533   Any |= convertArg(AI.WorkGroupIDY, ArgInfo.WorkGroupIDY);
534   Any |= convertArg(AI.WorkGroupIDZ, ArgInfo.WorkGroupIDZ);
535   Any |= convertArg(AI.WorkGroupInfo, ArgInfo.WorkGroupInfo);
536   Any |= convertArg(AI.PrivateSegmentWaveByteOffset,
537                     ArgInfo.PrivateSegmentWaveByteOffset);
538   Any |= convertArg(AI.ImplicitArgPtr, ArgInfo.ImplicitArgPtr);
539   Any |= convertArg(AI.ImplicitBufferPtr, ArgInfo.ImplicitBufferPtr);
540   Any |= convertArg(AI.WorkItemIDX, ArgInfo.WorkItemIDX);
541   Any |= convertArg(AI.WorkItemIDY, ArgInfo.WorkItemIDY);
542   Any |= convertArg(AI.WorkItemIDZ, ArgInfo.WorkItemIDZ);
543 
544   if (Any)
545     return AI;
546 
547   return None;
548 }
549 
550 yaml::SIMachineFunctionInfo::SIMachineFunctionInfo(
551     const llvm::SIMachineFunctionInfo &MFI, const TargetRegisterInfo &TRI,
552     const llvm::MachineFunction &MF)
553     : ExplicitKernArgSize(MFI.getExplicitKernArgSize()),
554       MaxKernArgAlign(MFI.getMaxKernArgAlign()), LDSSize(MFI.getLDSSize()),
555       DynLDSAlign(MFI.getDynLDSAlign()), IsEntryFunction(MFI.isEntryFunction()),
556       NoSignedZerosFPMath(MFI.hasNoSignedZerosFPMath()),
557       MemoryBound(MFI.isMemoryBound()), WaveLimiter(MFI.needsWaveLimiter()),
558       HasSpilledSGPRs(MFI.hasSpilledSGPRs()),
559       HasSpilledVGPRs(MFI.hasSpilledVGPRs()),
560       HighBitsOf32BitAddress(MFI.get32BitAddressHighBits()),
561       Occupancy(MFI.getOccupancy()),
562       ScratchRSrcReg(regToString(MFI.getScratchRSrcReg(), TRI)),
563       FrameOffsetReg(regToString(MFI.getFrameOffsetReg(), TRI)),
564       StackPtrOffsetReg(regToString(MFI.getStackPtrOffsetReg(), TRI)),
565       ArgInfo(convertArgumentInfo(MFI.getArgInfo(), TRI)), Mode(MFI.getMode()) {
566   auto SFI = MFI.getOptionalScavengeFI();
567   if (SFI)
568     ScavengeFI = yaml::FrameIndex(*SFI, MF.getFrameInfo());
569 }
570 
571 void yaml::SIMachineFunctionInfo::mappingImpl(yaml::IO &YamlIO) {
572   MappingTraits<SIMachineFunctionInfo>::mapping(YamlIO, *this);
573 }
574 
575 bool SIMachineFunctionInfo::initializeBaseYamlFields(
576     const yaml::SIMachineFunctionInfo &YamlMFI, const MachineFunction &MF,
577     PerFunctionMIParsingState &PFS, SMDiagnostic &Error, SMRange &SourceRange) {
578   ExplicitKernArgSize = YamlMFI.ExplicitKernArgSize;
579   MaxKernArgAlign = assumeAligned(YamlMFI.MaxKernArgAlign);
580   LDSSize = YamlMFI.LDSSize;
581   DynLDSAlign = YamlMFI.DynLDSAlign;
582   HighBitsOf32BitAddress = YamlMFI.HighBitsOf32BitAddress;
583   Occupancy = YamlMFI.Occupancy;
584   IsEntryFunction = YamlMFI.IsEntryFunction;
585   NoSignedZerosFPMath = YamlMFI.NoSignedZerosFPMath;
586   MemoryBound = YamlMFI.MemoryBound;
587   WaveLimiter = YamlMFI.WaveLimiter;
588   HasSpilledSGPRs = YamlMFI.HasSpilledSGPRs;
589   HasSpilledVGPRs = YamlMFI.HasSpilledVGPRs;
590 
591   if (YamlMFI.ScavengeFI) {
592     auto FIOrErr = YamlMFI.ScavengeFI->getFI(MF.getFrameInfo());
593     if (!FIOrErr) {
594       // Create a diagnostic for a the frame index.
595       const MemoryBuffer &Buffer =
596           *PFS.SM->getMemoryBuffer(PFS.SM->getMainFileID());
597 
598       Error = SMDiagnostic(*PFS.SM, SMLoc(), Buffer.getBufferIdentifier(), 1, 1,
599                            SourceMgr::DK_Error, toString(FIOrErr.takeError()),
600                            "", None, None);
601       SourceRange = YamlMFI.ScavengeFI->SourceRange;
602       return true;
603     }
604     ScavengeFI = *FIOrErr;
605   } else {
606     ScavengeFI = None;
607   }
608   return false;
609 }
610 
611 // Remove VGPR which was reserved for SGPR spills if there are no spilled SGPRs
612 bool SIMachineFunctionInfo::removeVGPRForSGPRSpill(Register ReservedVGPR,
613                                                    MachineFunction &MF) {
614   for (auto *i = SpillVGPRs.begin(); i < SpillVGPRs.end(); i++) {
615     if (i->VGPR == ReservedVGPR) {
616       SpillVGPRs.erase(i);
617 
618       for (MachineBasicBlock &MBB : MF) {
619         MBB.removeLiveIn(ReservedVGPR);
620         MBB.sortUniqueLiveIns();
621       }
622       this->VGPRReservedForSGPRSpill = AMDGPU::NoRegister;
623       return true;
624     }
625   }
626   return false;
627 }
628