1 //===- SIMachineFunctionInfo.cpp - SI Machine Function Info ---------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #include "SIMachineFunctionInfo.h"
10 #include "AMDGPUTargetMachine.h"
11 #include "AMDGPUSubtarget.h"
12 #include "SIRegisterInfo.h"
13 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
14 #include "Utils/AMDGPUBaseInfo.h"
15 #include "llvm/ADT/Optional.h"
16 #include "llvm/CodeGen/LiveIntervals.h"
17 #include "llvm/CodeGen/MachineBasicBlock.h"
18 #include "llvm/CodeGen/MachineFrameInfo.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/MachineRegisterInfo.h"
21 #include "llvm/CodeGen/MIRParser/MIParser.h"
22 #include "llvm/IR/CallingConv.h"
23 #include "llvm/IR/DiagnosticInfo.h"
24 #include "llvm/IR/Function.h"
25 #include <cassert>
26 #include <vector>
27 
28 #define MAX_LANES 64
29 
30 using namespace llvm;
31 
32 SIMachineFunctionInfo::SIMachineFunctionInfo(const MachineFunction &MF)
33   : AMDGPUMachineFunction(MF),
34     PrivateSegmentBuffer(false),
35     DispatchPtr(false),
36     QueuePtr(false),
37     KernargSegmentPtr(false),
38     DispatchID(false),
39     FlatScratchInit(false),
40     WorkGroupIDX(false),
41     WorkGroupIDY(false),
42     WorkGroupIDZ(false),
43     WorkGroupInfo(false),
44     PrivateSegmentWaveByteOffset(false),
45     WorkItemIDX(false),
46     WorkItemIDY(false),
47     WorkItemIDZ(false),
48     ImplicitBufferPtr(false),
49     ImplicitArgPtr(false),
50     GITPtrHigh(0xffffffff),
51     HighBitsOf32BitAddress(0),
52     GDSSize(0) {
53   const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
54   const Function &F = MF.getFunction();
55   FlatWorkGroupSizes = ST.getFlatWorkGroupSizes(F);
56   WavesPerEU = ST.getWavesPerEU(F);
57 
58   Occupancy = ST.computeOccupancy(F, getLDSSize());
59   CallingConv::ID CC = F.getCallingConv();
60 
61   // FIXME: Should have analysis or something rather than attribute to detect
62   // calls.
63   const bool HasCalls = F.hasFnAttribute("amdgpu-calls");
64 
65   const bool IsKernel = CC == CallingConv::AMDGPU_KERNEL ||
66                         CC == CallingConv::SPIR_KERNEL;
67 
68   if (IsKernel) {
69     if (!F.arg_empty() || ST.getImplicitArgNumBytes(F) != 0)
70       KernargSegmentPtr = true;
71     WorkGroupIDX = true;
72     WorkItemIDX = true;
73   } else if (CC == CallingConv::AMDGPU_PS) {
74     PSInputAddr = AMDGPU::getInitialPSInputAddr(F);
75   }
76 
77   if (!isEntryFunction()) {
78     if (CC != CallingConv::AMDGPU_Gfx)
79       ArgInfo = AMDGPUArgumentUsageInfo::FixedABIFunctionInfo;
80 
81     // TODO: Pick a high register, and shift down, similar to a kernel.
82     FrameOffsetReg = AMDGPU::SGPR33;
83     StackPtrOffsetReg = AMDGPU::SGPR32;
84 
85     if (!ST.enableFlatScratch()) {
86       // Non-entry functions have no special inputs for now, other registers
87       // required for scratch access.
88       ScratchRSrcReg = AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3;
89 
90       ArgInfo.PrivateSegmentBuffer =
91         ArgDescriptor::createRegister(ScratchRSrcReg);
92     }
93 
94     if (!F.hasFnAttribute("amdgpu-no-implicitarg-ptr"))
95       ImplicitArgPtr = true;
96   } else {
97     ImplicitArgPtr = false;
98     MaxKernArgAlign = std::max(ST.getAlignmentForImplicitArgPtr(),
99                                MaxKernArgAlign);
100   }
101 
102   bool isAmdHsaOrMesa = ST.isAmdHsaOrMesa(F);
103   if (isAmdHsaOrMesa && !ST.enableFlatScratch())
104     PrivateSegmentBuffer = true;
105   else if (ST.isMesaGfxShader(F))
106     ImplicitBufferPtr = true;
107 
108   if (!AMDGPU::isGraphics(CC)) {
109     if (IsKernel || !F.hasFnAttribute("amdgpu-no-workgroup-id-x"))
110       WorkGroupIDX = true;
111 
112     if (!F.hasFnAttribute("amdgpu-no-workgroup-id-y"))
113       WorkGroupIDY = true;
114 
115     if (!F.hasFnAttribute("amdgpu-no-workgroup-id-z"))
116       WorkGroupIDZ = true;
117 
118     if (IsKernel || !F.hasFnAttribute("amdgpu-no-workitem-id-x"))
119       WorkItemIDX = true;
120 
121     if (!F.hasFnAttribute("amdgpu-no-workitem-id-y"))
122       WorkItemIDY = true;
123 
124     if (!F.hasFnAttribute("amdgpu-no-workitem-id-z"))
125       WorkItemIDZ = true;
126 
127     if (!F.hasFnAttribute("amdgpu-no-dispatch-ptr"))
128       DispatchPtr = true;
129 
130     if (!F.hasFnAttribute("amdgpu-no-queue-ptr"))
131       QueuePtr = true;
132 
133     if (!F.hasFnAttribute("amdgpu-no-dispatch-id"))
134       DispatchID = true;
135   }
136 
137   // FIXME: This attribute is a hack, we just need an analysis on the function
138   // to look for allocas.
139   bool HasStackObjects = F.hasFnAttribute("amdgpu-stack-objects");
140 
141   // TODO: This could be refined a lot. The attribute is a poor way of
142   // detecting calls or stack objects that may require it before argument
143   // lowering.
144   if (ST.hasFlatAddressSpace() && isEntryFunction() &&
145       (isAmdHsaOrMesa || ST.enableFlatScratch()) &&
146       (HasCalls || HasStackObjects || ST.enableFlatScratch()) &&
147       !ST.flatScratchIsArchitected()) {
148     FlatScratchInit = true;
149   }
150 
151   if (isEntryFunction()) {
152     // X, XY, and XYZ are the only supported combinations, so make sure Y is
153     // enabled if Z is.
154     if (WorkItemIDZ)
155       WorkItemIDY = true;
156 
157     if (!ST.flatScratchIsArchitected()) {
158       PrivateSegmentWaveByteOffset = true;
159 
160       // HS and GS always have the scratch wave offset in SGPR5 on GFX9.
161       if (ST.getGeneration() >= AMDGPUSubtarget::GFX9 &&
162           (CC == CallingConv::AMDGPU_HS || CC == CallingConv::AMDGPU_GS))
163         ArgInfo.PrivateSegmentWaveByteOffset =
164             ArgDescriptor::createRegister(AMDGPU::SGPR5);
165     }
166   }
167 
168   Attribute A = F.getFnAttribute("amdgpu-git-ptr-high");
169   StringRef S = A.getValueAsString();
170   if (!S.empty())
171     S.consumeInteger(0, GITPtrHigh);
172 
173   A = F.getFnAttribute("amdgpu-32bit-address-high-bits");
174   S = A.getValueAsString();
175   if (!S.empty())
176     S.consumeInteger(0, HighBitsOf32BitAddress);
177 
178   S = F.getFnAttribute("amdgpu-gds-size").getValueAsString();
179   if (!S.empty())
180     S.consumeInteger(0, GDSSize);
181 }
182 
183 void SIMachineFunctionInfo::limitOccupancy(const MachineFunction &MF) {
184   limitOccupancy(getMaxWavesPerEU());
185   const GCNSubtarget& ST = MF.getSubtarget<GCNSubtarget>();
186   limitOccupancy(ST.getOccupancyWithLocalMemSize(getLDSSize(),
187                  MF.getFunction()));
188 }
189 
190 Register SIMachineFunctionInfo::addPrivateSegmentBuffer(
191   const SIRegisterInfo &TRI) {
192   ArgInfo.PrivateSegmentBuffer =
193     ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
194     getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SGPR_128RegClass));
195   NumUserSGPRs += 4;
196   return ArgInfo.PrivateSegmentBuffer.getRegister();
197 }
198 
199 Register SIMachineFunctionInfo::addDispatchPtr(const SIRegisterInfo &TRI) {
200   ArgInfo.DispatchPtr = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
201     getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
202   NumUserSGPRs += 2;
203   return ArgInfo.DispatchPtr.getRegister();
204 }
205 
206 Register SIMachineFunctionInfo::addQueuePtr(const SIRegisterInfo &TRI) {
207   ArgInfo.QueuePtr = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
208     getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
209   NumUserSGPRs += 2;
210   return ArgInfo.QueuePtr.getRegister();
211 }
212 
213 Register SIMachineFunctionInfo::addKernargSegmentPtr(const SIRegisterInfo &TRI) {
214   ArgInfo.KernargSegmentPtr
215     = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
216     getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
217   NumUserSGPRs += 2;
218   return ArgInfo.KernargSegmentPtr.getRegister();
219 }
220 
221 Register SIMachineFunctionInfo::addDispatchID(const SIRegisterInfo &TRI) {
222   ArgInfo.DispatchID = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
223     getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
224   NumUserSGPRs += 2;
225   return ArgInfo.DispatchID.getRegister();
226 }
227 
228 Register SIMachineFunctionInfo::addFlatScratchInit(const SIRegisterInfo &TRI) {
229   ArgInfo.FlatScratchInit = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
230     getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
231   NumUserSGPRs += 2;
232   return ArgInfo.FlatScratchInit.getRegister();
233 }
234 
235 Register SIMachineFunctionInfo::addImplicitBufferPtr(const SIRegisterInfo &TRI) {
236   ArgInfo.ImplicitBufferPtr = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
237     getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
238   NumUserSGPRs += 2;
239   return ArgInfo.ImplicitBufferPtr.getRegister();
240 }
241 
242 bool SIMachineFunctionInfo::isCalleeSavedReg(const MCPhysReg *CSRegs,
243                                              MCPhysReg Reg) {
244   for (unsigned I = 0; CSRegs[I]; ++I) {
245     if (CSRegs[I] == Reg)
246       return true;
247   }
248 
249   return false;
250 }
251 
252 /// \p returns true if \p NumLanes slots are available in VGPRs already used for
253 /// SGPR spilling.
254 //
255 // FIXME: This only works after processFunctionBeforeFrameFinalized
256 bool SIMachineFunctionInfo::haveFreeLanesForSGPRSpill(const MachineFunction &MF,
257                                                       unsigned NumNeed) const {
258   const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
259   unsigned WaveSize = ST.getWavefrontSize();
260   return NumVGPRSpillLanes + NumNeed <= WaveSize * SpillVGPRs.size();
261 }
262 
263 /// Reserve a slice of a VGPR to support spilling for FrameIndex \p FI.
264 bool SIMachineFunctionInfo::allocateSGPRSpillToVGPR(MachineFunction &MF,
265                                                     int FI) {
266   std::vector<SpilledReg> &SpillLanes = SGPRToVGPRSpills[FI];
267 
268   // This has already been allocated.
269   if (!SpillLanes.empty())
270     return true;
271 
272   const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
273   const SIRegisterInfo *TRI = ST.getRegisterInfo();
274   MachineFrameInfo &FrameInfo = MF.getFrameInfo();
275   MachineRegisterInfo &MRI = MF.getRegInfo();
276   unsigned WaveSize = ST.getWavefrontSize();
277 
278   unsigned Size = FrameInfo.getObjectSize(FI);
279   unsigned NumLanes = Size / 4;
280 
281   if (NumLanes > WaveSize)
282     return false;
283 
284   assert(Size >= 4 && "invalid sgpr spill size");
285   assert(TRI->spillSGPRToVGPR() && "not spilling SGPRs to VGPRs");
286 
287   // Make sure to handle the case where a wide SGPR spill may span between two
288   // VGPRs.
289   for (unsigned I = 0; I < NumLanes; ++I, ++NumVGPRSpillLanes) {
290     Register LaneVGPR;
291     unsigned VGPRIndex = (NumVGPRSpillLanes % WaveSize);
292 
293     if (VGPRIndex == 0) {
294       LaneVGPR = TRI->findUnusedRegister(MRI, &AMDGPU::VGPR_32RegClass, MF);
295       if (LaneVGPR == AMDGPU::NoRegister) {
296         // We have no VGPRs left for spilling SGPRs. Reset because we will not
297         // partially spill the SGPR to VGPRs.
298         SGPRToVGPRSpills.erase(FI);
299         NumVGPRSpillLanes -= I;
300 
301         // FIXME: We can run out of free registers with split allocation if
302         // IPRA is enabled and a called function already uses every VGPR.
303 #if 0
304         DiagnosticInfoResourceLimit DiagOutOfRegs(MF.getFunction(),
305                                                   "VGPRs for SGPR spilling",
306                                                   0, DS_Error);
307         MF.getFunction().getContext().diagnose(DiagOutOfRegs);
308 #endif
309         return false;
310       }
311 
312       Optional<int> SpillFI;
313       // We need to preserve inactive lanes, so always save, even caller-save
314       // registers.
315       if (!isEntryFunction()) {
316         SpillFI = FrameInfo.CreateSpillStackObject(4, Align(4));
317       }
318 
319       SpillVGPRs.push_back(SGPRSpillVGPR(LaneVGPR, SpillFI));
320 
321       // Add this register as live-in to all blocks to avoid machine verifer
322       // complaining about use of an undefined physical register.
323       for (MachineBasicBlock &BB : MF)
324         BB.addLiveIn(LaneVGPR);
325     } else {
326       LaneVGPR = SpillVGPRs.back().VGPR;
327     }
328 
329     SpillLanes.push_back(SpilledReg(LaneVGPR, VGPRIndex));
330   }
331 
332   return true;
333 }
334 
335 /// Reserve AGPRs or VGPRs to support spilling for FrameIndex \p FI.
336 /// Either AGPR is spilled to VGPR to vice versa.
337 /// Returns true if a \p FI can be eliminated completely.
338 bool SIMachineFunctionInfo::allocateVGPRSpillToAGPR(MachineFunction &MF,
339                                                     int FI,
340                                                     bool isAGPRtoVGPR) {
341   MachineRegisterInfo &MRI = MF.getRegInfo();
342   MachineFrameInfo &FrameInfo = MF.getFrameInfo();
343   const GCNSubtarget &ST =  MF.getSubtarget<GCNSubtarget>();
344 
345   assert(ST.hasMAIInsts() && FrameInfo.isSpillSlotObjectIndex(FI));
346 
347   auto &Spill = VGPRToAGPRSpills[FI];
348 
349   // This has already been allocated.
350   if (!Spill.Lanes.empty())
351     return Spill.FullyAllocated;
352 
353   unsigned Size = FrameInfo.getObjectSize(FI);
354   unsigned NumLanes = Size / 4;
355   Spill.Lanes.resize(NumLanes, AMDGPU::NoRegister);
356 
357   const TargetRegisterClass &RC =
358       isAGPRtoVGPR ? AMDGPU::VGPR_32RegClass : AMDGPU::AGPR_32RegClass;
359   auto Regs = RC.getRegisters();
360 
361   auto &SpillRegs = isAGPRtoVGPR ? SpillAGPR : SpillVGPR;
362   const SIRegisterInfo *TRI = ST.getRegisterInfo();
363   Spill.FullyAllocated = true;
364 
365   // FIXME: Move allocation logic out of MachineFunctionInfo and initialize
366   // once.
367   BitVector OtherUsedRegs;
368   OtherUsedRegs.resize(TRI->getNumRegs());
369 
370   const uint32_t *CSRMask =
371       TRI->getCallPreservedMask(MF, MF.getFunction().getCallingConv());
372   if (CSRMask)
373     OtherUsedRegs.setBitsInMask(CSRMask);
374 
375   // TODO: Should include register tuples, but doesn't matter with current
376   // usage.
377   for (MCPhysReg Reg : SpillAGPR)
378     OtherUsedRegs.set(Reg);
379   for (MCPhysReg Reg : SpillVGPR)
380     OtherUsedRegs.set(Reg);
381 
382   SmallVectorImpl<MCPhysReg>::const_iterator NextSpillReg = Regs.begin();
383   for (int I = NumLanes - 1; I >= 0; --I) {
384     NextSpillReg = std::find_if(
385         NextSpillReg, Regs.end(), [&MRI, &OtherUsedRegs](MCPhysReg Reg) {
386           return MRI.isAllocatable(Reg) && !MRI.isPhysRegUsed(Reg) &&
387                  !OtherUsedRegs[Reg];
388         });
389 
390     if (NextSpillReg == Regs.end()) { // Registers exhausted
391       Spill.FullyAllocated = false;
392       break;
393     }
394 
395     OtherUsedRegs.set(*NextSpillReg);
396     SpillRegs.push_back(*NextSpillReg);
397     Spill.Lanes[I] = *NextSpillReg++;
398   }
399 
400   return Spill.FullyAllocated;
401 }
402 
403 void SIMachineFunctionInfo::removeDeadFrameIndices(MachineFrameInfo &MFI) {
404   // Remove dead frame indices from function frame, however keep FP & BP since
405   // spills for them haven't been inserted yet. And also make sure to remove the
406   // frame indices from `SGPRToVGPRSpills` data structure, otherwise, it could
407   // result in an unexpected side effect and bug, in case of any re-mapping of
408   // freed frame indices by later pass(es) like "stack slot coloring".
409   for (auto &R : make_early_inc_range(SGPRToVGPRSpills)) {
410     if (R.first != FramePointerSaveIndex && R.first != BasePointerSaveIndex) {
411       MFI.RemoveStackObject(R.first);
412       SGPRToVGPRSpills.erase(R.first);
413     }
414   }
415 
416   // All other SPGRs must be allocated on the default stack, so reset the stack
417   // ID.
418   for (int i = MFI.getObjectIndexBegin(), e = MFI.getObjectIndexEnd(); i != e;
419        ++i)
420     if (i != FramePointerSaveIndex && i != BasePointerSaveIndex)
421       MFI.setStackID(i, TargetStackID::Default);
422 
423   for (auto &R : VGPRToAGPRSpills) {
424     if (R.second.IsDead)
425       MFI.RemoveStackObject(R.first);
426   }
427 }
428 
429 int SIMachineFunctionInfo::getScavengeFI(MachineFrameInfo &MFI,
430                                          const SIRegisterInfo &TRI) {
431   if (ScavengeFI)
432     return *ScavengeFI;
433   if (isEntryFunction()) {
434     ScavengeFI = MFI.CreateFixedObject(
435         TRI.getSpillSize(AMDGPU::SGPR_32RegClass), 0, false);
436   } else {
437     ScavengeFI = MFI.CreateStackObject(
438         TRI.getSpillSize(AMDGPU::SGPR_32RegClass),
439         TRI.getSpillAlign(AMDGPU::SGPR_32RegClass), false);
440   }
441   return *ScavengeFI;
442 }
443 
444 MCPhysReg SIMachineFunctionInfo::getNextUserSGPR() const {
445   assert(NumSystemSGPRs == 0 && "System SGPRs must be added after user SGPRs");
446   return AMDGPU::SGPR0 + NumUserSGPRs;
447 }
448 
449 MCPhysReg SIMachineFunctionInfo::getNextSystemSGPR() const {
450   return AMDGPU::SGPR0 + NumUserSGPRs + NumSystemSGPRs;
451 }
452 
453 Register
454 SIMachineFunctionInfo::getGITPtrLoReg(const MachineFunction &MF) const {
455   const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
456   if (!ST.isAmdPalOS())
457     return Register();
458   Register GitPtrLo = AMDGPU::SGPR0; // Low GIT address passed in
459   if (ST.hasMergedShaders()) {
460     switch (MF.getFunction().getCallingConv()) {
461     case CallingConv::AMDGPU_HS:
462     case CallingConv::AMDGPU_GS:
463       // Low GIT address is passed in s8 rather than s0 for an LS+HS or
464       // ES+GS merged shader on gfx9+.
465       GitPtrLo = AMDGPU::SGPR8;
466       return GitPtrLo;
467     default:
468       return GitPtrLo;
469     }
470   }
471   return GitPtrLo;
472 }
473 
474 static yaml::StringValue regToString(Register Reg,
475                                      const TargetRegisterInfo &TRI) {
476   yaml::StringValue Dest;
477   {
478     raw_string_ostream OS(Dest.Value);
479     OS << printReg(Reg, &TRI);
480   }
481   return Dest;
482 }
483 
484 static Optional<yaml::SIArgumentInfo>
485 convertArgumentInfo(const AMDGPUFunctionArgInfo &ArgInfo,
486                     const TargetRegisterInfo &TRI) {
487   yaml::SIArgumentInfo AI;
488 
489   auto convertArg = [&](Optional<yaml::SIArgument> &A,
490                         const ArgDescriptor &Arg) {
491     if (!Arg)
492       return false;
493 
494     // Create a register or stack argument.
495     yaml::SIArgument SA = yaml::SIArgument::createArgument(Arg.isRegister());
496     if (Arg.isRegister()) {
497       raw_string_ostream OS(SA.RegisterName.Value);
498       OS << printReg(Arg.getRegister(), &TRI);
499     } else
500       SA.StackOffset = Arg.getStackOffset();
501     // Check and update the optional mask.
502     if (Arg.isMasked())
503       SA.Mask = Arg.getMask();
504 
505     A = SA;
506     return true;
507   };
508 
509   bool Any = false;
510   Any |= convertArg(AI.PrivateSegmentBuffer, ArgInfo.PrivateSegmentBuffer);
511   Any |= convertArg(AI.DispatchPtr, ArgInfo.DispatchPtr);
512   Any |= convertArg(AI.QueuePtr, ArgInfo.QueuePtr);
513   Any |= convertArg(AI.KernargSegmentPtr, ArgInfo.KernargSegmentPtr);
514   Any |= convertArg(AI.DispatchID, ArgInfo.DispatchID);
515   Any |= convertArg(AI.FlatScratchInit, ArgInfo.FlatScratchInit);
516   Any |= convertArg(AI.PrivateSegmentSize, ArgInfo.PrivateSegmentSize);
517   Any |= convertArg(AI.WorkGroupIDX, ArgInfo.WorkGroupIDX);
518   Any |= convertArg(AI.WorkGroupIDY, ArgInfo.WorkGroupIDY);
519   Any |= convertArg(AI.WorkGroupIDZ, ArgInfo.WorkGroupIDZ);
520   Any |= convertArg(AI.WorkGroupInfo, ArgInfo.WorkGroupInfo);
521   Any |= convertArg(AI.PrivateSegmentWaveByteOffset,
522                     ArgInfo.PrivateSegmentWaveByteOffset);
523   Any |= convertArg(AI.ImplicitArgPtr, ArgInfo.ImplicitArgPtr);
524   Any |= convertArg(AI.ImplicitBufferPtr, ArgInfo.ImplicitBufferPtr);
525   Any |= convertArg(AI.WorkItemIDX, ArgInfo.WorkItemIDX);
526   Any |= convertArg(AI.WorkItemIDY, ArgInfo.WorkItemIDY);
527   Any |= convertArg(AI.WorkItemIDZ, ArgInfo.WorkItemIDZ);
528 
529   if (Any)
530     return AI;
531 
532   return None;
533 }
534 
535 yaml::SIMachineFunctionInfo::SIMachineFunctionInfo(
536     const llvm::SIMachineFunctionInfo &MFI, const TargetRegisterInfo &TRI,
537     const llvm::MachineFunction &MF)
538     : ExplicitKernArgSize(MFI.getExplicitKernArgSize()),
539       MaxKernArgAlign(MFI.getMaxKernArgAlign()), LDSSize(MFI.getLDSSize()),
540       DynLDSAlign(MFI.getDynLDSAlign()), IsEntryFunction(MFI.isEntryFunction()),
541       NoSignedZerosFPMath(MFI.hasNoSignedZerosFPMath()),
542       MemoryBound(MFI.isMemoryBound()), WaveLimiter(MFI.needsWaveLimiter()),
543       HasSpilledSGPRs(MFI.hasSpilledSGPRs()),
544       HasSpilledVGPRs(MFI.hasSpilledVGPRs()),
545       HighBitsOf32BitAddress(MFI.get32BitAddressHighBits()),
546       Occupancy(MFI.getOccupancy()),
547       ScratchRSrcReg(regToString(MFI.getScratchRSrcReg(), TRI)),
548       FrameOffsetReg(regToString(MFI.getFrameOffsetReg(), TRI)),
549       StackPtrOffsetReg(regToString(MFI.getStackPtrOffsetReg(), TRI)),
550       ArgInfo(convertArgumentInfo(MFI.getArgInfo(), TRI)), Mode(MFI.getMode()) {
551   auto SFI = MFI.getOptionalScavengeFI();
552   if (SFI)
553     ScavengeFI = yaml::FrameIndex(*SFI, MF.getFrameInfo());
554 }
555 
556 void yaml::SIMachineFunctionInfo::mappingImpl(yaml::IO &YamlIO) {
557   MappingTraits<SIMachineFunctionInfo>::mapping(YamlIO, *this);
558 }
559 
560 bool SIMachineFunctionInfo::initializeBaseYamlFields(
561     const yaml::SIMachineFunctionInfo &YamlMFI, const MachineFunction &MF,
562     PerFunctionMIParsingState &PFS, SMDiagnostic &Error, SMRange &SourceRange) {
563   ExplicitKernArgSize = YamlMFI.ExplicitKernArgSize;
564   MaxKernArgAlign = assumeAligned(YamlMFI.MaxKernArgAlign);
565   LDSSize = YamlMFI.LDSSize;
566   DynLDSAlign = YamlMFI.DynLDSAlign;
567   HighBitsOf32BitAddress = YamlMFI.HighBitsOf32BitAddress;
568   Occupancy = YamlMFI.Occupancy;
569   IsEntryFunction = YamlMFI.IsEntryFunction;
570   NoSignedZerosFPMath = YamlMFI.NoSignedZerosFPMath;
571   MemoryBound = YamlMFI.MemoryBound;
572   WaveLimiter = YamlMFI.WaveLimiter;
573   HasSpilledSGPRs = YamlMFI.HasSpilledSGPRs;
574   HasSpilledVGPRs = YamlMFI.HasSpilledVGPRs;
575 
576   if (YamlMFI.ScavengeFI) {
577     auto FIOrErr = YamlMFI.ScavengeFI->getFI(MF.getFrameInfo());
578     if (!FIOrErr) {
579       // Create a diagnostic for a the frame index.
580       const MemoryBuffer &Buffer =
581           *PFS.SM->getMemoryBuffer(PFS.SM->getMainFileID());
582 
583       Error = SMDiagnostic(*PFS.SM, SMLoc(), Buffer.getBufferIdentifier(), 1, 1,
584                            SourceMgr::DK_Error, toString(FIOrErr.takeError()),
585                            "", None, None);
586       SourceRange = YamlMFI.ScavengeFI->SourceRange;
587       return true;
588     }
589     ScavengeFI = *FIOrErr;
590   } else {
591     ScavengeFI = None;
592   }
593   return false;
594 }
595 
596 bool SIMachineFunctionInfo::usesAGPRs(const MachineFunction &MF) const {
597   if (UsesAGPRs)
598     return *UsesAGPRs;
599 
600   if (!AMDGPU::isEntryFunctionCC(MF.getFunction().getCallingConv()) ||
601       MF.getFrameInfo().hasCalls()) {
602     UsesAGPRs = true;
603     return true;
604   }
605 
606   const MachineRegisterInfo &MRI = MF.getRegInfo();
607 
608   for (unsigned I = 0, E = MRI.getNumVirtRegs(); I != E; ++I) {
609     const Register Reg = Register::index2VirtReg(I);
610     const TargetRegisterClass *RC = MRI.getRegClassOrNull(Reg);
611     if (RC && SIRegisterInfo::isAGPRClass(RC)) {
612       UsesAGPRs = true;
613       return true;
614     } else if (!RC && !MRI.use_empty(Reg) && MRI.getType(Reg).isValid()) {
615       // Defer caching UsesAGPRs, function might not yet been regbank selected.
616       return true;
617     }
618   }
619 
620   for (MCRegister Reg : AMDGPU::AGPR_32RegClass) {
621     if (MRI.isPhysRegUsed(Reg)) {
622       UsesAGPRs = true;
623       return true;
624     }
625   }
626 
627   UsesAGPRs = false;
628   return false;
629 }
630