1 //===- SIMachineFunctionInfo.cpp - SI Machine Function Info ---------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #include "SIMachineFunctionInfo.h"
10 #include "AMDGPUTargetMachine.h"
11 #include "AMDGPUSubtarget.h"
12 #include "SIRegisterInfo.h"
13 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
14 #include "Utils/AMDGPUBaseInfo.h"
15 #include "llvm/ADT/Optional.h"
16 #include "llvm/CodeGen/LiveIntervals.h"
17 #include "llvm/CodeGen/MachineBasicBlock.h"
18 #include "llvm/CodeGen/MachineFrameInfo.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/MachineRegisterInfo.h"
21 #include "llvm/CodeGen/MIRParser/MIParser.h"
22 #include "llvm/IR/CallingConv.h"
23 #include "llvm/IR/DiagnosticInfo.h"
24 #include "llvm/IR/Function.h"
25 #include <cassert>
26 #include <vector>
27 
28 #define MAX_LANES 64
29 
30 using namespace llvm;
31 
32 SIMachineFunctionInfo::SIMachineFunctionInfo(const MachineFunction &MF)
33   : AMDGPUMachineFunction(MF),
34     BufferPSV(static_cast<const AMDGPUTargetMachine &>(MF.getTarget())),
35     ImagePSV(static_cast<const AMDGPUTargetMachine &>(MF.getTarget())),
36     GWSResourcePSV(static_cast<const AMDGPUTargetMachine &>(MF.getTarget())),
37     PrivateSegmentBuffer(false),
38     DispatchPtr(false),
39     QueuePtr(false),
40     KernargSegmentPtr(false),
41     DispatchID(false),
42     FlatScratchInit(false),
43     WorkGroupIDX(false),
44     WorkGroupIDY(false),
45     WorkGroupIDZ(false),
46     WorkGroupInfo(false),
47     PrivateSegmentWaveByteOffset(false),
48     WorkItemIDX(false),
49     WorkItemIDY(false),
50     WorkItemIDZ(false),
51     ImplicitBufferPtr(false),
52     ImplicitArgPtr(false),
53     GITPtrHigh(0xffffffff),
54     HighBitsOf32BitAddress(0) {
55   const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
56   const Function &F = MF.getFunction();
57   FlatWorkGroupSizes = ST.getFlatWorkGroupSizes(F);
58   WavesPerEU = ST.getWavesPerEU(F);
59 
60   Occupancy = ST.computeOccupancy(F, getLDSSize());
61   CallingConv::ID CC = F.getCallingConv();
62 
63   // FIXME: Should have analysis or something rather than attribute to detect
64   // calls.
65   const bool HasCalls = F.hasFnAttribute("amdgpu-calls");
66 
67   const bool IsKernel = CC == CallingConv::AMDGPU_KERNEL ||
68                         CC == CallingConv::SPIR_KERNEL;
69 
70   if (IsKernel) {
71     if (!F.arg_empty() || ST.getImplicitArgNumBytes(F) != 0)
72       KernargSegmentPtr = true;
73     WorkGroupIDX = true;
74     WorkItemIDX = true;
75   } else if (CC == CallingConv::AMDGPU_PS) {
76     PSInputAddr = AMDGPU::getInitialPSInputAddr(F);
77   }
78 
79   MayNeedAGPRs = ST.hasMAIInsts();
80 
81   if (!isEntryFunction()) {
82     if (CC != CallingConv::AMDGPU_Gfx)
83       ArgInfo = AMDGPUArgumentUsageInfo::FixedABIFunctionInfo;
84 
85     // TODO: Pick a high register, and shift down, similar to a kernel.
86     FrameOffsetReg = AMDGPU::SGPR33;
87     StackPtrOffsetReg = AMDGPU::SGPR32;
88 
89     if (!ST.enableFlatScratch()) {
90       // Non-entry functions have no special inputs for now, other registers
91       // required for scratch access.
92       ScratchRSrcReg = AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3;
93 
94       ArgInfo.PrivateSegmentBuffer =
95         ArgDescriptor::createRegister(ScratchRSrcReg);
96     }
97 
98     if (!F.hasFnAttribute("amdgpu-no-implicitarg-ptr"))
99       ImplicitArgPtr = true;
100   } else {
101     ImplicitArgPtr = false;
102     MaxKernArgAlign = std::max(ST.getAlignmentForImplicitArgPtr(),
103                                MaxKernArgAlign);
104 
105     if (ST.hasGFX90AInsts() &&
106         ST.getMaxNumVGPRs(F) <= AMDGPU::VGPR_32RegClass.getNumRegs() &&
107         !mayUseAGPRs(MF))
108       MayNeedAGPRs = false; // We will select all MAI with VGPR operands.
109   }
110 
111   bool isAmdHsaOrMesa = ST.isAmdHsaOrMesa(F);
112   if (isAmdHsaOrMesa && !ST.enableFlatScratch())
113     PrivateSegmentBuffer = true;
114   else if (ST.isMesaGfxShader(F))
115     ImplicitBufferPtr = true;
116 
117   if (!AMDGPU::isGraphics(CC)) {
118     if (IsKernel || !F.hasFnAttribute("amdgpu-no-workgroup-id-x"))
119       WorkGroupIDX = true;
120 
121     if (!F.hasFnAttribute("amdgpu-no-workgroup-id-y"))
122       WorkGroupIDY = true;
123 
124     if (!F.hasFnAttribute("amdgpu-no-workgroup-id-z"))
125       WorkGroupIDZ = true;
126 
127     if (IsKernel || !F.hasFnAttribute("amdgpu-no-workitem-id-x"))
128       WorkItemIDX = true;
129 
130     if (!F.hasFnAttribute("amdgpu-no-workitem-id-y") &&
131         ST.getMaxWorkitemID(F, 1) != 0)
132       WorkItemIDY = true;
133 
134     if (!F.hasFnAttribute("amdgpu-no-workitem-id-z") &&
135         ST.getMaxWorkitemID(F, 2) != 0)
136       WorkItemIDZ = true;
137 
138     if (!F.hasFnAttribute("amdgpu-no-dispatch-ptr"))
139       DispatchPtr = true;
140 
141     if (!F.hasFnAttribute("amdgpu-no-queue-ptr"))
142       QueuePtr = true;
143 
144     if (!F.hasFnAttribute("amdgpu-no-dispatch-id"))
145       DispatchID = true;
146   }
147 
148   // FIXME: This attribute is a hack, we just need an analysis on the function
149   // to look for allocas.
150   bool HasStackObjects = F.hasFnAttribute("amdgpu-stack-objects");
151 
152   // TODO: This could be refined a lot. The attribute is a poor way of
153   // detecting calls or stack objects that may require it before argument
154   // lowering.
155   if (ST.hasFlatAddressSpace() && isEntryFunction() &&
156       (isAmdHsaOrMesa || ST.enableFlatScratch()) &&
157       (HasCalls || HasStackObjects || ST.enableFlatScratch()) &&
158       !ST.flatScratchIsArchitected()) {
159     FlatScratchInit = true;
160   }
161 
162   if (isEntryFunction()) {
163     // X, XY, and XYZ are the only supported combinations, so make sure Y is
164     // enabled if Z is.
165     if (WorkItemIDZ)
166       WorkItemIDY = true;
167 
168     if (!ST.flatScratchIsArchitected()) {
169       PrivateSegmentWaveByteOffset = true;
170 
171       // HS and GS always have the scratch wave offset in SGPR5 on GFX9.
172       if (ST.getGeneration() >= AMDGPUSubtarget::GFX9 &&
173           (CC == CallingConv::AMDGPU_HS || CC == CallingConv::AMDGPU_GS))
174         ArgInfo.PrivateSegmentWaveByteOffset =
175             ArgDescriptor::createRegister(AMDGPU::SGPR5);
176     }
177   }
178 
179   Attribute A = F.getFnAttribute("amdgpu-git-ptr-high");
180   StringRef S = A.getValueAsString();
181   if (!S.empty())
182     S.consumeInteger(0, GITPtrHigh);
183 
184   A = F.getFnAttribute("amdgpu-32bit-address-high-bits");
185   S = A.getValueAsString();
186   if (!S.empty())
187     S.consumeInteger(0, HighBitsOf32BitAddress);
188 
189   // On GFX908, in order to guarantee copying between AGPRs, we need a scratch
190   // VGPR available at all times. For now, reserve highest available VGPR. After
191   // RA, shift it to the lowest available unused VGPR if the one exist.
192   if (ST.hasMAIInsts() && !ST.hasGFX90AInsts()) {
193     VGPRForAGPRCopy =
194         AMDGPU::VGPR_32RegClass.getRegister(ST.getMaxNumVGPRs(F) - 1);
195   }
196 }
197 
198 void SIMachineFunctionInfo::limitOccupancy(const MachineFunction &MF) {
199   limitOccupancy(getMaxWavesPerEU());
200   const GCNSubtarget& ST = MF.getSubtarget<GCNSubtarget>();
201   limitOccupancy(ST.getOccupancyWithLocalMemSize(getLDSSize(),
202                  MF.getFunction()));
203 }
204 
205 Register SIMachineFunctionInfo::addPrivateSegmentBuffer(
206   const SIRegisterInfo &TRI) {
207   ArgInfo.PrivateSegmentBuffer =
208     ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
209     getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SGPR_128RegClass));
210   NumUserSGPRs += 4;
211   return ArgInfo.PrivateSegmentBuffer.getRegister();
212 }
213 
214 Register SIMachineFunctionInfo::addDispatchPtr(const SIRegisterInfo &TRI) {
215   ArgInfo.DispatchPtr = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
216     getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
217   NumUserSGPRs += 2;
218   return ArgInfo.DispatchPtr.getRegister();
219 }
220 
221 Register SIMachineFunctionInfo::addQueuePtr(const SIRegisterInfo &TRI) {
222   ArgInfo.QueuePtr = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
223     getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
224   NumUserSGPRs += 2;
225   return ArgInfo.QueuePtr.getRegister();
226 }
227 
228 Register SIMachineFunctionInfo::addKernargSegmentPtr(const SIRegisterInfo &TRI) {
229   ArgInfo.KernargSegmentPtr
230     = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
231     getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
232   NumUserSGPRs += 2;
233   return ArgInfo.KernargSegmentPtr.getRegister();
234 }
235 
236 Register SIMachineFunctionInfo::addDispatchID(const SIRegisterInfo &TRI) {
237   ArgInfo.DispatchID = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
238     getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
239   NumUserSGPRs += 2;
240   return ArgInfo.DispatchID.getRegister();
241 }
242 
243 Register SIMachineFunctionInfo::addFlatScratchInit(const SIRegisterInfo &TRI) {
244   ArgInfo.FlatScratchInit = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
245     getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
246   NumUserSGPRs += 2;
247   return ArgInfo.FlatScratchInit.getRegister();
248 }
249 
250 Register SIMachineFunctionInfo::addImplicitBufferPtr(const SIRegisterInfo &TRI) {
251   ArgInfo.ImplicitBufferPtr = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
252     getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
253   NumUserSGPRs += 2;
254   return ArgInfo.ImplicitBufferPtr.getRegister();
255 }
256 
257 bool SIMachineFunctionInfo::isCalleeSavedReg(const MCPhysReg *CSRegs,
258                                              MCPhysReg Reg) {
259   for (unsigned I = 0; CSRegs[I]; ++I) {
260     if (CSRegs[I] == Reg)
261       return true;
262   }
263 
264   return false;
265 }
266 
267 /// \p returns true if \p NumLanes slots are available in VGPRs already used for
268 /// SGPR spilling.
269 //
270 // FIXME: This only works after processFunctionBeforeFrameFinalized
271 bool SIMachineFunctionInfo::haveFreeLanesForSGPRSpill(const MachineFunction &MF,
272                                                       unsigned NumNeed) const {
273   const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
274   unsigned WaveSize = ST.getWavefrontSize();
275   return NumVGPRSpillLanes + NumNeed <= WaveSize * SpillVGPRs.size();
276 }
277 
278 /// Reserve a slice of a VGPR to support spilling for FrameIndex \p FI.
279 bool SIMachineFunctionInfo::allocateSGPRSpillToVGPR(MachineFunction &MF,
280                                                     int FI) {
281   std::vector<SIRegisterInfo::SpilledReg> &SpillLanes = SGPRToVGPRSpills[FI];
282 
283   // This has already been allocated.
284   if (!SpillLanes.empty())
285     return true;
286 
287   const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
288   const SIRegisterInfo *TRI = ST.getRegisterInfo();
289   MachineFrameInfo &FrameInfo = MF.getFrameInfo();
290   MachineRegisterInfo &MRI = MF.getRegInfo();
291   unsigned WaveSize = ST.getWavefrontSize();
292 
293   unsigned Size = FrameInfo.getObjectSize(FI);
294   unsigned NumLanes = Size / 4;
295 
296   if (NumLanes > WaveSize)
297     return false;
298 
299   assert(Size >= 4 && "invalid sgpr spill size");
300   assert(TRI->spillSGPRToVGPR() && "not spilling SGPRs to VGPRs");
301 
302   // Make sure to handle the case where a wide SGPR spill may span between two
303   // VGPRs.
304   for (unsigned I = 0; I < NumLanes; ++I, ++NumVGPRSpillLanes) {
305     Register LaneVGPR;
306     unsigned VGPRIndex = (NumVGPRSpillLanes % WaveSize);
307 
308     if (VGPRIndex == 0) {
309       LaneVGPR = TRI->findUnusedRegister(MRI, &AMDGPU::VGPR_32RegClass, MF);
310       if (LaneVGPR == AMDGPU::NoRegister) {
311         // We have no VGPRs left for spilling SGPRs. Reset because we will not
312         // partially spill the SGPR to VGPRs.
313         SGPRToVGPRSpills.erase(FI);
314         NumVGPRSpillLanes -= I;
315 
316         // FIXME: We can run out of free registers with split allocation if
317         // IPRA is enabled and a called function already uses every VGPR.
318 #if 0
319         DiagnosticInfoResourceLimit DiagOutOfRegs(MF.getFunction(),
320                                                   "VGPRs for SGPR spilling",
321                                                   0, DS_Error);
322         MF.getFunction().getContext().diagnose(DiagOutOfRegs);
323 #endif
324         return false;
325       }
326 
327       Optional<int> SpillFI;
328       // We need to preserve inactive lanes, so always save, even caller-save
329       // registers.
330       if (!isEntryFunction()) {
331         SpillFI = FrameInfo.CreateSpillStackObject(4, Align(4));
332       }
333 
334       SpillVGPRs.push_back(SGPRSpillVGPR(LaneVGPR, SpillFI));
335 
336       // Add this register as live-in to all blocks to avoid machine verifier
337       // complaining about use of an undefined physical register.
338       for (MachineBasicBlock &BB : MF)
339         BB.addLiveIn(LaneVGPR);
340     } else {
341       LaneVGPR = SpillVGPRs.back().VGPR;
342     }
343 
344     SpillLanes.push_back(SIRegisterInfo::SpilledReg(LaneVGPR, VGPRIndex));
345   }
346 
347   return true;
348 }
349 
350 /// Reserve AGPRs or VGPRs to support spilling for FrameIndex \p FI.
351 /// Either AGPR is spilled to VGPR to vice versa.
352 /// Returns true if a \p FI can be eliminated completely.
353 bool SIMachineFunctionInfo::allocateVGPRSpillToAGPR(MachineFunction &MF,
354                                                     int FI,
355                                                     bool isAGPRtoVGPR) {
356   MachineRegisterInfo &MRI = MF.getRegInfo();
357   MachineFrameInfo &FrameInfo = MF.getFrameInfo();
358   const GCNSubtarget &ST =  MF.getSubtarget<GCNSubtarget>();
359 
360   assert(ST.hasMAIInsts() && FrameInfo.isSpillSlotObjectIndex(FI));
361 
362   auto &Spill = VGPRToAGPRSpills[FI];
363 
364   // This has already been allocated.
365   if (!Spill.Lanes.empty())
366     return Spill.FullyAllocated;
367 
368   unsigned Size = FrameInfo.getObjectSize(FI);
369   unsigned NumLanes = Size / 4;
370   Spill.Lanes.resize(NumLanes, AMDGPU::NoRegister);
371 
372   const TargetRegisterClass &RC =
373       isAGPRtoVGPR ? AMDGPU::VGPR_32RegClass : AMDGPU::AGPR_32RegClass;
374   auto Regs = RC.getRegisters();
375 
376   auto &SpillRegs = isAGPRtoVGPR ? SpillAGPR : SpillVGPR;
377   const SIRegisterInfo *TRI = ST.getRegisterInfo();
378   Spill.FullyAllocated = true;
379 
380   // FIXME: Move allocation logic out of MachineFunctionInfo and initialize
381   // once.
382   BitVector OtherUsedRegs;
383   OtherUsedRegs.resize(TRI->getNumRegs());
384 
385   const uint32_t *CSRMask =
386       TRI->getCallPreservedMask(MF, MF.getFunction().getCallingConv());
387   if (CSRMask)
388     OtherUsedRegs.setBitsInMask(CSRMask);
389 
390   // TODO: Should include register tuples, but doesn't matter with current
391   // usage.
392   for (MCPhysReg Reg : SpillAGPR)
393     OtherUsedRegs.set(Reg);
394   for (MCPhysReg Reg : SpillVGPR)
395     OtherUsedRegs.set(Reg);
396 
397   SmallVectorImpl<MCPhysReg>::const_iterator NextSpillReg = Regs.begin();
398   for (int I = NumLanes - 1; I >= 0; --I) {
399     NextSpillReg = std::find_if(
400         NextSpillReg, Regs.end(), [&MRI, &OtherUsedRegs](MCPhysReg Reg) {
401           return MRI.isAllocatable(Reg) && !MRI.isPhysRegUsed(Reg) &&
402                  !OtherUsedRegs[Reg];
403         });
404 
405     if (NextSpillReg == Regs.end()) { // Registers exhausted
406       Spill.FullyAllocated = false;
407       break;
408     }
409 
410     OtherUsedRegs.set(*NextSpillReg);
411     SpillRegs.push_back(*NextSpillReg);
412     Spill.Lanes[I] = *NextSpillReg++;
413   }
414 
415   return Spill.FullyAllocated;
416 }
417 
418 bool SIMachineFunctionInfo::removeDeadFrameIndices(
419     MachineFrameInfo &MFI, bool ResetSGPRSpillStackIDs) {
420   // Remove dead frame indices from function frame, however keep FP & BP since
421   // spills for them haven't been inserted yet. And also make sure to remove the
422   // frame indices from `SGPRToVGPRSpills` data structure, otherwise, it could
423   // result in an unexpected side effect and bug, in case of any re-mapping of
424   // freed frame indices by later pass(es) like "stack slot coloring".
425   for (auto &R : make_early_inc_range(SGPRToVGPRSpills)) {
426     if (R.first != FramePointerSaveIndex && R.first != BasePointerSaveIndex) {
427       MFI.RemoveStackObject(R.first);
428       SGPRToVGPRSpills.erase(R.first);
429     }
430   }
431 
432   bool HaveSGPRToMemory = false;
433 
434   if (ResetSGPRSpillStackIDs) {
435     // All other SPGRs must be allocated on the default stack, so reset the
436     // stack ID.
437     for (int i = MFI.getObjectIndexBegin(), e = MFI.getObjectIndexEnd(); i != e;
438          ++i) {
439       if (i != FramePointerSaveIndex && i != BasePointerSaveIndex) {
440         if (MFI.getStackID(i) == TargetStackID::SGPRSpill) {
441           MFI.setStackID(i, TargetStackID::Default);
442           HaveSGPRToMemory = true;
443         }
444       }
445     }
446   }
447 
448   for (auto &R : VGPRToAGPRSpills) {
449     if (R.second.IsDead)
450       MFI.RemoveStackObject(R.first);
451   }
452 
453   return HaveSGPRToMemory;
454 }
455 
456 void SIMachineFunctionInfo::allocateWWMReservedSpillSlots(
457     MachineFrameInfo &MFI, const SIRegisterInfo &TRI) {
458   assert(WWMReservedFrameIndexes.empty());
459 
460   WWMReservedFrameIndexes.resize(WWMReservedRegs.size());
461 
462   int I = 0;
463   for (Register VGPR : WWMReservedRegs) {
464     const TargetRegisterClass *RC = TRI.getPhysRegClass(VGPR);
465     WWMReservedFrameIndexes[I++] = MFI.CreateSpillStackObject(
466         TRI.getSpillSize(*RC), TRI.getSpillAlign(*RC));
467   }
468 }
469 
470 int SIMachineFunctionInfo::getScavengeFI(MachineFrameInfo &MFI,
471                                          const SIRegisterInfo &TRI) {
472   if (ScavengeFI)
473     return *ScavengeFI;
474   if (isEntryFunction()) {
475     ScavengeFI = MFI.CreateFixedObject(
476         TRI.getSpillSize(AMDGPU::SGPR_32RegClass), 0, false);
477   } else {
478     ScavengeFI = MFI.CreateStackObject(
479         TRI.getSpillSize(AMDGPU::SGPR_32RegClass),
480         TRI.getSpillAlign(AMDGPU::SGPR_32RegClass), false);
481   }
482   return *ScavengeFI;
483 }
484 
485 MCPhysReg SIMachineFunctionInfo::getNextUserSGPR() const {
486   assert(NumSystemSGPRs == 0 && "System SGPRs must be added after user SGPRs");
487   return AMDGPU::SGPR0 + NumUserSGPRs;
488 }
489 
490 MCPhysReg SIMachineFunctionInfo::getNextSystemSGPR() const {
491   return AMDGPU::SGPR0 + NumUserSGPRs + NumSystemSGPRs;
492 }
493 
494 Register
495 SIMachineFunctionInfo::getGITPtrLoReg(const MachineFunction &MF) const {
496   const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
497   if (!ST.isAmdPalOS())
498     return Register();
499   Register GitPtrLo = AMDGPU::SGPR0; // Low GIT address passed in
500   if (ST.hasMergedShaders()) {
501     switch (MF.getFunction().getCallingConv()) {
502     case CallingConv::AMDGPU_HS:
503     case CallingConv::AMDGPU_GS:
504       // Low GIT address is passed in s8 rather than s0 for an LS+HS or
505       // ES+GS merged shader on gfx9+.
506       GitPtrLo = AMDGPU::SGPR8;
507       return GitPtrLo;
508     default:
509       return GitPtrLo;
510     }
511   }
512   return GitPtrLo;
513 }
514 
515 static yaml::StringValue regToString(Register Reg,
516                                      const TargetRegisterInfo &TRI) {
517   yaml::StringValue Dest;
518   {
519     raw_string_ostream OS(Dest.Value);
520     OS << printReg(Reg, &TRI);
521   }
522   return Dest;
523 }
524 
525 static Optional<yaml::SIArgumentInfo>
526 convertArgumentInfo(const AMDGPUFunctionArgInfo &ArgInfo,
527                     const TargetRegisterInfo &TRI) {
528   yaml::SIArgumentInfo AI;
529 
530   auto convertArg = [&](Optional<yaml::SIArgument> &A,
531                         const ArgDescriptor &Arg) {
532     if (!Arg)
533       return false;
534 
535     // Create a register or stack argument.
536     yaml::SIArgument SA = yaml::SIArgument::createArgument(Arg.isRegister());
537     if (Arg.isRegister()) {
538       raw_string_ostream OS(SA.RegisterName.Value);
539       OS << printReg(Arg.getRegister(), &TRI);
540     } else
541       SA.StackOffset = Arg.getStackOffset();
542     // Check and update the optional mask.
543     if (Arg.isMasked())
544       SA.Mask = Arg.getMask();
545 
546     A = SA;
547     return true;
548   };
549 
550   bool Any = false;
551   Any |= convertArg(AI.PrivateSegmentBuffer, ArgInfo.PrivateSegmentBuffer);
552   Any |= convertArg(AI.DispatchPtr, ArgInfo.DispatchPtr);
553   Any |= convertArg(AI.QueuePtr, ArgInfo.QueuePtr);
554   Any |= convertArg(AI.KernargSegmentPtr, ArgInfo.KernargSegmentPtr);
555   Any |= convertArg(AI.DispatchID, ArgInfo.DispatchID);
556   Any |= convertArg(AI.FlatScratchInit, ArgInfo.FlatScratchInit);
557   Any |= convertArg(AI.PrivateSegmentSize, ArgInfo.PrivateSegmentSize);
558   Any |= convertArg(AI.WorkGroupIDX, ArgInfo.WorkGroupIDX);
559   Any |= convertArg(AI.WorkGroupIDY, ArgInfo.WorkGroupIDY);
560   Any |= convertArg(AI.WorkGroupIDZ, ArgInfo.WorkGroupIDZ);
561   Any |= convertArg(AI.WorkGroupInfo, ArgInfo.WorkGroupInfo);
562   Any |= convertArg(AI.PrivateSegmentWaveByteOffset,
563                     ArgInfo.PrivateSegmentWaveByteOffset);
564   Any |= convertArg(AI.ImplicitArgPtr, ArgInfo.ImplicitArgPtr);
565   Any |= convertArg(AI.ImplicitBufferPtr, ArgInfo.ImplicitBufferPtr);
566   Any |= convertArg(AI.WorkItemIDX, ArgInfo.WorkItemIDX);
567   Any |= convertArg(AI.WorkItemIDY, ArgInfo.WorkItemIDY);
568   Any |= convertArg(AI.WorkItemIDZ, ArgInfo.WorkItemIDZ);
569 
570   if (Any)
571     return AI;
572 
573   return None;
574 }
575 
576 yaml::SIMachineFunctionInfo::SIMachineFunctionInfo(
577     const llvm::SIMachineFunctionInfo &MFI, const TargetRegisterInfo &TRI,
578     const llvm::MachineFunction &MF)
579     : ExplicitKernArgSize(MFI.getExplicitKernArgSize()),
580       MaxKernArgAlign(MFI.getMaxKernArgAlign()), LDSSize(MFI.getLDSSize()),
581       GDSSize(MFI.getGDSSize()),
582       DynLDSAlign(MFI.getDynLDSAlign()), IsEntryFunction(MFI.isEntryFunction()),
583       NoSignedZerosFPMath(MFI.hasNoSignedZerosFPMath()),
584       MemoryBound(MFI.isMemoryBound()), WaveLimiter(MFI.needsWaveLimiter()),
585       HasSpilledSGPRs(MFI.hasSpilledSGPRs()),
586       HasSpilledVGPRs(MFI.hasSpilledVGPRs()),
587       HighBitsOf32BitAddress(MFI.get32BitAddressHighBits()),
588       Occupancy(MFI.getOccupancy()),
589       ScratchRSrcReg(regToString(MFI.getScratchRSrcReg(), TRI)),
590       FrameOffsetReg(regToString(MFI.getFrameOffsetReg(), TRI)),
591       StackPtrOffsetReg(regToString(MFI.getStackPtrOffsetReg(), TRI)),
592       BytesInStackArgArea(MFI.getBytesInStackArgArea()),
593       ReturnsVoid(MFI.returnsVoid()),
594       ArgInfo(convertArgumentInfo(MFI.getArgInfo(), TRI)), Mode(MFI.getMode()) {
595   for (Register Reg : MFI.WWMReservedRegs)
596     WWMReservedRegs.push_back(regToString(Reg, TRI));
597 
598   if (MFI.getVGPRForAGPRCopy())
599     VGPRForAGPRCopy = regToString(MFI.getVGPRForAGPRCopy(), TRI);
600   auto SFI = MFI.getOptionalScavengeFI();
601   if (SFI)
602     ScavengeFI = yaml::FrameIndex(*SFI, MF.getFrameInfo());
603 }
604 
605 void yaml::SIMachineFunctionInfo::mappingImpl(yaml::IO &YamlIO) {
606   MappingTraits<SIMachineFunctionInfo>::mapping(YamlIO, *this);
607 }
608 
609 bool SIMachineFunctionInfo::initializeBaseYamlFields(
610     const yaml::SIMachineFunctionInfo &YamlMFI, const MachineFunction &MF,
611     PerFunctionMIParsingState &PFS, SMDiagnostic &Error, SMRange &SourceRange) {
612   ExplicitKernArgSize = YamlMFI.ExplicitKernArgSize;
613   MaxKernArgAlign = assumeAligned(YamlMFI.MaxKernArgAlign);
614   LDSSize = YamlMFI.LDSSize;
615   GDSSize = YamlMFI.GDSSize;
616   DynLDSAlign = YamlMFI.DynLDSAlign;
617   HighBitsOf32BitAddress = YamlMFI.HighBitsOf32BitAddress;
618   Occupancy = YamlMFI.Occupancy;
619   IsEntryFunction = YamlMFI.IsEntryFunction;
620   NoSignedZerosFPMath = YamlMFI.NoSignedZerosFPMath;
621   MemoryBound = YamlMFI.MemoryBound;
622   WaveLimiter = YamlMFI.WaveLimiter;
623   HasSpilledSGPRs = YamlMFI.HasSpilledSGPRs;
624   HasSpilledVGPRs = YamlMFI.HasSpilledVGPRs;
625   BytesInStackArgArea = YamlMFI.BytesInStackArgArea;
626   ReturnsVoid = YamlMFI.ReturnsVoid;
627 
628   if (YamlMFI.ScavengeFI) {
629     auto FIOrErr = YamlMFI.ScavengeFI->getFI(MF.getFrameInfo());
630     if (!FIOrErr) {
631       // Create a diagnostic for a the frame index.
632       const MemoryBuffer &Buffer =
633           *PFS.SM->getMemoryBuffer(PFS.SM->getMainFileID());
634 
635       Error = SMDiagnostic(*PFS.SM, SMLoc(), Buffer.getBufferIdentifier(), 1, 1,
636                            SourceMgr::DK_Error, toString(FIOrErr.takeError()),
637                            "", None, None);
638       SourceRange = YamlMFI.ScavengeFI->SourceRange;
639       return true;
640     }
641     ScavengeFI = *FIOrErr;
642   } else {
643     ScavengeFI = None;
644   }
645   return false;
646 }
647 
648 bool SIMachineFunctionInfo::mayUseAGPRs(const MachineFunction &MF) const {
649   for (const BasicBlock &BB : MF.getFunction()) {
650     for (const Instruction &I : BB) {
651       const auto *CB = dyn_cast<CallBase>(&I);
652       if (!CB)
653         continue;
654 
655       if (CB->isInlineAsm()) {
656         const InlineAsm *IA = dyn_cast<InlineAsm>(CB->getCalledOperand());
657         for (const auto &CI : IA->ParseConstraints()) {
658           for (StringRef Code : CI.Codes) {
659             Code.consume_front("{");
660             if (Code.startswith("a"))
661               return true;
662           }
663         }
664         continue;
665       }
666 
667       const Function *Callee =
668           dyn_cast<Function>(CB->getCalledOperand()->stripPointerCasts());
669       if (!Callee)
670         return true;
671 
672       if (Callee->getIntrinsicID() == Intrinsic::not_intrinsic)
673         return true;
674     }
675   }
676 
677   return false;
678 }
679 
680 bool SIMachineFunctionInfo::usesAGPRs(const MachineFunction &MF) const {
681   if (UsesAGPRs)
682     return *UsesAGPRs;
683 
684   if (!mayNeedAGPRs()) {
685     UsesAGPRs = false;
686     return false;
687   }
688 
689   if (!AMDGPU::isEntryFunctionCC(MF.getFunction().getCallingConv()) ||
690       MF.getFrameInfo().hasCalls()) {
691     UsesAGPRs = true;
692     return true;
693   }
694 
695   const MachineRegisterInfo &MRI = MF.getRegInfo();
696 
697   for (unsigned I = 0, E = MRI.getNumVirtRegs(); I != E; ++I) {
698     const Register Reg = Register::index2VirtReg(I);
699     const TargetRegisterClass *RC = MRI.getRegClassOrNull(Reg);
700     if (RC && SIRegisterInfo::isAGPRClass(RC)) {
701       UsesAGPRs = true;
702       return true;
703     } else if (!RC && !MRI.use_empty(Reg) && MRI.getType(Reg).isValid()) {
704       // Defer caching UsesAGPRs, function might not yet been regbank selected.
705       return true;
706     }
707   }
708 
709   for (MCRegister Reg : AMDGPU::AGPR_32RegClass) {
710     if (MRI.isPhysRegUsed(Reg)) {
711       UsesAGPRs = true;
712       return true;
713     }
714   }
715 
716   UsesAGPRs = false;
717   return false;
718 }
719