1 //===-- SIMachineFunctionInfo.cpp - SI Machine Function Info -------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 /// \file
9 //===----------------------------------------------------------------------===//
10 
11 
12 #include "SIMachineFunctionInfo.h"
13 #include "AMDGPUSubtarget.h"
14 #include "SIInstrInfo.h"
15 #include "llvm/CodeGen/MachineInstrBuilder.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineRegisterInfo.h"
18 #include "llvm/IR/Function.h"
19 #include "llvm/IR/LLVMContext.h"
20 
21 #define MAX_LANES 64
22 
23 using namespace llvm;
24 
25 
26 // Pin the vtable to this file.
27 void SIMachineFunctionInfo::anchor() {}
28 
29 SIMachineFunctionInfo::SIMachineFunctionInfo(const MachineFunction &MF)
30   : AMDGPUMachineFunction(MF),
31     TIDReg(AMDGPU::NoRegister),
32     HasSpilledSGPRs(false),
33     HasSpilledVGPRs(false),
34     PSInputAddr(0),
35     NumUserSGPRs(0),
36     LDSWaveSpillSize(0) { }
37 
38 SIMachineFunctionInfo::SpilledReg SIMachineFunctionInfo::getSpilledReg(
39                                                        MachineFunction *MF,
40                                                        unsigned FrameIndex,
41                                                        unsigned SubIdx) {
42   const MachineFrameInfo *FrameInfo = MF->getFrameInfo();
43   const SIRegisterInfo *TRI = static_cast<const SIRegisterInfo *>(
44       MF->getSubtarget<AMDGPUSubtarget>().getRegisterInfo());
45   MachineRegisterInfo &MRI = MF->getRegInfo();
46   int64_t Offset = FrameInfo->getObjectOffset(FrameIndex);
47   Offset += SubIdx * 4;
48 
49   unsigned LaneVGPRIdx = Offset / (64 * 4);
50   unsigned Lane = (Offset / 4) % 64;
51 
52   struct SpilledReg Spill;
53 
54   if (!LaneVGPRs.count(LaneVGPRIdx)) {
55     unsigned LaneVGPR = TRI->findUnusedRegister(MRI, &AMDGPU::VGPR_32RegClass);
56     LaneVGPRs[LaneVGPRIdx] = LaneVGPR;
57 
58     // Add this register as live-in to all blocks to avoid machine verifer
59     // complaining about use of an undefined physical register.
60     for (MachineFunction::iterator BI = MF->begin(), BE = MF->end();
61          BI != BE; ++BI) {
62       BI->addLiveIn(LaneVGPR);
63     }
64   }
65 
66   Spill.VGPR = LaneVGPRs[LaneVGPRIdx];
67   Spill.Lane = Lane;
68   return Spill;
69 }
70 
71 unsigned SIMachineFunctionInfo::getMaximumWorkGroupSize(
72                                               const MachineFunction &MF) const {
73   const AMDGPUSubtarget &ST = MF.getSubtarget<AMDGPUSubtarget>();
74   // FIXME: We should get this information from kernel attributes if it
75   // is available.
76   return getShaderType() == ShaderType::COMPUTE ? 256 : ST.getWavefrontSize();
77 }
78