1 //===- SIMachineFunctionInfo.cpp - SI Machine Function Info ---------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #include "SIMachineFunctionInfo.h"
10 #include "AMDGPUTargetMachine.h"
11 #include "AMDGPUSubtarget.h"
12 #include "SIRegisterInfo.h"
13 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
14 #include "Utils/AMDGPUBaseInfo.h"
15 #include "llvm/ADT/Optional.h"
16 #include "llvm/CodeGen/LiveIntervals.h"
17 #include "llvm/CodeGen/MachineBasicBlock.h"
18 #include "llvm/CodeGen/MachineFrameInfo.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/MachineRegisterInfo.h"
21 #include "llvm/CodeGen/MIRParser/MIParser.h"
22 #include "llvm/IR/CallingConv.h"
23 #include "llvm/IR/DiagnosticInfo.h"
24 #include "llvm/IR/Function.h"
25 #include <cassert>
26 #include <vector>
27 
28 #define MAX_LANES 64
29 
30 using namespace llvm;
31 
32 SIMachineFunctionInfo::SIMachineFunctionInfo(const MachineFunction &MF)
33   : AMDGPUMachineFunction(MF),
34     PrivateSegmentBuffer(false),
35     DispatchPtr(false),
36     QueuePtr(false),
37     KernargSegmentPtr(false),
38     DispatchID(false),
39     FlatScratchInit(false),
40     WorkGroupIDX(false),
41     WorkGroupIDY(false),
42     WorkGroupIDZ(false),
43     WorkGroupInfo(false),
44     PrivateSegmentWaveByteOffset(false),
45     WorkItemIDX(false),
46     WorkItemIDY(false),
47     WorkItemIDZ(false),
48     ImplicitBufferPtr(false),
49     ImplicitArgPtr(false),
50     HostcallPtr(false),
51     GITPtrHigh(0xffffffff),
52     HighBitsOf32BitAddress(0),
53     GDSSize(0) {
54   const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
55   const Function &F = MF.getFunction();
56   FlatWorkGroupSizes = ST.getFlatWorkGroupSizes(F);
57   WavesPerEU = ST.getWavesPerEU(F);
58 
59   Occupancy = ST.computeOccupancy(F, getLDSSize());
60   CallingConv::ID CC = F.getCallingConv();
61 
62   // FIXME: Should have analysis or something rather than attribute to detect
63   // calls.
64   const bool HasCalls = F.hasFnAttribute("amdgpu-calls");
65 
66   const bool IsKernel = CC == CallingConv::AMDGPU_KERNEL ||
67                         CC == CallingConv::SPIR_KERNEL;
68 
69   if (IsKernel) {
70     if (!F.arg_empty() || ST.getImplicitArgNumBytes(F) != 0)
71       KernargSegmentPtr = true;
72     WorkGroupIDX = true;
73     WorkItemIDX = true;
74   } else if (CC == CallingConv::AMDGPU_PS) {
75     PSInputAddr = AMDGPU::getInitialPSInputAddr(F);
76   }
77 
78   MayNeedAGPRs = ST.hasMAIInsts();
79 
80   if (!isEntryFunction()) {
81     if (CC != CallingConv::AMDGPU_Gfx)
82       ArgInfo = AMDGPUArgumentUsageInfo::FixedABIFunctionInfo;
83 
84     // TODO: Pick a high register, and shift down, similar to a kernel.
85     FrameOffsetReg = AMDGPU::SGPR33;
86     StackPtrOffsetReg = AMDGPU::SGPR32;
87 
88     if (!ST.enableFlatScratch()) {
89       // Non-entry functions have no special inputs for now, other registers
90       // required for scratch access.
91       ScratchRSrcReg = AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3;
92 
93       ArgInfo.PrivateSegmentBuffer =
94         ArgDescriptor::createRegister(ScratchRSrcReg);
95     }
96 
97     if (!F.hasFnAttribute("amdgpu-no-implicitarg-ptr"))
98       ImplicitArgPtr = true;
99   } else {
100     ImplicitArgPtr = false;
101     MaxKernArgAlign = std::max(ST.getAlignmentForImplicitArgPtr(),
102                                MaxKernArgAlign);
103 
104     if (ST.hasGFX90AInsts() &&
105         ST.getMaxNumVGPRs(F) <= AMDGPU::VGPR_32RegClass.getNumRegs() &&
106         !mayUseAGPRs(MF))
107       MayNeedAGPRs = false; // We will select all MAI with VGPR operands.
108   }
109 
110   bool isAmdHsaOrMesa = ST.isAmdHsaOrMesa(F);
111   if (isAmdHsaOrMesa && !ST.enableFlatScratch())
112     PrivateSegmentBuffer = true;
113   else if (ST.isMesaGfxShader(F))
114     ImplicitBufferPtr = true;
115 
116   if (!AMDGPU::isGraphics(CC)) {
117     if (IsKernel || !F.hasFnAttribute("amdgpu-no-workgroup-id-x"))
118       WorkGroupIDX = true;
119 
120     if (!F.hasFnAttribute("amdgpu-no-workgroup-id-y"))
121       WorkGroupIDY = true;
122 
123     if (!F.hasFnAttribute("amdgpu-no-workgroup-id-z"))
124       WorkGroupIDZ = true;
125 
126     if (IsKernel || !F.hasFnAttribute("amdgpu-no-workitem-id-x"))
127       WorkItemIDX = true;
128 
129     if (!F.hasFnAttribute("amdgpu-no-workitem-id-y") &&
130         ST.getMaxWorkitemID(F, 1) != 0)
131       WorkItemIDY = true;
132 
133     if (!F.hasFnAttribute("amdgpu-no-workitem-id-z") &&
134         ST.getMaxWorkitemID(F, 2) != 0)
135       WorkItemIDZ = true;
136 
137     if (!F.hasFnAttribute("amdgpu-no-dispatch-ptr"))
138       DispatchPtr = true;
139 
140     if (!F.hasFnAttribute("amdgpu-no-queue-ptr"))
141       QueuePtr = true;
142 
143     if (!F.hasFnAttribute("amdgpu-no-dispatch-id"))
144       DispatchID = true;
145 
146     if (!F.hasFnAttribute("amdgpu-no-hostcall-ptr"))
147       HostcallPtr = true;
148   }
149 
150   // FIXME: This attribute is a hack, we just need an analysis on the function
151   // to look for allocas.
152   bool HasStackObjects = F.hasFnAttribute("amdgpu-stack-objects");
153 
154   // TODO: This could be refined a lot. The attribute is a poor way of
155   // detecting calls or stack objects that may require it before argument
156   // lowering.
157   if (ST.hasFlatAddressSpace() && isEntryFunction() &&
158       (isAmdHsaOrMesa || ST.enableFlatScratch()) &&
159       (HasCalls || HasStackObjects || ST.enableFlatScratch()) &&
160       !ST.flatScratchIsArchitected()) {
161     FlatScratchInit = true;
162   }
163 
164   if (isEntryFunction()) {
165     // X, XY, and XYZ are the only supported combinations, so make sure Y is
166     // enabled if Z is.
167     if (WorkItemIDZ)
168       WorkItemIDY = true;
169 
170     if (!ST.flatScratchIsArchitected()) {
171       PrivateSegmentWaveByteOffset = true;
172 
173       // HS and GS always have the scratch wave offset in SGPR5 on GFX9.
174       if (ST.getGeneration() >= AMDGPUSubtarget::GFX9 &&
175           (CC == CallingConv::AMDGPU_HS || CC == CallingConv::AMDGPU_GS))
176         ArgInfo.PrivateSegmentWaveByteOffset =
177             ArgDescriptor::createRegister(AMDGPU::SGPR5);
178     }
179   }
180 
181   Attribute A = F.getFnAttribute("amdgpu-git-ptr-high");
182   StringRef S = A.getValueAsString();
183   if (!S.empty())
184     S.consumeInteger(0, GITPtrHigh);
185 
186   A = F.getFnAttribute("amdgpu-32bit-address-high-bits");
187   S = A.getValueAsString();
188   if (!S.empty())
189     S.consumeInteger(0, HighBitsOf32BitAddress);
190 
191   S = F.getFnAttribute("amdgpu-gds-size").getValueAsString();
192   if (!S.empty())
193     S.consumeInteger(0, GDSSize);
194 }
195 
196 void SIMachineFunctionInfo::limitOccupancy(const MachineFunction &MF) {
197   limitOccupancy(getMaxWavesPerEU());
198   const GCNSubtarget& ST = MF.getSubtarget<GCNSubtarget>();
199   limitOccupancy(ST.getOccupancyWithLocalMemSize(getLDSSize(),
200                  MF.getFunction()));
201 }
202 
203 Register SIMachineFunctionInfo::addPrivateSegmentBuffer(
204   const SIRegisterInfo &TRI) {
205   ArgInfo.PrivateSegmentBuffer =
206     ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
207     getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SGPR_128RegClass));
208   NumUserSGPRs += 4;
209   return ArgInfo.PrivateSegmentBuffer.getRegister();
210 }
211 
212 Register SIMachineFunctionInfo::addDispatchPtr(const SIRegisterInfo &TRI) {
213   ArgInfo.DispatchPtr = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
214     getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
215   NumUserSGPRs += 2;
216   return ArgInfo.DispatchPtr.getRegister();
217 }
218 
219 Register SIMachineFunctionInfo::addQueuePtr(const SIRegisterInfo &TRI) {
220   ArgInfo.QueuePtr = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
221     getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
222   NumUserSGPRs += 2;
223   return ArgInfo.QueuePtr.getRegister();
224 }
225 
226 Register SIMachineFunctionInfo::addKernargSegmentPtr(const SIRegisterInfo &TRI) {
227   ArgInfo.KernargSegmentPtr
228     = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
229     getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
230   NumUserSGPRs += 2;
231   return ArgInfo.KernargSegmentPtr.getRegister();
232 }
233 
234 Register SIMachineFunctionInfo::addDispatchID(const SIRegisterInfo &TRI) {
235   ArgInfo.DispatchID = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
236     getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
237   NumUserSGPRs += 2;
238   return ArgInfo.DispatchID.getRegister();
239 }
240 
241 Register SIMachineFunctionInfo::addFlatScratchInit(const SIRegisterInfo &TRI) {
242   ArgInfo.FlatScratchInit = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
243     getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
244   NumUserSGPRs += 2;
245   return ArgInfo.FlatScratchInit.getRegister();
246 }
247 
248 Register SIMachineFunctionInfo::addImplicitBufferPtr(const SIRegisterInfo &TRI) {
249   ArgInfo.ImplicitBufferPtr = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
250     getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
251   NumUserSGPRs += 2;
252   return ArgInfo.ImplicitBufferPtr.getRegister();
253 }
254 
255 bool SIMachineFunctionInfo::isCalleeSavedReg(const MCPhysReg *CSRegs,
256                                              MCPhysReg Reg) {
257   for (unsigned I = 0; CSRegs[I]; ++I) {
258     if (CSRegs[I] == Reg)
259       return true;
260   }
261 
262   return false;
263 }
264 
265 /// \p returns true if \p NumLanes slots are available in VGPRs already used for
266 /// SGPR spilling.
267 //
268 // FIXME: This only works after processFunctionBeforeFrameFinalized
269 bool SIMachineFunctionInfo::haveFreeLanesForSGPRSpill(const MachineFunction &MF,
270                                                       unsigned NumNeed) const {
271   const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
272   unsigned WaveSize = ST.getWavefrontSize();
273   return NumVGPRSpillLanes + NumNeed <= WaveSize * SpillVGPRs.size();
274 }
275 
276 /// Reserve a slice of a VGPR to support spilling for FrameIndex \p FI.
277 bool SIMachineFunctionInfo::allocateSGPRSpillToVGPR(MachineFunction &MF,
278                                                     int FI) {
279   std::vector<SpilledReg> &SpillLanes = SGPRToVGPRSpills[FI];
280 
281   // This has already been allocated.
282   if (!SpillLanes.empty())
283     return true;
284 
285   const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
286   const SIRegisterInfo *TRI = ST.getRegisterInfo();
287   MachineFrameInfo &FrameInfo = MF.getFrameInfo();
288   MachineRegisterInfo &MRI = MF.getRegInfo();
289   unsigned WaveSize = ST.getWavefrontSize();
290 
291   unsigned Size = FrameInfo.getObjectSize(FI);
292   unsigned NumLanes = Size / 4;
293 
294   if (NumLanes > WaveSize)
295     return false;
296 
297   assert(Size >= 4 && "invalid sgpr spill size");
298   assert(TRI->spillSGPRToVGPR() && "not spilling SGPRs to VGPRs");
299 
300   // Make sure to handle the case where a wide SGPR spill may span between two
301   // VGPRs.
302   for (unsigned I = 0; I < NumLanes; ++I, ++NumVGPRSpillLanes) {
303     Register LaneVGPR;
304     unsigned VGPRIndex = (NumVGPRSpillLanes % WaveSize);
305 
306     if (VGPRIndex == 0) {
307       LaneVGPR = TRI->findUnusedRegister(MRI, &AMDGPU::VGPR_32RegClass, MF);
308       if (LaneVGPR == AMDGPU::NoRegister) {
309         // We have no VGPRs left for spilling SGPRs. Reset because we will not
310         // partially spill the SGPR to VGPRs.
311         SGPRToVGPRSpills.erase(FI);
312         NumVGPRSpillLanes -= I;
313 
314         // FIXME: We can run out of free registers with split allocation if
315         // IPRA is enabled and a called function already uses every VGPR.
316 #if 0
317         DiagnosticInfoResourceLimit DiagOutOfRegs(MF.getFunction(),
318                                                   "VGPRs for SGPR spilling",
319                                                   0, DS_Error);
320         MF.getFunction().getContext().diagnose(DiagOutOfRegs);
321 #endif
322         return false;
323       }
324 
325       Optional<int> SpillFI;
326       // We need to preserve inactive lanes, so always save, even caller-save
327       // registers.
328       if (!isEntryFunction()) {
329         SpillFI = FrameInfo.CreateSpillStackObject(4, Align(4));
330       }
331 
332       SpillVGPRs.push_back(SGPRSpillVGPR(LaneVGPR, SpillFI));
333 
334       // Add this register as live-in to all blocks to avoid machine verifer
335       // complaining about use of an undefined physical register.
336       for (MachineBasicBlock &BB : MF)
337         BB.addLiveIn(LaneVGPR);
338     } else {
339       LaneVGPR = SpillVGPRs.back().VGPR;
340     }
341 
342     SpillLanes.push_back(SpilledReg(LaneVGPR, VGPRIndex));
343   }
344 
345   return true;
346 }
347 
348 /// Reserve AGPRs or VGPRs to support spilling for FrameIndex \p FI.
349 /// Either AGPR is spilled to VGPR to vice versa.
350 /// Returns true if a \p FI can be eliminated completely.
351 bool SIMachineFunctionInfo::allocateVGPRSpillToAGPR(MachineFunction &MF,
352                                                     int FI,
353                                                     bool isAGPRtoVGPR) {
354   MachineRegisterInfo &MRI = MF.getRegInfo();
355   MachineFrameInfo &FrameInfo = MF.getFrameInfo();
356   const GCNSubtarget &ST =  MF.getSubtarget<GCNSubtarget>();
357 
358   assert(ST.hasMAIInsts() && FrameInfo.isSpillSlotObjectIndex(FI));
359 
360   auto &Spill = VGPRToAGPRSpills[FI];
361 
362   // This has already been allocated.
363   if (!Spill.Lanes.empty())
364     return Spill.FullyAllocated;
365 
366   unsigned Size = FrameInfo.getObjectSize(FI);
367   unsigned NumLanes = Size / 4;
368   Spill.Lanes.resize(NumLanes, AMDGPU::NoRegister);
369 
370   const TargetRegisterClass &RC =
371       isAGPRtoVGPR ? AMDGPU::VGPR_32RegClass : AMDGPU::AGPR_32RegClass;
372   auto Regs = RC.getRegisters();
373 
374   auto &SpillRegs = isAGPRtoVGPR ? SpillAGPR : SpillVGPR;
375   const SIRegisterInfo *TRI = ST.getRegisterInfo();
376   Spill.FullyAllocated = true;
377 
378   // FIXME: Move allocation logic out of MachineFunctionInfo and initialize
379   // once.
380   BitVector OtherUsedRegs;
381   OtherUsedRegs.resize(TRI->getNumRegs());
382 
383   const uint32_t *CSRMask =
384       TRI->getCallPreservedMask(MF, MF.getFunction().getCallingConv());
385   if (CSRMask)
386     OtherUsedRegs.setBitsInMask(CSRMask);
387 
388   // TODO: Should include register tuples, but doesn't matter with current
389   // usage.
390   for (MCPhysReg Reg : SpillAGPR)
391     OtherUsedRegs.set(Reg);
392   for (MCPhysReg Reg : SpillVGPR)
393     OtherUsedRegs.set(Reg);
394 
395   SmallVectorImpl<MCPhysReg>::const_iterator NextSpillReg = Regs.begin();
396   for (int I = NumLanes - 1; I >= 0; --I) {
397     NextSpillReg = std::find_if(
398         NextSpillReg, Regs.end(), [&MRI, &OtherUsedRegs](MCPhysReg Reg) {
399           return MRI.isAllocatable(Reg) && !MRI.isPhysRegUsed(Reg) &&
400                  !OtherUsedRegs[Reg];
401         });
402 
403     if (NextSpillReg == Regs.end()) { // Registers exhausted
404       Spill.FullyAllocated = false;
405       break;
406     }
407 
408     OtherUsedRegs.set(*NextSpillReg);
409     SpillRegs.push_back(*NextSpillReg);
410     Spill.Lanes[I] = *NextSpillReg++;
411   }
412 
413   return Spill.FullyAllocated;
414 }
415 
416 bool SIMachineFunctionInfo::removeDeadFrameIndices(
417     MachineFrameInfo &MFI, bool ResetSGPRSpillStackIDs) {
418   // Remove dead frame indices from function frame, however keep FP & BP since
419   // spills for them haven't been inserted yet. And also make sure to remove the
420   // frame indices from `SGPRToVGPRSpills` data structure, otherwise, it could
421   // result in an unexpected side effect and bug, in case of any re-mapping of
422   // freed frame indices by later pass(es) like "stack slot coloring".
423   for (auto &R : make_early_inc_range(SGPRToVGPRSpills)) {
424     if (R.first != FramePointerSaveIndex && R.first != BasePointerSaveIndex) {
425       MFI.RemoveStackObject(R.first);
426       SGPRToVGPRSpills.erase(R.first);
427     }
428   }
429 
430   bool HaveSGPRToMemory = false;
431 
432   if (ResetSGPRSpillStackIDs) {
433     // All other SPGRs must be allocated on the default stack, so reset the
434     // stack ID.
435     for (int i = MFI.getObjectIndexBegin(), e = MFI.getObjectIndexEnd(); i != e;
436          ++i) {
437       if (i != FramePointerSaveIndex && i != BasePointerSaveIndex) {
438         if (MFI.getStackID(i) == TargetStackID::SGPRSpill) {
439           MFI.setStackID(i, TargetStackID::Default);
440           HaveSGPRToMemory = true;
441         }
442       }
443     }
444   }
445 
446   for (auto &R : VGPRToAGPRSpills) {
447     if (R.second.IsDead)
448       MFI.RemoveStackObject(R.first);
449   }
450 
451   return HaveSGPRToMemory;
452 }
453 
454 int SIMachineFunctionInfo::getScavengeFI(MachineFrameInfo &MFI,
455                                          const SIRegisterInfo &TRI) {
456   if (ScavengeFI)
457     return *ScavengeFI;
458   if (isEntryFunction()) {
459     ScavengeFI = MFI.CreateFixedObject(
460         TRI.getSpillSize(AMDGPU::SGPR_32RegClass), 0, false);
461   } else {
462     ScavengeFI = MFI.CreateStackObject(
463         TRI.getSpillSize(AMDGPU::SGPR_32RegClass),
464         TRI.getSpillAlign(AMDGPU::SGPR_32RegClass), false);
465   }
466   return *ScavengeFI;
467 }
468 
469 MCPhysReg SIMachineFunctionInfo::getNextUserSGPR() const {
470   assert(NumSystemSGPRs == 0 && "System SGPRs must be added after user SGPRs");
471   return AMDGPU::SGPR0 + NumUserSGPRs;
472 }
473 
474 MCPhysReg SIMachineFunctionInfo::getNextSystemSGPR() const {
475   return AMDGPU::SGPR0 + NumUserSGPRs + NumSystemSGPRs;
476 }
477 
478 Register
479 SIMachineFunctionInfo::getGITPtrLoReg(const MachineFunction &MF) const {
480   const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
481   if (!ST.isAmdPalOS())
482     return Register();
483   Register GitPtrLo = AMDGPU::SGPR0; // Low GIT address passed in
484   if (ST.hasMergedShaders()) {
485     switch (MF.getFunction().getCallingConv()) {
486     case CallingConv::AMDGPU_HS:
487     case CallingConv::AMDGPU_GS:
488       // Low GIT address is passed in s8 rather than s0 for an LS+HS or
489       // ES+GS merged shader on gfx9+.
490       GitPtrLo = AMDGPU::SGPR8;
491       return GitPtrLo;
492     default:
493       return GitPtrLo;
494     }
495   }
496   return GitPtrLo;
497 }
498 
499 static yaml::StringValue regToString(Register Reg,
500                                      const TargetRegisterInfo &TRI) {
501   yaml::StringValue Dest;
502   {
503     raw_string_ostream OS(Dest.Value);
504     OS << printReg(Reg, &TRI);
505   }
506   return Dest;
507 }
508 
509 static Optional<yaml::SIArgumentInfo>
510 convertArgumentInfo(const AMDGPUFunctionArgInfo &ArgInfo,
511                     const TargetRegisterInfo &TRI) {
512   yaml::SIArgumentInfo AI;
513 
514   auto convertArg = [&](Optional<yaml::SIArgument> &A,
515                         const ArgDescriptor &Arg) {
516     if (!Arg)
517       return false;
518 
519     // Create a register or stack argument.
520     yaml::SIArgument SA = yaml::SIArgument::createArgument(Arg.isRegister());
521     if (Arg.isRegister()) {
522       raw_string_ostream OS(SA.RegisterName.Value);
523       OS << printReg(Arg.getRegister(), &TRI);
524     } else
525       SA.StackOffset = Arg.getStackOffset();
526     // Check and update the optional mask.
527     if (Arg.isMasked())
528       SA.Mask = Arg.getMask();
529 
530     A = SA;
531     return true;
532   };
533 
534   bool Any = false;
535   Any |= convertArg(AI.PrivateSegmentBuffer, ArgInfo.PrivateSegmentBuffer);
536   Any |= convertArg(AI.DispatchPtr, ArgInfo.DispatchPtr);
537   Any |= convertArg(AI.QueuePtr, ArgInfo.QueuePtr);
538   Any |= convertArg(AI.KernargSegmentPtr, ArgInfo.KernargSegmentPtr);
539   Any |= convertArg(AI.DispatchID, ArgInfo.DispatchID);
540   Any |= convertArg(AI.FlatScratchInit, ArgInfo.FlatScratchInit);
541   Any |= convertArg(AI.PrivateSegmentSize, ArgInfo.PrivateSegmentSize);
542   Any |= convertArg(AI.WorkGroupIDX, ArgInfo.WorkGroupIDX);
543   Any |= convertArg(AI.WorkGroupIDY, ArgInfo.WorkGroupIDY);
544   Any |= convertArg(AI.WorkGroupIDZ, ArgInfo.WorkGroupIDZ);
545   Any |= convertArg(AI.WorkGroupInfo, ArgInfo.WorkGroupInfo);
546   Any |= convertArg(AI.PrivateSegmentWaveByteOffset,
547                     ArgInfo.PrivateSegmentWaveByteOffset);
548   Any |= convertArg(AI.ImplicitArgPtr, ArgInfo.ImplicitArgPtr);
549   Any |= convertArg(AI.ImplicitBufferPtr, ArgInfo.ImplicitBufferPtr);
550   Any |= convertArg(AI.WorkItemIDX, ArgInfo.WorkItemIDX);
551   Any |= convertArg(AI.WorkItemIDY, ArgInfo.WorkItemIDY);
552   Any |= convertArg(AI.WorkItemIDZ, ArgInfo.WorkItemIDZ);
553 
554   if (Any)
555     return AI;
556 
557   return None;
558 }
559 
560 yaml::SIMachineFunctionInfo::SIMachineFunctionInfo(
561     const llvm::SIMachineFunctionInfo &MFI, const TargetRegisterInfo &TRI,
562     const llvm::MachineFunction &MF)
563     : ExplicitKernArgSize(MFI.getExplicitKernArgSize()),
564       MaxKernArgAlign(MFI.getMaxKernArgAlign()), LDSSize(MFI.getLDSSize()),
565       DynLDSAlign(MFI.getDynLDSAlign()), IsEntryFunction(MFI.isEntryFunction()),
566       NoSignedZerosFPMath(MFI.hasNoSignedZerosFPMath()),
567       MemoryBound(MFI.isMemoryBound()), WaveLimiter(MFI.needsWaveLimiter()),
568       HasSpilledSGPRs(MFI.hasSpilledSGPRs()),
569       HasSpilledVGPRs(MFI.hasSpilledVGPRs()),
570       HighBitsOf32BitAddress(MFI.get32BitAddressHighBits()),
571       Occupancy(MFI.getOccupancy()),
572       ScratchRSrcReg(regToString(MFI.getScratchRSrcReg(), TRI)),
573       FrameOffsetReg(regToString(MFI.getFrameOffsetReg(), TRI)),
574       StackPtrOffsetReg(regToString(MFI.getStackPtrOffsetReg(), TRI)),
575       ArgInfo(convertArgumentInfo(MFI.getArgInfo(), TRI)), Mode(MFI.getMode()) {
576   auto SFI = MFI.getOptionalScavengeFI();
577   if (SFI)
578     ScavengeFI = yaml::FrameIndex(*SFI, MF.getFrameInfo());
579 }
580 
581 void yaml::SIMachineFunctionInfo::mappingImpl(yaml::IO &YamlIO) {
582   MappingTraits<SIMachineFunctionInfo>::mapping(YamlIO, *this);
583 }
584 
585 bool SIMachineFunctionInfo::initializeBaseYamlFields(
586     const yaml::SIMachineFunctionInfo &YamlMFI, const MachineFunction &MF,
587     PerFunctionMIParsingState &PFS, SMDiagnostic &Error, SMRange &SourceRange) {
588   ExplicitKernArgSize = YamlMFI.ExplicitKernArgSize;
589   MaxKernArgAlign = assumeAligned(YamlMFI.MaxKernArgAlign);
590   LDSSize = YamlMFI.LDSSize;
591   DynLDSAlign = YamlMFI.DynLDSAlign;
592   HighBitsOf32BitAddress = YamlMFI.HighBitsOf32BitAddress;
593   Occupancy = YamlMFI.Occupancy;
594   IsEntryFunction = YamlMFI.IsEntryFunction;
595   NoSignedZerosFPMath = YamlMFI.NoSignedZerosFPMath;
596   MemoryBound = YamlMFI.MemoryBound;
597   WaveLimiter = YamlMFI.WaveLimiter;
598   HasSpilledSGPRs = YamlMFI.HasSpilledSGPRs;
599   HasSpilledVGPRs = YamlMFI.HasSpilledVGPRs;
600 
601   if (YamlMFI.ScavengeFI) {
602     auto FIOrErr = YamlMFI.ScavengeFI->getFI(MF.getFrameInfo());
603     if (!FIOrErr) {
604       // Create a diagnostic for a the frame index.
605       const MemoryBuffer &Buffer =
606           *PFS.SM->getMemoryBuffer(PFS.SM->getMainFileID());
607 
608       Error = SMDiagnostic(*PFS.SM, SMLoc(), Buffer.getBufferIdentifier(), 1, 1,
609                            SourceMgr::DK_Error, toString(FIOrErr.takeError()),
610                            "", None, None);
611       SourceRange = YamlMFI.ScavengeFI->SourceRange;
612       return true;
613     }
614     ScavengeFI = *FIOrErr;
615   } else {
616     ScavengeFI = None;
617   }
618   return false;
619 }
620 
621 bool SIMachineFunctionInfo::mayUseAGPRs(const MachineFunction &MF) const {
622   for (const BasicBlock &BB : MF.getFunction()) {
623     for (const Instruction &I : BB) {
624       const auto *CB = dyn_cast<CallBase>(&I);
625       if (!CB)
626         continue;
627 
628       if (CB->isInlineAsm()) {
629         const InlineAsm *IA = dyn_cast<InlineAsm>(CB->getCalledOperand());
630         for (const auto &CI : IA->ParseConstraints()) {
631           for (StringRef Code : CI.Codes) {
632             Code.consume_front("{");
633             if (Code.startswith("a"))
634               return true;
635           }
636         }
637         continue;
638       }
639 
640       const Function *Callee =
641           dyn_cast<Function>(CB->getCalledOperand()->stripPointerCasts());
642       if (!Callee)
643         return true;
644 
645       if (Callee->getIntrinsicID() == Intrinsic::not_intrinsic)
646         return true;
647     }
648   }
649 
650   return false;
651 }
652 
653 bool SIMachineFunctionInfo::usesAGPRs(const MachineFunction &MF) const {
654   if (UsesAGPRs)
655     return *UsesAGPRs;
656 
657   if (!mayNeedAGPRs()) {
658     UsesAGPRs = false;
659     return false;
660   }
661 
662   if (!AMDGPU::isEntryFunctionCC(MF.getFunction().getCallingConv()) ||
663       MF.getFrameInfo().hasCalls()) {
664     UsesAGPRs = true;
665     return true;
666   }
667 
668   const MachineRegisterInfo &MRI = MF.getRegInfo();
669 
670   for (unsigned I = 0, E = MRI.getNumVirtRegs(); I != E; ++I) {
671     const Register Reg = Register::index2VirtReg(I);
672     const TargetRegisterClass *RC = MRI.getRegClassOrNull(Reg);
673     if (RC && SIRegisterInfo::isAGPRClass(RC)) {
674       UsesAGPRs = true;
675       return true;
676     } else if (!RC && !MRI.use_empty(Reg) && MRI.getType(Reg).isValid()) {
677       // Defer caching UsesAGPRs, function might not yet been regbank selected.
678       return true;
679     }
680   }
681 
682   for (MCRegister Reg : AMDGPU::AGPR_32RegClass) {
683     if (MRI.isPhysRegUsed(Reg)) {
684       UsesAGPRs = true;
685       return true;
686     }
687   }
688 
689   UsesAGPRs = false;
690   return false;
691 }
692