1 //===- SIMachineFunctionInfo.cpp - SI Machine Function Info ---------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #include "SIMachineFunctionInfo.h"
10 #include "AMDGPUTargetMachine.h"
11 #include "AMDGPUSubtarget.h"
12 #include "SIRegisterInfo.h"
13 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
14 #include "Utils/AMDGPUBaseInfo.h"
15 #include "llvm/ADT/Optional.h"
16 #include "llvm/CodeGen/LiveIntervals.h"
17 #include "llvm/CodeGen/MachineBasicBlock.h"
18 #include "llvm/CodeGen/MachineFrameInfo.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/MachineRegisterInfo.h"
21 #include "llvm/CodeGen/MIRParser/MIParser.h"
22 #include "llvm/IR/CallingConv.h"
23 #include "llvm/IR/DiagnosticInfo.h"
24 #include "llvm/IR/Function.h"
25 #include <cassert>
26 #include <vector>
27 
28 #define MAX_LANES 64
29 
30 using namespace llvm;
31 
32 SIMachineFunctionInfo::SIMachineFunctionInfo(const MachineFunction &MF)
33   : AMDGPUMachineFunction(MF),
34     PrivateSegmentBuffer(false),
35     DispatchPtr(false),
36     QueuePtr(false),
37     KernargSegmentPtr(false),
38     DispatchID(false),
39     FlatScratchInit(false),
40     WorkGroupIDX(false),
41     WorkGroupIDY(false),
42     WorkGroupIDZ(false),
43     WorkGroupInfo(false),
44     PrivateSegmentWaveByteOffset(false),
45     WorkItemIDX(false),
46     WorkItemIDY(false),
47     WorkItemIDZ(false),
48     ImplicitBufferPtr(false),
49     ImplicitArgPtr(false),
50     GITPtrHigh(0xffffffff),
51     HighBitsOf32BitAddress(0),
52     GDSSize(0) {
53   const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
54   const Function &F = MF.getFunction();
55   FlatWorkGroupSizes = ST.getFlatWorkGroupSizes(F);
56   WavesPerEU = ST.getWavesPerEU(F);
57 
58   Occupancy = ST.computeOccupancy(F, getLDSSize());
59   CallingConv::ID CC = F.getCallingConv();
60 
61   // FIXME: Should have analysis or something rather than attribute to detect
62   // calls.
63   const bool HasCalls = F.hasFnAttribute("amdgpu-calls");
64 
65   const bool IsKernel = CC == CallingConv::AMDGPU_KERNEL ||
66                         CC == CallingConv::SPIR_KERNEL;
67 
68   if (IsKernel) {
69     if (!F.arg_empty() || ST.getImplicitArgNumBytes(F) != 0)
70       KernargSegmentPtr = true;
71     WorkGroupIDX = true;
72     WorkItemIDX = true;
73   } else if (CC == CallingConv::AMDGPU_PS) {
74     PSInputAddr = AMDGPU::getInitialPSInputAddr(F);
75   }
76 
77   if (!isEntryFunction()) {
78     if (CC != CallingConv::AMDGPU_Gfx)
79       ArgInfo = AMDGPUArgumentUsageInfo::FixedABIFunctionInfo;
80 
81     // TODO: Pick a high register, and shift down, similar to a kernel.
82     FrameOffsetReg = AMDGPU::SGPR33;
83     StackPtrOffsetReg = AMDGPU::SGPR32;
84 
85     if (!ST.enableFlatScratch()) {
86       // Non-entry functions have no special inputs for now, other registers
87       // required for scratch access.
88       ScratchRSrcReg = AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3;
89 
90       ArgInfo.PrivateSegmentBuffer =
91         ArgDescriptor::createRegister(ScratchRSrcReg);
92     }
93 
94     if (!F.hasFnAttribute("amdgpu-no-implicitarg-ptr"))
95       ImplicitArgPtr = true;
96   } else {
97     ImplicitArgPtr = false;
98     MaxKernArgAlign = std::max(ST.getAlignmentForImplicitArgPtr(),
99                                MaxKernArgAlign);
100   }
101 
102   bool isAmdHsaOrMesa = ST.isAmdHsaOrMesa(F);
103   if (isAmdHsaOrMesa && !ST.enableFlatScratch())
104     PrivateSegmentBuffer = true;
105   else if (ST.isMesaGfxShader(F))
106     ImplicitBufferPtr = true;
107 
108   if (!AMDGPU::isGraphics(CC)) {
109     if (IsKernel || !F.hasFnAttribute("amdgpu-no-workgroup-id-x"))
110       WorkGroupIDX = true;
111 
112     if (!F.hasFnAttribute("amdgpu-no-workgroup-id-y"))
113       WorkGroupIDY = true;
114 
115     if (!F.hasFnAttribute("amdgpu-no-workgroup-id-z"))
116       WorkGroupIDZ = true;
117 
118     if (IsKernel || !F.hasFnAttribute("amdgpu-no-workitem-id-x"))
119       WorkItemIDX = true;
120 
121     if (!F.hasFnAttribute("amdgpu-no-workitem-id-y"))
122       WorkItemIDY = true;
123 
124     if (!F.hasFnAttribute("amdgpu-no-workitem-id-z"))
125       WorkItemIDZ = true;
126 
127     if (!F.hasFnAttribute("amdgpu-no-dispatch-ptr"))
128       DispatchPtr = true;
129 
130     if (!F.hasFnAttribute("amdgpu-no-queue-ptr"))
131       QueuePtr = true;
132 
133     if (!F.hasFnAttribute("amdgpu-no-dispatch-id"))
134       DispatchID = true;
135   }
136 
137   // FIXME: This attribute is a hack, we just need an analysis on the function
138   // to look for allocas.
139   bool HasStackObjects = F.hasFnAttribute("amdgpu-stack-objects");
140 
141   // TODO: This could be refined a lot. The attribute is a poor way of
142   // detecting calls or stack objects that may require it before argument
143   // lowering.
144   if (ST.hasFlatAddressSpace() && isEntryFunction() &&
145       (isAmdHsaOrMesa || ST.enableFlatScratch()) &&
146       (HasCalls || HasStackObjects || ST.enableFlatScratch()) &&
147       !ST.flatScratchIsArchitected()) {
148     FlatScratchInit = true;
149   }
150 
151   if (isEntryFunction()) {
152     // X, XY, and XYZ are the only supported combinations, so make sure Y is
153     // enabled if Z is.
154     if (WorkItemIDZ)
155       WorkItemIDY = true;
156 
157     if (!ST.flatScratchIsArchitected()) {
158       PrivateSegmentWaveByteOffset = true;
159 
160       // HS and GS always have the scratch wave offset in SGPR5 on GFX9.
161       if (ST.getGeneration() >= AMDGPUSubtarget::GFX9 &&
162           (CC == CallingConv::AMDGPU_HS || CC == CallingConv::AMDGPU_GS))
163         ArgInfo.PrivateSegmentWaveByteOffset =
164             ArgDescriptor::createRegister(AMDGPU::SGPR5);
165     }
166   }
167 
168   Attribute A = F.getFnAttribute("amdgpu-git-ptr-high");
169   StringRef S = A.getValueAsString();
170   if (!S.empty())
171     S.consumeInteger(0, GITPtrHigh);
172 
173   A = F.getFnAttribute("amdgpu-32bit-address-high-bits");
174   S = A.getValueAsString();
175   if (!S.empty())
176     S.consumeInteger(0, HighBitsOf32BitAddress);
177 
178   S = F.getFnAttribute("amdgpu-gds-size").getValueAsString();
179   if (!S.empty())
180     S.consumeInteger(0, GDSSize);
181 }
182 
183 void SIMachineFunctionInfo::limitOccupancy(const MachineFunction &MF) {
184   limitOccupancy(getMaxWavesPerEU());
185   const GCNSubtarget& ST = MF.getSubtarget<GCNSubtarget>();
186   limitOccupancy(ST.getOccupancyWithLocalMemSize(getLDSSize(),
187                  MF.getFunction()));
188 }
189 
190 Register SIMachineFunctionInfo::addPrivateSegmentBuffer(
191   const SIRegisterInfo &TRI) {
192   ArgInfo.PrivateSegmentBuffer =
193     ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
194     getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SGPR_128RegClass));
195   NumUserSGPRs += 4;
196   return ArgInfo.PrivateSegmentBuffer.getRegister();
197 }
198 
199 Register SIMachineFunctionInfo::addDispatchPtr(const SIRegisterInfo &TRI) {
200   ArgInfo.DispatchPtr = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
201     getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
202   NumUserSGPRs += 2;
203   return ArgInfo.DispatchPtr.getRegister();
204 }
205 
206 Register SIMachineFunctionInfo::addQueuePtr(const SIRegisterInfo &TRI) {
207   ArgInfo.QueuePtr = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
208     getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
209   NumUserSGPRs += 2;
210   return ArgInfo.QueuePtr.getRegister();
211 }
212 
213 Register SIMachineFunctionInfo::addKernargSegmentPtr(const SIRegisterInfo &TRI) {
214   ArgInfo.KernargSegmentPtr
215     = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
216     getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
217   NumUserSGPRs += 2;
218   return ArgInfo.KernargSegmentPtr.getRegister();
219 }
220 
221 Register SIMachineFunctionInfo::addDispatchID(const SIRegisterInfo &TRI) {
222   ArgInfo.DispatchID = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
223     getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
224   NumUserSGPRs += 2;
225   return ArgInfo.DispatchID.getRegister();
226 }
227 
228 Register SIMachineFunctionInfo::addFlatScratchInit(const SIRegisterInfo &TRI) {
229   ArgInfo.FlatScratchInit = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
230     getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
231   NumUserSGPRs += 2;
232   return ArgInfo.FlatScratchInit.getRegister();
233 }
234 
235 Register SIMachineFunctionInfo::addImplicitBufferPtr(const SIRegisterInfo &TRI) {
236   ArgInfo.ImplicitBufferPtr = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
237     getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
238   NumUserSGPRs += 2;
239   return ArgInfo.ImplicitBufferPtr.getRegister();
240 }
241 
242 bool SIMachineFunctionInfo::isCalleeSavedReg(const MCPhysReg *CSRegs,
243                                              MCPhysReg Reg) {
244   for (unsigned I = 0; CSRegs[I]; ++I) {
245     if (CSRegs[I] == Reg)
246       return true;
247   }
248 
249   return false;
250 }
251 
252 /// \p returns true if \p NumLanes slots are available in VGPRs already used for
253 /// SGPR spilling.
254 //
255 // FIXME: This only works after processFunctionBeforeFrameFinalized
256 bool SIMachineFunctionInfo::haveFreeLanesForSGPRSpill(const MachineFunction &MF,
257                                                       unsigned NumNeed) const {
258   const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
259   unsigned WaveSize = ST.getWavefrontSize();
260   return NumVGPRSpillLanes + NumNeed <= WaveSize * SpillVGPRs.size();
261 }
262 
263 /// Reserve a slice of a VGPR to support spilling for FrameIndex \p FI.
264 bool SIMachineFunctionInfo::allocateSGPRSpillToVGPR(MachineFunction &MF,
265                                                     int FI) {
266   std::vector<SpilledReg> &SpillLanes = SGPRToVGPRSpills[FI];
267 
268   // This has already been allocated.
269   if (!SpillLanes.empty())
270     return true;
271 
272   const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
273   const SIRegisterInfo *TRI = ST.getRegisterInfo();
274   MachineFrameInfo &FrameInfo = MF.getFrameInfo();
275   MachineRegisterInfo &MRI = MF.getRegInfo();
276   unsigned WaveSize = ST.getWavefrontSize();
277   SIMachineFunctionInfo *FuncInfo = MF.getInfo<SIMachineFunctionInfo>();
278 
279   unsigned Size = FrameInfo.getObjectSize(FI);
280   unsigned NumLanes = Size / 4;
281 
282   if (NumLanes > WaveSize)
283     return false;
284 
285   assert(Size >= 4 && "invalid sgpr spill size");
286   assert(TRI->spillSGPRToVGPR() && "not spilling SGPRs to VGPRs");
287 
288   // Make sure to handle the case where a wide SGPR spill may span between two
289   // VGPRs.
290   for (unsigned I = 0; I < NumLanes; ++I, ++NumVGPRSpillLanes) {
291     Register LaneVGPR;
292     unsigned VGPRIndex = (NumVGPRSpillLanes % WaveSize);
293 
294     // Reserve a VGPR (when NumVGPRSpillLanes = 0, WaveSize, 2*WaveSize, ..) and
295     // when one of the two conditions is true:
296     // 1. One reserved VGPR being tracked by VGPRReservedForSGPRSpill is not yet
297     // reserved.
298     // 2. All spill lanes of reserved VGPR(s) are full and another spill lane is
299     // required.
300     if (FuncInfo->VGPRReservedForSGPRSpill && NumVGPRSpillLanes < WaveSize) {
301       assert(FuncInfo->VGPRReservedForSGPRSpill == SpillVGPRs.back().VGPR);
302       LaneVGPR = FuncInfo->VGPRReservedForSGPRSpill;
303     } else if (VGPRIndex == 0) {
304       LaneVGPR = TRI->findUnusedRegister(MRI, &AMDGPU::VGPR_32RegClass, MF);
305       if (LaneVGPR == AMDGPU::NoRegister) {
306         // We have no VGPRs left for spilling SGPRs. Reset because we will not
307         // partially spill the SGPR to VGPRs.
308         SGPRToVGPRSpills.erase(FI);
309         NumVGPRSpillLanes -= I;
310 
311 #if 0
312         DiagnosticInfoResourceLimit DiagOutOfRegs(MF.getFunction(),
313                                                   "VGPRs for SGPR spilling",
314                                                   0, DS_Error);
315         MF.getFunction().getContext().diagnose(DiagOutOfRegs);
316 #endif
317         return false;
318       }
319 
320       Optional<int> SpillFI;
321       // We need to preserve inactive lanes, so always save, even caller-save
322       // registers.
323       if (!isEntryFunction()) {
324         SpillFI = FrameInfo.CreateSpillStackObject(4, Align(4));
325       }
326 
327       SpillVGPRs.push_back(SGPRSpillVGPR(LaneVGPR, SpillFI));
328 
329       // Add this register as live-in to all blocks to avoid machine verifer
330       // complaining about use of an undefined physical register.
331       for (MachineBasicBlock &BB : MF)
332         BB.addLiveIn(LaneVGPR);
333     } else {
334       LaneVGPR = SpillVGPRs.back().VGPR;
335     }
336 
337     SpillLanes.push_back(SpilledReg(LaneVGPR, VGPRIndex));
338   }
339 
340   return true;
341 }
342 
343 /// Reserve a VGPR for spilling of SGPRs
344 bool SIMachineFunctionInfo::reserveVGPRforSGPRSpills(MachineFunction &MF) {
345   const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
346   const SIRegisterInfo *TRI = ST.getRegisterInfo();
347   SIMachineFunctionInfo *FuncInfo = MF.getInfo<SIMachineFunctionInfo>();
348 
349   Register LaneVGPR = TRI->findUnusedRegister(
350       MF.getRegInfo(), &AMDGPU::VGPR_32RegClass, MF, true);
351   if (LaneVGPR == Register())
352     return false;
353   SpillVGPRs.push_back(SGPRSpillVGPR(LaneVGPR, None));
354   FuncInfo->VGPRReservedForSGPRSpill = LaneVGPR;
355   return true;
356 }
357 
358 /// Reserve AGPRs or VGPRs to support spilling for FrameIndex \p FI.
359 /// Either AGPR is spilled to VGPR to vice versa.
360 /// Returns true if a \p FI can be eliminated completely.
361 bool SIMachineFunctionInfo::allocateVGPRSpillToAGPR(MachineFunction &MF,
362                                                     int FI,
363                                                     bool isAGPRtoVGPR) {
364   MachineRegisterInfo &MRI = MF.getRegInfo();
365   MachineFrameInfo &FrameInfo = MF.getFrameInfo();
366   const GCNSubtarget &ST =  MF.getSubtarget<GCNSubtarget>();
367 
368   assert(ST.hasMAIInsts() && FrameInfo.isSpillSlotObjectIndex(FI));
369 
370   auto &Spill = VGPRToAGPRSpills[FI];
371 
372   // This has already been allocated.
373   if (!Spill.Lanes.empty())
374     return Spill.FullyAllocated;
375 
376   unsigned Size = FrameInfo.getObjectSize(FI);
377   unsigned NumLanes = Size / 4;
378   Spill.Lanes.resize(NumLanes, AMDGPU::NoRegister);
379 
380   const TargetRegisterClass &RC =
381       isAGPRtoVGPR ? AMDGPU::VGPR_32RegClass : AMDGPU::AGPR_32RegClass;
382   auto Regs = RC.getRegisters();
383 
384   auto &SpillRegs = isAGPRtoVGPR ? SpillAGPR : SpillVGPR;
385   const SIRegisterInfo *TRI = ST.getRegisterInfo();
386   Spill.FullyAllocated = true;
387 
388   // FIXME: Move allocation logic out of MachineFunctionInfo and initialize
389   // once.
390   BitVector OtherUsedRegs;
391   OtherUsedRegs.resize(TRI->getNumRegs());
392 
393   const uint32_t *CSRMask =
394       TRI->getCallPreservedMask(MF, MF.getFunction().getCallingConv());
395   if (CSRMask)
396     OtherUsedRegs.setBitsInMask(CSRMask);
397 
398   // TODO: Should include register tuples, but doesn't matter with current
399   // usage.
400   for (MCPhysReg Reg : SpillAGPR)
401     OtherUsedRegs.set(Reg);
402   for (MCPhysReg Reg : SpillVGPR)
403     OtherUsedRegs.set(Reg);
404 
405   SmallVectorImpl<MCPhysReg>::const_iterator NextSpillReg = Regs.begin();
406   for (int I = NumLanes - 1; I >= 0; --I) {
407     NextSpillReg = std::find_if(
408         NextSpillReg, Regs.end(), [&MRI, &OtherUsedRegs](MCPhysReg Reg) {
409           return MRI.isAllocatable(Reg) && !MRI.isPhysRegUsed(Reg) &&
410                  !OtherUsedRegs[Reg];
411         });
412 
413     if (NextSpillReg == Regs.end()) { // Registers exhausted
414       Spill.FullyAllocated = false;
415       break;
416     }
417 
418     OtherUsedRegs.set(*NextSpillReg);
419     SpillRegs.push_back(*NextSpillReg);
420     Spill.Lanes[I] = *NextSpillReg++;
421   }
422 
423   return Spill.FullyAllocated;
424 }
425 
426 void SIMachineFunctionInfo::removeDeadFrameIndices(MachineFrameInfo &MFI) {
427   // Remove dead frame indices from function frame, however keep FP & BP since
428   // spills for them haven't been inserted yet. And also make sure to remove the
429   // frame indices from `SGPRToVGPRSpills` data structure, otherwise, it could
430   // result in an unexpected side effect and bug, in case of any re-mapping of
431   // freed frame indices by later pass(es) like "stack slot coloring".
432   for (auto &R : make_early_inc_range(SGPRToVGPRSpills)) {
433     if (R.first != FramePointerSaveIndex && R.first != BasePointerSaveIndex) {
434       MFI.RemoveStackObject(R.first);
435       SGPRToVGPRSpills.erase(R.first);
436     }
437   }
438 
439   // All other SPGRs must be allocated on the default stack, so reset the stack
440   // ID.
441   for (int i = MFI.getObjectIndexBegin(), e = MFI.getObjectIndexEnd(); i != e;
442        ++i)
443     if (i != FramePointerSaveIndex && i != BasePointerSaveIndex)
444       MFI.setStackID(i, TargetStackID::Default);
445 
446   for (auto &R : VGPRToAGPRSpills) {
447     if (R.second.IsDead)
448       MFI.RemoveStackObject(R.first);
449   }
450 }
451 
452 int SIMachineFunctionInfo::getScavengeFI(MachineFrameInfo &MFI,
453                                          const SIRegisterInfo &TRI) {
454   if (ScavengeFI)
455     return *ScavengeFI;
456   if (isEntryFunction()) {
457     ScavengeFI = MFI.CreateFixedObject(
458         TRI.getSpillSize(AMDGPU::SGPR_32RegClass), 0, false);
459   } else {
460     ScavengeFI = MFI.CreateStackObject(
461         TRI.getSpillSize(AMDGPU::SGPR_32RegClass),
462         TRI.getSpillAlign(AMDGPU::SGPR_32RegClass), false);
463   }
464   return *ScavengeFI;
465 }
466 
467 MCPhysReg SIMachineFunctionInfo::getNextUserSGPR() const {
468   assert(NumSystemSGPRs == 0 && "System SGPRs must be added after user SGPRs");
469   return AMDGPU::SGPR0 + NumUserSGPRs;
470 }
471 
472 MCPhysReg SIMachineFunctionInfo::getNextSystemSGPR() const {
473   return AMDGPU::SGPR0 + NumUserSGPRs + NumSystemSGPRs;
474 }
475 
476 Register
477 SIMachineFunctionInfo::getGITPtrLoReg(const MachineFunction &MF) const {
478   const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
479   if (!ST.isAmdPalOS())
480     return Register();
481   Register GitPtrLo = AMDGPU::SGPR0; // Low GIT address passed in
482   if (ST.hasMergedShaders()) {
483     switch (MF.getFunction().getCallingConv()) {
484     case CallingConv::AMDGPU_HS:
485     case CallingConv::AMDGPU_GS:
486       // Low GIT address is passed in s8 rather than s0 for an LS+HS or
487       // ES+GS merged shader on gfx9+.
488       GitPtrLo = AMDGPU::SGPR8;
489       return GitPtrLo;
490     default:
491       return GitPtrLo;
492     }
493   }
494   return GitPtrLo;
495 }
496 
497 static yaml::StringValue regToString(Register Reg,
498                                      const TargetRegisterInfo &TRI) {
499   yaml::StringValue Dest;
500   {
501     raw_string_ostream OS(Dest.Value);
502     OS << printReg(Reg, &TRI);
503   }
504   return Dest;
505 }
506 
507 static Optional<yaml::SIArgumentInfo>
508 convertArgumentInfo(const AMDGPUFunctionArgInfo &ArgInfo,
509                     const TargetRegisterInfo &TRI) {
510   yaml::SIArgumentInfo AI;
511 
512   auto convertArg = [&](Optional<yaml::SIArgument> &A,
513                         const ArgDescriptor &Arg) {
514     if (!Arg)
515       return false;
516 
517     // Create a register or stack argument.
518     yaml::SIArgument SA = yaml::SIArgument::createArgument(Arg.isRegister());
519     if (Arg.isRegister()) {
520       raw_string_ostream OS(SA.RegisterName.Value);
521       OS << printReg(Arg.getRegister(), &TRI);
522     } else
523       SA.StackOffset = Arg.getStackOffset();
524     // Check and update the optional mask.
525     if (Arg.isMasked())
526       SA.Mask = Arg.getMask();
527 
528     A = SA;
529     return true;
530   };
531 
532   bool Any = false;
533   Any |= convertArg(AI.PrivateSegmentBuffer, ArgInfo.PrivateSegmentBuffer);
534   Any |= convertArg(AI.DispatchPtr, ArgInfo.DispatchPtr);
535   Any |= convertArg(AI.QueuePtr, ArgInfo.QueuePtr);
536   Any |= convertArg(AI.KernargSegmentPtr, ArgInfo.KernargSegmentPtr);
537   Any |= convertArg(AI.DispatchID, ArgInfo.DispatchID);
538   Any |= convertArg(AI.FlatScratchInit, ArgInfo.FlatScratchInit);
539   Any |= convertArg(AI.PrivateSegmentSize, ArgInfo.PrivateSegmentSize);
540   Any |= convertArg(AI.WorkGroupIDX, ArgInfo.WorkGroupIDX);
541   Any |= convertArg(AI.WorkGroupIDY, ArgInfo.WorkGroupIDY);
542   Any |= convertArg(AI.WorkGroupIDZ, ArgInfo.WorkGroupIDZ);
543   Any |= convertArg(AI.WorkGroupInfo, ArgInfo.WorkGroupInfo);
544   Any |= convertArg(AI.PrivateSegmentWaveByteOffset,
545                     ArgInfo.PrivateSegmentWaveByteOffset);
546   Any |= convertArg(AI.ImplicitArgPtr, ArgInfo.ImplicitArgPtr);
547   Any |= convertArg(AI.ImplicitBufferPtr, ArgInfo.ImplicitBufferPtr);
548   Any |= convertArg(AI.WorkItemIDX, ArgInfo.WorkItemIDX);
549   Any |= convertArg(AI.WorkItemIDY, ArgInfo.WorkItemIDY);
550   Any |= convertArg(AI.WorkItemIDZ, ArgInfo.WorkItemIDZ);
551 
552   if (Any)
553     return AI;
554 
555   return None;
556 }
557 
558 yaml::SIMachineFunctionInfo::SIMachineFunctionInfo(
559     const llvm::SIMachineFunctionInfo &MFI, const TargetRegisterInfo &TRI,
560     const llvm::MachineFunction &MF)
561     : ExplicitKernArgSize(MFI.getExplicitKernArgSize()),
562       MaxKernArgAlign(MFI.getMaxKernArgAlign()), LDSSize(MFI.getLDSSize()),
563       DynLDSAlign(MFI.getDynLDSAlign()), IsEntryFunction(MFI.isEntryFunction()),
564       NoSignedZerosFPMath(MFI.hasNoSignedZerosFPMath()),
565       MemoryBound(MFI.isMemoryBound()), WaveLimiter(MFI.needsWaveLimiter()),
566       HasSpilledSGPRs(MFI.hasSpilledSGPRs()),
567       HasSpilledVGPRs(MFI.hasSpilledVGPRs()),
568       HighBitsOf32BitAddress(MFI.get32BitAddressHighBits()),
569       Occupancy(MFI.getOccupancy()),
570       ScratchRSrcReg(regToString(MFI.getScratchRSrcReg(), TRI)),
571       FrameOffsetReg(regToString(MFI.getFrameOffsetReg(), TRI)),
572       StackPtrOffsetReg(regToString(MFI.getStackPtrOffsetReg(), TRI)),
573       ArgInfo(convertArgumentInfo(MFI.getArgInfo(), TRI)), Mode(MFI.getMode()) {
574   auto SFI = MFI.getOptionalScavengeFI();
575   if (SFI)
576     ScavengeFI = yaml::FrameIndex(*SFI, MF.getFrameInfo());
577 }
578 
579 void yaml::SIMachineFunctionInfo::mappingImpl(yaml::IO &YamlIO) {
580   MappingTraits<SIMachineFunctionInfo>::mapping(YamlIO, *this);
581 }
582 
583 bool SIMachineFunctionInfo::initializeBaseYamlFields(
584     const yaml::SIMachineFunctionInfo &YamlMFI, const MachineFunction &MF,
585     PerFunctionMIParsingState &PFS, SMDiagnostic &Error, SMRange &SourceRange) {
586   ExplicitKernArgSize = YamlMFI.ExplicitKernArgSize;
587   MaxKernArgAlign = assumeAligned(YamlMFI.MaxKernArgAlign);
588   LDSSize = YamlMFI.LDSSize;
589   DynLDSAlign = YamlMFI.DynLDSAlign;
590   HighBitsOf32BitAddress = YamlMFI.HighBitsOf32BitAddress;
591   Occupancy = YamlMFI.Occupancy;
592   IsEntryFunction = YamlMFI.IsEntryFunction;
593   NoSignedZerosFPMath = YamlMFI.NoSignedZerosFPMath;
594   MemoryBound = YamlMFI.MemoryBound;
595   WaveLimiter = YamlMFI.WaveLimiter;
596   HasSpilledSGPRs = YamlMFI.HasSpilledSGPRs;
597   HasSpilledVGPRs = YamlMFI.HasSpilledVGPRs;
598 
599   if (YamlMFI.ScavengeFI) {
600     auto FIOrErr = YamlMFI.ScavengeFI->getFI(MF.getFrameInfo());
601     if (!FIOrErr) {
602       // Create a diagnostic for a the frame index.
603       const MemoryBuffer &Buffer =
604           *PFS.SM->getMemoryBuffer(PFS.SM->getMainFileID());
605 
606       Error = SMDiagnostic(*PFS.SM, SMLoc(), Buffer.getBufferIdentifier(), 1, 1,
607                            SourceMgr::DK_Error, toString(FIOrErr.takeError()),
608                            "", None, None);
609       SourceRange = YamlMFI.ScavengeFI->SourceRange;
610       return true;
611     }
612     ScavengeFI = *FIOrErr;
613   } else {
614     ScavengeFI = None;
615   }
616   return false;
617 }
618 
619 // Remove VGPR which was reserved for SGPR spills if there are no spilled SGPRs
620 bool SIMachineFunctionInfo::removeVGPRForSGPRSpill(Register ReservedVGPR,
621                                                    MachineFunction &MF) {
622   for (auto *i = SpillVGPRs.begin(); i < SpillVGPRs.end(); i++) {
623     if (i->VGPR == ReservedVGPR) {
624       SpillVGPRs.erase(i);
625 
626       for (MachineBasicBlock &MBB : MF) {
627         MBB.removeLiveIn(ReservedVGPR);
628         MBB.sortUniqueLiveIns();
629       }
630       this->VGPRReservedForSGPRSpill = AMDGPU::NoRegister;
631       return true;
632     }
633   }
634   return false;
635 }
636 
637 bool SIMachineFunctionInfo::usesAGPRs(const MachineFunction &MF) const {
638   if (UsesAGPRs)
639     return *UsesAGPRs;
640 
641   if (!AMDGPU::isEntryFunctionCC(MF.getFunction().getCallingConv()) ||
642       MF.getFrameInfo().hasCalls()) {
643     UsesAGPRs = true;
644     return true;
645   }
646 
647   const MachineRegisterInfo &MRI = MF.getRegInfo();
648 
649   for (unsigned I = 0, E = MRI.getNumVirtRegs(); I != E; ++I) {
650     const Register Reg = Register::index2VirtReg(I);
651     const TargetRegisterClass *RC = MRI.getRegClassOrNull(Reg);
652     if (RC && SIRegisterInfo::isAGPRClass(RC)) {
653       UsesAGPRs = true;
654       return true;
655     } else if (!RC && !MRI.use_empty(Reg) && MRI.getType(Reg).isValid()) {
656       // Defer caching UsesAGPRs, function might not yet been regbank selected.
657       return true;
658     }
659   }
660 
661   for (MCRegister Reg : AMDGPU::AGPR_32RegClass) {
662     if (MRI.isPhysRegUsed(Reg)) {
663       UsesAGPRs = true;
664       return true;
665     }
666   }
667 
668   UsesAGPRs = false;
669   return false;
670 }
671