1 //===- SIMachineFunctionInfo.cpp - SI Machine Function Info ---------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #include "SIMachineFunctionInfo.h"
10 #include "AMDGPUTargetMachine.h"
11 #include "AMDGPUSubtarget.h"
12 #include "SIRegisterInfo.h"
13 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
14 #include "Utils/AMDGPUBaseInfo.h"
15 #include "llvm/ADT/Optional.h"
16 #include "llvm/CodeGen/LiveIntervals.h"
17 #include "llvm/CodeGen/MachineBasicBlock.h"
18 #include "llvm/CodeGen/MachineFrameInfo.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/MachineRegisterInfo.h"
21 #include "llvm/CodeGen/MIRParser/MIParser.h"
22 #include "llvm/IR/CallingConv.h"
23 #include "llvm/IR/DiagnosticInfo.h"
24 #include "llvm/IR/Function.h"
25 #include <cassert>
26 #include <vector>
27 
28 #define MAX_LANES 64
29 
30 using namespace llvm;
31 
32 SIMachineFunctionInfo::SIMachineFunctionInfo(const MachineFunction &MF)
33   : AMDGPUMachineFunction(MF),
34     PrivateSegmentBuffer(false),
35     DispatchPtr(false),
36     QueuePtr(false),
37     KernargSegmentPtr(false),
38     DispatchID(false),
39     FlatScratchInit(false),
40     WorkGroupIDX(false),
41     WorkGroupIDY(false),
42     WorkGroupIDZ(false),
43     WorkGroupInfo(false),
44     PrivateSegmentWaveByteOffset(false),
45     WorkItemIDX(false),
46     WorkItemIDY(false),
47     WorkItemIDZ(false),
48     ImplicitBufferPtr(false),
49     ImplicitArgPtr(false),
50     GITPtrHigh(0xffffffff),
51     HighBitsOf32BitAddress(0),
52     GDSSize(0) {
53   const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
54   const Function &F = MF.getFunction();
55   FlatWorkGroupSizes = ST.getFlatWorkGroupSizes(F);
56   WavesPerEU = ST.getWavesPerEU(F);
57 
58   Occupancy = ST.computeOccupancy(F, getLDSSize());
59   CallingConv::ID CC = F.getCallingConv();
60 
61   // FIXME: Should have analysis or something rather than attribute to detect
62   // calls.
63   const bool HasCalls = F.hasFnAttribute("amdgpu-calls");
64 
65   const bool IsKernel = CC == CallingConv::AMDGPU_KERNEL ||
66                         CC == CallingConv::SPIR_KERNEL;
67 
68   if (IsKernel) {
69     if (!F.arg_empty() || ST.getImplicitArgNumBytes(F) != 0)
70       KernargSegmentPtr = true;
71     WorkGroupIDX = true;
72     WorkItemIDX = true;
73   } else if (CC == CallingConv::AMDGPU_PS) {
74     PSInputAddr = AMDGPU::getInitialPSInputAddr(F);
75   }
76 
77   MayNeedAGPRs = ST.hasMAIInsts();
78 
79   if (!isEntryFunction()) {
80     if (CC != CallingConv::AMDGPU_Gfx)
81       ArgInfo = AMDGPUArgumentUsageInfo::FixedABIFunctionInfo;
82 
83     // TODO: Pick a high register, and shift down, similar to a kernel.
84     FrameOffsetReg = AMDGPU::SGPR33;
85     StackPtrOffsetReg = AMDGPU::SGPR32;
86 
87     if (!ST.enableFlatScratch()) {
88       // Non-entry functions have no special inputs for now, other registers
89       // required for scratch access.
90       ScratchRSrcReg = AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3;
91 
92       ArgInfo.PrivateSegmentBuffer =
93         ArgDescriptor::createRegister(ScratchRSrcReg);
94     }
95 
96     if (!F.hasFnAttribute("amdgpu-no-implicitarg-ptr"))
97       ImplicitArgPtr = true;
98   } else {
99     ImplicitArgPtr = false;
100     MaxKernArgAlign = std::max(ST.getAlignmentForImplicitArgPtr(),
101                                MaxKernArgAlign);
102 
103     if (ST.hasGFX90AInsts() &&
104         ST.getMaxNumVGPRs(F) <= AMDGPU::VGPR_32RegClass.getNumRegs() &&
105         !mayUseAGPRs(MF))
106       MayNeedAGPRs = false; // We will select all MAI with VGPR operands.
107   }
108 
109   bool isAmdHsaOrMesa = ST.isAmdHsaOrMesa(F);
110   if (isAmdHsaOrMesa && !ST.enableFlatScratch())
111     PrivateSegmentBuffer = true;
112   else if (ST.isMesaGfxShader(F))
113     ImplicitBufferPtr = true;
114 
115   if (!AMDGPU::isGraphics(CC)) {
116     if (IsKernel || !F.hasFnAttribute("amdgpu-no-workgroup-id-x"))
117       WorkGroupIDX = true;
118 
119     if (!F.hasFnAttribute("amdgpu-no-workgroup-id-y"))
120       WorkGroupIDY = true;
121 
122     if (!F.hasFnAttribute("amdgpu-no-workgroup-id-z"))
123       WorkGroupIDZ = true;
124 
125     if (IsKernel || !F.hasFnAttribute("amdgpu-no-workitem-id-x"))
126       WorkItemIDX = true;
127 
128     if (!F.hasFnAttribute("amdgpu-no-workitem-id-y") &&
129         ST.getMaxWorkitemID(F, 1) != 0)
130       WorkItemIDY = true;
131 
132     if (!F.hasFnAttribute("amdgpu-no-workitem-id-z") &&
133         ST.getMaxWorkitemID(F, 2) != 0)
134       WorkItemIDZ = true;
135 
136     if (!F.hasFnAttribute("amdgpu-no-dispatch-ptr"))
137       DispatchPtr = true;
138 
139     if (!F.hasFnAttribute("amdgpu-no-queue-ptr"))
140       QueuePtr = true;
141 
142     if (!F.hasFnAttribute("amdgpu-no-dispatch-id"))
143       DispatchID = true;
144   }
145 
146   // FIXME: This attribute is a hack, we just need an analysis on the function
147   // to look for allocas.
148   bool HasStackObjects = F.hasFnAttribute("amdgpu-stack-objects");
149 
150   // TODO: This could be refined a lot. The attribute is a poor way of
151   // detecting calls or stack objects that may require it before argument
152   // lowering.
153   if (ST.hasFlatAddressSpace() && isEntryFunction() &&
154       (isAmdHsaOrMesa || ST.enableFlatScratch()) &&
155       (HasCalls || HasStackObjects || ST.enableFlatScratch()) &&
156       !ST.flatScratchIsArchitected()) {
157     FlatScratchInit = true;
158   }
159 
160   if (isEntryFunction()) {
161     // X, XY, and XYZ are the only supported combinations, so make sure Y is
162     // enabled if Z is.
163     if (WorkItemIDZ)
164       WorkItemIDY = true;
165 
166     if (!ST.flatScratchIsArchitected()) {
167       PrivateSegmentWaveByteOffset = true;
168 
169       // HS and GS always have the scratch wave offset in SGPR5 on GFX9.
170       if (ST.getGeneration() >= AMDGPUSubtarget::GFX9 &&
171           (CC == CallingConv::AMDGPU_HS || CC == CallingConv::AMDGPU_GS))
172         ArgInfo.PrivateSegmentWaveByteOffset =
173             ArgDescriptor::createRegister(AMDGPU::SGPR5);
174     }
175   }
176 
177   Attribute A = F.getFnAttribute("amdgpu-git-ptr-high");
178   StringRef S = A.getValueAsString();
179   if (!S.empty())
180     S.consumeInteger(0, GITPtrHigh);
181 
182   A = F.getFnAttribute("amdgpu-32bit-address-high-bits");
183   S = A.getValueAsString();
184   if (!S.empty())
185     S.consumeInteger(0, HighBitsOf32BitAddress);
186 
187   S = F.getFnAttribute("amdgpu-gds-size").getValueAsString();
188   if (!S.empty())
189     S.consumeInteger(0, GDSSize);
190 
191   // On GFX908, in order to guarantee copying between AGPRs, we need a scratch
192   // VGPR available at all times.
193   if (ST.hasMAIInsts() && !ST.hasGFX90AInsts()) {
194     VGPRForAGPRCopy = AMDGPU::VGPR_32RegClass.getRegister(32);
195   }
196 }
197 
198 void SIMachineFunctionInfo::limitOccupancy(const MachineFunction &MF) {
199   limitOccupancy(getMaxWavesPerEU());
200   const GCNSubtarget& ST = MF.getSubtarget<GCNSubtarget>();
201   limitOccupancy(ST.getOccupancyWithLocalMemSize(getLDSSize(),
202                  MF.getFunction()));
203 }
204 
205 Register SIMachineFunctionInfo::addPrivateSegmentBuffer(
206   const SIRegisterInfo &TRI) {
207   ArgInfo.PrivateSegmentBuffer =
208     ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
209     getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SGPR_128RegClass));
210   NumUserSGPRs += 4;
211   return ArgInfo.PrivateSegmentBuffer.getRegister();
212 }
213 
214 Register SIMachineFunctionInfo::addDispatchPtr(const SIRegisterInfo &TRI) {
215   ArgInfo.DispatchPtr = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
216     getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
217   NumUserSGPRs += 2;
218   return ArgInfo.DispatchPtr.getRegister();
219 }
220 
221 Register SIMachineFunctionInfo::addQueuePtr(const SIRegisterInfo &TRI) {
222   ArgInfo.QueuePtr = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
223     getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
224   NumUserSGPRs += 2;
225   return ArgInfo.QueuePtr.getRegister();
226 }
227 
228 Register SIMachineFunctionInfo::addKernargSegmentPtr(const SIRegisterInfo &TRI) {
229   ArgInfo.KernargSegmentPtr
230     = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
231     getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
232   NumUserSGPRs += 2;
233   return ArgInfo.KernargSegmentPtr.getRegister();
234 }
235 
236 Register SIMachineFunctionInfo::addDispatchID(const SIRegisterInfo &TRI) {
237   ArgInfo.DispatchID = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
238     getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
239   NumUserSGPRs += 2;
240   return ArgInfo.DispatchID.getRegister();
241 }
242 
243 Register SIMachineFunctionInfo::addFlatScratchInit(const SIRegisterInfo &TRI) {
244   ArgInfo.FlatScratchInit = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
245     getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
246   NumUserSGPRs += 2;
247   return ArgInfo.FlatScratchInit.getRegister();
248 }
249 
250 Register SIMachineFunctionInfo::addImplicitBufferPtr(const SIRegisterInfo &TRI) {
251   ArgInfo.ImplicitBufferPtr = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
252     getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
253   NumUserSGPRs += 2;
254   return ArgInfo.ImplicitBufferPtr.getRegister();
255 }
256 
257 bool SIMachineFunctionInfo::isCalleeSavedReg(const MCPhysReg *CSRegs,
258                                              MCPhysReg Reg) {
259   for (unsigned I = 0; CSRegs[I]; ++I) {
260     if (CSRegs[I] == Reg)
261       return true;
262   }
263 
264   return false;
265 }
266 
267 /// \p returns true if \p NumLanes slots are available in VGPRs already used for
268 /// SGPR spilling.
269 //
270 // FIXME: This only works after processFunctionBeforeFrameFinalized
271 bool SIMachineFunctionInfo::haveFreeLanesForSGPRSpill(const MachineFunction &MF,
272                                                       unsigned NumNeed) const {
273   const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
274   unsigned WaveSize = ST.getWavefrontSize();
275   return NumVGPRSpillLanes + NumNeed <= WaveSize * SpillVGPRs.size();
276 }
277 
278 /// Reserve a slice of a VGPR to support spilling for FrameIndex \p FI.
279 bool SIMachineFunctionInfo::allocateSGPRSpillToVGPR(MachineFunction &MF,
280                                                     int FI) {
281   std::vector<SpilledReg> &SpillLanes = SGPRToVGPRSpills[FI];
282 
283   // This has already been allocated.
284   if (!SpillLanes.empty())
285     return true;
286 
287   const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
288   const SIRegisterInfo *TRI = ST.getRegisterInfo();
289   MachineFrameInfo &FrameInfo = MF.getFrameInfo();
290   MachineRegisterInfo &MRI = MF.getRegInfo();
291   unsigned WaveSize = ST.getWavefrontSize();
292 
293   unsigned Size = FrameInfo.getObjectSize(FI);
294   unsigned NumLanes = Size / 4;
295 
296   if (NumLanes > WaveSize)
297     return false;
298 
299   assert(Size >= 4 && "invalid sgpr spill size");
300   assert(TRI->spillSGPRToVGPR() && "not spilling SGPRs to VGPRs");
301 
302   // Make sure to handle the case where a wide SGPR spill may span between two
303   // VGPRs.
304   for (unsigned I = 0; I < NumLanes; ++I, ++NumVGPRSpillLanes) {
305     Register LaneVGPR;
306     unsigned VGPRIndex = (NumVGPRSpillLanes % WaveSize);
307 
308     if (VGPRIndex == 0) {
309       LaneVGPR = TRI->findUnusedRegister(MRI, &AMDGPU::VGPR_32RegClass, MF);
310       if (LaneVGPR == AMDGPU::NoRegister) {
311         // We have no VGPRs left for spilling SGPRs. Reset because we will not
312         // partially spill the SGPR to VGPRs.
313         SGPRToVGPRSpills.erase(FI);
314         NumVGPRSpillLanes -= I;
315 
316         // FIXME: We can run out of free registers with split allocation if
317         // IPRA is enabled and a called function already uses every VGPR.
318 #if 0
319         DiagnosticInfoResourceLimit DiagOutOfRegs(MF.getFunction(),
320                                                   "VGPRs for SGPR spilling",
321                                                   0, DS_Error);
322         MF.getFunction().getContext().diagnose(DiagOutOfRegs);
323 #endif
324         return false;
325       }
326 
327       Optional<int> SpillFI;
328       // We need to preserve inactive lanes, so always save, even caller-save
329       // registers.
330       if (!isEntryFunction()) {
331         SpillFI = FrameInfo.CreateSpillStackObject(4, Align(4));
332       }
333 
334       SpillVGPRs.push_back(SGPRSpillVGPR(LaneVGPR, SpillFI));
335 
336       // Add this register as live-in to all blocks to avoid machine verifier
337       // complaining about use of an undefined physical register.
338       for (MachineBasicBlock &BB : MF)
339         BB.addLiveIn(LaneVGPR);
340     } else {
341       LaneVGPR = SpillVGPRs.back().VGPR;
342     }
343 
344     SpillLanes.push_back(SpilledReg(LaneVGPR, VGPRIndex));
345   }
346 
347   return true;
348 }
349 
350 /// Reserve AGPRs or VGPRs to support spilling for FrameIndex \p FI.
351 /// Either AGPR is spilled to VGPR to vice versa.
352 /// Returns true if a \p FI can be eliminated completely.
353 bool SIMachineFunctionInfo::allocateVGPRSpillToAGPR(MachineFunction &MF,
354                                                     int FI,
355                                                     bool isAGPRtoVGPR) {
356   MachineRegisterInfo &MRI = MF.getRegInfo();
357   MachineFrameInfo &FrameInfo = MF.getFrameInfo();
358   const GCNSubtarget &ST =  MF.getSubtarget<GCNSubtarget>();
359 
360   assert(ST.hasMAIInsts() && FrameInfo.isSpillSlotObjectIndex(FI));
361 
362   auto &Spill = VGPRToAGPRSpills[FI];
363 
364   // This has already been allocated.
365   if (!Spill.Lanes.empty())
366     return Spill.FullyAllocated;
367 
368   unsigned Size = FrameInfo.getObjectSize(FI);
369   unsigned NumLanes = Size / 4;
370   Spill.Lanes.resize(NumLanes, AMDGPU::NoRegister);
371 
372   const TargetRegisterClass &RC =
373       isAGPRtoVGPR ? AMDGPU::VGPR_32RegClass : AMDGPU::AGPR_32RegClass;
374   auto Regs = RC.getRegisters();
375 
376   auto &SpillRegs = isAGPRtoVGPR ? SpillAGPR : SpillVGPR;
377   const SIRegisterInfo *TRI = ST.getRegisterInfo();
378   Spill.FullyAllocated = true;
379 
380   // FIXME: Move allocation logic out of MachineFunctionInfo and initialize
381   // once.
382   BitVector OtherUsedRegs;
383   OtherUsedRegs.resize(TRI->getNumRegs());
384 
385   const uint32_t *CSRMask =
386       TRI->getCallPreservedMask(MF, MF.getFunction().getCallingConv());
387   if (CSRMask)
388     OtherUsedRegs.setBitsInMask(CSRMask);
389 
390   // TODO: Should include register tuples, but doesn't matter with current
391   // usage.
392   for (MCPhysReg Reg : SpillAGPR)
393     OtherUsedRegs.set(Reg);
394   for (MCPhysReg Reg : SpillVGPR)
395     OtherUsedRegs.set(Reg);
396 
397   SmallVectorImpl<MCPhysReg>::const_iterator NextSpillReg = Regs.begin();
398   for (int I = NumLanes - 1; I >= 0; --I) {
399     NextSpillReg = std::find_if(
400         NextSpillReg, Regs.end(), [&MRI, &OtherUsedRegs](MCPhysReg Reg) {
401           return MRI.isAllocatable(Reg) && !MRI.isPhysRegUsed(Reg) &&
402                  !OtherUsedRegs[Reg];
403         });
404 
405     if (NextSpillReg == Regs.end()) { // Registers exhausted
406       Spill.FullyAllocated = false;
407       break;
408     }
409 
410     OtherUsedRegs.set(*NextSpillReg);
411     SpillRegs.push_back(*NextSpillReg);
412     Spill.Lanes[I] = *NextSpillReg++;
413   }
414 
415   return Spill.FullyAllocated;
416 }
417 
418 bool SIMachineFunctionInfo::removeDeadFrameIndices(
419     MachineFrameInfo &MFI, bool ResetSGPRSpillStackIDs) {
420   // Remove dead frame indices from function frame, however keep FP & BP since
421   // spills for them haven't been inserted yet. And also make sure to remove the
422   // frame indices from `SGPRToVGPRSpills` data structure, otherwise, it could
423   // result in an unexpected side effect and bug, in case of any re-mapping of
424   // freed frame indices by later pass(es) like "stack slot coloring".
425   for (auto &R : make_early_inc_range(SGPRToVGPRSpills)) {
426     if (R.first != FramePointerSaveIndex && R.first != BasePointerSaveIndex) {
427       MFI.RemoveStackObject(R.first);
428       SGPRToVGPRSpills.erase(R.first);
429     }
430   }
431 
432   bool HaveSGPRToMemory = false;
433 
434   if (ResetSGPRSpillStackIDs) {
435     // All other SPGRs must be allocated on the default stack, so reset the
436     // stack ID.
437     for (int i = MFI.getObjectIndexBegin(), e = MFI.getObjectIndexEnd(); i != e;
438          ++i) {
439       if (i != FramePointerSaveIndex && i != BasePointerSaveIndex) {
440         if (MFI.getStackID(i) == TargetStackID::SGPRSpill) {
441           MFI.setStackID(i, TargetStackID::Default);
442           HaveSGPRToMemory = true;
443         }
444       }
445     }
446   }
447 
448   for (auto &R : VGPRToAGPRSpills) {
449     if (R.second.IsDead)
450       MFI.RemoveStackObject(R.first);
451   }
452 
453   return HaveSGPRToMemory;
454 }
455 
456 int SIMachineFunctionInfo::getScavengeFI(MachineFrameInfo &MFI,
457                                          const SIRegisterInfo &TRI) {
458   if (ScavengeFI)
459     return *ScavengeFI;
460   if (isEntryFunction()) {
461     ScavengeFI = MFI.CreateFixedObject(
462         TRI.getSpillSize(AMDGPU::SGPR_32RegClass), 0, false);
463   } else {
464     ScavengeFI = MFI.CreateStackObject(
465         TRI.getSpillSize(AMDGPU::SGPR_32RegClass),
466         TRI.getSpillAlign(AMDGPU::SGPR_32RegClass), false);
467   }
468   return *ScavengeFI;
469 }
470 
471 MCPhysReg SIMachineFunctionInfo::getNextUserSGPR() const {
472   assert(NumSystemSGPRs == 0 && "System SGPRs must be added after user SGPRs");
473   return AMDGPU::SGPR0 + NumUserSGPRs;
474 }
475 
476 MCPhysReg SIMachineFunctionInfo::getNextSystemSGPR() const {
477   return AMDGPU::SGPR0 + NumUserSGPRs + NumSystemSGPRs;
478 }
479 
480 Register
481 SIMachineFunctionInfo::getGITPtrLoReg(const MachineFunction &MF) const {
482   const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
483   if (!ST.isAmdPalOS())
484     return Register();
485   Register GitPtrLo = AMDGPU::SGPR0; // Low GIT address passed in
486   if (ST.hasMergedShaders()) {
487     switch (MF.getFunction().getCallingConv()) {
488     case CallingConv::AMDGPU_HS:
489     case CallingConv::AMDGPU_GS:
490       // Low GIT address is passed in s8 rather than s0 for an LS+HS or
491       // ES+GS merged shader on gfx9+.
492       GitPtrLo = AMDGPU::SGPR8;
493       return GitPtrLo;
494     default:
495       return GitPtrLo;
496     }
497   }
498   return GitPtrLo;
499 }
500 
501 static yaml::StringValue regToString(Register Reg,
502                                      const TargetRegisterInfo &TRI) {
503   yaml::StringValue Dest;
504   {
505     raw_string_ostream OS(Dest.Value);
506     OS << printReg(Reg, &TRI);
507   }
508   return Dest;
509 }
510 
511 static Optional<yaml::SIArgumentInfo>
512 convertArgumentInfo(const AMDGPUFunctionArgInfo &ArgInfo,
513                     const TargetRegisterInfo &TRI) {
514   yaml::SIArgumentInfo AI;
515 
516   auto convertArg = [&](Optional<yaml::SIArgument> &A,
517                         const ArgDescriptor &Arg) {
518     if (!Arg)
519       return false;
520 
521     // Create a register or stack argument.
522     yaml::SIArgument SA = yaml::SIArgument::createArgument(Arg.isRegister());
523     if (Arg.isRegister()) {
524       raw_string_ostream OS(SA.RegisterName.Value);
525       OS << printReg(Arg.getRegister(), &TRI);
526     } else
527       SA.StackOffset = Arg.getStackOffset();
528     // Check and update the optional mask.
529     if (Arg.isMasked())
530       SA.Mask = Arg.getMask();
531 
532     A = SA;
533     return true;
534   };
535 
536   bool Any = false;
537   Any |= convertArg(AI.PrivateSegmentBuffer, ArgInfo.PrivateSegmentBuffer);
538   Any |= convertArg(AI.DispatchPtr, ArgInfo.DispatchPtr);
539   Any |= convertArg(AI.QueuePtr, ArgInfo.QueuePtr);
540   Any |= convertArg(AI.KernargSegmentPtr, ArgInfo.KernargSegmentPtr);
541   Any |= convertArg(AI.DispatchID, ArgInfo.DispatchID);
542   Any |= convertArg(AI.FlatScratchInit, ArgInfo.FlatScratchInit);
543   Any |= convertArg(AI.PrivateSegmentSize, ArgInfo.PrivateSegmentSize);
544   Any |= convertArg(AI.WorkGroupIDX, ArgInfo.WorkGroupIDX);
545   Any |= convertArg(AI.WorkGroupIDY, ArgInfo.WorkGroupIDY);
546   Any |= convertArg(AI.WorkGroupIDZ, ArgInfo.WorkGroupIDZ);
547   Any |= convertArg(AI.WorkGroupInfo, ArgInfo.WorkGroupInfo);
548   Any |= convertArg(AI.PrivateSegmentWaveByteOffset,
549                     ArgInfo.PrivateSegmentWaveByteOffset);
550   Any |= convertArg(AI.ImplicitArgPtr, ArgInfo.ImplicitArgPtr);
551   Any |= convertArg(AI.ImplicitBufferPtr, ArgInfo.ImplicitBufferPtr);
552   Any |= convertArg(AI.WorkItemIDX, ArgInfo.WorkItemIDX);
553   Any |= convertArg(AI.WorkItemIDY, ArgInfo.WorkItemIDY);
554   Any |= convertArg(AI.WorkItemIDZ, ArgInfo.WorkItemIDZ);
555 
556   if (Any)
557     return AI;
558 
559   return None;
560 }
561 
562 yaml::SIMachineFunctionInfo::SIMachineFunctionInfo(
563     const llvm::SIMachineFunctionInfo &MFI, const TargetRegisterInfo &TRI,
564     const llvm::MachineFunction &MF)
565     : ExplicitKernArgSize(MFI.getExplicitKernArgSize()),
566       MaxKernArgAlign(MFI.getMaxKernArgAlign()), LDSSize(MFI.getLDSSize()),
567       DynLDSAlign(MFI.getDynLDSAlign()), IsEntryFunction(MFI.isEntryFunction()),
568       NoSignedZerosFPMath(MFI.hasNoSignedZerosFPMath()),
569       MemoryBound(MFI.isMemoryBound()), WaveLimiter(MFI.needsWaveLimiter()),
570       HasSpilledSGPRs(MFI.hasSpilledSGPRs()),
571       HasSpilledVGPRs(MFI.hasSpilledVGPRs()),
572       HighBitsOf32BitAddress(MFI.get32BitAddressHighBits()),
573       Occupancy(MFI.getOccupancy()),
574       ScratchRSrcReg(regToString(MFI.getScratchRSrcReg(), TRI)),
575       FrameOffsetReg(regToString(MFI.getFrameOffsetReg(), TRI)),
576       StackPtrOffsetReg(regToString(MFI.getStackPtrOffsetReg(), TRI)),
577       ArgInfo(convertArgumentInfo(MFI.getArgInfo(), TRI)), Mode(MFI.getMode()) {
578   auto SFI = MFI.getOptionalScavengeFI();
579   if (SFI)
580     ScavengeFI = yaml::FrameIndex(*SFI, MF.getFrameInfo());
581 }
582 
583 void yaml::SIMachineFunctionInfo::mappingImpl(yaml::IO &YamlIO) {
584   MappingTraits<SIMachineFunctionInfo>::mapping(YamlIO, *this);
585 }
586 
587 bool SIMachineFunctionInfo::initializeBaseYamlFields(
588     const yaml::SIMachineFunctionInfo &YamlMFI, const MachineFunction &MF,
589     PerFunctionMIParsingState &PFS, SMDiagnostic &Error, SMRange &SourceRange) {
590   ExplicitKernArgSize = YamlMFI.ExplicitKernArgSize;
591   MaxKernArgAlign = assumeAligned(YamlMFI.MaxKernArgAlign);
592   LDSSize = YamlMFI.LDSSize;
593   DynLDSAlign = YamlMFI.DynLDSAlign;
594   HighBitsOf32BitAddress = YamlMFI.HighBitsOf32BitAddress;
595   Occupancy = YamlMFI.Occupancy;
596   IsEntryFunction = YamlMFI.IsEntryFunction;
597   NoSignedZerosFPMath = YamlMFI.NoSignedZerosFPMath;
598   MemoryBound = YamlMFI.MemoryBound;
599   WaveLimiter = YamlMFI.WaveLimiter;
600   HasSpilledSGPRs = YamlMFI.HasSpilledSGPRs;
601   HasSpilledVGPRs = YamlMFI.HasSpilledVGPRs;
602 
603   if (YamlMFI.ScavengeFI) {
604     auto FIOrErr = YamlMFI.ScavengeFI->getFI(MF.getFrameInfo());
605     if (!FIOrErr) {
606       // Create a diagnostic for a the frame index.
607       const MemoryBuffer &Buffer =
608           *PFS.SM->getMemoryBuffer(PFS.SM->getMainFileID());
609 
610       Error = SMDiagnostic(*PFS.SM, SMLoc(), Buffer.getBufferIdentifier(), 1, 1,
611                            SourceMgr::DK_Error, toString(FIOrErr.takeError()),
612                            "", None, None);
613       SourceRange = YamlMFI.ScavengeFI->SourceRange;
614       return true;
615     }
616     ScavengeFI = *FIOrErr;
617   } else {
618     ScavengeFI = None;
619   }
620   return false;
621 }
622 
623 bool SIMachineFunctionInfo::mayUseAGPRs(const MachineFunction &MF) const {
624   for (const BasicBlock &BB : MF.getFunction()) {
625     for (const Instruction &I : BB) {
626       const auto *CB = dyn_cast<CallBase>(&I);
627       if (!CB)
628         continue;
629 
630       if (CB->isInlineAsm()) {
631         const InlineAsm *IA = dyn_cast<InlineAsm>(CB->getCalledOperand());
632         for (const auto &CI : IA->ParseConstraints()) {
633           for (StringRef Code : CI.Codes) {
634             Code.consume_front("{");
635             if (Code.startswith("a"))
636               return true;
637           }
638         }
639         continue;
640       }
641 
642       const Function *Callee =
643           dyn_cast<Function>(CB->getCalledOperand()->stripPointerCasts());
644       if (!Callee)
645         return true;
646 
647       if (Callee->getIntrinsicID() == Intrinsic::not_intrinsic)
648         return true;
649     }
650   }
651 
652   return false;
653 }
654 
655 bool SIMachineFunctionInfo::usesAGPRs(const MachineFunction &MF) const {
656   if (UsesAGPRs)
657     return *UsesAGPRs;
658 
659   if (!mayNeedAGPRs()) {
660     UsesAGPRs = false;
661     return false;
662   }
663 
664   if (!AMDGPU::isEntryFunctionCC(MF.getFunction().getCallingConv()) ||
665       MF.getFrameInfo().hasCalls()) {
666     UsesAGPRs = true;
667     return true;
668   }
669 
670   const MachineRegisterInfo &MRI = MF.getRegInfo();
671 
672   for (unsigned I = 0, E = MRI.getNumVirtRegs(); I != E; ++I) {
673     const Register Reg = Register::index2VirtReg(I);
674     const TargetRegisterClass *RC = MRI.getRegClassOrNull(Reg);
675     if (RC && SIRegisterInfo::isAGPRClass(RC)) {
676       UsesAGPRs = true;
677       return true;
678     } else if (!RC && !MRI.use_empty(Reg) && MRI.getType(Reg).isValid()) {
679       // Defer caching UsesAGPRs, function might not yet been regbank selected.
680       return true;
681     }
682   }
683 
684   for (MCRegister Reg : AMDGPU::AGPR_32RegClass) {
685     if (MRI.isPhysRegUsed(Reg)) {
686       UsesAGPRs = true;
687       return true;
688     }
689   }
690 
691   UsesAGPRs = false;
692   return false;
693 }
694