1 //===- SIMachineFunctionInfo.cpp - SI Machine Function Info ---------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #include "SIMachineFunctionInfo.h"
10 #include "AMDGPUTargetMachine.h"
11 #include "AMDGPUSubtarget.h"
12 #include "SIRegisterInfo.h"
13 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
14 #include "Utils/AMDGPUBaseInfo.h"
15 #include "llvm/ADT/Optional.h"
16 #include "llvm/CodeGen/LiveIntervals.h"
17 #include "llvm/CodeGen/MachineBasicBlock.h"
18 #include "llvm/CodeGen/MachineFrameInfo.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/MachineRegisterInfo.h"
21 #include "llvm/CodeGen/MIRParser/MIParser.h"
22 #include "llvm/IR/CallingConv.h"
23 #include "llvm/IR/DiagnosticInfo.h"
24 #include "llvm/IR/Function.h"
25 #include <cassert>
26 #include <vector>
27 
28 #define MAX_LANES 64
29 
30 using namespace llvm;
31 
32 SIMachineFunctionInfo::SIMachineFunctionInfo(const MachineFunction &MF)
33   : AMDGPUMachineFunction(MF),
34     PrivateSegmentBuffer(false),
35     DispatchPtr(false),
36     QueuePtr(false),
37     KernargSegmentPtr(false),
38     DispatchID(false),
39     FlatScratchInit(false),
40     WorkGroupIDX(false),
41     WorkGroupIDY(false),
42     WorkGroupIDZ(false),
43     WorkGroupInfo(false),
44     PrivateSegmentWaveByteOffset(false),
45     WorkItemIDX(false),
46     WorkItemIDY(false),
47     WorkItemIDZ(false),
48     ImplicitBufferPtr(false),
49     ImplicitArgPtr(false),
50     GITPtrHigh(0xffffffff),
51     HighBitsOf32BitAddress(0),
52     GDSSize(0) {
53   const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
54   const Function &F = MF.getFunction();
55   FlatWorkGroupSizes = ST.getFlatWorkGroupSizes(F);
56   WavesPerEU = ST.getWavesPerEU(F);
57 
58   Occupancy = ST.computeOccupancy(F, getLDSSize());
59   CallingConv::ID CC = F.getCallingConv();
60 
61   // FIXME: Should have analysis or something rather than attribute to detect
62   // calls.
63   const bool HasCalls = F.hasFnAttribute("amdgpu-calls");
64 
65   // Enable all kernel inputs if we have the fixed ABI. Don't bother if we don't
66   // have any calls.
67   const bool UseFixedABI = AMDGPUTargetMachine::EnableFixedFunctionABI &&
68                            CC != CallingConv::AMDGPU_Gfx &&
69                            (!isEntryFunction() || HasCalls);
70   const bool IsKernel = CC == CallingConv::AMDGPU_KERNEL ||
71                         CC == CallingConv::SPIR_KERNEL;
72 
73   if (IsKernel) {
74     if (!F.arg_empty() || ST.getImplicitArgNumBytes(F) != 0)
75       KernargSegmentPtr = true;
76     WorkGroupIDX = true;
77     WorkItemIDX = true;
78   } else if (CC == CallingConv::AMDGPU_PS) {
79     PSInputAddr = AMDGPU::getInitialPSInputAddr(F);
80   }
81 
82   if (!isEntryFunction()) {
83     if (UseFixedABI)
84       ArgInfo = AMDGPUArgumentUsageInfo::FixedABIFunctionInfo;
85 
86     // TODO: Pick a high register, and shift down, similar to a kernel.
87     FrameOffsetReg = AMDGPU::SGPR33;
88     StackPtrOffsetReg = AMDGPU::SGPR32;
89 
90     if (!ST.enableFlatScratch()) {
91       // Non-entry functions have no special inputs for now, other registers
92       // required for scratch access.
93       ScratchRSrcReg = AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3;
94 
95       ArgInfo.PrivateSegmentBuffer =
96         ArgDescriptor::createRegister(ScratchRSrcReg);
97     }
98 
99     if (!F.hasFnAttribute("amdgpu-no-implicitarg-ptr"))
100       ImplicitArgPtr = true;
101   } else {
102     ImplicitArgPtr = false;
103     MaxKernArgAlign = std::max(ST.getAlignmentForImplicitArgPtr(),
104                                MaxKernArgAlign);
105   }
106 
107   bool isAmdHsaOrMesa = ST.isAmdHsaOrMesa(F);
108   if (isAmdHsaOrMesa && !ST.enableFlatScratch())
109     PrivateSegmentBuffer = true;
110   else if (ST.isMesaGfxShader(F))
111     ImplicitBufferPtr = true;
112 
113   if (!AMDGPU::isGraphics(CC)) {
114     if (IsKernel || !F.hasFnAttribute("amdgpu-no-workgroup-id-x"))
115       WorkGroupIDX = true;
116 
117     if (!F.hasFnAttribute("amdgpu-no-workgroup-id-y"))
118       WorkGroupIDY = true;
119 
120     if (!F.hasFnAttribute("amdgpu-no-workgroup-id-z"))
121       WorkGroupIDZ = true;
122 
123     if (IsKernel || !F.hasFnAttribute("amdgpu-no-workitem-id-x"))
124       WorkItemIDX = true;
125 
126     if (!F.hasFnAttribute("amdgpu-no-workitem-id-y"))
127       WorkItemIDY = true;
128 
129     if (!F.hasFnAttribute("amdgpu-no-workitem-id-z"))
130       WorkItemIDZ = true;
131 
132     if (!F.hasFnAttribute("amdgpu-no-dispatch-ptr"))
133       DispatchPtr = true;
134 
135     if (!F.hasFnAttribute("amdgpu-no-queue-ptr"))
136       QueuePtr = true;
137 
138     if (!F.hasFnAttribute("amdgpu-no-dispatch-id"))
139       DispatchID = true;
140   }
141 
142   // FIXME: This attribute is a hack, we just need an analysis on the function
143   // to look for allocas.
144   bool HasStackObjects = F.hasFnAttribute("amdgpu-stack-objects");
145 
146   // TODO: This could be refined a lot. The attribute is a poor way of
147   // detecting calls or stack objects that may require it before argument
148   // lowering.
149   if (ST.hasFlatAddressSpace() && isEntryFunction() &&
150       (isAmdHsaOrMesa || ST.enableFlatScratch()) &&
151       (HasCalls || HasStackObjects || ST.enableFlatScratch()) &&
152       !ST.flatScratchIsArchitected()) {
153     FlatScratchInit = true;
154   }
155 
156   if (isEntryFunction()) {
157     // X, XY, and XYZ are the only supported combinations, so make sure Y is
158     // enabled if Z is.
159     if (WorkItemIDZ)
160       WorkItemIDY = true;
161 
162     if (!ST.flatScratchIsArchitected()) {
163       PrivateSegmentWaveByteOffset = true;
164 
165       // HS and GS always have the scratch wave offset in SGPR5 on GFX9.
166       if (ST.getGeneration() >= AMDGPUSubtarget::GFX9 &&
167           (CC == CallingConv::AMDGPU_HS || CC == CallingConv::AMDGPU_GS))
168         ArgInfo.PrivateSegmentWaveByteOffset =
169             ArgDescriptor::createRegister(AMDGPU::SGPR5);
170     }
171   }
172 
173   Attribute A = F.getFnAttribute("amdgpu-git-ptr-high");
174   StringRef S = A.getValueAsString();
175   if (!S.empty())
176     S.consumeInteger(0, GITPtrHigh);
177 
178   A = F.getFnAttribute("amdgpu-32bit-address-high-bits");
179   S = A.getValueAsString();
180   if (!S.empty())
181     S.consumeInteger(0, HighBitsOf32BitAddress);
182 
183   S = F.getFnAttribute("amdgpu-gds-size").getValueAsString();
184   if (!S.empty())
185     S.consumeInteger(0, GDSSize);
186 }
187 
188 void SIMachineFunctionInfo::limitOccupancy(const MachineFunction &MF) {
189   limitOccupancy(getMaxWavesPerEU());
190   const GCNSubtarget& ST = MF.getSubtarget<GCNSubtarget>();
191   limitOccupancy(ST.getOccupancyWithLocalMemSize(getLDSSize(),
192                  MF.getFunction()));
193 }
194 
195 Register SIMachineFunctionInfo::addPrivateSegmentBuffer(
196   const SIRegisterInfo &TRI) {
197   ArgInfo.PrivateSegmentBuffer =
198     ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
199     getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SGPR_128RegClass));
200   NumUserSGPRs += 4;
201   return ArgInfo.PrivateSegmentBuffer.getRegister();
202 }
203 
204 Register SIMachineFunctionInfo::addDispatchPtr(const SIRegisterInfo &TRI) {
205   ArgInfo.DispatchPtr = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
206     getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
207   NumUserSGPRs += 2;
208   return ArgInfo.DispatchPtr.getRegister();
209 }
210 
211 Register SIMachineFunctionInfo::addQueuePtr(const SIRegisterInfo &TRI) {
212   ArgInfo.QueuePtr = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
213     getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
214   NumUserSGPRs += 2;
215   return ArgInfo.QueuePtr.getRegister();
216 }
217 
218 Register SIMachineFunctionInfo::addKernargSegmentPtr(const SIRegisterInfo &TRI) {
219   ArgInfo.KernargSegmentPtr
220     = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
221     getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
222   NumUserSGPRs += 2;
223   return ArgInfo.KernargSegmentPtr.getRegister();
224 }
225 
226 Register SIMachineFunctionInfo::addDispatchID(const SIRegisterInfo &TRI) {
227   ArgInfo.DispatchID = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
228     getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
229   NumUserSGPRs += 2;
230   return ArgInfo.DispatchID.getRegister();
231 }
232 
233 Register SIMachineFunctionInfo::addFlatScratchInit(const SIRegisterInfo &TRI) {
234   ArgInfo.FlatScratchInit = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
235     getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
236   NumUserSGPRs += 2;
237   return ArgInfo.FlatScratchInit.getRegister();
238 }
239 
240 Register SIMachineFunctionInfo::addImplicitBufferPtr(const SIRegisterInfo &TRI) {
241   ArgInfo.ImplicitBufferPtr = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
242     getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
243   NumUserSGPRs += 2;
244   return ArgInfo.ImplicitBufferPtr.getRegister();
245 }
246 
247 bool SIMachineFunctionInfo::isCalleeSavedReg(const MCPhysReg *CSRegs,
248                                              MCPhysReg Reg) {
249   for (unsigned I = 0; CSRegs[I]; ++I) {
250     if (CSRegs[I] == Reg)
251       return true;
252   }
253 
254   return false;
255 }
256 
257 /// \p returns true if \p NumLanes slots are available in VGPRs already used for
258 /// SGPR spilling.
259 //
260 // FIXME: This only works after processFunctionBeforeFrameFinalized
261 bool SIMachineFunctionInfo::haveFreeLanesForSGPRSpill(const MachineFunction &MF,
262                                                       unsigned NumNeed) const {
263   const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
264   unsigned WaveSize = ST.getWavefrontSize();
265   return NumVGPRSpillLanes + NumNeed <= WaveSize * SpillVGPRs.size();
266 }
267 
268 /// Reserve a slice of a VGPR to support spilling for FrameIndex \p FI.
269 bool SIMachineFunctionInfo::allocateSGPRSpillToVGPR(MachineFunction &MF,
270                                                     int FI) {
271   std::vector<SpilledReg> &SpillLanes = SGPRToVGPRSpills[FI];
272 
273   // This has already been allocated.
274   if (!SpillLanes.empty())
275     return true;
276 
277   const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
278   const SIRegisterInfo *TRI = ST.getRegisterInfo();
279   MachineFrameInfo &FrameInfo = MF.getFrameInfo();
280   MachineRegisterInfo &MRI = MF.getRegInfo();
281   unsigned WaveSize = ST.getWavefrontSize();
282   SIMachineFunctionInfo *FuncInfo = MF.getInfo<SIMachineFunctionInfo>();
283 
284   unsigned Size = FrameInfo.getObjectSize(FI);
285   unsigned NumLanes = Size / 4;
286 
287   if (NumLanes > WaveSize)
288     return false;
289 
290   assert(Size >= 4 && "invalid sgpr spill size");
291   assert(TRI->spillSGPRToVGPR() && "not spilling SGPRs to VGPRs");
292 
293   // Make sure to handle the case where a wide SGPR spill may span between two
294   // VGPRs.
295   for (unsigned I = 0; I < NumLanes; ++I, ++NumVGPRSpillLanes) {
296     Register LaneVGPR;
297     unsigned VGPRIndex = (NumVGPRSpillLanes % WaveSize);
298 
299     // Reserve a VGPR (when NumVGPRSpillLanes = 0, WaveSize, 2*WaveSize, ..) and
300     // when one of the two conditions is true:
301     // 1. One reserved VGPR being tracked by VGPRReservedForSGPRSpill is not yet
302     // reserved.
303     // 2. All spill lanes of reserved VGPR(s) are full and another spill lane is
304     // required.
305     if (FuncInfo->VGPRReservedForSGPRSpill && NumVGPRSpillLanes < WaveSize) {
306       assert(FuncInfo->VGPRReservedForSGPRSpill == SpillVGPRs.back().VGPR);
307       LaneVGPR = FuncInfo->VGPRReservedForSGPRSpill;
308     } else if (VGPRIndex == 0) {
309       LaneVGPR = TRI->findUnusedRegister(MRI, &AMDGPU::VGPR_32RegClass, MF);
310       if (LaneVGPR == AMDGPU::NoRegister) {
311         // We have no VGPRs left for spilling SGPRs. Reset because we will not
312         // partially spill the SGPR to VGPRs.
313         SGPRToVGPRSpills.erase(FI);
314         NumVGPRSpillLanes -= I;
315 
316 #if 0
317         DiagnosticInfoResourceLimit DiagOutOfRegs(MF.getFunction(),
318                                                   "VGPRs for SGPR spilling",
319                                                   0, DS_Error);
320         MF.getFunction().getContext().diagnose(DiagOutOfRegs);
321 #endif
322         return false;
323       }
324 
325       Optional<int> SpillFI;
326       // We need to preserve inactive lanes, so always save, even caller-save
327       // registers.
328       if (!isEntryFunction()) {
329         SpillFI = FrameInfo.CreateSpillStackObject(4, Align(4));
330       }
331 
332       SpillVGPRs.push_back(SGPRSpillVGPR(LaneVGPR, SpillFI));
333 
334       // Add this register as live-in to all blocks to avoid machine verifer
335       // complaining about use of an undefined physical register.
336       for (MachineBasicBlock &BB : MF)
337         BB.addLiveIn(LaneVGPR);
338     } else {
339       LaneVGPR = SpillVGPRs.back().VGPR;
340     }
341 
342     SpillLanes.push_back(SpilledReg(LaneVGPR, VGPRIndex));
343   }
344 
345   return true;
346 }
347 
348 /// Reserve a VGPR for spilling of SGPRs
349 bool SIMachineFunctionInfo::reserveVGPRforSGPRSpills(MachineFunction &MF) {
350   const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
351   const SIRegisterInfo *TRI = ST.getRegisterInfo();
352   SIMachineFunctionInfo *FuncInfo = MF.getInfo<SIMachineFunctionInfo>();
353 
354   Register LaneVGPR = TRI->findUnusedRegister(
355       MF.getRegInfo(), &AMDGPU::VGPR_32RegClass, MF, true);
356   if (LaneVGPR == Register())
357     return false;
358   SpillVGPRs.push_back(SGPRSpillVGPR(LaneVGPR, None));
359   FuncInfo->VGPRReservedForSGPRSpill = LaneVGPR;
360   return true;
361 }
362 
363 /// Reserve AGPRs or VGPRs to support spilling for FrameIndex \p FI.
364 /// Either AGPR is spilled to VGPR to vice versa.
365 /// Returns true if a \p FI can be eliminated completely.
366 bool SIMachineFunctionInfo::allocateVGPRSpillToAGPR(MachineFunction &MF,
367                                                     int FI,
368                                                     bool isAGPRtoVGPR) {
369   MachineRegisterInfo &MRI = MF.getRegInfo();
370   MachineFrameInfo &FrameInfo = MF.getFrameInfo();
371   const GCNSubtarget &ST =  MF.getSubtarget<GCNSubtarget>();
372 
373   assert(ST.hasMAIInsts() && FrameInfo.isSpillSlotObjectIndex(FI));
374 
375   auto &Spill = VGPRToAGPRSpills[FI];
376 
377   // This has already been allocated.
378   if (!Spill.Lanes.empty())
379     return Spill.FullyAllocated;
380 
381   unsigned Size = FrameInfo.getObjectSize(FI);
382   unsigned NumLanes = Size / 4;
383   Spill.Lanes.resize(NumLanes, AMDGPU::NoRegister);
384 
385   const TargetRegisterClass &RC =
386       isAGPRtoVGPR ? AMDGPU::VGPR_32RegClass : AMDGPU::AGPR_32RegClass;
387   auto Regs = RC.getRegisters();
388 
389   auto &SpillRegs = isAGPRtoVGPR ? SpillAGPR : SpillVGPR;
390   const SIRegisterInfo *TRI = ST.getRegisterInfo();
391   Spill.FullyAllocated = true;
392 
393   // FIXME: Move allocation logic out of MachineFunctionInfo and initialize
394   // once.
395   BitVector OtherUsedRegs;
396   OtherUsedRegs.resize(TRI->getNumRegs());
397 
398   const uint32_t *CSRMask =
399       TRI->getCallPreservedMask(MF, MF.getFunction().getCallingConv());
400   if (CSRMask)
401     OtherUsedRegs.setBitsInMask(CSRMask);
402 
403   // TODO: Should include register tuples, but doesn't matter with current
404   // usage.
405   for (MCPhysReg Reg : SpillAGPR)
406     OtherUsedRegs.set(Reg);
407   for (MCPhysReg Reg : SpillVGPR)
408     OtherUsedRegs.set(Reg);
409 
410   SmallVectorImpl<MCPhysReg>::const_iterator NextSpillReg = Regs.begin();
411   for (int I = NumLanes - 1; I >= 0; --I) {
412     NextSpillReg = std::find_if(
413         NextSpillReg, Regs.end(), [&MRI, &OtherUsedRegs](MCPhysReg Reg) {
414           return MRI.isAllocatable(Reg) && !MRI.isPhysRegUsed(Reg) &&
415                  !OtherUsedRegs[Reg];
416         });
417 
418     if (NextSpillReg == Regs.end()) { // Registers exhausted
419       Spill.FullyAllocated = false;
420       break;
421     }
422 
423     OtherUsedRegs.set(*NextSpillReg);
424     SpillRegs.push_back(*NextSpillReg);
425     Spill.Lanes[I] = *NextSpillReg++;
426   }
427 
428   return Spill.FullyAllocated;
429 }
430 
431 void SIMachineFunctionInfo::removeDeadFrameIndices(MachineFrameInfo &MFI) {
432   // Remove dead frame indices from function frame, however keep FP & BP since
433   // spills for them haven't been inserted yet. And also make sure to remove the
434   // frame indices from `SGPRToVGPRSpills` data structure, otherwise, it could
435   // result in an unexpected side effect and bug, in case of any re-mapping of
436   // freed frame indices by later pass(es) like "stack slot coloring".
437   for (auto &R : make_early_inc_range(SGPRToVGPRSpills)) {
438     if (R.first != FramePointerSaveIndex && R.first != BasePointerSaveIndex) {
439       MFI.RemoveStackObject(R.first);
440       SGPRToVGPRSpills.erase(R.first);
441     }
442   }
443 
444   // All other SPGRs must be allocated on the default stack, so reset the stack
445   // ID.
446   for (int i = MFI.getObjectIndexBegin(), e = MFI.getObjectIndexEnd(); i != e;
447        ++i)
448     if (i != FramePointerSaveIndex && i != BasePointerSaveIndex)
449       MFI.setStackID(i, TargetStackID::Default);
450 
451   for (auto &R : VGPRToAGPRSpills) {
452     if (R.second.FullyAllocated)
453       MFI.RemoveStackObject(R.first);
454   }
455 }
456 
457 int SIMachineFunctionInfo::getScavengeFI(MachineFrameInfo &MFI,
458                                          const SIRegisterInfo &TRI) {
459   if (ScavengeFI)
460     return *ScavengeFI;
461   if (isEntryFunction()) {
462     ScavengeFI = MFI.CreateFixedObject(
463         TRI.getSpillSize(AMDGPU::SGPR_32RegClass), 0, false);
464   } else {
465     ScavengeFI = MFI.CreateStackObject(
466         TRI.getSpillSize(AMDGPU::SGPR_32RegClass),
467         TRI.getSpillAlign(AMDGPU::SGPR_32RegClass), false);
468   }
469   return *ScavengeFI;
470 }
471 
472 MCPhysReg SIMachineFunctionInfo::getNextUserSGPR() const {
473   assert(NumSystemSGPRs == 0 && "System SGPRs must be added after user SGPRs");
474   return AMDGPU::SGPR0 + NumUserSGPRs;
475 }
476 
477 MCPhysReg SIMachineFunctionInfo::getNextSystemSGPR() const {
478   return AMDGPU::SGPR0 + NumUserSGPRs + NumSystemSGPRs;
479 }
480 
481 Register
482 SIMachineFunctionInfo::getGITPtrLoReg(const MachineFunction &MF) const {
483   const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
484   if (!ST.isAmdPalOS())
485     return Register();
486   Register GitPtrLo = AMDGPU::SGPR0; // Low GIT address passed in
487   if (ST.hasMergedShaders()) {
488     switch (MF.getFunction().getCallingConv()) {
489     case CallingConv::AMDGPU_HS:
490     case CallingConv::AMDGPU_GS:
491       // Low GIT address is passed in s8 rather than s0 for an LS+HS or
492       // ES+GS merged shader on gfx9+.
493       GitPtrLo = AMDGPU::SGPR8;
494       return GitPtrLo;
495     default:
496       return GitPtrLo;
497     }
498   }
499   return GitPtrLo;
500 }
501 
502 static yaml::StringValue regToString(Register Reg,
503                                      const TargetRegisterInfo &TRI) {
504   yaml::StringValue Dest;
505   {
506     raw_string_ostream OS(Dest.Value);
507     OS << printReg(Reg, &TRI);
508   }
509   return Dest;
510 }
511 
512 static Optional<yaml::SIArgumentInfo>
513 convertArgumentInfo(const AMDGPUFunctionArgInfo &ArgInfo,
514                     const TargetRegisterInfo &TRI) {
515   yaml::SIArgumentInfo AI;
516 
517   auto convertArg = [&](Optional<yaml::SIArgument> &A,
518                         const ArgDescriptor &Arg) {
519     if (!Arg)
520       return false;
521 
522     // Create a register or stack argument.
523     yaml::SIArgument SA = yaml::SIArgument::createArgument(Arg.isRegister());
524     if (Arg.isRegister()) {
525       raw_string_ostream OS(SA.RegisterName.Value);
526       OS << printReg(Arg.getRegister(), &TRI);
527     } else
528       SA.StackOffset = Arg.getStackOffset();
529     // Check and update the optional mask.
530     if (Arg.isMasked())
531       SA.Mask = Arg.getMask();
532 
533     A = SA;
534     return true;
535   };
536 
537   bool Any = false;
538   Any |= convertArg(AI.PrivateSegmentBuffer, ArgInfo.PrivateSegmentBuffer);
539   Any |= convertArg(AI.DispatchPtr, ArgInfo.DispatchPtr);
540   Any |= convertArg(AI.QueuePtr, ArgInfo.QueuePtr);
541   Any |= convertArg(AI.KernargSegmentPtr, ArgInfo.KernargSegmentPtr);
542   Any |= convertArg(AI.DispatchID, ArgInfo.DispatchID);
543   Any |= convertArg(AI.FlatScratchInit, ArgInfo.FlatScratchInit);
544   Any |= convertArg(AI.PrivateSegmentSize, ArgInfo.PrivateSegmentSize);
545   Any |= convertArg(AI.WorkGroupIDX, ArgInfo.WorkGroupIDX);
546   Any |= convertArg(AI.WorkGroupIDY, ArgInfo.WorkGroupIDY);
547   Any |= convertArg(AI.WorkGroupIDZ, ArgInfo.WorkGroupIDZ);
548   Any |= convertArg(AI.WorkGroupInfo, ArgInfo.WorkGroupInfo);
549   Any |= convertArg(AI.PrivateSegmentWaveByteOffset,
550                     ArgInfo.PrivateSegmentWaveByteOffset);
551   Any |= convertArg(AI.ImplicitArgPtr, ArgInfo.ImplicitArgPtr);
552   Any |= convertArg(AI.ImplicitBufferPtr, ArgInfo.ImplicitBufferPtr);
553   Any |= convertArg(AI.WorkItemIDX, ArgInfo.WorkItemIDX);
554   Any |= convertArg(AI.WorkItemIDY, ArgInfo.WorkItemIDY);
555   Any |= convertArg(AI.WorkItemIDZ, ArgInfo.WorkItemIDZ);
556 
557   if (Any)
558     return AI;
559 
560   return None;
561 }
562 
563 yaml::SIMachineFunctionInfo::SIMachineFunctionInfo(
564     const llvm::SIMachineFunctionInfo &MFI, const TargetRegisterInfo &TRI,
565     const llvm::MachineFunction &MF)
566     : ExplicitKernArgSize(MFI.getExplicitKernArgSize()),
567       MaxKernArgAlign(MFI.getMaxKernArgAlign()), LDSSize(MFI.getLDSSize()),
568       DynLDSAlign(MFI.getDynLDSAlign()), IsEntryFunction(MFI.isEntryFunction()),
569       NoSignedZerosFPMath(MFI.hasNoSignedZerosFPMath()),
570       MemoryBound(MFI.isMemoryBound()), WaveLimiter(MFI.needsWaveLimiter()),
571       HasSpilledSGPRs(MFI.hasSpilledSGPRs()),
572       HasSpilledVGPRs(MFI.hasSpilledVGPRs()),
573       HighBitsOf32BitAddress(MFI.get32BitAddressHighBits()),
574       Occupancy(MFI.getOccupancy()),
575       ScratchRSrcReg(regToString(MFI.getScratchRSrcReg(), TRI)),
576       FrameOffsetReg(regToString(MFI.getFrameOffsetReg(), TRI)),
577       StackPtrOffsetReg(regToString(MFI.getStackPtrOffsetReg(), TRI)),
578       ArgInfo(convertArgumentInfo(MFI.getArgInfo(), TRI)), Mode(MFI.getMode()) {
579   auto SFI = MFI.getOptionalScavengeFI();
580   if (SFI)
581     ScavengeFI = yaml::FrameIndex(*SFI, MF.getFrameInfo());
582 }
583 
584 void yaml::SIMachineFunctionInfo::mappingImpl(yaml::IO &YamlIO) {
585   MappingTraits<SIMachineFunctionInfo>::mapping(YamlIO, *this);
586 }
587 
588 bool SIMachineFunctionInfo::initializeBaseYamlFields(
589     const yaml::SIMachineFunctionInfo &YamlMFI, const MachineFunction &MF,
590     PerFunctionMIParsingState &PFS, SMDiagnostic &Error, SMRange &SourceRange) {
591   ExplicitKernArgSize = YamlMFI.ExplicitKernArgSize;
592   MaxKernArgAlign = assumeAligned(YamlMFI.MaxKernArgAlign);
593   LDSSize = YamlMFI.LDSSize;
594   DynLDSAlign = YamlMFI.DynLDSAlign;
595   HighBitsOf32BitAddress = YamlMFI.HighBitsOf32BitAddress;
596   Occupancy = YamlMFI.Occupancy;
597   IsEntryFunction = YamlMFI.IsEntryFunction;
598   NoSignedZerosFPMath = YamlMFI.NoSignedZerosFPMath;
599   MemoryBound = YamlMFI.MemoryBound;
600   WaveLimiter = YamlMFI.WaveLimiter;
601   HasSpilledSGPRs = YamlMFI.HasSpilledSGPRs;
602   HasSpilledVGPRs = YamlMFI.HasSpilledVGPRs;
603 
604   if (YamlMFI.ScavengeFI) {
605     auto FIOrErr = YamlMFI.ScavengeFI->getFI(MF.getFrameInfo());
606     if (!FIOrErr) {
607       // Create a diagnostic for a the frame index.
608       const MemoryBuffer &Buffer =
609           *PFS.SM->getMemoryBuffer(PFS.SM->getMainFileID());
610 
611       Error = SMDiagnostic(*PFS.SM, SMLoc(), Buffer.getBufferIdentifier(), 1, 1,
612                            SourceMgr::DK_Error, toString(FIOrErr.takeError()),
613                            "", None, None);
614       SourceRange = YamlMFI.ScavengeFI->SourceRange;
615       return true;
616     }
617     ScavengeFI = *FIOrErr;
618   } else {
619     ScavengeFI = None;
620   }
621   return false;
622 }
623 
624 // Remove VGPR which was reserved for SGPR spills if there are no spilled SGPRs
625 bool SIMachineFunctionInfo::removeVGPRForSGPRSpill(Register ReservedVGPR,
626                                                    MachineFunction &MF) {
627   for (auto *i = SpillVGPRs.begin(); i < SpillVGPRs.end(); i++) {
628     if (i->VGPR == ReservedVGPR) {
629       SpillVGPRs.erase(i);
630 
631       for (MachineBasicBlock &MBB : MF) {
632         MBB.removeLiveIn(ReservedVGPR);
633         MBB.sortUniqueLiveIns();
634       }
635       this->VGPRReservedForSGPRSpill = AMDGPU::NoRegister;
636       return true;
637     }
638   }
639   return false;
640 }
641 
642 bool SIMachineFunctionInfo::usesAGPRs(const MachineFunction &MF) const {
643   if (UsesAGPRs)
644     return *UsesAGPRs;
645 
646   if (!AMDGPU::isEntryFunctionCC(MF.getFunction().getCallingConv()) ||
647       MF.getFrameInfo().hasCalls()) {
648     UsesAGPRs = true;
649     return true;
650   }
651 
652   const MachineRegisterInfo &MRI = MF.getRegInfo();
653 
654   for (unsigned I = 0, E = MRI.getNumVirtRegs(); I != E; ++I) {
655     const Register Reg = Register::index2VirtReg(I);
656     const TargetRegisterClass *RC = MRI.getRegClassOrNull(Reg);
657     if (RC && SIRegisterInfo::isAGPRClass(RC)) {
658       UsesAGPRs = true;
659       return true;
660     } else if (!RC && !MRI.use_empty(Reg) && MRI.getType(Reg).isValid()) {
661       // Defer caching UsesAGPRs, function might not yet been regbank selected.
662       return true;
663     }
664   }
665 
666   for (MCRegister Reg : AMDGPU::AGPR_32RegClass) {
667     if (MRI.isPhysRegUsed(Reg)) {
668       UsesAGPRs = true;
669       return true;
670     }
671   }
672 
673   UsesAGPRs = false;
674   return false;
675 }
676