1 //===-- SIMachineFunctionInfo.cpp -------- SI Machine Function Info -------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
10 #include "SIMachineFunctionInfo.h"
11 #include "AMDGPUSubtarget.h"
12 #include "SIInstrInfo.h"
13 #include "llvm/CodeGen/MachineFrameInfo.h"
14 #include "llvm/CodeGen/MachineInstrBuilder.h"
15 #include "llvm/CodeGen/MachineRegisterInfo.h"
16 #include "llvm/IR/Function.h"
17 #include "llvm/IR/LLVMContext.h"
18 
19 #define MAX_LANES 64
20 
21 using namespace llvm;
22 
23 static cl::opt<bool> EnableSpillSGPRToVGPR(
24   "amdgpu-spill-sgpr-to-vgpr",
25   cl::desc("Enable spilling VGPRs to SGPRs"),
26   cl::ReallyHidden,
27   cl::init(true));
28 
29 // Pin the vtable to this file.
30 void SIMachineFunctionInfo::anchor() {}
31 
32 SIMachineFunctionInfo::SIMachineFunctionInfo(const MachineFunction &MF)
33   : AMDGPUMachineFunction(MF),
34     TIDReg(AMDGPU::NoRegister),
35     ScratchRSrcReg(AMDGPU::NoRegister),
36     ScratchWaveOffsetReg(AMDGPU::NoRegister),
37     PrivateSegmentBufferUserSGPR(AMDGPU::NoRegister),
38     DispatchPtrUserSGPR(AMDGPU::NoRegister),
39     QueuePtrUserSGPR(AMDGPU::NoRegister),
40     KernargSegmentPtrUserSGPR(AMDGPU::NoRegister),
41     DispatchIDUserSGPR(AMDGPU::NoRegister),
42     FlatScratchInitUserSGPR(AMDGPU::NoRegister),
43     PrivateSegmentSizeUserSGPR(AMDGPU::NoRegister),
44     GridWorkGroupCountXUserSGPR(AMDGPU::NoRegister),
45     GridWorkGroupCountYUserSGPR(AMDGPU::NoRegister),
46     GridWorkGroupCountZUserSGPR(AMDGPU::NoRegister),
47     WorkGroupIDXSystemSGPR(AMDGPU::NoRegister),
48     WorkGroupIDYSystemSGPR(AMDGPU::NoRegister),
49     WorkGroupIDZSystemSGPR(AMDGPU::NoRegister),
50     WorkGroupInfoSystemSGPR(AMDGPU::NoRegister),
51     PrivateSegmentWaveByteOffsetSystemSGPR(AMDGPU::NoRegister),
52     PSInputAddr(0),
53     ReturnsVoid(true),
54     MaximumWorkGroupSize(0),
55     DebuggerReservedVGPRCount(0),
56     DebuggerWorkGroupIDStackObjectIndices({{0, 0, 0}}),
57     DebuggerWorkItemIDStackObjectIndices({{0, 0, 0}}),
58     LDSWaveSpillSize(0),
59     PSInputEna(0),
60     NumUserSGPRs(0),
61     NumSystemSGPRs(0),
62     HasSpilledSGPRs(false),
63     HasSpilledVGPRs(false),
64     HasNonSpillStackObjects(false),
65     HasFlatInstructions(false),
66     NumSpilledSGPRs(0),
67     NumSpilledVGPRs(0),
68     PrivateSegmentBuffer(false),
69     DispatchPtr(false),
70     QueuePtr(false),
71     KernargSegmentPtr(false),
72     DispatchID(false),
73     FlatScratchInit(false),
74     GridWorkgroupCountX(false),
75     GridWorkgroupCountY(false),
76     GridWorkgroupCountZ(false),
77     WorkGroupIDX(false),
78     WorkGroupIDY(false),
79     WorkGroupIDZ(false),
80     WorkGroupInfo(false),
81     PrivateSegmentWaveByteOffset(false),
82     WorkItemIDX(false),
83     WorkItemIDY(false),
84     WorkItemIDZ(false) {
85   const SISubtarget &ST = MF.getSubtarget<SISubtarget>();
86   const Function *F = MF.getFunction();
87 
88   PSInputAddr = AMDGPU::getInitialPSInputAddr(*F);
89 
90   const MachineFrameInfo *FrameInfo = MF.getFrameInfo();
91 
92   if (!AMDGPU::isShader(F->getCallingConv())) {
93     KernargSegmentPtr = true;
94     WorkGroupIDX = true;
95     WorkItemIDX = true;
96   }
97 
98   if (F->hasFnAttribute("amdgpu-work-group-id-y") || ST.debuggerEmitPrologue())
99     WorkGroupIDY = true;
100 
101   if (F->hasFnAttribute("amdgpu-work-group-id-z") || ST.debuggerEmitPrologue())
102     WorkGroupIDZ = true;
103 
104   if (F->hasFnAttribute("amdgpu-work-item-id-y") || ST.debuggerEmitPrologue())
105     WorkItemIDY = true;
106 
107   if (F->hasFnAttribute("amdgpu-work-item-id-z") || ST.debuggerEmitPrologue())
108     WorkItemIDZ = true;
109 
110   // X, XY, and XYZ are the only supported combinations, so make sure Y is
111   // enabled if Z is.
112   if (WorkItemIDZ)
113     WorkItemIDY = true;
114 
115   bool MaySpill = ST.isVGPRSpillingEnabled(*F);
116   bool HasStackObjects = FrameInfo->hasStackObjects();
117 
118   if (HasStackObjects || MaySpill)
119     PrivateSegmentWaveByteOffset = true;
120 
121   if (ST.isAmdHsaOS()) {
122     if (HasStackObjects || MaySpill)
123       PrivateSegmentBuffer = true;
124 
125     if (F->hasFnAttribute("amdgpu-dispatch-ptr"))
126       DispatchPtr = true;
127 
128     if (F->hasFnAttribute("amdgpu-queue-ptr"))
129       QueuePtr = true;
130 
131     if (F->hasFnAttribute("amdgpu-dispatch-id"))
132       DispatchID = true;
133   }
134 
135   // We don't need to worry about accessing spills with flat instructions.
136   // TODO: On VI where we must use flat for global, we should be able to omit
137   // this if it is never used for generic access.
138   if (HasStackObjects && ST.getGeneration() >= SISubtarget::SEA_ISLANDS &&
139       ST.isAmdHsaOS())
140     FlatScratchInit = true;
141 
142   if (AMDGPU::isCompute(F->getCallingConv()))
143     MaximumWorkGroupSize = AMDGPU::getMaximumWorkGroupSize(*F);
144   else
145     MaximumWorkGroupSize = ST.getWavefrontSize();
146 
147   if (ST.debuggerReserveRegs())
148     DebuggerReservedVGPRCount = 4;
149 }
150 
151 unsigned SIMachineFunctionInfo::addPrivateSegmentBuffer(
152   const SIRegisterInfo &TRI) {
153   PrivateSegmentBufferUserSGPR = TRI.getMatchingSuperReg(
154     getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_128RegClass);
155   NumUserSGPRs += 4;
156   return PrivateSegmentBufferUserSGPR;
157 }
158 
159 unsigned SIMachineFunctionInfo::addDispatchPtr(const SIRegisterInfo &TRI) {
160   DispatchPtrUserSGPR = TRI.getMatchingSuperReg(
161     getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass);
162   NumUserSGPRs += 2;
163   return DispatchPtrUserSGPR;
164 }
165 
166 unsigned SIMachineFunctionInfo::addQueuePtr(const SIRegisterInfo &TRI) {
167   QueuePtrUserSGPR = TRI.getMatchingSuperReg(
168     getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass);
169   NumUserSGPRs += 2;
170   return QueuePtrUserSGPR;
171 }
172 
173 unsigned SIMachineFunctionInfo::addKernargSegmentPtr(const SIRegisterInfo &TRI) {
174   KernargSegmentPtrUserSGPR = TRI.getMatchingSuperReg(
175     getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass);
176   NumUserSGPRs += 2;
177   return KernargSegmentPtrUserSGPR;
178 }
179 
180 unsigned SIMachineFunctionInfo::addDispatchID(const SIRegisterInfo &TRI) {
181   DispatchIDUserSGPR = TRI.getMatchingSuperReg(
182     getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass);
183   NumUserSGPRs += 2;
184   return DispatchIDUserSGPR;
185 }
186 
187 unsigned SIMachineFunctionInfo::addFlatScratchInit(const SIRegisterInfo &TRI) {
188   FlatScratchInitUserSGPR = TRI.getMatchingSuperReg(
189     getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass);
190   NumUserSGPRs += 2;
191   return FlatScratchInitUserSGPR;
192 }
193 
194 SIMachineFunctionInfo::SpilledReg SIMachineFunctionInfo::getSpilledReg (
195                                                        MachineFunction *MF,
196                                                        unsigned FrameIndex,
197                                                        unsigned SubIdx) {
198   if (!EnableSpillSGPRToVGPR)
199     return SpilledReg();
200 
201   const SISubtarget &ST = MF->getSubtarget<SISubtarget>();
202   const SIRegisterInfo *TRI = ST.getRegisterInfo();
203 
204   MachineFrameInfo *FrameInfo = MF->getFrameInfo();
205   MachineRegisterInfo &MRI = MF->getRegInfo();
206   int64_t Offset = FrameInfo->getObjectOffset(FrameIndex);
207   Offset += SubIdx * 4;
208 
209   unsigned LaneVGPRIdx = Offset / (64 * 4);
210   unsigned Lane = (Offset / 4) % 64;
211 
212   struct SpilledReg Spill;
213   Spill.Lane = Lane;
214 
215   if (!LaneVGPRs.count(LaneVGPRIdx)) {
216     unsigned LaneVGPR = TRI->findUnusedRegister(MRI, &AMDGPU::VGPR_32RegClass);
217 
218     if (LaneVGPR == AMDGPU::NoRegister)
219       // We have no VGPRs left for spilling SGPRs.
220       return Spill;
221 
222     LaneVGPRs[LaneVGPRIdx] = LaneVGPR;
223 
224     // Add this register as live-in to all blocks to avoid machine verifer
225     // complaining about use of an undefined physical register.
226     for (MachineFunction::iterator BI = MF->begin(), BE = MF->end();
227          BI != BE; ++BI) {
228       BI->addLiveIn(LaneVGPR);
229     }
230   }
231 
232   Spill.VGPR = LaneVGPRs[LaneVGPRIdx];
233   return Spill;
234 }
235 
236 unsigned SIMachineFunctionInfo::getMaximumWorkGroupSize(
237                                               const MachineFunction &MF) const {
238   return MaximumWorkGroupSize;
239 }
240