1 //===- SIMachineFunctionInfo.cpp - SI Machine Function Info ---------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #include "SIMachineFunctionInfo.h"
10 #include "AMDGPUArgumentUsageInfo.h"
11 #include "AMDGPUTargetMachine.h"
12 #include "AMDGPUSubtarget.h"
13 #include "SIRegisterInfo.h"
14 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
15 #include "Utils/AMDGPUBaseInfo.h"
16 #include "llvm/ADT/Optional.h"
17 #include "llvm/CodeGen/MachineBasicBlock.h"
18 #include "llvm/CodeGen/MachineFrameInfo.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/MachineRegisterInfo.h"
21 #include "llvm/IR/CallingConv.h"
22 #include "llvm/IR/Function.h"
23 #include <cassert>
24 #include <vector>
25 
26 #define MAX_LANES 64
27 
28 using namespace llvm;
29 
30 SIMachineFunctionInfo::SIMachineFunctionInfo(const MachineFunction &MF)
31   : AMDGPUMachineFunction(MF),
32     PrivateSegmentBuffer(false),
33     DispatchPtr(false),
34     QueuePtr(false),
35     KernargSegmentPtr(false),
36     DispatchID(false),
37     FlatScratchInit(false),
38     WorkGroupIDX(false),
39     WorkGroupIDY(false),
40     WorkGroupIDZ(false),
41     WorkGroupInfo(false),
42     PrivateSegmentWaveByteOffset(false),
43     WorkItemIDX(false),
44     WorkItemIDY(false),
45     WorkItemIDZ(false),
46     ImplicitBufferPtr(false),
47     ImplicitArgPtr(false),
48     GITPtrHigh(0xffffffff),
49     HighBitsOf32BitAddress(0),
50     GDSSize(0) {
51   const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
52   const Function &F = MF.getFunction();
53   FlatWorkGroupSizes = ST.getFlatWorkGroupSizes(F);
54   WavesPerEU = ST.getWavesPerEU(F);
55 
56   Occupancy = ST.computeOccupancy(MF, getLDSSize());
57   CallingConv::ID CC = F.getCallingConv();
58   const MachineFrameInfo &FrameInfo = MF.getFrameInfo();
59 
60   // FIXME: Should have analysis or something rather than attribute to detect
61   // calls.
62   const bool HasCalls = FrameInfo.hasCalls() || F.hasFnAttribute("amdgpu-calls");
63 
64   // Enable all kernel inputs if we have the fixed ABI. Don't bother if we don't
65   // have any calls.
66   const bool UseFixedABI = AMDGPUTargetMachine::EnableFixedFunctionABI &&
67                            (!isEntryFunction() || HasCalls);
68 
69   if (CC == CallingConv::AMDGPU_KERNEL || CC == CallingConv::SPIR_KERNEL) {
70     if (!F.arg_empty())
71       KernargSegmentPtr = true;
72     WorkGroupIDX = true;
73     WorkItemIDX = true;
74   } else if (CC == CallingConv::AMDGPU_PS) {
75     PSInputAddr = AMDGPU::getInitialPSInputAddr(F);
76   }
77 
78   if (!isEntryFunction()) {
79     // Non-entry functions have no special inputs for now, other registers
80     // required for scratch access.
81     ScratchRSrcReg = AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3;
82 
83     // TODO: Pick a high register, and shift down, similar to a kernel.
84     FrameOffsetReg = AMDGPU::SGPR33;
85     StackPtrOffsetReg = AMDGPU::SGPR32;
86 
87     ArgInfo.PrivateSegmentBuffer =
88       ArgDescriptor::createRegister(ScratchRSrcReg);
89 
90     if (F.hasFnAttribute("amdgpu-implicitarg-ptr"))
91       ImplicitArgPtr = true;
92   } else {
93     if (F.hasFnAttribute("amdgpu-implicitarg-ptr")) {
94       KernargSegmentPtr = true;
95       MaxKernArgAlign = std::max(ST.getAlignmentForImplicitArgPtr(),
96                                  MaxKernArgAlign);
97     }
98   }
99 
100   if (UseFixedABI) {
101     WorkGroupIDX = true;
102     WorkGroupIDY = true;
103     WorkGroupIDZ = true;
104     WorkItemIDX = true;
105     WorkItemIDY = true;
106     WorkItemIDZ = true;
107     ImplicitArgPtr = true;
108   } else {
109     if (F.hasFnAttribute("amdgpu-work-group-id-x"))
110       WorkGroupIDX = true;
111 
112     if (F.hasFnAttribute("amdgpu-work-group-id-y"))
113       WorkGroupIDY = true;
114 
115     if (F.hasFnAttribute("amdgpu-work-group-id-z"))
116       WorkGroupIDZ = true;
117 
118     if (F.hasFnAttribute("amdgpu-work-item-id-x"))
119       WorkItemIDX = true;
120 
121     if (F.hasFnAttribute("amdgpu-work-item-id-y"))
122       WorkItemIDY = true;
123 
124     if (F.hasFnAttribute("amdgpu-work-item-id-z"))
125       WorkItemIDZ = true;
126   }
127 
128   bool HasStackObjects = FrameInfo.hasStackObjects();
129 
130   if (isEntryFunction()) {
131     // X, XY, and XYZ are the only supported combinations, so make sure Y is
132     // enabled if Z is.
133     if (WorkItemIDZ)
134       WorkItemIDY = true;
135 
136     PrivateSegmentWaveByteOffset = true;
137 
138     // HS and GS always have the scratch wave offset in SGPR5 on GFX9.
139     if (ST.getGeneration() >= AMDGPUSubtarget::GFX9 &&
140         (CC == CallingConv::AMDGPU_HS || CC == CallingConv::AMDGPU_GS))
141       ArgInfo.PrivateSegmentWaveByteOffset =
142           ArgDescriptor::createRegister(AMDGPU::SGPR5);
143   }
144 
145   bool isAmdHsaOrMesa = ST.isAmdHsaOrMesa(F);
146   if (isAmdHsaOrMesa) {
147     PrivateSegmentBuffer = true;
148 
149     if (UseFixedABI) {
150       DispatchPtr = true;
151       QueuePtr = true;
152 
153       // FIXME: We don't need this?
154       DispatchID = true;
155     } else {
156       if (F.hasFnAttribute("amdgpu-dispatch-ptr"))
157         DispatchPtr = true;
158 
159       if (F.hasFnAttribute("amdgpu-queue-ptr"))
160         QueuePtr = true;
161 
162       if (F.hasFnAttribute("amdgpu-dispatch-id"))
163         DispatchID = true;
164     }
165   } else if (ST.isMesaGfxShader(F)) {
166     ImplicitBufferPtr = true;
167   }
168 
169   if (UseFixedABI || F.hasFnAttribute("amdgpu-kernarg-segment-ptr"))
170     KernargSegmentPtr = true;
171 
172   if (ST.hasFlatAddressSpace() && isEntryFunction() && isAmdHsaOrMesa) {
173     auto hasNonSpillStackObjects = [&]() {
174       // Avoid expensive checking if there's no stack objects.
175       if (!HasStackObjects)
176         return false;
177       for (auto OI = FrameInfo.getObjectIndexBegin(),
178                 OE = FrameInfo.getObjectIndexEnd(); OI != OE; ++OI)
179         if (!FrameInfo.isSpillSlotObjectIndex(OI))
180           return true;
181       // All stack objects are spill slots.
182       return false;
183     };
184     // TODO: This could be refined a lot. The attribute is a poor way of
185     // detecting calls that may require it before argument lowering.
186     if (HasCalls || hasNonSpillStackObjects())
187       FlatScratchInit = true;
188   }
189 
190   Attribute A = F.getFnAttribute("amdgpu-git-ptr-high");
191   StringRef S = A.getValueAsString();
192   if (!S.empty())
193     S.consumeInteger(0, GITPtrHigh);
194 
195   A = F.getFnAttribute("amdgpu-32bit-address-high-bits");
196   S = A.getValueAsString();
197   if (!S.empty())
198     S.consumeInteger(0, HighBitsOf32BitAddress);
199 
200   S = F.getFnAttribute("amdgpu-gds-size").getValueAsString();
201   if (!S.empty())
202     S.consumeInteger(0, GDSSize);
203 }
204 
205 void SIMachineFunctionInfo::limitOccupancy(const MachineFunction &MF) {
206   limitOccupancy(getMaxWavesPerEU());
207   const GCNSubtarget& ST = MF.getSubtarget<GCNSubtarget>();
208   limitOccupancy(ST.getOccupancyWithLocalMemSize(getLDSSize(),
209                  MF.getFunction()));
210 }
211 
212 Register SIMachineFunctionInfo::addPrivateSegmentBuffer(
213   const SIRegisterInfo &TRI) {
214   ArgInfo.PrivateSegmentBuffer =
215     ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
216     getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SGPR_128RegClass));
217   NumUserSGPRs += 4;
218   return ArgInfo.PrivateSegmentBuffer.getRegister();
219 }
220 
221 Register SIMachineFunctionInfo::addDispatchPtr(const SIRegisterInfo &TRI) {
222   ArgInfo.DispatchPtr = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
223     getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
224   NumUserSGPRs += 2;
225   return ArgInfo.DispatchPtr.getRegister();
226 }
227 
228 Register SIMachineFunctionInfo::addQueuePtr(const SIRegisterInfo &TRI) {
229   ArgInfo.QueuePtr = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
230     getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
231   NumUserSGPRs += 2;
232   return ArgInfo.QueuePtr.getRegister();
233 }
234 
235 Register SIMachineFunctionInfo::addKernargSegmentPtr(const SIRegisterInfo &TRI) {
236   ArgInfo.KernargSegmentPtr
237     = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
238     getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
239   NumUserSGPRs += 2;
240   return ArgInfo.KernargSegmentPtr.getRegister();
241 }
242 
243 Register SIMachineFunctionInfo::addDispatchID(const SIRegisterInfo &TRI) {
244   ArgInfo.DispatchID = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
245     getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
246   NumUserSGPRs += 2;
247   return ArgInfo.DispatchID.getRegister();
248 }
249 
250 Register SIMachineFunctionInfo::addFlatScratchInit(const SIRegisterInfo &TRI) {
251   ArgInfo.FlatScratchInit = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
252     getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
253   NumUserSGPRs += 2;
254   return ArgInfo.FlatScratchInit.getRegister();
255 }
256 
257 Register SIMachineFunctionInfo::addImplicitBufferPtr(const SIRegisterInfo &TRI) {
258   ArgInfo.ImplicitBufferPtr = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
259     getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
260   NumUserSGPRs += 2;
261   return ArgInfo.ImplicitBufferPtr.getRegister();
262 }
263 
264 static bool isCalleeSavedReg(const MCPhysReg *CSRegs, MCPhysReg Reg) {
265   for (unsigned I = 0; CSRegs[I]; ++I) {
266     if (CSRegs[I] == Reg)
267       return true;
268   }
269 
270   return false;
271 }
272 
273 /// \p returns true if \p NumLanes slots are available in VGPRs already used for
274 /// SGPR spilling.
275 //
276 // FIXME: This only works after processFunctionBeforeFrameFinalized
277 bool SIMachineFunctionInfo::haveFreeLanesForSGPRSpill(const MachineFunction &MF,
278                                                       unsigned NumNeed) const {
279   const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
280   unsigned WaveSize = ST.getWavefrontSize();
281   return NumVGPRSpillLanes + NumNeed <= WaveSize * SpillVGPRs.size();
282 }
283 
284 /// Reserve a slice of a VGPR to support spilling for FrameIndex \p FI.
285 bool SIMachineFunctionInfo::allocateSGPRSpillToVGPR(MachineFunction &MF,
286                                                     int FI) {
287   std::vector<SpilledReg> &SpillLanes = SGPRToVGPRSpills[FI];
288 
289   // This has already been allocated.
290   if (!SpillLanes.empty())
291     return true;
292 
293   const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
294   const SIRegisterInfo *TRI = ST.getRegisterInfo();
295   MachineFrameInfo &FrameInfo = MF.getFrameInfo();
296   MachineRegisterInfo &MRI = MF.getRegInfo();
297   unsigned WaveSize = ST.getWavefrontSize();
298 
299   unsigned Size = FrameInfo.getObjectSize(FI);
300   assert(Size >= 4 && Size <= 64 && "invalid sgpr spill size");
301   assert(TRI->spillSGPRToVGPR() && "not spilling SGPRs to VGPRs");
302 
303   int NumLanes = Size / 4;
304 
305   const MCPhysReg *CSRegs = MRI.getCalleeSavedRegs();
306 
307   // Make sure to handle the case where a wide SGPR spill may span between two
308   // VGPRs.
309   for (int I = 0; I < NumLanes; ++I, ++NumVGPRSpillLanes) {
310     Register LaneVGPR;
311     unsigned VGPRIndex = (NumVGPRSpillLanes % WaveSize);
312 
313     if (VGPRIndex == 0) {
314       LaneVGPR = TRI->findUnusedRegister(MRI, &AMDGPU::VGPR_32RegClass, MF);
315       if (LaneVGPR == AMDGPU::NoRegister) {
316         // We have no VGPRs left for spilling SGPRs. Reset because we will not
317         // partially spill the SGPR to VGPRs.
318         SGPRToVGPRSpills.erase(FI);
319         NumVGPRSpillLanes -= I;
320         return false;
321       }
322 
323       Optional<int> CSRSpillFI;
324       if ((FrameInfo.hasCalls() || !isEntryFunction()) && CSRegs &&
325           isCalleeSavedReg(CSRegs, LaneVGPR)) {
326         CSRSpillFI = FrameInfo.CreateSpillStackObject(4, Align(4));
327       }
328 
329       SpillVGPRs.push_back(SGPRSpillVGPRCSR(LaneVGPR, CSRSpillFI));
330 
331       // Add this register as live-in to all blocks to avoid machine verifer
332       // complaining about use of an undefined physical register.
333       for (MachineBasicBlock &BB : MF)
334         BB.addLiveIn(LaneVGPR);
335     } else {
336       LaneVGPR = SpillVGPRs.back().VGPR;
337     }
338 
339     SpillLanes.push_back(SpilledReg(LaneVGPR, VGPRIndex));
340   }
341 
342   return true;
343 }
344 
345 /// Reserve AGPRs or VGPRs to support spilling for FrameIndex \p FI.
346 /// Either AGPR is spilled to VGPR to vice versa.
347 /// Returns true if a \p FI can be eliminated completely.
348 bool SIMachineFunctionInfo::allocateVGPRSpillToAGPR(MachineFunction &MF,
349                                                     int FI,
350                                                     bool isAGPRtoVGPR) {
351   MachineRegisterInfo &MRI = MF.getRegInfo();
352   MachineFrameInfo &FrameInfo = MF.getFrameInfo();
353   const GCNSubtarget &ST =  MF.getSubtarget<GCNSubtarget>();
354 
355   assert(ST.hasMAIInsts() && FrameInfo.isSpillSlotObjectIndex(FI));
356 
357   auto &Spill = VGPRToAGPRSpills[FI];
358 
359   // This has already been allocated.
360   if (!Spill.Lanes.empty())
361     return Spill.FullyAllocated;
362 
363   unsigned Size = FrameInfo.getObjectSize(FI);
364   unsigned NumLanes = Size / 4;
365   Spill.Lanes.resize(NumLanes, AMDGPU::NoRegister);
366 
367   const TargetRegisterClass &RC =
368       isAGPRtoVGPR ? AMDGPU::VGPR_32RegClass : AMDGPU::AGPR_32RegClass;
369   auto Regs = RC.getRegisters();
370 
371   auto &SpillRegs = isAGPRtoVGPR ? SpillAGPR : SpillVGPR;
372   const SIRegisterInfo *TRI = ST.getRegisterInfo();
373   Spill.FullyAllocated = true;
374 
375   // FIXME: Move allocation logic out of MachineFunctionInfo and initialize
376   // once.
377   BitVector OtherUsedRegs;
378   OtherUsedRegs.resize(TRI->getNumRegs());
379 
380   const uint32_t *CSRMask =
381       TRI->getCallPreservedMask(MF, MF.getFunction().getCallingConv());
382   if (CSRMask)
383     OtherUsedRegs.setBitsInMask(CSRMask);
384 
385   // TODO: Should include register tuples, but doesn't matter with current
386   // usage.
387   for (MCPhysReg Reg : SpillAGPR)
388     OtherUsedRegs.set(Reg);
389   for (MCPhysReg Reg : SpillVGPR)
390     OtherUsedRegs.set(Reg);
391 
392   SmallVectorImpl<MCPhysReg>::const_iterator NextSpillReg = Regs.begin();
393   for (unsigned I = 0; I < NumLanes; ++I) {
394     NextSpillReg = std::find_if(
395         NextSpillReg, Regs.end(), [&MRI, &OtherUsedRegs](MCPhysReg Reg) {
396           return MRI.isAllocatable(Reg) && !MRI.isPhysRegUsed(Reg) &&
397                  !OtherUsedRegs[Reg];
398         });
399 
400     if (NextSpillReg == Regs.end()) { // Registers exhausted
401       Spill.FullyAllocated = false;
402       break;
403     }
404 
405     OtherUsedRegs.set(*NextSpillReg);
406     SpillRegs.push_back(*NextSpillReg);
407     Spill.Lanes[I] = *NextSpillReg++;
408   }
409 
410   return Spill.FullyAllocated;
411 }
412 
413 void SIMachineFunctionInfo::removeDeadFrameIndices(MachineFrameInfo &MFI) {
414   // The FP spill hasn't been inserted yet, so keep it around.
415   for (auto &R : SGPRToVGPRSpills) {
416     if (R.first != FramePointerSaveIndex)
417       MFI.RemoveStackObject(R.first);
418   }
419 
420   // All other SPGRs must be allocated on the default stack, so reset the stack
421   // ID.
422   for (int i = MFI.getObjectIndexBegin(), e = MFI.getObjectIndexEnd(); i != e;
423        ++i)
424     if (i != FramePointerSaveIndex)
425       MFI.setStackID(i, TargetStackID::Default);
426 
427   for (auto &R : VGPRToAGPRSpills) {
428     if (R.second.FullyAllocated)
429       MFI.RemoveStackObject(R.first);
430   }
431 }
432 
433 MCPhysReg SIMachineFunctionInfo::getNextUserSGPR() const {
434   assert(NumSystemSGPRs == 0 && "System SGPRs must be added after user SGPRs");
435   return AMDGPU::SGPR0 + NumUserSGPRs;
436 }
437 
438 MCPhysReg SIMachineFunctionInfo::getNextSystemSGPR() const {
439   return AMDGPU::SGPR0 + NumUserSGPRs + NumSystemSGPRs;
440 }
441 
442 Register
443 SIMachineFunctionInfo::getGITPtrLoReg(const MachineFunction &MF) const {
444   const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
445   if (!ST.isAmdPalOS())
446     return Register();
447   Register GitPtrLo = AMDGPU::SGPR0; // Low GIT address passed in
448   if (ST.hasMergedShaders()) {
449     switch (MF.getFunction().getCallingConv()) {
450     case CallingConv::AMDGPU_HS:
451     case CallingConv::AMDGPU_GS:
452       // Low GIT address is passed in s8 rather than s0 for an LS+HS or
453       // ES+GS merged shader on gfx9+.
454       GitPtrLo = AMDGPU::SGPR8;
455       return GitPtrLo;
456     default:
457       return GitPtrLo;
458     }
459   }
460   return GitPtrLo;
461 }
462 
463 static yaml::StringValue regToString(Register Reg,
464                                      const TargetRegisterInfo &TRI) {
465   yaml::StringValue Dest;
466   {
467     raw_string_ostream OS(Dest.Value);
468     OS << printReg(Reg, &TRI);
469   }
470   return Dest;
471 }
472 
473 static Optional<yaml::SIArgumentInfo>
474 convertArgumentInfo(const AMDGPUFunctionArgInfo &ArgInfo,
475                     const TargetRegisterInfo &TRI) {
476   yaml::SIArgumentInfo AI;
477 
478   auto convertArg = [&](Optional<yaml::SIArgument> &A,
479                         const ArgDescriptor &Arg) {
480     if (!Arg)
481       return false;
482 
483     // Create a register or stack argument.
484     yaml::SIArgument SA = yaml::SIArgument::createArgument(Arg.isRegister());
485     if (Arg.isRegister()) {
486       raw_string_ostream OS(SA.RegisterName.Value);
487       OS << printReg(Arg.getRegister(), &TRI);
488     } else
489       SA.StackOffset = Arg.getStackOffset();
490     // Check and update the optional mask.
491     if (Arg.isMasked())
492       SA.Mask = Arg.getMask();
493 
494     A = SA;
495     return true;
496   };
497 
498   bool Any = false;
499   Any |= convertArg(AI.PrivateSegmentBuffer, ArgInfo.PrivateSegmentBuffer);
500   Any |= convertArg(AI.DispatchPtr, ArgInfo.DispatchPtr);
501   Any |= convertArg(AI.QueuePtr, ArgInfo.QueuePtr);
502   Any |= convertArg(AI.KernargSegmentPtr, ArgInfo.KernargSegmentPtr);
503   Any |= convertArg(AI.DispatchID, ArgInfo.DispatchID);
504   Any |= convertArg(AI.FlatScratchInit, ArgInfo.FlatScratchInit);
505   Any |= convertArg(AI.PrivateSegmentSize, ArgInfo.PrivateSegmentSize);
506   Any |= convertArg(AI.WorkGroupIDX, ArgInfo.WorkGroupIDX);
507   Any |= convertArg(AI.WorkGroupIDY, ArgInfo.WorkGroupIDY);
508   Any |= convertArg(AI.WorkGroupIDZ, ArgInfo.WorkGroupIDZ);
509   Any |= convertArg(AI.WorkGroupInfo, ArgInfo.WorkGroupInfo);
510   Any |= convertArg(AI.PrivateSegmentWaveByteOffset,
511                     ArgInfo.PrivateSegmentWaveByteOffset);
512   Any |= convertArg(AI.ImplicitArgPtr, ArgInfo.ImplicitArgPtr);
513   Any |= convertArg(AI.ImplicitBufferPtr, ArgInfo.ImplicitBufferPtr);
514   Any |= convertArg(AI.WorkItemIDX, ArgInfo.WorkItemIDX);
515   Any |= convertArg(AI.WorkItemIDY, ArgInfo.WorkItemIDY);
516   Any |= convertArg(AI.WorkItemIDZ, ArgInfo.WorkItemIDZ);
517 
518   if (Any)
519     return AI;
520 
521   return None;
522 }
523 
524 yaml::SIMachineFunctionInfo::SIMachineFunctionInfo(
525   const llvm::SIMachineFunctionInfo& MFI,
526   const TargetRegisterInfo &TRI)
527   : ExplicitKernArgSize(MFI.getExplicitKernArgSize()),
528     MaxKernArgAlign(MFI.getMaxKernArgAlign()),
529     LDSSize(MFI.getLDSSize()),
530     IsEntryFunction(MFI.isEntryFunction()),
531     NoSignedZerosFPMath(MFI.hasNoSignedZerosFPMath()),
532     MemoryBound(MFI.isMemoryBound()),
533     WaveLimiter(MFI.needsWaveLimiter()),
534     HighBitsOf32BitAddress(MFI.get32BitAddressHighBits()),
535     ScratchRSrcReg(regToString(MFI.getScratchRSrcReg(), TRI)),
536     FrameOffsetReg(regToString(MFI.getFrameOffsetReg(), TRI)),
537     StackPtrOffsetReg(regToString(MFI.getStackPtrOffsetReg(), TRI)),
538     ArgInfo(convertArgumentInfo(MFI.getArgInfo(), TRI)),
539     Mode(MFI.getMode()) {}
540 
541 void yaml::SIMachineFunctionInfo::mappingImpl(yaml::IO &YamlIO) {
542   MappingTraits<SIMachineFunctionInfo>::mapping(YamlIO, *this);
543 }
544 
545 bool SIMachineFunctionInfo::initializeBaseYamlFields(
546   const yaml::SIMachineFunctionInfo &YamlMFI) {
547   ExplicitKernArgSize = YamlMFI.ExplicitKernArgSize;
548   MaxKernArgAlign = assumeAligned(YamlMFI.MaxKernArgAlign);
549   LDSSize = YamlMFI.LDSSize;
550   HighBitsOf32BitAddress = YamlMFI.HighBitsOf32BitAddress;
551   IsEntryFunction = YamlMFI.IsEntryFunction;
552   NoSignedZerosFPMath = YamlMFI.NoSignedZerosFPMath;
553   MemoryBound = YamlMFI.MemoryBound;
554   WaveLimiter = YamlMFI.WaveLimiter;
555   return false;
556 }
557