1 //===- SIMachineFunctionInfo.cpp - SI Machine Function Info ---------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #include "SIMachineFunctionInfo.h"
10 #include "AMDGPUTargetMachine.h"
11 
12 #define MAX_LANES 64
13 
14 using namespace llvm;
15 
16 SIMachineFunctionInfo::SIMachineFunctionInfo(const MachineFunction &MF)
17   : AMDGPUMachineFunction(MF),
18     PrivateSegmentBuffer(false),
19     DispatchPtr(false),
20     QueuePtr(false),
21     KernargSegmentPtr(false),
22     DispatchID(false),
23     FlatScratchInit(false),
24     WorkGroupIDX(false),
25     WorkGroupIDY(false),
26     WorkGroupIDZ(false),
27     WorkGroupInfo(false),
28     PrivateSegmentWaveByteOffset(false),
29     WorkItemIDX(false),
30     WorkItemIDY(false),
31     WorkItemIDZ(false),
32     ImplicitBufferPtr(false),
33     ImplicitArgPtr(false),
34     GITPtrHigh(0xffffffff),
35     HighBitsOf32BitAddress(0),
36     GDSSize(0) {
37   const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
38   const Function &F = MF.getFunction();
39   FlatWorkGroupSizes = ST.getFlatWorkGroupSizes(F);
40   WavesPerEU = ST.getWavesPerEU(F);
41 
42   Occupancy = ST.computeOccupancy(F, getLDSSize());
43   CallingConv::ID CC = F.getCallingConv();
44 
45   // FIXME: Should have analysis or something rather than attribute to detect
46   // calls.
47   const bool HasCalls = F.hasFnAttribute("amdgpu-calls");
48 
49   // Enable all kernel inputs if we have the fixed ABI. Don't bother if we don't
50   // have any calls.
51   const bool UseFixedABI = AMDGPUTargetMachine::EnableFixedFunctionABI &&
52                            CC != CallingConv::AMDGPU_Gfx &&
53                            (!isEntryFunction() || HasCalls);
54 
55   if (CC == CallingConv::AMDGPU_KERNEL || CC == CallingConv::SPIR_KERNEL) {
56     if (!F.arg_empty())
57       KernargSegmentPtr = true;
58     WorkGroupIDX = true;
59     WorkItemIDX = true;
60   } else if (CC == CallingConv::AMDGPU_PS) {
61     PSInputAddr = AMDGPU::getInitialPSInputAddr(F);
62   }
63 
64   if (!isEntryFunction()) {
65     if (UseFixedABI)
66       ArgInfo = AMDGPUArgumentUsageInfo::FixedABIFunctionInfo;
67 
68     // TODO: Pick a high register, and shift down, similar to a kernel.
69     FrameOffsetReg = AMDGPU::SGPR33;
70     StackPtrOffsetReg = AMDGPU::SGPR32;
71 
72     if (!ST.enableFlatScratch()) {
73       // Non-entry functions have no special inputs for now, other registers
74       // required for scratch access.
75       ScratchRSrcReg = AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3;
76 
77       ArgInfo.PrivateSegmentBuffer =
78         ArgDescriptor::createRegister(ScratchRSrcReg);
79     }
80 
81     if (F.hasFnAttribute("amdgpu-implicitarg-ptr"))
82       ImplicitArgPtr = true;
83   } else {
84     if (F.hasFnAttribute("amdgpu-implicitarg-ptr")) {
85       KernargSegmentPtr = true;
86       MaxKernArgAlign = std::max(ST.getAlignmentForImplicitArgPtr(),
87                                  MaxKernArgAlign);
88     }
89   }
90 
91   if (UseFixedABI) {
92     WorkGroupIDX = true;
93     WorkGroupIDY = true;
94     WorkGroupIDZ = true;
95     WorkItemIDX = true;
96     WorkItemIDY = true;
97     WorkItemIDZ = true;
98     ImplicitArgPtr = true;
99   } else {
100     if (F.hasFnAttribute("amdgpu-work-group-id-x"))
101       WorkGroupIDX = true;
102 
103     if (F.hasFnAttribute("amdgpu-work-group-id-y"))
104       WorkGroupIDY = true;
105 
106     if (F.hasFnAttribute("amdgpu-work-group-id-z"))
107       WorkGroupIDZ = true;
108 
109     if (F.hasFnAttribute("amdgpu-work-item-id-x"))
110       WorkItemIDX = true;
111 
112     if (F.hasFnAttribute("amdgpu-work-item-id-y"))
113       WorkItemIDY = true;
114 
115     if (F.hasFnAttribute("amdgpu-work-item-id-z"))
116       WorkItemIDZ = true;
117   }
118 
119   bool HasStackObjects = F.hasFnAttribute("amdgpu-stack-objects");
120   if (isEntryFunction()) {
121     // X, XY, and XYZ are the only supported combinations, so make sure Y is
122     // enabled if Z is.
123     if (WorkItemIDZ)
124       WorkItemIDY = true;
125 
126     PrivateSegmentWaveByteOffset = true;
127 
128     // HS and GS always have the scratch wave offset in SGPR5 on GFX9.
129     if (ST.getGeneration() >= AMDGPUSubtarget::GFX9 &&
130         (CC == CallingConv::AMDGPU_HS || CC == CallingConv::AMDGPU_GS))
131       ArgInfo.PrivateSegmentWaveByteOffset =
132           ArgDescriptor::createRegister(AMDGPU::SGPR5);
133   }
134 
135   bool isAmdHsaOrMesa = ST.isAmdHsaOrMesa(F);
136   if (isAmdHsaOrMesa) {
137     if (!ST.enableFlatScratch())
138       PrivateSegmentBuffer = true;
139 
140     if (UseFixedABI) {
141       DispatchPtr = true;
142       QueuePtr = true;
143 
144       // FIXME: We don't need this?
145       DispatchID = true;
146     } else {
147       if (F.hasFnAttribute("amdgpu-dispatch-ptr"))
148         DispatchPtr = true;
149 
150       if (F.hasFnAttribute("amdgpu-queue-ptr"))
151         QueuePtr = true;
152 
153       if (F.hasFnAttribute("amdgpu-dispatch-id"))
154         DispatchID = true;
155     }
156   } else if (ST.isMesaGfxShader(F)) {
157     ImplicitBufferPtr = true;
158   }
159 
160   if (UseFixedABI || F.hasFnAttribute("amdgpu-kernarg-segment-ptr"))
161     KernargSegmentPtr = true;
162 
163   if (ST.hasFlatAddressSpace() && isEntryFunction() &&
164       (isAmdHsaOrMesa || ST.enableFlatScratch())) {
165     // TODO: This could be refined a lot. The attribute is a poor way of
166     // detecting calls or stack objects that may require it before argument
167     // lowering.
168     if (HasCalls || HasStackObjects || ST.enableFlatScratch())
169       FlatScratchInit = true;
170   }
171 
172   Attribute A = F.getFnAttribute("amdgpu-git-ptr-high");
173   StringRef S = A.getValueAsString();
174   if (!S.empty())
175     S.consumeInteger(0, GITPtrHigh);
176 
177   A = F.getFnAttribute("amdgpu-32bit-address-high-bits");
178   S = A.getValueAsString();
179   if (!S.empty())
180     S.consumeInteger(0, HighBitsOf32BitAddress);
181 
182   S = F.getFnAttribute("amdgpu-gds-size").getValueAsString();
183   if (!S.empty())
184     S.consumeInteger(0, GDSSize);
185 }
186 
187 void SIMachineFunctionInfo::limitOccupancy(const MachineFunction &MF) {
188   limitOccupancy(getMaxWavesPerEU());
189   const GCNSubtarget& ST = MF.getSubtarget<GCNSubtarget>();
190   limitOccupancy(ST.getOccupancyWithLocalMemSize(getLDSSize(),
191                  MF.getFunction()));
192 }
193 
194 Register SIMachineFunctionInfo::addPrivateSegmentBuffer(
195   const SIRegisterInfo &TRI) {
196   ArgInfo.PrivateSegmentBuffer =
197     ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
198     getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SGPR_128RegClass));
199   NumUserSGPRs += 4;
200   return ArgInfo.PrivateSegmentBuffer.getRegister();
201 }
202 
203 Register SIMachineFunctionInfo::addDispatchPtr(const SIRegisterInfo &TRI) {
204   ArgInfo.DispatchPtr = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
205     getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
206   NumUserSGPRs += 2;
207   return ArgInfo.DispatchPtr.getRegister();
208 }
209 
210 Register SIMachineFunctionInfo::addQueuePtr(const SIRegisterInfo &TRI) {
211   ArgInfo.QueuePtr = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
212     getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
213   NumUserSGPRs += 2;
214   return ArgInfo.QueuePtr.getRegister();
215 }
216 
217 Register SIMachineFunctionInfo::addKernargSegmentPtr(const SIRegisterInfo &TRI) {
218   ArgInfo.KernargSegmentPtr
219     = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
220     getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
221   NumUserSGPRs += 2;
222   return ArgInfo.KernargSegmentPtr.getRegister();
223 }
224 
225 Register SIMachineFunctionInfo::addDispatchID(const SIRegisterInfo &TRI) {
226   ArgInfo.DispatchID = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
227     getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
228   NumUserSGPRs += 2;
229   return ArgInfo.DispatchID.getRegister();
230 }
231 
232 Register SIMachineFunctionInfo::addFlatScratchInit(const SIRegisterInfo &TRI) {
233   ArgInfo.FlatScratchInit = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
234     getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
235   NumUserSGPRs += 2;
236   return ArgInfo.FlatScratchInit.getRegister();
237 }
238 
239 Register SIMachineFunctionInfo::addImplicitBufferPtr(const SIRegisterInfo &TRI) {
240   ArgInfo.ImplicitBufferPtr = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
241     getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
242   NumUserSGPRs += 2;
243   return ArgInfo.ImplicitBufferPtr.getRegister();
244 }
245 
246 bool SIMachineFunctionInfo::isCalleeSavedReg(const MCPhysReg *CSRegs,
247                                              MCPhysReg Reg) {
248   for (unsigned I = 0; CSRegs[I]; ++I) {
249     if (CSRegs[I] == Reg)
250       return true;
251   }
252 
253   return false;
254 }
255 
256 /// \p returns true if \p NumLanes slots are available in VGPRs already used for
257 /// SGPR spilling.
258 //
259 // FIXME: This only works after processFunctionBeforeFrameFinalized
260 bool SIMachineFunctionInfo::haveFreeLanesForSGPRSpill(const MachineFunction &MF,
261                                                       unsigned NumNeed) const {
262   const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
263   unsigned WaveSize = ST.getWavefrontSize();
264   return NumVGPRSpillLanes + NumNeed <= WaveSize * SpillVGPRs.size();
265 }
266 
267 /// Reserve a slice of a VGPR to support spilling for FrameIndex \p FI.
268 bool SIMachineFunctionInfo::allocateSGPRSpillToVGPR(MachineFunction &MF,
269                                                     int FI) {
270   std::vector<SpilledReg> &SpillLanes = SGPRToVGPRSpills[FI];
271 
272   // This has already been allocated.
273   if (!SpillLanes.empty())
274     return true;
275 
276   const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
277   const SIRegisterInfo *TRI = ST.getRegisterInfo();
278   MachineFrameInfo &FrameInfo = MF.getFrameInfo();
279   MachineRegisterInfo &MRI = MF.getRegInfo();
280   unsigned WaveSize = ST.getWavefrontSize();
281   SIMachineFunctionInfo *FuncInfo = MF.getInfo<SIMachineFunctionInfo>();
282 
283   unsigned Size = FrameInfo.getObjectSize(FI);
284   unsigned NumLanes = Size / 4;
285 
286   if (NumLanes > WaveSize)
287     return false;
288 
289   assert(Size >= 4 && "invalid sgpr spill size");
290   assert(TRI->spillSGPRToVGPR() && "not spilling SGPRs to VGPRs");
291 
292   // Make sure to handle the case where a wide SGPR spill may span between two
293   // VGPRs.
294   for (unsigned I = 0; I < NumLanes; ++I, ++NumVGPRSpillLanes) {
295     Register LaneVGPR;
296     unsigned VGPRIndex = (NumVGPRSpillLanes % WaveSize);
297 
298     // Reserve a VGPR (when NumVGPRSpillLanes = 0, WaveSize, 2*WaveSize, ..) and
299     // when one of the two conditions is true:
300     // 1. One reserved VGPR being tracked by VGPRReservedForSGPRSpill is not yet
301     // reserved.
302     // 2. All spill lanes of reserved VGPR(s) are full and another spill lane is
303     // required.
304     if (FuncInfo->VGPRReservedForSGPRSpill && NumVGPRSpillLanes < WaveSize) {
305       assert(FuncInfo->VGPRReservedForSGPRSpill == SpillVGPRs.back().VGPR);
306       LaneVGPR = FuncInfo->VGPRReservedForSGPRSpill;
307     } else if (VGPRIndex == 0) {
308       LaneVGPR = TRI->findUnusedRegister(MRI, &AMDGPU::VGPR_32RegClass, MF);
309       if (LaneVGPR == AMDGPU::NoRegister) {
310         // We have no VGPRs left for spilling SGPRs. Reset because we will not
311         // partially spill the SGPR to VGPRs.
312         SGPRToVGPRSpills.erase(FI);
313         NumVGPRSpillLanes -= I;
314         return false;
315       }
316 
317       Optional<int> SpillFI;
318       // We need to preserve inactive lanes, so always save, even caller-save
319       // registers.
320       if (!isEntryFunction()) {
321         SpillFI = FrameInfo.CreateSpillStackObject(4, Align(4));
322       }
323 
324       SpillVGPRs.push_back(SGPRSpillVGPR(LaneVGPR, SpillFI));
325 
326       // Add this register as live-in to all blocks to avoid machine verifer
327       // complaining about use of an undefined physical register.
328       for (MachineBasicBlock &BB : MF)
329         BB.addLiveIn(LaneVGPR);
330     } else {
331       LaneVGPR = SpillVGPRs.back().VGPR;
332     }
333 
334     SpillLanes.push_back(SpilledReg(LaneVGPR, VGPRIndex));
335   }
336 
337   return true;
338 }
339 
340 /// Reserve a VGPR for spilling of SGPRs
341 bool SIMachineFunctionInfo::reserveVGPRforSGPRSpills(MachineFunction &MF) {
342   const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
343   const SIRegisterInfo *TRI = ST.getRegisterInfo();
344   SIMachineFunctionInfo *FuncInfo = MF.getInfo<SIMachineFunctionInfo>();
345 
346   Register LaneVGPR = TRI->findUnusedRegister(
347       MF.getRegInfo(), &AMDGPU::VGPR_32RegClass, MF, true);
348   if (LaneVGPR == Register())
349     return false;
350   SpillVGPRs.push_back(SGPRSpillVGPR(LaneVGPR, None));
351   FuncInfo->VGPRReservedForSGPRSpill = LaneVGPR;
352   return true;
353 }
354 
355 /// Reserve AGPRs or VGPRs to support spilling for FrameIndex \p FI.
356 /// Either AGPR is spilled to VGPR to vice versa.
357 /// Returns true if a \p FI can be eliminated completely.
358 bool SIMachineFunctionInfo::allocateVGPRSpillToAGPR(MachineFunction &MF,
359                                                     int FI,
360                                                     bool isAGPRtoVGPR) {
361   MachineRegisterInfo &MRI = MF.getRegInfo();
362   MachineFrameInfo &FrameInfo = MF.getFrameInfo();
363   const GCNSubtarget &ST =  MF.getSubtarget<GCNSubtarget>();
364 
365   assert(ST.hasMAIInsts() && FrameInfo.isSpillSlotObjectIndex(FI));
366 
367   auto &Spill = VGPRToAGPRSpills[FI];
368 
369   // This has already been allocated.
370   if (!Spill.Lanes.empty())
371     return Spill.FullyAllocated;
372 
373   unsigned Size = FrameInfo.getObjectSize(FI);
374   unsigned NumLanes = Size / 4;
375   Spill.Lanes.resize(NumLanes, AMDGPU::NoRegister);
376 
377   const TargetRegisterClass &RC =
378       isAGPRtoVGPR ? AMDGPU::VGPR_32RegClass : AMDGPU::AGPR_32RegClass;
379   auto Regs = RC.getRegisters();
380 
381   auto &SpillRegs = isAGPRtoVGPR ? SpillAGPR : SpillVGPR;
382   const SIRegisterInfo *TRI = ST.getRegisterInfo();
383   Spill.FullyAllocated = true;
384 
385   // FIXME: Move allocation logic out of MachineFunctionInfo and initialize
386   // once.
387   BitVector OtherUsedRegs;
388   OtherUsedRegs.resize(TRI->getNumRegs());
389 
390   const uint32_t *CSRMask =
391       TRI->getCallPreservedMask(MF, MF.getFunction().getCallingConv());
392   if (CSRMask)
393     OtherUsedRegs.setBitsInMask(CSRMask);
394 
395   // TODO: Should include register tuples, but doesn't matter with current
396   // usage.
397   for (MCPhysReg Reg : SpillAGPR)
398     OtherUsedRegs.set(Reg);
399   for (MCPhysReg Reg : SpillVGPR)
400     OtherUsedRegs.set(Reg);
401 
402   SmallVectorImpl<MCPhysReg>::const_iterator NextSpillReg = Regs.begin();
403   for (unsigned I = 0; I < NumLanes; ++I) {
404     NextSpillReg = std::find_if(
405         NextSpillReg, Regs.end(), [&MRI, &OtherUsedRegs](MCPhysReg Reg) {
406           return MRI.isAllocatable(Reg) && !MRI.isPhysRegUsed(Reg) &&
407                  !OtherUsedRegs[Reg];
408         });
409 
410     if (NextSpillReg == Regs.end()) { // Registers exhausted
411       Spill.FullyAllocated = false;
412       break;
413     }
414 
415     OtherUsedRegs.set(*NextSpillReg);
416     SpillRegs.push_back(*NextSpillReg);
417     Spill.Lanes[I] = *NextSpillReg++;
418   }
419 
420   return Spill.FullyAllocated;
421 }
422 
423 void SIMachineFunctionInfo::removeDeadFrameIndices(MachineFrameInfo &MFI) {
424   // The FP & BP spills haven't been inserted yet, so keep them around.
425   for (auto &R : SGPRToVGPRSpills) {
426     if (R.first != FramePointerSaveIndex && R.first != BasePointerSaveIndex)
427       MFI.RemoveStackObject(R.first);
428   }
429 
430   // All other SPGRs must be allocated on the default stack, so reset the stack
431   // ID.
432   for (int i = MFI.getObjectIndexBegin(), e = MFI.getObjectIndexEnd(); i != e;
433        ++i)
434     if (i != FramePointerSaveIndex && i != BasePointerSaveIndex)
435       MFI.setStackID(i, TargetStackID::Default);
436 
437   for (auto &R : VGPRToAGPRSpills) {
438     if (R.second.FullyAllocated)
439       MFI.RemoveStackObject(R.first);
440   }
441 }
442 
443 int SIMachineFunctionInfo::getScavengeFI(MachineFrameInfo &MFI,
444                                          const SIRegisterInfo &TRI) {
445   if (ScavengeFI)
446     return *ScavengeFI;
447   if (isEntryFunction()) {
448     ScavengeFI = MFI.CreateFixedObject(
449         TRI.getSpillSize(AMDGPU::SGPR_32RegClass), 0, false);
450   } else {
451     ScavengeFI = MFI.CreateStackObject(
452         TRI.getSpillSize(AMDGPU::SGPR_32RegClass),
453         TRI.getSpillAlign(AMDGPU::SGPR_32RegClass), false);
454   }
455   return *ScavengeFI;
456 }
457 
458 MCPhysReg SIMachineFunctionInfo::getNextUserSGPR() const {
459   assert(NumSystemSGPRs == 0 && "System SGPRs must be added after user SGPRs");
460   return AMDGPU::SGPR0 + NumUserSGPRs;
461 }
462 
463 MCPhysReg SIMachineFunctionInfo::getNextSystemSGPR() const {
464   return AMDGPU::SGPR0 + NumUserSGPRs + NumSystemSGPRs;
465 }
466 
467 Register
468 SIMachineFunctionInfo::getGITPtrLoReg(const MachineFunction &MF) const {
469   const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
470   if (!ST.isAmdPalOS())
471     return Register();
472   Register GitPtrLo = AMDGPU::SGPR0; // Low GIT address passed in
473   if (ST.hasMergedShaders()) {
474     switch (MF.getFunction().getCallingConv()) {
475     case CallingConv::AMDGPU_HS:
476     case CallingConv::AMDGPU_GS:
477       // Low GIT address is passed in s8 rather than s0 for an LS+HS or
478       // ES+GS merged shader on gfx9+.
479       GitPtrLo = AMDGPU::SGPR8;
480       return GitPtrLo;
481     default:
482       return GitPtrLo;
483     }
484   }
485   return GitPtrLo;
486 }
487 
488 static yaml::StringValue regToString(Register Reg,
489                                      const TargetRegisterInfo &TRI) {
490   yaml::StringValue Dest;
491   {
492     raw_string_ostream OS(Dest.Value);
493     OS << printReg(Reg, &TRI);
494   }
495   return Dest;
496 }
497 
498 static Optional<yaml::SIArgumentInfo>
499 convertArgumentInfo(const AMDGPUFunctionArgInfo &ArgInfo,
500                     const TargetRegisterInfo &TRI) {
501   yaml::SIArgumentInfo AI;
502 
503   auto convertArg = [&](Optional<yaml::SIArgument> &A,
504                         const ArgDescriptor &Arg) {
505     if (!Arg)
506       return false;
507 
508     // Create a register or stack argument.
509     yaml::SIArgument SA = yaml::SIArgument::createArgument(Arg.isRegister());
510     if (Arg.isRegister()) {
511       raw_string_ostream OS(SA.RegisterName.Value);
512       OS << printReg(Arg.getRegister(), &TRI);
513     } else
514       SA.StackOffset = Arg.getStackOffset();
515     // Check and update the optional mask.
516     if (Arg.isMasked())
517       SA.Mask = Arg.getMask();
518 
519     A = SA;
520     return true;
521   };
522 
523   bool Any = false;
524   Any |= convertArg(AI.PrivateSegmentBuffer, ArgInfo.PrivateSegmentBuffer);
525   Any |= convertArg(AI.DispatchPtr, ArgInfo.DispatchPtr);
526   Any |= convertArg(AI.QueuePtr, ArgInfo.QueuePtr);
527   Any |= convertArg(AI.KernargSegmentPtr, ArgInfo.KernargSegmentPtr);
528   Any |= convertArg(AI.DispatchID, ArgInfo.DispatchID);
529   Any |= convertArg(AI.FlatScratchInit, ArgInfo.FlatScratchInit);
530   Any |= convertArg(AI.PrivateSegmentSize, ArgInfo.PrivateSegmentSize);
531   Any |= convertArg(AI.WorkGroupIDX, ArgInfo.WorkGroupIDX);
532   Any |= convertArg(AI.WorkGroupIDY, ArgInfo.WorkGroupIDY);
533   Any |= convertArg(AI.WorkGroupIDZ, ArgInfo.WorkGroupIDZ);
534   Any |= convertArg(AI.WorkGroupInfo, ArgInfo.WorkGroupInfo);
535   Any |= convertArg(AI.PrivateSegmentWaveByteOffset,
536                     ArgInfo.PrivateSegmentWaveByteOffset);
537   Any |= convertArg(AI.ImplicitArgPtr, ArgInfo.ImplicitArgPtr);
538   Any |= convertArg(AI.ImplicitBufferPtr, ArgInfo.ImplicitBufferPtr);
539   Any |= convertArg(AI.WorkItemIDX, ArgInfo.WorkItemIDX);
540   Any |= convertArg(AI.WorkItemIDY, ArgInfo.WorkItemIDY);
541   Any |= convertArg(AI.WorkItemIDZ, ArgInfo.WorkItemIDZ);
542 
543   if (Any)
544     return AI;
545 
546   return None;
547 }
548 
549 yaml::SIMachineFunctionInfo::SIMachineFunctionInfo(
550     const llvm::SIMachineFunctionInfo &MFI, const TargetRegisterInfo &TRI)
551     : ExplicitKernArgSize(MFI.getExplicitKernArgSize()),
552       MaxKernArgAlign(MFI.getMaxKernArgAlign()), LDSSize(MFI.getLDSSize()),
553       DynLDSAlign(MFI.getDynLDSAlign()), IsEntryFunction(MFI.isEntryFunction()),
554       NoSignedZerosFPMath(MFI.hasNoSignedZerosFPMath()),
555       MemoryBound(MFI.isMemoryBound()), WaveLimiter(MFI.needsWaveLimiter()),
556       HasSpilledSGPRs(MFI.hasSpilledSGPRs()),
557       HasSpilledVGPRs(MFI.hasSpilledVGPRs()),
558       HighBitsOf32BitAddress(MFI.get32BitAddressHighBits()),
559       Occupancy(MFI.getOccupancy()),
560       ScratchRSrcReg(regToString(MFI.getScratchRSrcReg(), TRI)),
561       FrameOffsetReg(regToString(MFI.getFrameOffsetReg(), TRI)),
562       StackPtrOffsetReg(regToString(MFI.getStackPtrOffsetReg(), TRI)),
563       ArgInfo(convertArgumentInfo(MFI.getArgInfo(), TRI)), Mode(MFI.getMode()) {
564 }
565 
566 void yaml::SIMachineFunctionInfo::mappingImpl(yaml::IO &YamlIO) {
567   MappingTraits<SIMachineFunctionInfo>::mapping(YamlIO, *this);
568 }
569 
570 bool SIMachineFunctionInfo::initializeBaseYamlFields(
571   const yaml::SIMachineFunctionInfo &YamlMFI) {
572   ExplicitKernArgSize = YamlMFI.ExplicitKernArgSize;
573   MaxKernArgAlign = assumeAligned(YamlMFI.MaxKernArgAlign);
574   LDSSize = YamlMFI.LDSSize;
575   DynLDSAlign = YamlMFI.DynLDSAlign;
576   HighBitsOf32BitAddress = YamlMFI.HighBitsOf32BitAddress;
577   Occupancy = YamlMFI.Occupancy;
578   IsEntryFunction = YamlMFI.IsEntryFunction;
579   NoSignedZerosFPMath = YamlMFI.NoSignedZerosFPMath;
580   MemoryBound = YamlMFI.MemoryBound;
581   WaveLimiter = YamlMFI.WaveLimiter;
582   HasSpilledSGPRs = YamlMFI.HasSpilledSGPRs;
583   HasSpilledVGPRs = YamlMFI.HasSpilledVGPRs;
584   return false;
585 }
586 
587 // Remove VGPR which was reserved for SGPR spills if there are no spilled SGPRs
588 bool SIMachineFunctionInfo::removeVGPRForSGPRSpill(Register ReservedVGPR,
589                                                    MachineFunction &MF) {
590   for (auto *i = SpillVGPRs.begin(); i < SpillVGPRs.end(); i++) {
591     if (i->VGPR == ReservedVGPR) {
592       SpillVGPRs.erase(i);
593 
594       for (MachineBasicBlock &MBB : MF) {
595         MBB.removeLiveIn(ReservedVGPR);
596         MBB.sortUniqueLiveIns();
597       }
598       this->VGPRReservedForSGPRSpill = AMDGPU::NoRegister;
599       return true;
600     }
601   }
602   return false;
603 }
604