1 //===-- SILowerI1Copies.cpp - Lower I1 Copies -----------------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 /// i1 values are usually inserted by the CFG Structurize pass and they are
9 /// unique in that they can be copied from VALU to SALU registers.
10 /// This is not possible for any other value type.  Since there are no
11 /// MOV instructions for i1, we to use V_CMP_* and V_CNDMASK to move the i1.
12 ///
13 //===----------------------------------------------------------------------===//
14 //
15 
16 #define DEBUG_TYPE "si-i1-copies"
17 #include "AMDGPU.h"
18 #include "AMDGPUSubtarget.h"
19 #include "SIInstrInfo.h"
20 #include "Utils/AMDGPULaneDominator.h"
21 #include "llvm/CodeGen/LiveIntervals.h"
22 #include "llvm/CodeGen/MachineFunctionPass.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/IR/Function.h"
26 #include "llvm/IR/LLVMContext.h"
27 #include "llvm/Support/Debug.h"
28 #include "llvm/Target/TargetMachine.h"
29 
30 using namespace llvm;
31 
32 namespace {
33 
34 class SILowerI1Copies : public MachineFunctionPass {
35 public:
36   static char ID;
37 
38 public:
39   SILowerI1Copies() : MachineFunctionPass(ID) {
40     initializeSILowerI1CopiesPass(*PassRegistry::getPassRegistry());
41   }
42 
43   bool runOnMachineFunction(MachineFunction &MF) override;
44 
45   StringRef getPassName() const override { return "SI Lower i1 Copies"; }
46 
47   void getAnalysisUsage(AnalysisUsage &AU) const override {
48     AU.setPreservesCFG();
49     MachineFunctionPass::getAnalysisUsage(AU);
50   }
51 };
52 
53 } // End anonymous namespace.
54 
55 INITIALIZE_PASS(SILowerI1Copies, DEBUG_TYPE,
56                 "SI Lower i1 Copies", false, false)
57 
58 char SILowerI1Copies::ID = 0;
59 
60 char &llvm::SILowerI1CopiesID = SILowerI1Copies::ID;
61 
62 FunctionPass *llvm::createSILowerI1CopiesPass() {
63   return new SILowerI1Copies();
64 }
65 
66 bool SILowerI1Copies::runOnMachineFunction(MachineFunction &MF) {
67   MachineRegisterInfo &MRI = MF.getRegInfo();
68   const SISubtarget &ST = MF.getSubtarget<SISubtarget>();
69   const SIInstrInfo *TII = ST.getInstrInfo();
70   const TargetRegisterInfo *TRI = &TII->getRegisterInfo();
71 
72   std::vector<unsigned> I1Defs;
73 
74   for (MachineFunction::iterator BI = MF.begin(), BE = MF.end();
75                                                   BI != BE; ++BI) {
76 
77     MachineBasicBlock &MBB = *BI;
78     MachineBasicBlock::iterator I, Next;
79     for (I = MBB.begin(); I != MBB.end(); I = Next) {
80       Next = std::next(I);
81       MachineInstr &MI = *I;
82 
83       if (MI.getOpcode() == AMDGPU::IMPLICIT_DEF) {
84         unsigned Reg = MI.getOperand(0).getReg();
85         const TargetRegisterClass *RC = MRI.getRegClass(Reg);
86         if (RC == &AMDGPU::VReg_1RegClass)
87           MRI.setRegClass(Reg, &AMDGPU::SReg_64RegClass);
88         continue;
89       }
90 
91       if (MI.getOpcode() != AMDGPU::COPY)
92         continue;
93 
94       const MachineOperand &Dst = MI.getOperand(0);
95       const MachineOperand &Src = MI.getOperand(1);
96 
97       if (!TargetRegisterInfo::isVirtualRegister(Src.getReg()) ||
98           !TargetRegisterInfo::isVirtualRegister(Dst.getReg()))
99         continue;
100 
101       const TargetRegisterClass *DstRC = MRI.getRegClass(Dst.getReg());
102       const TargetRegisterClass *SrcRC = MRI.getRegClass(Src.getReg());
103 
104       DebugLoc DL = MI.getDebugLoc();
105       MachineInstr *DefInst = MRI.getUniqueVRegDef(Src.getReg());
106       if (DstRC == &AMDGPU::VReg_1RegClass &&
107           TRI->getCommonSubClass(SrcRC, &AMDGPU::SGPR_64RegClass)) {
108         I1Defs.push_back(Dst.getReg());
109 
110         if (DefInst->getOpcode() == AMDGPU::S_MOV_B64) {
111           if (DefInst->getOperand(1).isImm()) {
112             I1Defs.push_back(Dst.getReg());
113 
114             int64_t Val = DefInst->getOperand(1).getImm();
115             assert(Val == 0 || Val == -1);
116 
117             BuildMI(MBB, &MI, DL, TII->get(AMDGPU::V_MOV_B32_e32))
118                 .add(Dst)
119                 .addImm(Val);
120             MI.eraseFromParent();
121             continue;
122           }
123         }
124 
125         unsigned int TmpSrc = MRI.createVirtualRegister(&AMDGPU::SReg_64_XEXECRegClass);
126         BuildMI(MBB, &MI, DL, TII->get(AMDGPU::COPY), TmpSrc)
127             .add(Src);
128         BuildMI(MBB, &MI, DL, TII->get(AMDGPU::V_CNDMASK_B32_e64))
129             .add(Dst)
130             .addImm(0)
131             .addImm(-1)
132             .addReg(TmpSrc);
133         MI.eraseFromParent();
134       } else if (TRI->getCommonSubClass(DstRC, &AMDGPU::SGPR_64RegClass) &&
135                  SrcRC == &AMDGPU::VReg_1RegClass) {
136         if (DefInst->getOpcode() == AMDGPU::V_CNDMASK_B32_e64 &&
137             DefInst->getOperand(1).isImm() && DefInst->getOperand(2).isImm() &&
138             DefInst->getOperand(1).getImm() == 0 &&
139             DefInst->getOperand(2).getImm() != 0 &&
140             DefInst->getOperand(3).isReg() &&
141             TargetRegisterInfo::isVirtualRegister(
142               DefInst->getOperand(3).getReg()) &&
143             TRI->getCommonSubClass(
144               MRI.getRegClass(DefInst->getOperand(3).getReg()),
145               &AMDGPU::SGPR_64RegClass) &&
146             AMDGPU::laneDominates(DefInst->getParent(), &MBB)) {
147           BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_AND_B64))
148               .add(Dst)
149               .addReg(AMDGPU::EXEC)
150               .add(DefInst->getOperand(3));
151         } else {
152           BuildMI(MBB, &MI, DL, TII->get(AMDGPU::V_CMP_NE_U32_e64))
153               .add(Dst)
154               .add(Src)
155               .addImm(0);
156         }
157         MI.eraseFromParent();
158       }
159     }
160   }
161 
162   for (unsigned Reg : I1Defs)
163     MRI.setRegClass(Reg, &AMDGPU::VGPR_32RegClass);
164 
165   return false;
166 }
167