1 //===-- SILowerI1Copies.cpp - Lower I1 Copies -----------------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 /// i1 values are usually inserted by the CFG Structurize pass and they are
9 /// unique in that they can be copied from VALU to SALU registers.
10 /// This is not possible for any other value type.  Since there are no
11 /// MOV instructions for i1, we to use V_CMP_* and V_CNDMASK to move the i1.
12 ///
13 //===----------------------------------------------------------------------===//
14 //
15 
16 #define DEBUG_TYPE "si-i1-copies"
17 #include "AMDGPU.h"
18 #include "AMDGPUSubtarget.h"
19 #include "SIInstrInfo.h"
20 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
21 #include "llvm/CodeGen/MachineFunctionPass.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 #include "llvm/IR/LLVMContext.h"
25 #include "llvm/IR/Function.h"
26 #include "llvm/Support/Debug.h"
27 #include "llvm/Target/TargetMachine.h"
28 
29 using namespace llvm;
30 
31 namespace {
32 
33 class SILowerI1Copies : public MachineFunctionPass {
34 public:
35   static char ID;
36 
37 public:
38   SILowerI1Copies() : MachineFunctionPass(ID) {
39     initializeSILowerI1CopiesPass(*PassRegistry::getPassRegistry());
40   }
41 
42   bool runOnMachineFunction(MachineFunction &MF) override;
43 
44   const char *getPassName() const override {
45     return "SI Lower i1 Copies";
46   }
47 
48   void getAnalysisUsage(AnalysisUsage &AU) const override {
49     AU.setPreservesCFG();
50     MachineFunctionPass::getAnalysisUsage(AU);
51   }
52 };
53 
54 } // End anonymous namespace.
55 
56 INITIALIZE_PASS(SILowerI1Copies, DEBUG_TYPE,
57                 "SI Lower i1 Copies", false, false)
58 
59 char SILowerI1Copies::ID = 0;
60 
61 char &llvm::SILowerI1CopiesID = SILowerI1Copies::ID;
62 
63 FunctionPass *llvm::createSILowerI1CopiesPass() {
64   return new SILowerI1Copies();
65 }
66 
67 bool SILowerI1Copies::runOnMachineFunction(MachineFunction &MF) {
68   MachineRegisterInfo &MRI = MF.getRegInfo();
69   const SIInstrInfo *TII =
70       static_cast<const SIInstrInfo *>(MF.getSubtarget().getInstrInfo());
71   const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
72   std::vector<unsigned> I1Defs;
73 
74   for (MachineFunction::iterator BI = MF.begin(), BE = MF.end();
75                                                   BI != BE; ++BI) {
76 
77     MachineBasicBlock &MBB = *BI;
78     MachineBasicBlock::iterator I, Next;
79     for (I = MBB.begin(); I != MBB.end(); I = Next) {
80       Next = std::next(I);
81       MachineInstr &MI = *I;
82 
83       if (MI.getOpcode() == AMDGPU::IMPLICIT_DEF) {
84         unsigned Reg = MI.getOperand(0).getReg();
85         const TargetRegisterClass *RC = MRI.getRegClass(Reg);
86         if (RC == &AMDGPU::VReg_1RegClass)
87           MRI.setRegClass(Reg, &AMDGPU::SReg_64RegClass);
88         continue;
89       }
90 
91       if (MI.getOpcode() != AMDGPU::COPY)
92         continue;
93 
94       const MachineOperand &Dst = MI.getOperand(0);
95       const MachineOperand &Src = MI.getOperand(1);
96 
97       if (!TargetRegisterInfo::isVirtualRegister(Src.getReg()) ||
98           !TargetRegisterInfo::isVirtualRegister(Dst.getReg()))
99         continue;
100 
101       const TargetRegisterClass *DstRC = MRI.getRegClass(Dst.getReg());
102       const TargetRegisterClass *SrcRC = MRI.getRegClass(Src.getReg());
103 
104       if (DstRC == &AMDGPU::VReg_1RegClass &&
105           TRI->getCommonSubClass(SrcRC, &AMDGPU::SGPR_64RegClass)) {
106         I1Defs.push_back(Dst.getReg());
107         DebugLoc DL = MI.getDebugLoc();
108 
109         MachineInstr *DefInst = MRI.getUniqueVRegDef(Src.getReg());
110         if (DefInst->getOpcode() == AMDGPU::S_MOV_B64) {
111           if (DefInst->getOperand(1).isImm()) {
112             I1Defs.push_back(Dst.getReg());
113 
114             int64_t Val = DefInst->getOperand(1).getImm();
115             assert(Val == 0 || Val == -1);
116 
117             BuildMI(MBB, &MI, DL, TII->get(AMDGPU::V_MOV_B32_e32))
118               .addOperand(Dst)
119               .addImm(Val);
120             MI.eraseFromParent();
121             continue;
122           }
123         }
124 
125         BuildMI(MBB, &MI, DL, TII->get(AMDGPU::V_CNDMASK_B32_e64))
126           .addOperand(Dst)
127           .addImm(0)
128           .addImm(-1)
129           .addOperand(Src);
130         MI.eraseFromParent();
131       } else if (TRI->getCommonSubClass(DstRC, &AMDGPU::SGPR_64RegClass) &&
132                  SrcRC == &AMDGPU::VReg_1RegClass) {
133         BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(AMDGPU::V_CMP_NE_I32_e64))
134           .addOperand(Dst)
135           .addOperand(Src)
136           .addImm(0);
137         MI.eraseFromParent();
138       }
139     }
140   }
141 
142   for (unsigned Reg : I1Defs)
143     MRI.setRegClass(Reg, &AMDGPU::VGPR_32RegClass);
144 
145   return false;
146 }
147