1//===-- SIInstructions.td - SI Instruction Defintions ---------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// This file was originally auto-generated from a GPU register header file and 10// all the instruction definitions were originally commented out. Instructions 11// that are not yet supported remain commented out. 12//===----------------------------------------------------------------------===// 13 14class InterpSlots { 15int P0 = 2; 16int P10 = 0; 17int P20 = 1; 18} 19def INTERP : InterpSlots; 20 21def InterpSlot : Operand<i32> { 22 let PrintMethod = "printInterpSlot"; 23} 24 25def SendMsgImm : Operand<i32> { 26 let PrintMethod = "printSendMsg"; 27} 28 29def isGCN : Predicate<"Subtarget->getGeneration() " 30 ">= AMDGPUSubtarget::SOUTHERN_ISLANDS">, 31 AssemblerPredicate<"FeatureGCN">; 32def isSI : Predicate<"Subtarget->getGeneration() " 33 "== AMDGPUSubtarget::SOUTHERN_ISLANDS">, 34 AssemblerPredicate<"FeatureSouthernIslands">; 35 36 37def has16BankLDS : Predicate<"Subtarget->getLDSBankCount() == 16">; 38def has32BankLDS : Predicate<"Subtarget->getLDSBankCount() == 32">; 39 40def SWaitMatchClass : AsmOperandClass { 41 let Name = "SWaitCnt"; 42 let RenderMethod = "addImmOperands"; 43 let ParserMethod = "parseSWaitCntOps"; 44} 45 46def WAIT_FLAG : InstFlag<"printWaitFlag"> { 47 let ParserMatchClass = SWaitMatchClass; 48} 49 50let SubtargetPredicate = isGCN in { 51 52//===----------------------------------------------------------------------===// 53// EXP Instructions 54//===----------------------------------------------------------------------===// 55 56defm EXP : EXP_m; 57 58//===----------------------------------------------------------------------===// 59// SMRD Instructions 60//===----------------------------------------------------------------------===// 61 62// We are using the SGPR_32 and not the SReg_32 register class for 32-bit 63// SMRD instructions, because the SGPR_32 register class does not include M0 64// and writing to M0 from an SMRD instruction will hang the GPU. 65defm S_LOAD_DWORD : SMRD_Helper <smrd<0x00>, "s_load_dword", SReg_64, SGPR_32>; 66defm S_LOAD_DWORDX2 : SMRD_Helper <smrd<0x01>, "s_load_dwordx2", SReg_64, SReg_64>; 67defm S_LOAD_DWORDX4 : SMRD_Helper <smrd<0x02>, "s_load_dwordx4", SReg_64, SReg_128>; 68defm S_LOAD_DWORDX8 : SMRD_Helper <smrd<0x03>, "s_load_dwordx8", SReg_64, SReg_256>; 69defm S_LOAD_DWORDX16 : SMRD_Helper <smrd<0x04>, "s_load_dwordx16", SReg_64, SReg_512>; 70 71defm S_BUFFER_LOAD_DWORD : SMRD_Helper < 72 smrd<0x08>, "s_buffer_load_dword", SReg_128, SGPR_32 73>; 74 75defm S_BUFFER_LOAD_DWORDX2 : SMRD_Helper < 76 smrd<0x09>, "s_buffer_load_dwordx2", SReg_128, SReg_64 77>; 78 79defm S_BUFFER_LOAD_DWORDX4 : SMRD_Helper < 80 smrd<0x0a>, "s_buffer_load_dwordx4", SReg_128, SReg_128 81>; 82 83defm S_BUFFER_LOAD_DWORDX8 : SMRD_Helper < 84 smrd<0x0b>, "s_buffer_load_dwordx8", SReg_128, SReg_256 85>; 86 87defm S_BUFFER_LOAD_DWORDX16 : SMRD_Helper < 88 smrd<0x0c>, "s_buffer_load_dwordx16", SReg_128, SReg_512 89>; 90 91let mayStore = ? in { 92// FIXME: mayStore = ? is a workaround for tablegen bug for different 93// inferred mayStore flags for the instruction pattern vs. standalone 94// Pat. Each considers the other contradictory. 95 96defm S_MEMTIME : SMRD_Special <smrd<0x1e, 0x24>, "s_memtime", 97 (outs SReg_64:$sdst), ?, " $sdst", [(set i64:$sdst, (int_amdgcn_s_memtime))] 98>; 99} 100 101defm S_DCACHE_INV : SMRD_Inval <smrd<0x1f, 0x20>, "s_dcache_inv", 102 int_amdgcn_s_dcache_inv>; 103 104//===----------------------------------------------------------------------===// 105// SOP1 Instructions 106//===----------------------------------------------------------------------===// 107 108let isMoveImm = 1 in { 109 let isReMaterializable = 1, isAsCheapAsAMove = 1 in { 110 defm S_MOV_B32 : SOP1_32 <sop1<0x03, 0x00>, "s_mov_b32", []>; 111 defm S_MOV_B64 : SOP1_64 <sop1<0x04, 0x01>, "s_mov_b64", []>; 112 } // End isRematerializeable = 1 113 114 let Uses = [SCC] in { 115 defm S_CMOV_B32 : SOP1_32 <sop1<0x05, 0x02>, "s_cmov_b32", []>; 116 defm S_CMOV_B64 : SOP1_64 <sop1<0x06, 0x03>, "s_cmov_b64", []>; 117 } // End Uses = [SCC] 118} // End isMoveImm = 1 119 120let Defs = [SCC] in { 121 defm S_NOT_B32 : SOP1_32 <sop1<0x07, 0x04>, "s_not_b32", 122 [(set i32:$sdst, (not i32:$src0))] 123 >; 124 125 defm S_NOT_B64 : SOP1_64 <sop1<0x08, 0x05>, "s_not_b64", 126 [(set i64:$sdst, (not i64:$src0))] 127 >; 128 defm S_WQM_B32 : SOP1_32 <sop1<0x09, 0x06>, "s_wqm_b32", []>; 129 defm S_WQM_B64 : SOP1_64 <sop1<0x0a, 0x07>, "s_wqm_b64", []>; 130} // End Defs = [SCC] 131 132 133defm S_BREV_B32 : SOP1_32 <sop1<0x0b, 0x08>, "s_brev_b32", 134 [(set i32:$sdst, (bitreverse i32:$src0))] 135>; 136defm S_BREV_B64 : SOP1_64 <sop1<0x0c, 0x09>, "s_brev_b64", []>; 137 138let Defs = [SCC] in { 139 defm S_BCNT0_I32_B32 : SOP1_32 <sop1<0x0d, 0x0a>, "s_bcnt0_i32_b32", []>; 140 defm S_BCNT0_I32_B64 : SOP1_32_64 <sop1<0x0e, 0x0b>, "s_bcnt0_i32_b64", []>; 141 defm S_BCNT1_I32_B32 : SOP1_32 <sop1<0x0f, 0x0c>, "s_bcnt1_i32_b32", 142 [(set i32:$sdst, (ctpop i32:$src0))] 143 >; 144 defm S_BCNT1_I32_B64 : SOP1_32_64 <sop1<0x10, 0x0d>, "s_bcnt1_i32_b64", []>; 145} // End Defs = [SCC] 146 147defm S_FF0_I32_B32 : SOP1_32 <sop1<0x11, 0x0e>, "s_ff0_i32_b32", []>; 148defm S_FF0_I32_B64 : SOP1_32_64 <sop1<0x12, 0x0f>, "s_ff0_i32_b64", []>; 149defm S_FF1_I32_B32 : SOP1_32 <sop1<0x13, 0x10>, "s_ff1_i32_b32", 150 [(set i32:$sdst, (cttz_zero_undef i32:$src0))] 151>; 152defm S_FF1_I32_B64 : SOP1_32_64 <sop1<0x14, 0x11>, "s_ff1_i32_b64", []>; 153 154defm S_FLBIT_I32_B32 : SOP1_32 <sop1<0x15, 0x12>, "s_flbit_i32_b32", 155 [(set i32:$sdst, (AMDGPUffbh_u32 i32:$src0))] 156>; 157 158defm S_FLBIT_I32_B64 : SOP1_32_64 <sop1<0x16, 0x13>, "s_flbit_i32_b64", []>; 159defm S_FLBIT_I32 : SOP1_32 <sop1<0x17, 0x14>, "s_flbit_i32", 160 [(set i32:$sdst, (int_AMDGPU_flbit_i32 i32:$src0))] 161>; 162defm S_FLBIT_I32_I64 : SOP1_32_64 <sop1<0x18, 0x15>, "s_flbit_i32_i64", []>; 163defm S_SEXT_I32_I8 : SOP1_32 <sop1<0x19, 0x16>, "s_sext_i32_i8", 164 [(set i32:$sdst, (sext_inreg i32:$src0, i8))] 165>; 166defm S_SEXT_I32_I16 : SOP1_32 <sop1<0x1a, 0x17>, "s_sext_i32_i16", 167 [(set i32:$sdst, (sext_inreg i32:$src0, i16))] 168>; 169 170defm S_BITSET0_B32 : SOP1_32 <sop1<0x1b, 0x18>, "s_bitset0_b32", []>; 171defm S_BITSET0_B64 : SOP1_64_32 <sop1<0x1c, 0x19>, "s_bitset0_b64", []>; 172defm S_BITSET1_B32 : SOP1_32 <sop1<0x1d, 0x1a>, "s_bitset1_b32", []>; 173defm S_BITSET1_B64 : SOP1_64_32 <sop1<0x1e, 0x1b>, "s_bitset1_b64", []>; 174defm S_GETPC_B64 : SOP1_64_0 <sop1<0x1f, 0x1c>, "s_getpc_b64", []>; 175defm S_SETPC_B64 : SOP1_1 <sop1<0x20, 0x1d>, "s_setpc_b64", []>; 176defm S_SWAPPC_B64 : SOP1_64 <sop1<0x21, 0x1e>, "s_swappc_b64", []>; 177defm S_RFE_B64 : SOP1_1 <sop1<0x22, 0x1f>, "s_rfe_b64", []>; 178 179let hasSideEffects = 1, Uses = [EXEC], Defs = [EXEC, SCC] in { 180 181defm S_AND_SAVEEXEC_B64 : SOP1_64 <sop1<0x24, 0x20>, "s_and_saveexec_b64", []>; 182defm S_OR_SAVEEXEC_B64 : SOP1_64 <sop1<0x25, 0x21>, "s_or_saveexec_b64", []>; 183defm S_XOR_SAVEEXEC_B64 : SOP1_64 <sop1<0x26, 0x22>, "s_xor_saveexec_b64", []>; 184defm S_ANDN2_SAVEEXEC_B64 : SOP1_64 <sop1<0x27, 0x23>, "s_andn2_saveexec_b64", []>; 185defm S_ORN2_SAVEEXEC_B64 : SOP1_64 <sop1<0x28, 0x24>, "s_orn2_saveexec_b64", []>; 186defm S_NAND_SAVEEXEC_B64 : SOP1_64 <sop1<0x29, 0x25>, "s_nand_saveexec_b64", []>; 187defm S_NOR_SAVEEXEC_B64 : SOP1_64 <sop1<0x2a, 0x26>, "s_nor_saveexec_b64", []>; 188defm S_XNOR_SAVEEXEC_B64 : SOP1_64 <sop1<0x2b, 0x27>, "s_xnor_saveexec_b64", []>; 189 190} // End hasSideEffects = 1, Uses = [EXEC], Defs = [EXEC, SCC] 191 192defm S_QUADMASK_B32 : SOP1_32 <sop1<0x2c, 0x28>, "s_quadmask_b32", []>; 193defm S_QUADMASK_B64 : SOP1_64 <sop1<0x2d, 0x29>, "s_quadmask_b64", []>; 194 195let Uses = [M0] in { 196defm S_MOVRELS_B32 : SOP1_32 <sop1<0x2e, 0x2a>, "s_movrels_b32", []>; 197defm S_MOVRELS_B64 : SOP1_64 <sop1<0x2f, 0x2b>, "s_movrels_b64", []>; 198defm S_MOVRELD_B32 : SOP1_32 <sop1<0x30, 0x2c>, "s_movreld_b32", []>; 199defm S_MOVRELD_B64 : SOP1_64 <sop1<0x31, 0x2d>, "s_movreld_b64", []>; 200} // End Uses = [M0] 201 202defm S_CBRANCH_JOIN : SOP1_1 <sop1<0x32, 0x2e>, "s_cbranch_join", []>; 203defm S_MOV_REGRD_B32 : SOP1_32 <sop1<0x33, 0x2f>, "s_mov_regrd_b32", []>; 204let Defs = [SCC] in { 205 defm S_ABS_I32 : SOP1_32 <sop1<0x34, 0x30>, "s_abs_i32", []>; 206} // End Defs = [SCC] 207defm S_MOV_FED_B32 : SOP1_32 <sop1<0x35, 0x31>, "s_mov_fed_b32", []>; 208 209//===----------------------------------------------------------------------===// 210// SOP2 Instructions 211//===----------------------------------------------------------------------===// 212 213let Defs = [SCC] in { // Carry out goes to SCC 214let isCommutable = 1 in { 215defm S_ADD_U32 : SOP2_32 <sop2<0x00>, "s_add_u32", []>; 216defm S_ADD_I32 : SOP2_32 <sop2<0x02>, "s_add_i32", 217 [(set i32:$sdst, (add SSrc_32:$src0, SSrc_32:$src1))] 218>; 219} // End isCommutable = 1 220 221defm S_SUB_U32 : SOP2_32 <sop2<0x01>, "s_sub_u32", []>; 222defm S_SUB_I32 : SOP2_32 <sop2<0x03>, "s_sub_i32", 223 [(set i32:$sdst, (sub SSrc_32:$src0, SSrc_32:$src1))] 224>; 225 226let Uses = [SCC] in { // Carry in comes from SCC 227let isCommutable = 1 in { 228defm S_ADDC_U32 : SOP2_32 <sop2<0x04>, "s_addc_u32", 229 [(set i32:$sdst, (adde (i32 SSrc_32:$src0), (i32 SSrc_32:$src1)))]>; 230} // End isCommutable = 1 231 232defm S_SUBB_U32 : SOP2_32 <sop2<0x05>, "s_subb_u32", 233 [(set i32:$sdst, (sube (i32 SSrc_32:$src0), (i32 SSrc_32:$src1)))]>; 234} // End Uses = [SCC] 235 236defm S_MIN_I32 : SOP2_32 <sop2<0x06>, "s_min_i32", 237 [(set i32:$sdst, (smin i32:$src0, i32:$src1))] 238>; 239defm S_MIN_U32 : SOP2_32 <sop2<0x07>, "s_min_u32", 240 [(set i32:$sdst, (umin i32:$src0, i32:$src1))] 241>; 242defm S_MAX_I32 : SOP2_32 <sop2<0x08>, "s_max_i32", 243 [(set i32:$sdst, (smax i32:$src0, i32:$src1))] 244>; 245defm S_MAX_U32 : SOP2_32 <sop2<0x09>, "s_max_u32", 246 [(set i32:$sdst, (umax i32:$src0, i32:$src1))] 247>; 248} // End Defs = [SCC] 249 250 251let Uses = [SCC] in { 252 defm S_CSELECT_B32 : SOP2_32 <sop2<0x0a>, "s_cselect_b32", []>; 253 defm S_CSELECT_B64 : SOP2_64 <sop2<0x0b>, "s_cselect_b64", []>; 254} // End Uses = [SCC] 255 256let Defs = [SCC] in { 257defm S_AND_B32 : SOP2_32 <sop2<0x0e, 0x0c>, "s_and_b32", 258 [(set i32:$sdst, (and i32:$src0, i32:$src1))] 259>; 260 261defm S_AND_B64 : SOP2_64 <sop2<0x0f, 0x0d>, "s_and_b64", 262 [(set i64:$sdst, (and i64:$src0, i64:$src1))] 263>; 264 265defm S_OR_B32 : SOP2_32 <sop2<0x10, 0x0e>, "s_or_b32", 266 [(set i32:$sdst, (or i32:$src0, i32:$src1))] 267>; 268 269defm S_OR_B64 : SOP2_64 <sop2<0x11, 0x0f>, "s_or_b64", 270 [(set i64:$sdst, (or i64:$src0, i64:$src1))] 271>; 272 273defm S_XOR_B32 : SOP2_32 <sop2<0x12, 0x10>, "s_xor_b32", 274 [(set i32:$sdst, (xor i32:$src0, i32:$src1))] 275>; 276 277defm S_XOR_B64 : SOP2_64 <sop2<0x13, 0x11>, "s_xor_b64", 278 [(set i64:$sdst, (xor i64:$src0, i64:$src1))] 279>; 280defm S_ANDN2_B32 : SOP2_32 <sop2<0x14, 0x12>, "s_andn2_b32", []>; 281defm S_ANDN2_B64 : SOP2_64 <sop2<0x15, 0x13>, "s_andn2_b64", []>; 282defm S_ORN2_B32 : SOP2_32 <sop2<0x16, 0x14>, "s_orn2_b32", []>; 283defm S_ORN2_B64 : SOP2_64 <sop2<0x17, 0x15>, "s_orn2_b64", []>; 284defm S_NAND_B32 : SOP2_32 <sop2<0x18, 0x16>, "s_nand_b32", []>; 285defm S_NAND_B64 : SOP2_64 <sop2<0x19, 0x17>, "s_nand_b64", []>; 286defm S_NOR_B32 : SOP2_32 <sop2<0x1a, 0x18>, "s_nor_b32", []>; 287defm S_NOR_B64 : SOP2_64 <sop2<0x1b, 0x19>, "s_nor_b64", []>; 288defm S_XNOR_B32 : SOP2_32 <sop2<0x1c, 0x1a>, "s_xnor_b32", []>; 289defm S_XNOR_B64 : SOP2_64 <sop2<0x1d, 0x1b>, "s_xnor_b64", []>; 290} // End Defs = [SCC] 291 292// Use added complexity so these patterns are preferred to the VALU patterns. 293let AddedComplexity = 1 in { 294let Defs = [SCC] in { 295 296defm S_LSHL_B32 : SOP2_32 <sop2<0x1e, 0x1c>, "s_lshl_b32", 297 [(set i32:$sdst, (shl i32:$src0, i32:$src1))] 298>; 299defm S_LSHL_B64 : SOP2_64_32 <sop2<0x1f, 0x1d>, "s_lshl_b64", 300 [(set i64:$sdst, (shl i64:$src0, i32:$src1))] 301>; 302defm S_LSHR_B32 : SOP2_32 <sop2<0x20, 0x1e>, "s_lshr_b32", 303 [(set i32:$sdst, (srl i32:$src0, i32:$src1))] 304>; 305defm S_LSHR_B64 : SOP2_64_32 <sop2<0x21, 0x1f>, "s_lshr_b64", 306 [(set i64:$sdst, (srl i64:$src0, i32:$src1))] 307>; 308defm S_ASHR_I32 : SOP2_32 <sop2<0x22, 0x20>, "s_ashr_i32", 309 [(set i32:$sdst, (sra i32:$src0, i32:$src1))] 310>; 311defm S_ASHR_I64 : SOP2_64_32 <sop2<0x23, 0x21>, "s_ashr_i64", 312 [(set i64:$sdst, (sra i64:$src0, i32:$src1))] 313>; 314} // End Defs = [SCC] 315 316defm S_BFM_B32 : SOP2_32 <sop2<0x24, 0x22>, "s_bfm_b32", 317 [(set i32:$sdst, (AMDGPUbfm i32:$src0, i32:$src1))]>; 318defm S_BFM_B64 : SOP2_64_32_32 <sop2<0x25, 0x23>, "s_bfm_b64", []>; 319defm S_MUL_I32 : SOP2_32 <sop2<0x26, 0x24>, "s_mul_i32", 320 [(set i32:$sdst, (mul i32:$src0, i32:$src1))] 321>; 322 323} // End AddedComplexity = 1 324 325let Defs = [SCC] in { 326defm S_BFE_U32 : SOP2_32 <sop2<0x27, 0x25>, "s_bfe_u32", []>; 327defm S_BFE_I32 : SOP2_32 <sop2<0x28, 0x26>, "s_bfe_i32", []>; 328defm S_BFE_U64 : SOP2_64_32 <sop2<0x29, 0x27>, "s_bfe_u64", []>; 329defm S_BFE_I64 : SOP2_64_32 <sop2<0x2a, 0x28>, "s_bfe_i64", []>; 330} // End Defs = [SCC] 331 332let sdst = 0 in { 333defm S_CBRANCH_G_FORK : SOP2_m < 334 sop2<0x2b, 0x29>, "s_cbranch_g_fork", (outs), 335 (ins SReg_64:$src0, SReg_64:$src1), "s_cbranch_g_fork $src0, $src1", [] 336>; 337} 338 339let Defs = [SCC] in { 340defm S_ABSDIFF_I32 : SOP2_32 <sop2<0x2c, 0x2a>, "s_absdiff_i32", []>; 341} // End Defs = [SCC] 342 343//===----------------------------------------------------------------------===// 344// SOPC Instructions 345//===----------------------------------------------------------------------===// 346 347def S_CMP_EQ_I32 : SOPC_CMP_32 <0x00000000, "s_cmp_eq_i32", COND_EQ>; 348def S_CMP_LG_I32 : SOPC_CMP_32 <0x00000001, "s_cmp_lg_i32", COND_NE>; 349def S_CMP_GT_I32 : SOPC_CMP_32 <0x00000002, "s_cmp_gt_i32", COND_SGT>; 350def S_CMP_GE_I32 : SOPC_CMP_32 <0x00000003, "s_cmp_ge_i32", COND_SGE>; 351def S_CMP_LT_I32 : SOPC_CMP_32 <0x00000004, "s_cmp_lt_i32", COND_SLT>; 352def S_CMP_LE_I32 : SOPC_CMP_32 <0x00000005, "s_cmp_le_i32", COND_SLE>; 353def S_CMP_EQ_U32 : SOPC_CMP_32 <0x00000006, "s_cmp_eq_u32", COND_EQ>; 354def S_CMP_LG_U32 : SOPC_CMP_32 <0x00000007, "s_cmp_lg_u32", COND_NE >; 355def S_CMP_GT_U32 : SOPC_CMP_32 <0x00000008, "s_cmp_gt_u32", COND_UGT>; 356def S_CMP_GE_U32 : SOPC_CMP_32 <0x00000009, "s_cmp_ge_u32", COND_UGE>; 357def S_CMP_LT_U32 : SOPC_CMP_32 <0x0000000a, "s_cmp_lt_u32", COND_ULT>; 358def S_CMP_LE_U32 : SOPC_CMP_32 <0x0000000b, "s_cmp_le_u32", COND_ULE>; 359def S_BITCMP0_B32 : SOPC_32 <0x0000000c, "s_bitcmp0_b32">; 360def S_BITCMP1_B32 : SOPC_32 <0x0000000d, "s_bitcmp1_b32">; 361def S_BITCMP0_B64 : SOPC_64_32 <0x0000000e, "s_bitcmp0_b64">; 362def S_BITCMP1_B64 : SOPC_64_32 <0x0000000f, "s_bitcmp1_b64">; 363def S_SETVSKIP : SOPC_32 <0x00000010, "s_setvskip">; 364 365//===----------------------------------------------------------------------===// 366// SOPK Instructions 367//===----------------------------------------------------------------------===// 368 369let isReMaterializable = 1, isMoveImm = 1 in { 370defm S_MOVK_I32 : SOPK_32 <sopk<0x00>, "s_movk_i32", []>; 371} // End isReMaterializable = 1 372let Uses = [SCC] in { 373 defm S_CMOVK_I32 : SOPK_32 <sopk<0x02, 0x01>, "s_cmovk_i32", []>; 374} 375 376let isCompare = 1 in { 377 378/* 379This instruction is disabled for now until we can figure out how to teach 380the instruction selector to correctly use the S_CMP* vs V_CMP* 381instructions. 382 383When this instruction is enabled the code generator sometimes produces this 384invalid sequence: 385 386SCC = S_CMPK_EQ_I32 SGPR0, imm 387VCC = COPY SCC 388VGPR0 = V_CNDMASK VCC, VGPR0, VGPR1 389 390defm S_CMPK_EQ_I32 : SOPK_SCC <sopk<0x03, 0x02>, "s_cmpk_eq_i32", 391 [(set i1:$dst, (setcc i32:$src0, imm:$src1, SETEQ))] 392>; 393*/ 394 395defm S_CMPK_EQ_I32 : SOPK_SCC <sopk<0x03, 0x02>, "s_cmpk_eq_i32", []>; 396defm S_CMPK_LG_I32 : SOPK_SCC <sopk<0x04, 0x03>, "s_cmpk_lg_i32", []>; 397defm S_CMPK_GT_I32 : SOPK_SCC <sopk<0x05, 0x04>, "s_cmpk_gt_i32", []>; 398defm S_CMPK_GE_I32 : SOPK_SCC <sopk<0x06, 0x05>, "s_cmpk_ge_i32", []>; 399defm S_CMPK_LT_I32 : SOPK_SCC <sopk<0x07, 0x06>, "s_cmpk_lt_i32", []>; 400defm S_CMPK_LE_I32 : SOPK_SCC <sopk<0x08, 0x07>, "s_cmpk_le_i32", []>; 401defm S_CMPK_EQ_U32 : SOPK_SCC <sopk<0x09, 0x08>, "s_cmpk_eq_u32", []>; 402defm S_CMPK_LG_U32 : SOPK_SCC <sopk<0x0a, 0x09>, "s_cmpk_lg_u32", []>; 403defm S_CMPK_GT_U32 : SOPK_SCC <sopk<0x0b, 0x0a>, "s_cmpk_gt_u32", []>; 404defm S_CMPK_GE_U32 : SOPK_SCC <sopk<0x0c, 0x0b>, "s_cmpk_ge_u32", []>; 405defm S_CMPK_LT_U32 : SOPK_SCC <sopk<0x0d, 0x0c>, "s_cmpk_lt_u32", []>; 406defm S_CMPK_LE_U32 : SOPK_SCC <sopk<0x0e, 0x0d>, "s_cmpk_le_u32", []>; 407} // End isCompare = 1 408 409let Defs = [SCC], isCommutable = 1, DisableEncoding = "$src0", 410 Constraints = "$sdst = $src0" in { 411 defm S_ADDK_I32 : SOPK_32TIE <sopk<0x0f, 0x0e>, "s_addk_i32", []>; 412 defm S_MULK_I32 : SOPK_32TIE <sopk<0x10, 0x0f>, "s_mulk_i32", []>; 413} 414 415defm S_CBRANCH_I_FORK : SOPK_m < 416 sopk<0x11, 0x10>, "s_cbranch_i_fork", (outs), 417 (ins SReg_64:$sdst, u16imm:$simm16), " $sdst, $simm16" 418>; 419 420let mayLoad = 1 in { 421defm S_GETREG_B32 : SOPK_32 <sopk<0x12, 0x11>, "s_getreg_b32", []>; 422} 423 424defm S_SETREG_B32 : SOPK_m < 425 sopk<0x13, 0x12>, "s_setreg_b32", (outs), 426 (ins SReg_32:$sdst, u16imm:$simm16), " $sdst, $simm16" 427>; 428// FIXME: Not on SI? 429//defm S_GETREG_REGRD_B32 : SOPK_32 <sopk<0x14, 0x13>, "s_getreg_regrd_b32", []>; 430defm S_SETREG_IMM32_B32 : SOPK_IMM32 < 431 sopk<0x15, 0x14>, "s_setreg_imm32_b32", (outs), 432 (ins i32imm:$imm, u16imm:$simm16), " $imm, $simm16" 433>; 434 435//===----------------------------------------------------------------------===// 436// SOPP Instructions 437//===----------------------------------------------------------------------===// 438 439def S_NOP : SOPP <0x00000000, (ins i16imm:$simm16), "s_nop $simm16">; 440 441let isTerminator = 1 in { 442 443def S_ENDPGM : SOPP <0x00000001, (ins), "s_endpgm", 444 [(IL_retflag)]> { 445 let simm16 = 0; 446 let isBarrier = 1; 447 let hasCtrlDep = 1; 448} 449 450let isBranch = 1 in { 451def S_BRANCH : SOPP < 452 0x00000002, (ins sopp_brtarget:$simm16), "s_branch $simm16", 453 [(br bb:$simm16)]> { 454 let isBarrier = 1; 455} 456 457let Uses = [SCC] in { 458def S_CBRANCH_SCC0 : SOPP < 459 0x00000004, (ins sopp_brtarget:$simm16), 460 "s_cbranch_scc0 $simm16" 461>; 462def S_CBRANCH_SCC1 : SOPP < 463 0x00000005, (ins sopp_brtarget:$simm16), 464 "s_cbranch_scc1 $simm16", 465 [(si_uniform_br_scc SCC, bb:$simm16)] 466>; 467} // End Uses = [SCC] 468 469let Uses = [VCC] in { 470def S_CBRANCH_VCCZ : SOPP < 471 0x00000006, (ins sopp_brtarget:$simm16), 472 "s_cbranch_vccz $simm16" 473>; 474def S_CBRANCH_VCCNZ : SOPP < 475 0x00000007, (ins sopp_brtarget:$simm16), 476 "s_cbranch_vccnz $simm16" 477>; 478} // End Uses = [VCC] 479 480let Uses = [EXEC] in { 481def S_CBRANCH_EXECZ : SOPP < 482 0x00000008, (ins sopp_brtarget:$simm16), 483 "s_cbranch_execz $simm16" 484>; 485def S_CBRANCH_EXECNZ : SOPP < 486 0x00000009, (ins sopp_brtarget:$simm16), 487 "s_cbranch_execnz $simm16" 488>; 489} // End Uses = [EXEC] 490 491 492} // End isBranch = 1 493} // End isTerminator = 1 494 495let hasSideEffects = 1 in { 496def S_BARRIER : SOPP <0x0000000a, (ins), "s_barrier", 497 [(int_amdgcn_s_barrier)] 498> { 499 let SchedRW = [WriteBarrier]; 500 let simm16 = 0; 501 let mayLoad = 1; 502 let mayStore = 1; 503 let isConvergent = 1; 504} 505 506def S_WAITCNT : SOPP <0x0000000c, (ins WAIT_FLAG:$simm16), "s_waitcnt $simm16">; 507def S_SETHALT : SOPP <0x0000000d, (ins i16imm:$simm16), "s_sethalt $simm16">; 508 509// On SI the documentation says sleep for approximately 64 * low 2 510// bits, consistent with the reported maximum of 448. On VI the 511// maximum reported is 960 cycles, so 960 / 64 = 15 max, so is the 512// maximum really 15 on VI? 513def S_SLEEP : SOPP <0x0000000e, (ins i32imm:$simm16), 514 "s_sleep $simm16", [(int_amdgcn_s_sleep SIMM16bit:$simm16)]> { 515 let hasSideEffects = 1; 516 let mayLoad = 1; 517 let mayStore = 1; 518} 519 520def S_SETPRIO : SOPP <0x0000000f, (ins i16imm:$simm16), "s_setprio $simm16">; 521 522let Uses = [EXEC, M0] in { 523 // FIXME: Should this be mayLoad+mayStore? 524 def S_SENDMSG : SOPP <0x00000010, (ins SendMsgImm:$simm16), "s_sendmsg $simm16", 525 [(AMDGPUsendmsg (i32 imm:$simm16))] 526 >; 527} // End Uses = [EXEC, M0] 528 529def S_SENDMSGHALT : SOPP <0x00000011, (ins i16imm:$simm16), "s_sendmsghalt $simm16">; 530def S_TRAP : SOPP <0x00000012, (ins i16imm:$simm16), "s_trap $simm16">; 531def S_ICACHE_INV : SOPP <0x00000013, (ins), "s_icache_inv"> { 532 let simm16 = 0; 533} 534def S_INCPERFLEVEL : SOPP <0x00000014, (ins i16imm:$simm16), "s_incperflevel $simm16">; 535def S_DECPERFLEVEL : SOPP <0x00000015, (ins i16imm:$simm16), "s_decperflevel $simm16">; 536def S_TTRACEDATA : SOPP <0x00000016, (ins), "s_ttracedata"> { 537 let simm16 = 0; 538} 539} // End hasSideEffects 540 541//===----------------------------------------------------------------------===// 542// VOPC Instructions 543//===----------------------------------------------------------------------===// 544 545let isCompare = 1, isCommutable = 1 in { 546 547defm V_CMP_F_F32 : VOPC_F32 <vopc<0x0, 0x40>, "v_cmp_f_f32">; 548defm V_CMP_LT_F32 : VOPC_F32 <vopc<0x1, 0x41>, "v_cmp_lt_f32", COND_OLT, "v_cmp_gt_f32">; 549defm V_CMP_EQ_F32 : VOPC_F32 <vopc<0x2, 0x42>, "v_cmp_eq_f32", COND_OEQ>; 550defm V_CMP_LE_F32 : VOPC_F32 <vopc<0x3, 0x43>, "v_cmp_le_f32", COND_OLE, "v_cmp_ge_f32">; 551defm V_CMP_GT_F32 : VOPC_F32 <vopc<0x4, 0x44>, "v_cmp_gt_f32", COND_OGT>; 552defm V_CMP_LG_F32 : VOPC_F32 <vopc<0x5, 0x45>, "v_cmp_lg_f32", COND_ONE>; 553defm V_CMP_GE_F32 : VOPC_F32 <vopc<0x6, 0x46>, "v_cmp_ge_f32", COND_OGE>; 554defm V_CMP_O_F32 : VOPC_F32 <vopc<0x7, 0x47>, "v_cmp_o_f32", COND_O>; 555defm V_CMP_U_F32 : VOPC_F32 <vopc<0x8, 0x48>, "v_cmp_u_f32", COND_UO>; 556defm V_CMP_NGE_F32 : VOPC_F32 <vopc<0x9, 0x49>, "v_cmp_nge_f32", COND_ULT, "v_cmp_nle_f32">; 557defm V_CMP_NLG_F32 : VOPC_F32 <vopc<0xa, 0x4a>, "v_cmp_nlg_f32", COND_UEQ>; 558defm V_CMP_NGT_F32 : VOPC_F32 <vopc<0xb, 0x4b>, "v_cmp_ngt_f32", COND_ULE, "v_cmp_nlt_f32">; 559defm V_CMP_NLE_F32 : VOPC_F32 <vopc<0xc, 0x4c>, "v_cmp_nle_f32", COND_UGT>; 560defm V_CMP_NEQ_F32 : VOPC_F32 <vopc<0xd, 0x4d>, "v_cmp_neq_f32", COND_UNE>; 561defm V_CMP_NLT_F32 : VOPC_F32 <vopc<0xe, 0x4e>, "v_cmp_nlt_f32", COND_UGE>; 562defm V_CMP_TRU_F32 : VOPC_F32 <vopc<0xf, 0x4f>, "v_cmp_tru_f32">; 563 564 565defm V_CMPX_F_F32 : VOPCX_F32 <vopc<0x10, 0x50>, "v_cmpx_f_f32">; 566defm V_CMPX_LT_F32 : VOPCX_F32 <vopc<0x11, 0x51>, "v_cmpx_lt_f32", "v_cmpx_gt_f32">; 567defm V_CMPX_EQ_F32 : VOPCX_F32 <vopc<0x12, 0x52>, "v_cmpx_eq_f32">; 568defm V_CMPX_LE_F32 : VOPCX_F32 <vopc<0x13, 0x53>, "v_cmpx_le_f32", "v_cmpx_ge_f32">; 569defm V_CMPX_GT_F32 : VOPCX_F32 <vopc<0x14, 0x54>, "v_cmpx_gt_f32">; 570defm V_CMPX_LG_F32 : VOPCX_F32 <vopc<0x15, 0x55>, "v_cmpx_lg_f32">; 571defm V_CMPX_GE_F32 : VOPCX_F32 <vopc<0x16, 0x56>, "v_cmpx_ge_f32">; 572defm V_CMPX_O_F32 : VOPCX_F32 <vopc<0x17, 0x57>, "v_cmpx_o_f32">; 573defm V_CMPX_U_F32 : VOPCX_F32 <vopc<0x18, 0x58>, "v_cmpx_u_f32">; 574defm V_CMPX_NGE_F32 : VOPCX_F32 <vopc<0x19, 0x59>, "v_cmpx_nge_f32">; 575defm V_CMPX_NLG_F32 : VOPCX_F32 <vopc<0x1a, 0x5a>, "v_cmpx_nlg_f32">; 576defm V_CMPX_NGT_F32 : VOPCX_F32 <vopc<0x1b, 0x5b>, "v_cmpx_ngt_f32">; 577defm V_CMPX_NLE_F32 : VOPCX_F32 <vopc<0x1c, 0x5c>, "v_cmpx_nle_f32">; 578defm V_CMPX_NEQ_F32 : VOPCX_F32 <vopc<0x1d, 0x5d>, "v_cmpx_neq_f32">; 579defm V_CMPX_NLT_F32 : VOPCX_F32 <vopc<0x1e, 0x5e>, "v_cmpx_nlt_f32">; 580defm V_CMPX_TRU_F32 : VOPCX_F32 <vopc<0x1f, 0x5f>, "v_cmpx_tru_f32">; 581 582 583defm V_CMP_F_F64 : VOPC_F64 <vopc<0x20, 0x60>, "v_cmp_f_f64">; 584defm V_CMP_LT_F64 : VOPC_F64 <vopc<0x21, 0x61>, "v_cmp_lt_f64", COND_OLT, "v_cmp_gt_f64">; 585defm V_CMP_EQ_F64 : VOPC_F64 <vopc<0x22, 0x62>, "v_cmp_eq_f64", COND_OEQ>; 586defm V_CMP_LE_F64 : VOPC_F64 <vopc<0x23, 0x63>, "v_cmp_le_f64", COND_OLE, "v_cmp_ge_f64">; 587defm V_CMP_GT_F64 : VOPC_F64 <vopc<0x24, 0x64>, "v_cmp_gt_f64", COND_OGT>; 588defm V_CMP_LG_F64 : VOPC_F64 <vopc<0x25, 0x65>, "v_cmp_lg_f64", COND_ONE>; 589defm V_CMP_GE_F64 : VOPC_F64 <vopc<0x26, 0x66>, "v_cmp_ge_f64", COND_OGE>; 590defm V_CMP_O_F64 : VOPC_F64 <vopc<0x27, 0x67>, "v_cmp_o_f64", COND_O>; 591defm V_CMP_U_F64 : VOPC_F64 <vopc<0x28, 0x68>, "v_cmp_u_f64", COND_UO>; 592defm V_CMP_NGE_F64 : VOPC_F64 <vopc<0x29, 0x69>, "v_cmp_nge_f64", COND_ULT, "v_cmp_nle_f64">; 593defm V_CMP_NLG_F64 : VOPC_F64 <vopc<0x2a, 0x6a>, "v_cmp_nlg_f64", COND_UEQ>; 594defm V_CMP_NGT_F64 : VOPC_F64 <vopc<0x2b, 0x6b>, "v_cmp_ngt_f64", COND_ULE, "v_cmp_nlt_f64">; 595defm V_CMP_NLE_F64 : VOPC_F64 <vopc<0x2c, 0x6c>, "v_cmp_nle_f64", COND_UGT>; 596defm V_CMP_NEQ_F64 : VOPC_F64 <vopc<0x2d, 0x6d>, "v_cmp_neq_f64", COND_UNE>; 597defm V_CMP_NLT_F64 : VOPC_F64 <vopc<0x2e, 0x6e>, "v_cmp_nlt_f64", COND_UGE>; 598defm V_CMP_TRU_F64 : VOPC_F64 <vopc<0x2f, 0x6f>, "v_cmp_tru_f64">; 599 600 601defm V_CMPX_F_F64 : VOPCX_F64 <vopc<0x30, 0x70>, "v_cmpx_f_f64">; 602defm V_CMPX_LT_F64 : VOPCX_F64 <vopc<0x31, 0x71>, "v_cmpx_lt_f64", "v_cmpx_gt_f64">; 603defm V_CMPX_EQ_F64 : VOPCX_F64 <vopc<0x32, 0x72>, "v_cmpx_eq_f64">; 604defm V_CMPX_LE_F64 : VOPCX_F64 <vopc<0x33, 0x73>, "v_cmpx_le_f64", "v_cmpx_ge_f64">; 605defm V_CMPX_GT_F64 : VOPCX_F64 <vopc<0x34, 0x74>, "v_cmpx_gt_f64">; 606defm V_CMPX_LG_F64 : VOPCX_F64 <vopc<0x35, 0x75>, "v_cmpx_lg_f64">; 607defm V_CMPX_GE_F64 : VOPCX_F64 <vopc<0x36, 0x76>, "v_cmpx_ge_f64">; 608defm V_CMPX_O_F64 : VOPCX_F64 <vopc<0x37, 0x77>, "v_cmpx_o_f64">; 609defm V_CMPX_U_F64 : VOPCX_F64 <vopc<0x38, 0x78>, "v_cmpx_u_f64">; 610defm V_CMPX_NGE_F64 : VOPCX_F64 <vopc<0x39, 0x79>, "v_cmpx_nge_f64", "v_cmpx_nle_f64">; 611defm V_CMPX_NLG_F64 : VOPCX_F64 <vopc<0x3a, 0x7a>, "v_cmpx_nlg_f64">; 612defm V_CMPX_NGT_F64 : VOPCX_F64 <vopc<0x3b, 0x7b>, "v_cmpx_ngt_f64", "v_cmpx_nlt_f64">; 613defm V_CMPX_NLE_F64 : VOPCX_F64 <vopc<0x3c, 0x7c>, "v_cmpx_nle_f64">; 614defm V_CMPX_NEQ_F64 : VOPCX_F64 <vopc<0x3d, 0x7d>, "v_cmpx_neq_f64">; 615defm V_CMPX_NLT_F64 : VOPCX_F64 <vopc<0x3e, 0x7e>, "v_cmpx_nlt_f64">; 616defm V_CMPX_TRU_F64 : VOPCX_F64 <vopc<0x3f, 0x7f>, "v_cmpx_tru_f64">; 617 618 619let SubtargetPredicate = isSICI in { 620 621defm V_CMPS_F_F32 : VOPC_F32 <vopc<0x40>, "v_cmps_f_f32">; 622defm V_CMPS_LT_F32 : VOPC_F32 <vopc<0x41>, "v_cmps_lt_f32", COND_NULL, "v_cmps_gt_f32">; 623defm V_CMPS_EQ_F32 : VOPC_F32 <vopc<0x42>, "v_cmps_eq_f32">; 624defm V_CMPS_LE_F32 : VOPC_F32 <vopc<0x43>, "v_cmps_le_f32", COND_NULL, "v_cmps_ge_f32">; 625defm V_CMPS_GT_F32 : VOPC_F32 <vopc<0x44>, "v_cmps_gt_f32">; 626defm V_CMPS_LG_F32 : VOPC_F32 <vopc<0x45>, "v_cmps_lg_f32">; 627defm V_CMPS_GE_F32 : VOPC_F32 <vopc<0x46>, "v_cmps_ge_f32">; 628defm V_CMPS_O_F32 : VOPC_F32 <vopc<0x47>, "v_cmps_o_f32">; 629defm V_CMPS_U_F32 : VOPC_F32 <vopc<0x48>, "v_cmps_u_f32">; 630defm V_CMPS_NGE_F32 : VOPC_F32 <vopc<0x49>, "v_cmps_nge_f32", COND_NULL, "v_cmps_nle_f32">; 631defm V_CMPS_NLG_F32 : VOPC_F32 <vopc<0x4a>, "v_cmps_nlg_f32">; 632defm V_CMPS_NGT_F32 : VOPC_F32 <vopc<0x4b>, "v_cmps_ngt_f32", COND_NULL, "v_cmps_nlt_f32">; 633defm V_CMPS_NLE_F32 : VOPC_F32 <vopc<0x4c>, "v_cmps_nle_f32">; 634defm V_CMPS_NEQ_F32 : VOPC_F32 <vopc<0x4d>, "v_cmps_neq_f32">; 635defm V_CMPS_NLT_F32 : VOPC_F32 <vopc<0x4e>, "v_cmps_nlt_f32">; 636defm V_CMPS_TRU_F32 : VOPC_F32 <vopc<0x4f>, "v_cmps_tru_f32">; 637 638 639defm V_CMPSX_F_F32 : VOPCX_F32 <vopc<0x50>, "v_cmpsx_f_f32">; 640defm V_CMPSX_LT_F32 : VOPCX_F32 <vopc<0x51>, "v_cmpsx_lt_f32", "v_cmpsx_gt_f32">; 641defm V_CMPSX_EQ_F32 : VOPCX_F32 <vopc<0x52>, "v_cmpsx_eq_f32">; 642defm V_CMPSX_LE_F32 : VOPCX_F32 <vopc<0x53>, "v_cmpsx_le_f32", "v_cmpsx_ge_f32">; 643defm V_CMPSX_GT_F32 : VOPCX_F32 <vopc<0x54>, "v_cmpsx_gt_f32">; 644defm V_CMPSX_LG_F32 : VOPCX_F32 <vopc<0x55>, "v_cmpsx_lg_f32">; 645defm V_CMPSX_GE_F32 : VOPCX_F32 <vopc<0x56>, "v_cmpsx_ge_f32">; 646defm V_CMPSX_O_F32 : VOPCX_F32 <vopc<0x57>, "v_cmpsx_o_f32">; 647defm V_CMPSX_U_F32 : VOPCX_F32 <vopc<0x58>, "v_cmpsx_u_f32">; 648defm V_CMPSX_NGE_F32 : VOPCX_F32 <vopc<0x59>, "v_cmpsx_nge_f32", "v_cmpsx_nle_f32">; 649defm V_CMPSX_NLG_F32 : VOPCX_F32 <vopc<0x5a>, "v_cmpsx_nlg_f32">; 650defm V_CMPSX_NGT_F32 : VOPCX_F32 <vopc<0x5b>, "v_cmpsx_ngt_f32", "v_cmpsx_nlt_f32">; 651defm V_CMPSX_NLE_F32 : VOPCX_F32 <vopc<0x5c>, "v_cmpsx_nle_f32">; 652defm V_CMPSX_NEQ_F32 : VOPCX_F32 <vopc<0x5d>, "v_cmpsx_neq_f32">; 653defm V_CMPSX_NLT_F32 : VOPCX_F32 <vopc<0x5e>, "v_cmpsx_nlt_f32">; 654defm V_CMPSX_TRU_F32 : VOPCX_F32 <vopc<0x5f>, "v_cmpsx_tru_f32">; 655 656 657defm V_CMPS_F_F64 : VOPC_F64 <vopc<0x60>, "v_cmps_f_f64">; 658defm V_CMPS_LT_F64 : VOPC_F64 <vopc<0x61>, "v_cmps_lt_f64", COND_NULL, "v_cmps_gt_f64">; 659defm V_CMPS_EQ_F64 : VOPC_F64 <vopc<0x62>, "v_cmps_eq_f64">; 660defm V_CMPS_LE_F64 : VOPC_F64 <vopc<0x63>, "v_cmps_le_f64", COND_NULL, "v_cmps_ge_f64">; 661defm V_CMPS_GT_F64 : VOPC_F64 <vopc<0x64>, "v_cmps_gt_f64">; 662defm V_CMPS_LG_F64 : VOPC_F64 <vopc<0x65>, "v_cmps_lg_f64">; 663defm V_CMPS_GE_F64 : VOPC_F64 <vopc<0x66>, "v_cmps_ge_f64">; 664defm V_CMPS_O_F64 : VOPC_F64 <vopc<0x67>, "v_cmps_o_f64">; 665defm V_CMPS_U_F64 : VOPC_F64 <vopc<0x68>, "v_cmps_u_f64">; 666defm V_CMPS_NGE_F64 : VOPC_F64 <vopc<0x69>, "v_cmps_nge_f64", COND_NULL, "v_cmps_nle_f64">; 667defm V_CMPS_NLG_F64 : VOPC_F64 <vopc<0x6a>, "v_cmps_nlg_f64">; 668defm V_CMPS_NGT_F64 : VOPC_F64 <vopc<0x6b>, "v_cmps_ngt_f64", COND_NULL, "v_cmps_nlt_f64">; 669defm V_CMPS_NLE_F64 : VOPC_F64 <vopc<0x6c>, "v_cmps_nle_f64">; 670defm V_CMPS_NEQ_F64 : VOPC_F64 <vopc<0x6d>, "v_cmps_neq_f64">; 671defm V_CMPS_NLT_F64 : VOPC_F64 <vopc<0x6e>, "v_cmps_nlt_f64">; 672defm V_CMPS_TRU_F64 : VOPC_F64 <vopc<0x6f>, "v_cmps_tru_f64">; 673 674 675defm V_CMPSX_F_F64 : VOPCX_F64 <vopc<0x70>, "v_cmpsx_f_f64">; 676defm V_CMPSX_LT_F64 : VOPCX_F64 <vopc<0x71>, "v_cmpsx_lt_f64", "v_cmpsx_gt_f64">; 677defm V_CMPSX_EQ_F64 : VOPCX_F64 <vopc<0x72>, "v_cmpsx_eq_f64">; 678defm V_CMPSX_LE_F64 : VOPCX_F64 <vopc<0x73>, "v_cmpsx_le_f64", "v_cmpsx_ge_f64">; 679defm V_CMPSX_GT_F64 : VOPCX_F64 <vopc<0x74>, "v_cmpsx_gt_f64">; 680defm V_CMPSX_LG_F64 : VOPCX_F64 <vopc<0x75>, "v_cmpsx_lg_f64">; 681defm V_CMPSX_GE_F64 : VOPCX_F64 <vopc<0x76>, "v_cmpsx_ge_f64">; 682defm V_CMPSX_O_F64 : VOPCX_F64 <vopc<0x77>, "v_cmpsx_o_f64">; 683defm V_CMPSX_U_F64 : VOPCX_F64 <vopc<0x78>, "v_cmpsx_u_f64">; 684defm V_CMPSX_NGE_F64 : VOPCX_F64 <vopc<0x79>, "v_cmpsx_nge_f64", "v_cmpsx_nle_f64">; 685defm V_CMPSX_NLG_F64 : VOPCX_F64 <vopc<0x7a>, "v_cmpsx_nlg_f64">; 686defm V_CMPSX_NGT_F64 : VOPCX_F64 <vopc<0x7b>, "v_cmpsx_ngt_f64", "v_cmpsx_nlt_f64">; 687defm V_CMPSX_NLE_F64 : VOPCX_F64 <vopc<0x7c>, "v_cmpsx_nle_f64">; 688defm V_CMPSX_NEQ_F64 : VOPCX_F64 <vopc<0x7d>, "v_cmpsx_neq_f64">; 689defm V_CMPSX_NLT_F64 : VOPCX_F64 <vopc<0x7e>, "v_cmpsx_nlt_f64">; 690defm V_CMPSX_TRU_F64 : VOPCX_F64 <vopc<0x7f>, "v_cmpsx_tru_f64">; 691 692} // End SubtargetPredicate = isSICI 693 694defm V_CMP_F_I32 : VOPC_I32 <vopc<0x80, 0xc0>, "v_cmp_f_i32">; 695defm V_CMP_LT_I32 : VOPC_I32 <vopc<0x81, 0xc1>, "v_cmp_lt_i32", COND_SLT, "v_cmp_gt_i32">; 696defm V_CMP_EQ_I32 : VOPC_I32 <vopc<0x82, 0xc2>, "v_cmp_eq_i32", COND_EQ>; 697defm V_CMP_LE_I32 : VOPC_I32 <vopc<0x83, 0xc3>, "v_cmp_le_i32", COND_SLE, "v_cmp_ge_i32">; 698defm V_CMP_GT_I32 : VOPC_I32 <vopc<0x84, 0xc4>, "v_cmp_gt_i32", COND_SGT>; 699defm V_CMP_NE_I32 : VOPC_I32 <vopc<0x85, 0xc5>, "v_cmp_ne_i32", COND_NE>; 700defm V_CMP_GE_I32 : VOPC_I32 <vopc<0x86, 0xc6>, "v_cmp_ge_i32", COND_SGE>; 701defm V_CMP_T_I32 : VOPC_I32 <vopc<0x87, 0xc7>, "v_cmp_t_i32">; 702 703 704defm V_CMPX_F_I32 : VOPCX_I32 <vopc<0x90, 0xd0>, "v_cmpx_f_i32">; 705defm V_CMPX_LT_I32 : VOPCX_I32 <vopc<0x91, 0xd1>, "v_cmpx_lt_i32", "v_cmpx_gt_i32">; 706defm V_CMPX_EQ_I32 : VOPCX_I32 <vopc<0x92, 0xd2>, "v_cmpx_eq_i32">; 707defm V_CMPX_LE_I32 : VOPCX_I32 <vopc<0x93, 0xd3>, "v_cmpx_le_i32", "v_cmpx_ge_i32">; 708defm V_CMPX_GT_I32 : VOPCX_I32 <vopc<0x94, 0xd4>, "v_cmpx_gt_i32">; 709defm V_CMPX_NE_I32 : VOPCX_I32 <vopc<0x95, 0xd5>, "v_cmpx_ne_i32">; 710defm V_CMPX_GE_I32 : VOPCX_I32 <vopc<0x96, 0xd6>, "v_cmpx_ge_i32">; 711defm V_CMPX_T_I32 : VOPCX_I32 <vopc<0x97, 0xd7>, "v_cmpx_t_i32">; 712 713 714defm V_CMP_F_I64 : VOPC_I64 <vopc<0xa0, 0xe0>, "v_cmp_f_i64">; 715defm V_CMP_LT_I64 : VOPC_I64 <vopc<0xa1, 0xe1>, "v_cmp_lt_i64", COND_SLT, "v_cmp_gt_i64">; 716defm V_CMP_EQ_I64 : VOPC_I64 <vopc<0xa2, 0xe2>, "v_cmp_eq_i64", COND_EQ>; 717defm V_CMP_LE_I64 : VOPC_I64 <vopc<0xa3, 0xe3>, "v_cmp_le_i64", COND_SLE, "v_cmp_ge_i64">; 718defm V_CMP_GT_I64 : VOPC_I64 <vopc<0xa4, 0xe4>, "v_cmp_gt_i64", COND_SGT>; 719defm V_CMP_NE_I64 : VOPC_I64 <vopc<0xa5, 0xe5>, "v_cmp_ne_i64", COND_NE>; 720defm V_CMP_GE_I64 : VOPC_I64 <vopc<0xa6, 0xe6>, "v_cmp_ge_i64", COND_SGE>; 721defm V_CMP_T_I64 : VOPC_I64 <vopc<0xa7, 0xe7>, "v_cmp_t_i64">; 722 723 724defm V_CMPX_F_I64 : VOPCX_I64 <vopc<0xb0, 0xf0>, "v_cmpx_f_i64">; 725defm V_CMPX_LT_I64 : VOPCX_I64 <vopc<0xb1, 0xf1>, "v_cmpx_lt_i64", "v_cmpx_gt_i64">; 726defm V_CMPX_EQ_I64 : VOPCX_I64 <vopc<0xb2, 0xf2>, "v_cmpx_eq_i64">; 727defm V_CMPX_LE_I64 : VOPCX_I64 <vopc<0xb3, 0xf3>, "v_cmpx_le_i64", "v_cmpx_ge_i64">; 728defm V_CMPX_GT_I64 : VOPCX_I64 <vopc<0xb4, 0xf4>, "v_cmpx_gt_i64">; 729defm V_CMPX_NE_I64 : VOPCX_I64 <vopc<0xb5, 0xf5>, "v_cmpx_ne_i64">; 730defm V_CMPX_GE_I64 : VOPCX_I64 <vopc<0xb6, 0xf6>, "v_cmpx_ge_i64">; 731defm V_CMPX_T_I64 : VOPCX_I64 <vopc<0xb7, 0xf7>, "v_cmpx_t_i64">; 732 733 734defm V_CMP_F_U32 : VOPC_I32 <vopc<0xc0, 0xc8>, "v_cmp_f_u32">; 735defm V_CMP_LT_U32 : VOPC_I32 <vopc<0xc1, 0xc9>, "v_cmp_lt_u32", COND_ULT, "v_cmp_gt_u32">; 736defm V_CMP_EQ_U32 : VOPC_I32 <vopc<0xc2, 0xca>, "v_cmp_eq_u32", COND_EQ>; 737defm V_CMP_LE_U32 : VOPC_I32 <vopc<0xc3, 0xcb>, "v_cmp_le_u32", COND_ULE, "v_cmp_ge_u32">; 738defm V_CMP_GT_U32 : VOPC_I32 <vopc<0xc4, 0xcc>, "v_cmp_gt_u32", COND_UGT>; 739defm V_CMP_NE_U32 : VOPC_I32 <vopc<0xc5, 0xcd>, "v_cmp_ne_u32", COND_NE>; 740defm V_CMP_GE_U32 : VOPC_I32 <vopc<0xc6, 0xce>, "v_cmp_ge_u32", COND_UGE>; 741defm V_CMP_T_U32 : VOPC_I32 <vopc<0xc7, 0xcf>, "v_cmp_t_u32">; 742 743 744defm V_CMPX_F_U32 : VOPCX_I32 <vopc<0xd0, 0xd8>, "v_cmpx_f_u32">; 745defm V_CMPX_LT_U32 : VOPCX_I32 <vopc<0xd1, 0xd9>, "v_cmpx_lt_u32", "v_cmpx_gt_u32">; 746defm V_CMPX_EQ_U32 : VOPCX_I32 <vopc<0xd2, 0xda>, "v_cmpx_eq_u32">; 747defm V_CMPX_LE_U32 : VOPCX_I32 <vopc<0xd3, 0xdb>, "v_cmpx_le_u32", "v_cmpx_le_u32">; 748defm V_CMPX_GT_U32 : VOPCX_I32 <vopc<0xd4, 0xdc>, "v_cmpx_gt_u32">; 749defm V_CMPX_NE_U32 : VOPCX_I32 <vopc<0xd5, 0xdd>, "v_cmpx_ne_u32">; 750defm V_CMPX_GE_U32 : VOPCX_I32 <vopc<0xd6, 0xde>, "v_cmpx_ge_u32">; 751defm V_CMPX_T_U32 : VOPCX_I32 <vopc<0xd7, 0xdf>, "v_cmpx_t_u32">; 752 753 754defm V_CMP_F_U64 : VOPC_I64 <vopc<0xe0, 0xe8>, "v_cmp_f_u64">; 755defm V_CMP_LT_U64 : VOPC_I64 <vopc<0xe1, 0xe9>, "v_cmp_lt_u64", COND_ULT, "v_cmp_gt_u64">; 756defm V_CMP_EQ_U64 : VOPC_I64 <vopc<0xe2, 0xea>, "v_cmp_eq_u64", COND_EQ>; 757defm V_CMP_LE_U64 : VOPC_I64 <vopc<0xe3, 0xeb>, "v_cmp_le_u64", COND_ULE, "v_cmp_ge_u64">; 758defm V_CMP_GT_U64 : VOPC_I64 <vopc<0xe4, 0xec>, "v_cmp_gt_u64", COND_UGT>; 759defm V_CMP_NE_U64 : VOPC_I64 <vopc<0xe5, 0xed>, "v_cmp_ne_u64", COND_NE>; 760defm V_CMP_GE_U64 : VOPC_I64 <vopc<0xe6, 0xee>, "v_cmp_ge_u64", COND_UGE>; 761defm V_CMP_T_U64 : VOPC_I64 <vopc<0xe7, 0xef>, "v_cmp_t_u64">; 762 763defm V_CMPX_F_U64 : VOPCX_I64 <vopc<0xf0, 0xf8>, "v_cmpx_f_u64">; 764defm V_CMPX_LT_U64 : VOPCX_I64 <vopc<0xf1, 0xf9>, "v_cmpx_lt_u64", "v_cmpx_gt_u64">; 765defm V_CMPX_EQ_U64 : VOPCX_I64 <vopc<0xf2, 0xfa>, "v_cmpx_eq_u64">; 766defm V_CMPX_LE_U64 : VOPCX_I64 <vopc<0xf3, 0xfb>, "v_cmpx_le_u64", "v_cmpx_ge_u64">; 767defm V_CMPX_GT_U64 : VOPCX_I64 <vopc<0xf4, 0xfc>, "v_cmpx_gt_u64">; 768defm V_CMPX_NE_U64 : VOPCX_I64 <vopc<0xf5, 0xfd>, "v_cmpx_ne_u64">; 769defm V_CMPX_GE_U64 : VOPCX_I64 <vopc<0xf6, 0xfe>, "v_cmpx_ge_u64">; 770defm V_CMPX_T_U64 : VOPCX_I64 <vopc<0xf7, 0xff>, "v_cmpx_t_u64">; 771 772} // End isCompare = 1, isCommutable = 1 773 774defm V_CMP_CLASS_F32 : VOPC_CLASS_F32 <vopc<0x88, 0x10>, "v_cmp_class_f32">; 775defm V_CMPX_CLASS_F32 : VOPCX_CLASS_F32 <vopc<0x98, 0x11>, "v_cmpx_class_f32">; 776defm V_CMP_CLASS_F64 : VOPC_CLASS_F64 <vopc<0xa8, 0x12>, "v_cmp_class_f64">; 777defm V_CMPX_CLASS_F64 : VOPCX_CLASS_F64 <vopc<0xb8, 0x13>, "v_cmpx_class_f64">; 778 779//===----------------------------------------------------------------------===// 780// DS Instructions 781//===----------------------------------------------------------------------===// 782 783defm DS_ADD_U32 : DS_1A1D_NORET <0x0, "ds_add_u32", VGPR_32>; 784defm DS_SUB_U32 : DS_1A1D_NORET <0x1, "ds_sub_u32", VGPR_32>; 785defm DS_RSUB_U32 : DS_1A1D_NORET <0x2, "ds_rsub_u32", VGPR_32>; 786defm DS_INC_U32 : DS_1A1D_NORET <0x3, "ds_inc_u32", VGPR_32>; 787defm DS_DEC_U32 : DS_1A1D_NORET <0x4, "ds_dec_u32", VGPR_32>; 788defm DS_MIN_I32 : DS_1A1D_NORET <0x5, "ds_min_i32", VGPR_32>; 789defm DS_MAX_I32 : DS_1A1D_NORET <0x6, "ds_max_i32", VGPR_32>; 790defm DS_MIN_U32 : DS_1A1D_NORET <0x7, "ds_min_u32", VGPR_32>; 791defm DS_MAX_U32 : DS_1A1D_NORET <0x8, "ds_max_u32", VGPR_32>; 792defm DS_AND_B32 : DS_1A1D_NORET <0x9, "ds_and_b32", VGPR_32>; 793defm DS_OR_B32 : DS_1A1D_NORET <0xa, "ds_or_b32", VGPR_32>; 794defm DS_XOR_B32 : DS_1A1D_NORET <0xb, "ds_xor_b32", VGPR_32>; 795defm DS_MSKOR_B32 : DS_1A2D_NORET <0xc, "ds_mskor_b32", VGPR_32>; 796let mayLoad = 0 in { 797defm DS_WRITE_B32 : DS_1A1D_NORET <0xd, "ds_write_b32", VGPR_32>; 798defm DS_WRITE2_B32 : DS_1A1D_Off8_NORET <0xe, "ds_write2_b32", VGPR_32>; 799defm DS_WRITE2ST64_B32 : DS_1A1D_Off8_NORET <0xf, "ds_write2st64_b32", VGPR_32>; 800} 801defm DS_CMPST_B32 : DS_1A2D_NORET <0x10, "ds_cmpst_b32", VGPR_32>; 802defm DS_CMPST_F32 : DS_1A2D_NORET <0x11, "ds_cmpst_f32", VGPR_32>; 803defm DS_MIN_F32 : DS_1A2D_NORET <0x12, "ds_min_f32", VGPR_32>; 804defm DS_MAX_F32 : DS_1A2D_NORET <0x13, "ds_max_f32", VGPR_32>; 805 806defm DS_GWS_INIT : DS_1A_GDS <0x19, "ds_gws_init">; 807defm DS_GWS_SEMA_V : DS_1A_GDS <0x1a, "ds_gws_sema_v">; 808defm DS_GWS_SEMA_BR : DS_1A_GDS <0x1b, "ds_gws_sema_br">; 809defm DS_GWS_SEMA_P : DS_1A_GDS <0x1c, "ds_gws_sema_p">; 810defm DS_GWS_BARRIER : DS_1A_GDS <0x1d, "ds_gws_barrier">; 811let mayLoad = 0 in { 812defm DS_WRITE_B8 : DS_1A1D_NORET <0x1e, "ds_write_b8", VGPR_32>; 813defm DS_WRITE_B16 : DS_1A1D_NORET <0x1f, "ds_write_b16", VGPR_32>; 814} 815defm DS_ADD_RTN_U32 : DS_1A1D_RET <0x20, "ds_add_rtn_u32", VGPR_32, "ds_add_u32">; 816defm DS_SUB_RTN_U32 : DS_1A1D_RET <0x21, "ds_sub_rtn_u32", VGPR_32, "ds_sub_u32">; 817defm DS_RSUB_RTN_U32 : DS_1A1D_RET <0x22, "ds_rsub_rtn_u32", VGPR_32, "ds_rsub_u32">; 818defm DS_INC_RTN_U32 : DS_1A1D_RET <0x23, "ds_inc_rtn_u32", VGPR_32, "ds_inc_u32">; 819defm DS_DEC_RTN_U32 : DS_1A1D_RET <0x24, "ds_dec_rtn_u32", VGPR_32, "ds_dec_u32">; 820defm DS_MIN_RTN_I32 : DS_1A1D_RET <0x25, "ds_min_rtn_i32", VGPR_32, "ds_min_i32">; 821defm DS_MAX_RTN_I32 : DS_1A1D_RET <0x26, "ds_max_rtn_i32", VGPR_32, "ds_max_i32">; 822defm DS_MIN_RTN_U32 : DS_1A1D_RET <0x27, "ds_min_rtn_u32", VGPR_32, "ds_min_u32">; 823defm DS_MAX_RTN_U32 : DS_1A1D_RET <0x28, "ds_max_rtn_u32", VGPR_32, "ds_max_u32">; 824defm DS_AND_RTN_B32 : DS_1A1D_RET <0x29, "ds_and_rtn_b32", VGPR_32, "ds_and_b32">; 825defm DS_OR_RTN_B32 : DS_1A1D_RET <0x2a, "ds_or_rtn_b32", VGPR_32, "ds_or_b32">; 826defm DS_XOR_RTN_B32 : DS_1A1D_RET <0x2b, "ds_xor_rtn_b32", VGPR_32, "ds_xor_b32">; 827defm DS_MSKOR_RTN_B32 : DS_1A2D_RET <0x2c, "ds_mskor_rtn_b32", VGPR_32, "ds_mskor_b32">; 828defm DS_WRXCHG_RTN_B32 : DS_1A1D_RET <0x2d, "ds_wrxchg_rtn_b32", VGPR_32>; 829defm DS_WRXCHG2_RTN_B32 : DS_1A2D_RET < 830 0x2e, "ds_wrxchg2_rtn_b32", VReg_64, "", VGPR_32 831>; 832defm DS_WRXCHG2ST64_RTN_B32 : DS_1A2D_RET < 833 0x2f, "ds_wrxchg2st64_rtn_b32", VReg_64, "", VGPR_32 834>; 835defm DS_CMPST_RTN_B32 : DS_1A2D_RET <0x30, "ds_cmpst_rtn_b32", VGPR_32, "ds_cmpst_b32">; 836defm DS_CMPST_RTN_F32 : DS_1A2D_RET <0x31, "ds_cmpst_rtn_f32", VGPR_32, "ds_cmpst_f32">; 837defm DS_MIN_RTN_F32 : DS_1A2D_RET <0x32, "ds_min_rtn_f32", VGPR_32, "ds_min_f32">; 838defm DS_MAX_RTN_F32 : DS_1A2D_RET <0x33, "ds_max_rtn_f32", VGPR_32, "ds_max_f32">; 839defm DS_SWIZZLE_B32 : DS_1A_RET <0x35, "ds_swizzle_b32", VGPR_32>; 840let mayStore = 0 in { 841defm DS_READ_B32 : DS_1A_RET <0x36, "ds_read_b32", VGPR_32>; 842defm DS_READ2_B32 : DS_1A_Off8_RET <0x37, "ds_read2_b32", VReg_64>; 843defm DS_READ2ST64_B32 : DS_1A_Off8_RET <0x38, "ds_read2st64_b32", VReg_64>; 844defm DS_READ_I8 : DS_1A_RET <0x39, "ds_read_i8", VGPR_32>; 845defm DS_READ_U8 : DS_1A_RET <0x3a, "ds_read_u8", VGPR_32>; 846defm DS_READ_I16 : DS_1A_RET <0x3b, "ds_read_i16", VGPR_32>; 847defm DS_READ_U16 : DS_1A_RET <0x3c, "ds_read_u16", VGPR_32>; 848} 849defm DS_CONSUME : DS_0A_RET <0x3d, "ds_consume">; 850defm DS_APPEND : DS_0A_RET <0x3e, "ds_append">; 851defm DS_ORDERED_COUNT : DS_1A_RET_GDS <0x3f, "ds_ordered_count">; 852defm DS_ADD_U64 : DS_1A1D_NORET <0x40, "ds_add_u64", VReg_64>; 853defm DS_SUB_U64 : DS_1A1D_NORET <0x41, "ds_sub_u64", VReg_64>; 854defm DS_RSUB_U64 : DS_1A1D_NORET <0x42, "ds_rsub_u64", VReg_64>; 855defm DS_INC_U64 : DS_1A1D_NORET <0x43, "ds_inc_u64", VReg_64>; 856defm DS_DEC_U64 : DS_1A1D_NORET <0x44, "ds_dec_u64", VReg_64>; 857defm DS_MIN_I64 : DS_1A1D_NORET <0x45, "ds_min_i64", VReg_64>; 858defm DS_MAX_I64 : DS_1A1D_NORET <0x46, "ds_max_i64", VReg_64>; 859defm DS_MIN_U64 : DS_1A1D_NORET <0x47, "ds_min_u64", VReg_64>; 860defm DS_MAX_U64 : DS_1A1D_NORET <0x48, "ds_max_u64", VReg_64>; 861defm DS_AND_B64 : DS_1A1D_NORET <0x49, "ds_and_b64", VReg_64>; 862defm DS_OR_B64 : DS_1A1D_NORET <0x4a, "ds_or_b64", VReg_64>; 863defm DS_XOR_B64 : DS_1A1D_NORET <0x4b, "ds_xor_b64", VReg_64>; 864defm DS_MSKOR_B64 : DS_1A2D_NORET <0x4c, "ds_mskor_b64", VReg_64>; 865let mayLoad = 0 in { 866defm DS_WRITE_B64 : DS_1A1D_NORET <0x4d, "ds_write_b64", VReg_64>; 867defm DS_WRITE2_B64 : DS_1A1D_Off8_NORET <0x4E, "ds_write2_b64", VReg_64>; 868defm DS_WRITE2ST64_B64 : DS_1A1D_Off8_NORET <0x4f, "ds_write2st64_b64", VReg_64>; 869} 870defm DS_CMPST_B64 : DS_1A2D_NORET <0x50, "ds_cmpst_b64", VReg_64>; 871defm DS_CMPST_F64 : DS_1A2D_NORET <0x51, "ds_cmpst_f64", VReg_64>; 872defm DS_MIN_F64 : DS_1A1D_NORET <0x52, "ds_min_f64", VReg_64>; 873defm DS_MAX_F64 : DS_1A1D_NORET <0x53, "ds_max_f64", VReg_64>; 874 875defm DS_ADD_RTN_U64 : DS_1A1D_RET <0x60, "ds_add_rtn_u64", VReg_64, "ds_add_u64">; 876defm DS_SUB_RTN_U64 : DS_1A1D_RET <0x61, "ds_sub_rtn_u64", VReg_64, "ds_sub_u64">; 877defm DS_RSUB_RTN_U64 : DS_1A1D_RET <0x62, "ds_rsub_rtn_u64", VReg_64, "ds_rsub_u64">; 878defm DS_INC_RTN_U64 : DS_1A1D_RET <0x63, "ds_inc_rtn_u64", VReg_64, "ds_inc_u64">; 879defm DS_DEC_RTN_U64 : DS_1A1D_RET <0x64, "ds_dec_rtn_u64", VReg_64, "ds_dec_u64">; 880defm DS_MIN_RTN_I64 : DS_1A1D_RET <0x65, "ds_min_rtn_i64", VReg_64, "ds_min_i64">; 881defm DS_MAX_RTN_I64 : DS_1A1D_RET <0x66, "ds_max_rtn_i64", VReg_64, "ds_max_i64">; 882defm DS_MIN_RTN_U64 : DS_1A1D_RET <0x67, "ds_min_rtn_u64", VReg_64, "ds_min_u64">; 883defm DS_MAX_RTN_U64 : DS_1A1D_RET <0x68, "ds_max_rtn_u64", VReg_64, "ds_max_u64">; 884defm DS_AND_RTN_B64 : DS_1A1D_RET <0x69, "ds_and_rtn_b64", VReg_64, "ds_and_b64">; 885defm DS_OR_RTN_B64 : DS_1A1D_RET <0x6a, "ds_or_rtn_b64", VReg_64, "ds_or_b64">; 886defm DS_XOR_RTN_B64 : DS_1A1D_RET <0x6b, "ds_xor_rtn_b64", VReg_64, "ds_xor_b64">; 887defm DS_MSKOR_RTN_B64 : DS_1A2D_RET <0x6c, "ds_mskor_rtn_b64", VReg_64, "ds_mskor_b64">; 888defm DS_WRXCHG_RTN_B64 : DS_1A1D_RET <0x6d, "ds_wrxchg_rtn_b64", VReg_64, "ds_wrxchg_b64">; 889defm DS_WRXCHG2_RTN_B64 : DS_1A2D_RET <0x6e, "ds_wrxchg2_rtn_b64", VReg_128, "ds_wrxchg2_b64", VReg_64>; 890defm DS_WRXCHG2ST64_RTN_B64 : DS_1A2D_RET <0x6f, "ds_wrxchg2st64_rtn_b64", VReg_128, "ds_wrxchg2st64_b64", VReg_64>; 891defm DS_CMPST_RTN_B64 : DS_1A2D_RET <0x70, "ds_cmpst_rtn_b64", VReg_64, "ds_cmpst_b64">; 892defm DS_CMPST_RTN_F64 : DS_1A2D_RET <0x71, "ds_cmpst_rtn_f64", VReg_64, "ds_cmpst_f64">; 893defm DS_MIN_RTN_F64 : DS_1A1D_RET <0x72, "ds_min_rtn_f64", VReg_64, "ds_min_f64">; 894defm DS_MAX_RTN_F64 : DS_1A1D_RET <0x73, "ds_max_rtn_f64", VReg_64, "ds_max_f64">; 895 896let mayStore = 0 in { 897defm DS_READ_B64 : DS_1A_RET <0x76, "ds_read_b64", VReg_64>; 898defm DS_READ2_B64 : DS_1A_Off8_RET <0x77, "ds_read2_b64", VReg_128>; 899defm DS_READ2ST64_B64 : DS_1A_Off8_RET <0x78, "ds_read2st64_b64", VReg_128>; 900} 901 902defm DS_ADD_SRC2_U32 : DS_1A <0x80, "ds_add_src2_u32">; 903defm DS_SUB_SRC2_U32 : DS_1A <0x81, "ds_sub_src2_u32">; 904defm DS_RSUB_SRC2_U32 : DS_1A <0x82, "ds_rsub_src2_u32">; 905defm DS_INC_SRC2_U32 : DS_1A <0x83, "ds_inc_src2_u32">; 906defm DS_DEC_SRC2_U32 : DS_1A <0x84, "ds_dec_src2_u32">; 907defm DS_MIN_SRC2_I32 : DS_1A <0x85, "ds_min_src2_i32">; 908defm DS_MAX_SRC2_I32 : DS_1A <0x86, "ds_max_src2_i32">; 909defm DS_MIN_SRC2_U32 : DS_1A <0x87, "ds_min_src2_u32">; 910defm DS_MAX_SRC2_U32 : DS_1A <0x88, "ds_max_src2_u32">; 911defm DS_AND_SRC2_B32 : DS_1A <0x89, "ds_and_src_b32">; 912defm DS_OR_SRC2_B32 : DS_1A <0x8a, "ds_or_src2_b32">; 913defm DS_XOR_SRC2_B32 : DS_1A <0x8b, "ds_xor_src2_b32">; 914defm DS_WRITE_SRC2_B32 : DS_1A <0x8c, "ds_write_src2_b32">; 915 916defm DS_MIN_SRC2_F32 : DS_1A <0x92, "ds_min_src2_f32">; 917defm DS_MAX_SRC2_F32 : DS_1A <0x93, "ds_max_src2_f32">; 918 919defm DS_ADD_SRC2_U64 : DS_1A <0xc0, "ds_add_src2_u64">; 920defm DS_SUB_SRC2_U64 : DS_1A <0xc1, "ds_sub_src2_u64">; 921defm DS_RSUB_SRC2_U64 : DS_1A <0xc2, "ds_rsub_src2_u64">; 922defm DS_INC_SRC2_U64 : DS_1A <0xc3, "ds_inc_src2_u64">; 923defm DS_DEC_SRC2_U64 : DS_1A <0xc4, "ds_dec_src2_u64">; 924defm DS_MIN_SRC2_I64 : DS_1A <0xc5, "ds_min_src2_i64">; 925defm DS_MAX_SRC2_I64 : DS_1A <0xc6, "ds_max_src2_i64">; 926defm DS_MIN_SRC2_U64 : DS_1A <0xc7, "ds_min_src2_u64">; 927defm DS_MAX_SRC2_U64 : DS_1A <0xc8, "ds_max_src2_u64">; 928defm DS_AND_SRC2_B64 : DS_1A <0xc9, "ds_and_src2_b64">; 929defm DS_OR_SRC2_B64 : DS_1A <0xca, "ds_or_src2_b64">; 930defm DS_XOR_SRC2_B64 : DS_1A <0xcb, "ds_xor_src2_b64">; 931defm DS_WRITE_SRC2_B64 : DS_1A <0xcc, "ds_write_src2_b64">; 932 933defm DS_MIN_SRC2_F64 : DS_1A <0xd2, "ds_min_src2_f64">; 934defm DS_MAX_SRC2_F64 : DS_1A <0xd3, "ds_max_src2_f64">; 935 936//===----------------------------------------------------------------------===// 937// MUBUF Instructions 938//===----------------------------------------------------------------------===// 939 940defm BUFFER_LOAD_FORMAT_X : MUBUF_Load_Helper < 941 mubuf<0x00>, "buffer_load_format_x", VGPR_32 942>; 943defm BUFFER_LOAD_FORMAT_XY : MUBUF_Load_Helper < 944 mubuf<0x01>, "buffer_load_format_xy", VReg_64 945>; 946defm BUFFER_LOAD_FORMAT_XYZ : MUBUF_Load_Helper < 947 mubuf<0x02>, "buffer_load_format_xyz", VReg_96 948>; 949defm BUFFER_LOAD_FORMAT_XYZW : MUBUF_Load_Helper < 950 mubuf<0x03>, "buffer_load_format_xyzw", VReg_128 951>; 952// Without mayLoad and hasSideEffects, TableGen complains about the pattern 953// matching llvm.amdgcn.buffer.store.format. Eventually, we'll need a way 954// to express the effects of the intrinsic more precisely. 955let mayLoad = 1, hasSideEffects = 1 in { 956 defm BUFFER_STORE_FORMAT_X : MUBUF_Store_Helper < 957 mubuf<0x04>, "buffer_store_format_x", VGPR_32 958 >; 959 defm BUFFER_STORE_FORMAT_XY : MUBUF_Store_Helper < 960 mubuf<0x05>, "buffer_store_format_xy", VReg_64 961 >; 962 defm BUFFER_STORE_FORMAT_XYZ : MUBUF_Store_Helper < 963 mubuf<0x06>, "buffer_store_format_xyz", VReg_96 964 >; 965 defm BUFFER_STORE_FORMAT_XYZW : MUBUF_Store_Helper < 966 mubuf<0x07>, "buffer_store_format_xyzw", VReg_128 967 >; 968} 969defm BUFFER_LOAD_UBYTE : MUBUF_Load_Helper < 970 mubuf<0x08, 0x10>, "buffer_load_ubyte", VGPR_32, i32, az_extloadi8_global 971>; 972defm BUFFER_LOAD_SBYTE : MUBUF_Load_Helper < 973 mubuf<0x09, 0x11>, "buffer_load_sbyte", VGPR_32, i32, sextloadi8_global 974>; 975defm BUFFER_LOAD_USHORT : MUBUF_Load_Helper < 976 mubuf<0x0a, 0x12>, "buffer_load_ushort", VGPR_32, i32, az_extloadi16_global 977>; 978defm BUFFER_LOAD_SSHORT : MUBUF_Load_Helper < 979 mubuf<0x0b, 0x13>, "buffer_load_sshort", VGPR_32, i32, sextloadi16_global 980>; 981defm BUFFER_LOAD_DWORD : MUBUF_Load_Helper < 982 mubuf<0x0c, 0x14>, "buffer_load_dword", VGPR_32, i32, mubuf_load 983>; 984defm BUFFER_LOAD_DWORDX2 : MUBUF_Load_Helper < 985 mubuf<0x0d, 0x15>, "buffer_load_dwordx2", VReg_64, v2i32, mubuf_load 986>; 987defm BUFFER_LOAD_DWORDX4 : MUBUF_Load_Helper < 988 mubuf<0x0e, 0x17>, "buffer_load_dwordx4", VReg_128, v4i32, mubuf_load 989>; 990 991defm BUFFER_STORE_BYTE : MUBUF_Store_Helper < 992 mubuf<0x18>, "buffer_store_byte", VGPR_32, i32, truncstorei8_global 993>; 994 995defm BUFFER_STORE_SHORT : MUBUF_Store_Helper < 996 mubuf<0x1a>, "buffer_store_short", VGPR_32, i32, truncstorei16_global 997>; 998 999defm BUFFER_STORE_DWORD : MUBUF_Store_Helper < 1000 mubuf<0x1c>, "buffer_store_dword", VGPR_32, i32, global_store 1001>; 1002 1003defm BUFFER_STORE_DWORDX2 : MUBUF_Store_Helper < 1004 mubuf<0x1d>, "buffer_store_dwordx2", VReg_64, v2i32, global_store 1005>; 1006 1007defm BUFFER_STORE_DWORDX4 : MUBUF_Store_Helper < 1008 mubuf<0x1e, 0x1f>, "buffer_store_dwordx4", VReg_128, v4i32, global_store 1009>; 1010 1011defm BUFFER_ATOMIC_SWAP : MUBUF_Atomic < 1012 mubuf<0x30, 0x40>, "buffer_atomic_swap", VGPR_32, i32, atomic_swap_global 1013>; 1014defm BUFFER_ATOMIC_CMPSWAP : MUBUF_Atomic < 1015 mubuf<0x31, 0x41>, "buffer_atomic_cmpswap", VReg_64, v2i32, null_frag 1016>; 1017defm BUFFER_ATOMIC_ADD : MUBUF_Atomic < 1018 mubuf<0x32, 0x42>, "buffer_atomic_add", VGPR_32, i32, atomic_add_global 1019>; 1020defm BUFFER_ATOMIC_SUB : MUBUF_Atomic < 1021 mubuf<0x33, 0x43>, "buffer_atomic_sub", VGPR_32, i32, atomic_sub_global 1022>; 1023//def BUFFER_ATOMIC_RSUB : MUBUF_ <mubuf<0x34>, "buffer_atomic_rsub", []>; // isn't on CI & VI 1024defm BUFFER_ATOMIC_SMIN : MUBUF_Atomic < 1025 mubuf<0x35, 0x44>, "buffer_atomic_smin", VGPR_32, i32, atomic_min_global 1026>; 1027defm BUFFER_ATOMIC_UMIN : MUBUF_Atomic < 1028 mubuf<0x36, 0x45>, "buffer_atomic_umin", VGPR_32, i32, atomic_umin_global 1029>; 1030defm BUFFER_ATOMIC_SMAX : MUBUF_Atomic < 1031 mubuf<0x37, 0x46>, "buffer_atomic_smax", VGPR_32, i32, atomic_max_global 1032>; 1033defm BUFFER_ATOMIC_UMAX : MUBUF_Atomic < 1034 mubuf<0x38, 0x47>, "buffer_atomic_umax", VGPR_32, i32, atomic_umax_global 1035>; 1036defm BUFFER_ATOMIC_AND : MUBUF_Atomic < 1037 mubuf<0x39, 0x48>, "buffer_atomic_and", VGPR_32, i32, atomic_and_global 1038>; 1039defm BUFFER_ATOMIC_OR : MUBUF_Atomic < 1040 mubuf<0x3a, 0x49>, "buffer_atomic_or", VGPR_32, i32, atomic_or_global 1041>; 1042defm BUFFER_ATOMIC_XOR : MUBUF_Atomic < 1043 mubuf<0x3b, 0x4a>, "buffer_atomic_xor", VGPR_32, i32, atomic_xor_global 1044>; 1045//def BUFFER_ATOMIC_INC : MUBUF_ <mubuf<0x3c, 0x4b>, "buffer_atomic_inc", []>; 1046//def BUFFER_ATOMIC_DEC : MUBUF_ <mubuf<0x3d, 0x4c>, "buffer_atomic_dec", []>; 1047//def BUFFER_ATOMIC_FCMPSWAP : MUBUF_ <mubuf<0x3e>, "buffer_atomic_fcmpswap", []>; // isn't on VI 1048//def BUFFER_ATOMIC_FMIN : MUBUF_ <mubuf<0x3f>, "buffer_atomic_fmin", []>; // isn't on VI 1049//def BUFFER_ATOMIC_FMAX : MUBUF_ <mubuf<0x40>, "buffer_atomic_fmax", []>; // isn't on VI 1050//def BUFFER_ATOMIC_SWAP_X2 : MUBUF_X2 <mubuf<0x50, 0x60>, "buffer_atomic_swap_x2", []>; 1051//def BUFFER_ATOMIC_CMPSWAP_X2 : MUBUF_X2 <mubuf<0x51, 0x61>, "buffer_atomic_cmpswap_x2", []>; 1052//def BUFFER_ATOMIC_ADD_X2 : MUBUF_X2 <mubuf<0x52, 0x62>, "buffer_atomic_add_x2", []>; 1053//def BUFFER_ATOMIC_SUB_X2 : MUBUF_X2 <mubuf<0x53, 0x63>, "buffer_atomic_sub_x2", []>; 1054//def BUFFER_ATOMIC_RSUB_X2 : MUBUF_X2 <mubuf<0x54>, "buffer_atomic_rsub_x2", []>; // isn't on CI & VI 1055//def BUFFER_ATOMIC_SMIN_X2 : MUBUF_X2 <mubuf<0x55, 0x64>, "buffer_atomic_smin_x2", []>; 1056//def BUFFER_ATOMIC_UMIN_X2 : MUBUF_X2 <mubuf<0x56, 0x65>, "buffer_atomic_umin_x2", []>; 1057//def BUFFER_ATOMIC_SMAX_X2 : MUBUF_X2 <mubuf<0x57, 0x66>, "buffer_atomic_smax_x2", []>; 1058//def BUFFER_ATOMIC_UMAX_X2 : MUBUF_X2 <mubuf<0x58, 0x67>, "buffer_atomic_umax_x2", []>; 1059//def BUFFER_ATOMIC_AND_X2 : MUBUF_X2 <mubuf<0x59, 0x68>, "buffer_atomic_and_x2", []>; 1060//def BUFFER_ATOMIC_OR_X2 : MUBUF_X2 <mubuf<0x5a, 0x69>, "buffer_atomic_or_x2", []>; 1061//def BUFFER_ATOMIC_XOR_X2 : MUBUF_X2 <mubuf<0x5b, 0x6a>, "buffer_atomic_xor_x2", []>; 1062//def BUFFER_ATOMIC_INC_X2 : MUBUF_X2 <mubuf<0x5c, 0x6b>, "buffer_atomic_inc_x2", []>; 1063//def BUFFER_ATOMIC_DEC_X2 : MUBUF_X2 <mubuf<0x5d, 0x6c>, "buffer_atomic_dec_x2", []>; 1064//def BUFFER_ATOMIC_FCMPSWAP_X2 : MUBUF_X2 <mubuf<0x5e>, "buffer_atomic_fcmpswap_x2", []>; // isn't on VI 1065//def BUFFER_ATOMIC_FMIN_X2 : MUBUF_X2 <mubuf<0x5f>, "buffer_atomic_fmin_x2", []>; // isn't on VI 1066//def BUFFER_ATOMIC_FMAX_X2 : MUBUF_X2 <mubuf<0x60>, "buffer_atomic_fmax_x2", []>; // isn't on VI 1067 1068let SubtargetPredicate = isSI, DisableVIDecoder = 1 in { 1069defm BUFFER_WBINVL1_SC : MUBUF_Invalidate <mubuf<0x70>, "buffer_wbinvl1_sc", int_amdgcn_buffer_wbinvl1_sc>; // isn't on CI & VI 1070} 1071 1072defm BUFFER_WBINVL1 : MUBUF_Invalidate <mubuf<0x71, 0x3e>, "buffer_wbinvl1", int_amdgcn_buffer_wbinvl1>; 1073 1074//===----------------------------------------------------------------------===// 1075// MTBUF Instructions 1076//===----------------------------------------------------------------------===// 1077 1078//def TBUFFER_LOAD_FORMAT_X : MTBUF_ <0x00000000, "tbuffer_load_format_x", []>; 1079//def TBUFFER_LOAD_FORMAT_XY : MTBUF_ <0x00000001, "tbuffer_load_format_xy", []>; 1080//def TBUFFER_LOAD_FORMAT_XYZ : MTBUF_ <0x00000002, "tbuffer_load_format_xyz", []>; 1081defm TBUFFER_LOAD_FORMAT_XYZW : MTBUF_Load_Helper <0x00000003, "tbuffer_load_format_xyzw", VReg_128>; 1082defm TBUFFER_STORE_FORMAT_X : MTBUF_Store_Helper <0x00000004, "tbuffer_store_format_x", VGPR_32>; 1083defm TBUFFER_STORE_FORMAT_XY : MTBUF_Store_Helper <0x00000005, "tbuffer_store_format_xy", VReg_64>; 1084defm TBUFFER_STORE_FORMAT_XYZ : MTBUF_Store_Helper <0x00000006, "tbuffer_store_format_xyz", VReg_128>; 1085defm TBUFFER_STORE_FORMAT_XYZW : MTBUF_Store_Helper <0x00000007, "tbuffer_store_format_xyzw", VReg_128>; 1086 1087//===----------------------------------------------------------------------===// 1088// MIMG Instructions 1089//===----------------------------------------------------------------------===// 1090 1091defm IMAGE_LOAD : MIMG_NoSampler <0x00000000, "image_load">; 1092defm IMAGE_LOAD_MIP : MIMG_NoSampler <0x00000001, "image_load_mip">; 1093//def IMAGE_LOAD_PCK : MIMG_NoPattern_ <"image_load_pck", 0x00000002>; 1094//def IMAGE_LOAD_PCK_SGN : MIMG_NoPattern_ <"image_load_pck_sgn", 0x00000003>; 1095//def IMAGE_LOAD_MIP_PCK : MIMG_NoPattern_ <"image_load_mip_pck", 0x00000004>; 1096//def IMAGE_LOAD_MIP_PCK_SGN : MIMG_NoPattern_ <"image_load_mip_pck_sgn", 0x00000005>; 1097defm IMAGE_STORE : MIMG_Store <0x00000008, "image_store">; 1098defm IMAGE_STORE_MIP : MIMG_Store <0x00000009, "image_store_mip">; 1099//def IMAGE_STORE_PCK : MIMG_NoPattern_ <"image_store_pck", 0x0000000a>; 1100//def IMAGE_STORE_MIP_PCK : MIMG_NoPattern_ <"image_store_mip_pck", 0x0000000b>; 1101defm IMAGE_GET_RESINFO : MIMG_NoSampler <0x0000000e, "image_get_resinfo">; 1102defm IMAGE_ATOMIC_SWAP : MIMG_Atomic <mimg<0x0f, 0x10>, "image_atomic_swap">; 1103defm IMAGE_ATOMIC_CMPSWAP : MIMG_Atomic <mimg<0x10, 0x11>, "image_atomic_cmpswap", VReg_64>; 1104defm IMAGE_ATOMIC_ADD : MIMG_Atomic <mimg<0x11, 0x12>, "image_atomic_add">; 1105defm IMAGE_ATOMIC_SUB : MIMG_Atomic <mimg<0x12, 0x13>, "image_atomic_sub">; 1106//def IMAGE_ATOMIC_RSUB : MIMG_NoPattern_ <"image_atomic_rsub", 0x00000013>; -- not on VI 1107defm IMAGE_ATOMIC_SMIN : MIMG_Atomic <mimg<0x14>, "image_atomic_smin">; 1108defm IMAGE_ATOMIC_UMIN : MIMG_Atomic <mimg<0x15>, "image_atomic_umin">; 1109defm IMAGE_ATOMIC_SMAX : MIMG_Atomic <mimg<0x16>, "image_atomic_smax">; 1110defm IMAGE_ATOMIC_UMAX : MIMG_Atomic <mimg<0x17>, "image_atomic_umax">; 1111defm IMAGE_ATOMIC_AND : MIMG_Atomic <mimg<0x18>, "image_atomic_and">; 1112defm IMAGE_ATOMIC_OR : MIMG_Atomic <mimg<0x19>, "image_atomic_or">; 1113defm IMAGE_ATOMIC_XOR : MIMG_Atomic <mimg<0x1a>, "image_atomic_xor">; 1114defm IMAGE_ATOMIC_INC : MIMG_Atomic <mimg<0x1b>, "image_atomic_inc">; 1115defm IMAGE_ATOMIC_DEC : MIMG_Atomic <mimg<0x1c>, "image_atomic_dec">; 1116//def IMAGE_ATOMIC_FCMPSWAP : MIMG_NoPattern_ <"image_atomic_fcmpswap", 0x0000001d>; -- not on VI 1117//def IMAGE_ATOMIC_FMIN : MIMG_NoPattern_ <"image_atomic_fmin", 0x0000001e>; -- not on VI 1118//def IMAGE_ATOMIC_FMAX : MIMG_NoPattern_ <"image_atomic_fmax", 0x0000001f>; -- not on VI 1119defm IMAGE_SAMPLE : MIMG_Sampler_WQM <0x00000020, "image_sample">; 1120defm IMAGE_SAMPLE_CL : MIMG_Sampler_WQM <0x00000021, "image_sample_cl">; 1121defm IMAGE_SAMPLE_D : MIMG_Sampler <0x00000022, "image_sample_d">; 1122defm IMAGE_SAMPLE_D_CL : MIMG_Sampler <0x00000023, "image_sample_d_cl">; 1123defm IMAGE_SAMPLE_L : MIMG_Sampler <0x00000024, "image_sample_l">; 1124defm IMAGE_SAMPLE_B : MIMG_Sampler_WQM <0x00000025, "image_sample_b">; 1125defm IMAGE_SAMPLE_B_CL : MIMG_Sampler_WQM <0x00000026, "image_sample_b_cl">; 1126defm IMAGE_SAMPLE_LZ : MIMG_Sampler <0x00000027, "image_sample_lz">; 1127defm IMAGE_SAMPLE_C : MIMG_Sampler_WQM <0x00000028, "image_sample_c">; 1128defm IMAGE_SAMPLE_C_CL : MIMG_Sampler_WQM <0x00000029, "image_sample_c_cl">; 1129defm IMAGE_SAMPLE_C_D : MIMG_Sampler <0x0000002a, "image_sample_c_d">; 1130defm IMAGE_SAMPLE_C_D_CL : MIMG_Sampler <0x0000002b, "image_sample_c_d_cl">; 1131defm IMAGE_SAMPLE_C_L : MIMG_Sampler <0x0000002c, "image_sample_c_l">; 1132defm IMAGE_SAMPLE_C_B : MIMG_Sampler_WQM <0x0000002d, "image_sample_c_b">; 1133defm IMAGE_SAMPLE_C_B_CL : MIMG_Sampler_WQM <0x0000002e, "image_sample_c_b_cl">; 1134defm IMAGE_SAMPLE_C_LZ : MIMG_Sampler <0x0000002f, "image_sample_c_lz">; 1135defm IMAGE_SAMPLE_O : MIMG_Sampler_WQM <0x00000030, "image_sample_o">; 1136defm IMAGE_SAMPLE_CL_O : MIMG_Sampler_WQM <0x00000031, "image_sample_cl_o">; 1137defm IMAGE_SAMPLE_D_O : MIMG_Sampler <0x00000032, "image_sample_d_o">; 1138defm IMAGE_SAMPLE_D_CL_O : MIMG_Sampler <0x00000033, "image_sample_d_cl_o">; 1139defm IMAGE_SAMPLE_L_O : MIMG_Sampler <0x00000034, "image_sample_l_o">; 1140defm IMAGE_SAMPLE_B_O : MIMG_Sampler_WQM <0x00000035, "image_sample_b_o">; 1141defm IMAGE_SAMPLE_B_CL_O : MIMG_Sampler_WQM <0x00000036, "image_sample_b_cl_o">; 1142defm IMAGE_SAMPLE_LZ_O : MIMG_Sampler <0x00000037, "image_sample_lz_o">; 1143defm IMAGE_SAMPLE_C_O : MIMG_Sampler_WQM <0x00000038, "image_sample_c_o">; 1144defm IMAGE_SAMPLE_C_CL_O : MIMG_Sampler_WQM <0x00000039, "image_sample_c_cl_o">; 1145defm IMAGE_SAMPLE_C_D_O : MIMG_Sampler <0x0000003a, "image_sample_c_d_o">; 1146defm IMAGE_SAMPLE_C_D_CL_O : MIMG_Sampler <0x0000003b, "image_sample_c_d_cl_o">; 1147defm IMAGE_SAMPLE_C_L_O : MIMG_Sampler <0x0000003c, "image_sample_c_l_o">; 1148defm IMAGE_SAMPLE_C_B_O : MIMG_Sampler_WQM <0x0000003d, "image_sample_c_b_o">; 1149defm IMAGE_SAMPLE_C_B_CL_O : MIMG_Sampler_WQM <0x0000003e, "image_sample_c_b_cl_o">; 1150defm IMAGE_SAMPLE_C_LZ_O : MIMG_Sampler <0x0000003f, "image_sample_c_lz_o">; 1151defm IMAGE_GATHER4 : MIMG_Gather_WQM <0x00000040, "image_gather4">; 1152defm IMAGE_GATHER4_CL : MIMG_Gather_WQM <0x00000041, "image_gather4_cl">; 1153defm IMAGE_GATHER4_L : MIMG_Gather <0x00000044, "image_gather4_l">; 1154defm IMAGE_GATHER4_B : MIMG_Gather_WQM <0x00000045, "image_gather4_b">; 1155defm IMAGE_GATHER4_B_CL : MIMG_Gather_WQM <0x00000046, "image_gather4_b_cl">; 1156defm IMAGE_GATHER4_LZ : MIMG_Gather <0x00000047, "image_gather4_lz">; 1157defm IMAGE_GATHER4_C : MIMG_Gather_WQM <0x00000048, "image_gather4_c">; 1158defm IMAGE_GATHER4_C_CL : MIMG_Gather_WQM <0x00000049, "image_gather4_c_cl">; 1159defm IMAGE_GATHER4_C_L : MIMG_Gather <0x0000004c, "image_gather4_c_l">; 1160defm IMAGE_GATHER4_C_B : MIMG_Gather_WQM <0x0000004d, "image_gather4_c_b">; 1161defm IMAGE_GATHER4_C_B_CL : MIMG_Gather_WQM <0x0000004e, "image_gather4_c_b_cl">; 1162defm IMAGE_GATHER4_C_LZ : MIMG_Gather <0x0000004f, "image_gather4_c_lz">; 1163defm IMAGE_GATHER4_O : MIMG_Gather_WQM <0x00000050, "image_gather4_o">; 1164defm IMAGE_GATHER4_CL_O : MIMG_Gather_WQM <0x00000051, "image_gather4_cl_o">; 1165defm IMAGE_GATHER4_L_O : MIMG_Gather <0x00000054, "image_gather4_l_o">; 1166defm IMAGE_GATHER4_B_O : MIMG_Gather_WQM <0x00000055, "image_gather4_b_o">; 1167defm IMAGE_GATHER4_B_CL_O : MIMG_Gather <0x00000056, "image_gather4_b_cl_o">; 1168defm IMAGE_GATHER4_LZ_O : MIMG_Gather <0x00000057, "image_gather4_lz_o">; 1169defm IMAGE_GATHER4_C_O : MIMG_Gather_WQM <0x00000058, "image_gather4_c_o">; 1170defm IMAGE_GATHER4_C_CL_O : MIMG_Gather_WQM <0x00000059, "image_gather4_c_cl_o">; 1171defm IMAGE_GATHER4_C_L_O : MIMG_Gather <0x0000005c, "image_gather4_c_l_o">; 1172defm IMAGE_GATHER4_C_B_O : MIMG_Gather_WQM <0x0000005d, "image_gather4_c_b_o">; 1173defm IMAGE_GATHER4_C_B_CL_O : MIMG_Gather_WQM <0x0000005e, "image_gather4_c_b_cl_o">; 1174defm IMAGE_GATHER4_C_LZ_O : MIMG_Gather <0x0000005f, "image_gather4_c_lz_o">; 1175defm IMAGE_GET_LOD : MIMG_Sampler_WQM <0x00000060, "image_get_lod">; 1176defm IMAGE_SAMPLE_CD : MIMG_Sampler <0x00000068, "image_sample_cd">; 1177defm IMAGE_SAMPLE_CD_CL : MIMG_Sampler <0x00000069, "image_sample_cd_cl">; 1178defm IMAGE_SAMPLE_C_CD : MIMG_Sampler <0x0000006a, "image_sample_c_cd">; 1179defm IMAGE_SAMPLE_C_CD_CL : MIMG_Sampler <0x0000006b, "image_sample_c_cd_cl">; 1180defm IMAGE_SAMPLE_CD_O : MIMG_Sampler <0x0000006c, "image_sample_cd_o">; 1181defm IMAGE_SAMPLE_CD_CL_O : MIMG_Sampler <0x0000006d, "image_sample_cd_cl_o">; 1182defm IMAGE_SAMPLE_C_CD_O : MIMG_Sampler <0x0000006e, "image_sample_c_cd_o">; 1183defm IMAGE_SAMPLE_C_CD_CL_O : MIMG_Sampler <0x0000006f, "image_sample_c_cd_cl_o">; 1184//def IMAGE_RSRC256 : MIMG_NoPattern_RSRC256 <"image_rsrc256", 0x0000007e>; 1185//def IMAGE_SAMPLER : MIMG_NoPattern_ <"image_sampler", 0x0000007f>; 1186 1187//===----------------------------------------------------------------------===// 1188// VOP1 Instructions 1189//===----------------------------------------------------------------------===// 1190 1191let vdst = 0, src0 = 0, VOPAsmPrefer32Bit = 1 in { 1192defm V_NOP : VOP1Inst <vop1<0x0>, "v_nop", VOP_NONE>; 1193} 1194 1195let isMoveImm = 1, isReMaterializable = 1, isAsCheapAsAMove = 1 in { 1196defm V_MOV_B32 : VOP1Inst <vop1<0x1>, "v_mov_b32", VOP_I32_I32>; 1197} // End isMoveImm = 1 1198 1199let Uses = [EXEC] in { 1200 1201// FIXME: Specify SchedRW for READFIRSTLANE_B32 1202 1203def V_READFIRSTLANE_B32 : VOP1 < 1204 0x00000002, 1205 (outs SReg_32:$vdst), 1206 (ins VGPR_32:$src0), 1207 "v_readfirstlane_b32 $vdst, $src0", 1208 [] 1209>; 1210 1211} 1212 1213let SchedRW = [WriteQuarterRate32] in { 1214 1215defm V_CVT_I32_F64 : VOP1Inst <vop1<0x3>, "v_cvt_i32_f64", 1216 VOP_I32_F64, fp_to_sint 1217>; 1218defm V_CVT_F64_I32 : VOP1Inst <vop1<0x4>, "v_cvt_f64_i32", 1219 VOP_F64_I32, sint_to_fp 1220>; 1221defm V_CVT_F32_I32 : VOP1Inst <vop1<0x5>, "v_cvt_f32_i32", 1222 VOP_F32_I32, sint_to_fp 1223>; 1224defm V_CVT_F32_U32 : VOP1Inst <vop1<0x6>, "v_cvt_f32_u32", 1225 VOP_F32_I32, uint_to_fp 1226>; 1227defm V_CVT_U32_F32 : VOP1Inst <vop1<0x7>, "v_cvt_u32_f32", 1228 VOP_I32_F32, fp_to_uint 1229>; 1230defm V_CVT_I32_F32 : VOP1Inst <vop1<0x8>, "v_cvt_i32_f32", 1231 VOP_I32_F32, fp_to_sint 1232>; 1233defm V_CVT_F16_F32 : VOP1Inst <vop1<0xa>, "v_cvt_f16_f32", 1234 VOP_I32_F32, fp_to_f16 1235>; 1236defm V_CVT_F32_F16 : VOP1Inst <vop1<0xb>, "v_cvt_f32_f16", 1237 VOP_F32_I32, f16_to_fp 1238>; 1239defm V_CVT_RPI_I32_F32 : VOP1Inst <vop1<0xc>, "v_cvt_rpi_i32_f32", 1240 VOP_I32_F32, cvt_rpi_i32_f32>; 1241defm V_CVT_FLR_I32_F32 : VOP1Inst <vop1<0xd>, "v_cvt_flr_i32_f32", 1242 VOP_I32_F32, cvt_flr_i32_f32>; 1243defm V_CVT_OFF_F32_I4 : VOP1Inst <vop1<0x0e>, "v_cvt_off_f32_i4", VOP_F32_I32>; 1244defm V_CVT_F32_F64 : VOP1Inst <vop1<0xf>, "v_cvt_f32_f64", 1245 VOP_F32_F64, fround 1246>; 1247defm V_CVT_F64_F32 : VOP1Inst <vop1<0x10>, "v_cvt_f64_f32", 1248 VOP_F64_F32, fextend 1249>; 1250defm V_CVT_F32_UBYTE0 : VOP1Inst <vop1<0x11>, "v_cvt_f32_ubyte0", 1251 VOP_F32_I32, AMDGPUcvt_f32_ubyte0 1252>; 1253defm V_CVT_F32_UBYTE1 : VOP1Inst <vop1<0x12>, "v_cvt_f32_ubyte1", 1254 VOP_F32_I32, AMDGPUcvt_f32_ubyte1 1255>; 1256defm V_CVT_F32_UBYTE2 : VOP1Inst <vop1<0x13>, "v_cvt_f32_ubyte2", 1257 VOP_F32_I32, AMDGPUcvt_f32_ubyte2 1258>; 1259defm V_CVT_F32_UBYTE3 : VOP1Inst <vop1<0x14>, "v_cvt_f32_ubyte3", 1260 VOP_F32_I32, AMDGPUcvt_f32_ubyte3 1261>; 1262defm V_CVT_U32_F64 : VOP1Inst <vop1<0x15>, "v_cvt_u32_f64", 1263 VOP_I32_F64, fp_to_uint 1264>; 1265defm V_CVT_F64_U32 : VOP1Inst <vop1<0x16>, "v_cvt_f64_u32", 1266 VOP_F64_I32, uint_to_fp 1267>; 1268 1269} // End SchedRW = [WriteQuarterRate32] 1270 1271defm V_FRACT_F32 : VOP1Inst <vop1<0x20, 0x1b>, "v_fract_f32", 1272 VOP_F32_F32, AMDGPUfract 1273>; 1274defm V_TRUNC_F32 : VOP1Inst <vop1<0x21, 0x1c>, "v_trunc_f32", 1275 VOP_F32_F32, ftrunc 1276>; 1277defm V_CEIL_F32 : VOP1Inst <vop1<0x22, 0x1d>, "v_ceil_f32", 1278 VOP_F32_F32, fceil 1279>; 1280defm V_RNDNE_F32 : VOP1Inst <vop1<0x23, 0x1e>, "v_rndne_f32", 1281 VOP_F32_F32, frint 1282>; 1283defm V_FLOOR_F32 : VOP1Inst <vop1<0x24, 0x1f>, "v_floor_f32", 1284 VOP_F32_F32, ffloor 1285>; 1286defm V_EXP_F32 : VOP1Inst <vop1<0x25, 0x20>, "v_exp_f32", 1287 VOP_F32_F32, fexp2 1288>; 1289 1290let SchedRW = [WriteQuarterRate32] in { 1291 1292defm V_LOG_F32 : VOP1Inst <vop1<0x27, 0x21>, "v_log_f32", 1293 VOP_F32_F32, flog2 1294>; 1295defm V_RCP_F32 : VOP1Inst <vop1<0x2a, 0x22>, "v_rcp_f32", 1296 VOP_F32_F32, AMDGPUrcp 1297>; 1298defm V_RCP_IFLAG_F32 : VOP1Inst <vop1<0x2b, 0x23>, "v_rcp_iflag_f32", 1299 VOP_F32_F32 1300>; 1301defm V_RSQ_F32 : VOP1Inst <vop1<0x2e, 0x24>, "v_rsq_f32", 1302 VOP_F32_F32, AMDGPUrsq 1303>; 1304 1305} // End SchedRW = [WriteQuarterRate32] 1306 1307let SchedRW = [WriteDouble] in { 1308 1309defm V_RCP_F64 : VOP1Inst <vop1<0x2f, 0x25>, "v_rcp_f64", 1310 VOP_F64_F64, AMDGPUrcp 1311>; 1312defm V_RSQ_F64 : VOP1Inst <vop1<0x31, 0x26>, "v_rsq_f64", 1313 VOP_F64_F64, AMDGPUrsq 1314>; 1315 1316} // End SchedRW = [WriteDouble]; 1317 1318defm V_SQRT_F32 : VOP1Inst <vop1<0x33, 0x27>, "v_sqrt_f32", 1319 VOP_F32_F32, fsqrt 1320>; 1321 1322let SchedRW = [WriteDouble] in { 1323 1324defm V_SQRT_F64 : VOP1Inst <vop1<0x34, 0x28>, "v_sqrt_f64", 1325 VOP_F64_F64, fsqrt 1326>; 1327 1328} // End SchedRW = [WriteDouble] 1329 1330let SchedRW = [WriteQuarterRate32] in { 1331 1332defm V_SIN_F32 : VOP1Inst <vop1<0x35, 0x29>, "v_sin_f32", 1333 VOP_F32_F32, AMDGPUsin 1334>; 1335defm V_COS_F32 : VOP1Inst <vop1<0x36, 0x2a>, "v_cos_f32", 1336 VOP_F32_F32, AMDGPUcos 1337>; 1338 1339} // End SchedRW = [WriteQuarterRate32] 1340 1341defm V_NOT_B32 : VOP1Inst <vop1<0x37, 0x2b>, "v_not_b32", VOP_I32_I32>; 1342defm V_BFREV_B32 : VOP1Inst <vop1<0x38, 0x2c>, "v_bfrev_b32", VOP_I32_I32>; 1343defm V_FFBH_U32 : VOP1Inst <vop1<0x39, 0x2d>, "v_ffbh_u32", VOP_I32_I32>; 1344defm V_FFBL_B32 : VOP1Inst <vop1<0x3a, 0x2e>, "v_ffbl_b32", VOP_I32_I32>; 1345defm V_FFBH_I32 : VOP1Inst <vop1<0x3b, 0x2f>, "v_ffbh_i32", VOP_I32_I32>; 1346defm V_FREXP_EXP_I32_F64 : VOP1Inst <vop1<0x3c,0x30>, "v_frexp_exp_i32_f64", 1347 VOP_I32_F64 1348>; 1349 1350let SchedRW = [WriteDoubleAdd] in { 1351defm V_FREXP_MANT_F64 : VOP1Inst <vop1<0x3d, 0x31>, "v_frexp_mant_f64", 1352 VOP_F64_F64, int_amdgcn_frexp_mant 1353>; 1354 1355defm V_FRACT_F64 : VOP1Inst <vop1<0x3e, 0x32>, "v_fract_f64", 1356 VOP_F64_F64 1357>; 1358} // End SchedRW = [WriteDoubleAdd] 1359 1360 1361defm V_FREXP_EXP_I32_F32 : VOP1Inst <vop1<0x3f, 0x33>, "v_frexp_exp_i32_f32", 1362 VOP_I32_F32 1363>; 1364defm V_FREXP_MANT_F32 : VOP1Inst <vop1<0x40, 0x34>, "v_frexp_mant_f32", 1365 VOP_F32_F32, int_amdgcn_frexp_mant 1366>; 1367let vdst = 0, src0 = 0, VOPAsmPrefer32Bit = 1 in { 1368defm V_CLREXCP : VOP1Inst <vop1<0x41,0x35>, "v_clrexcp", VOP_NONE>; 1369} 1370 1371let Uses = [M0, EXEC] in { 1372defm V_MOVRELD_B32 : VOP1Inst <vop1<0x42, 0x36>, "v_movreld_b32", VOP_I32_I32>; 1373defm V_MOVRELS_B32 : VOP1Inst <vop1<0x43, 0x37>, "v_movrels_b32", VOP_I32_I32>; 1374defm V_MOVRELSD_B32 : VOP1Inst <vop1<0x44, 0x38>, "v_movrelsd_b32", VOP_I32_I32>; 1375} // End Uses = [M0, EXEC] 1376 1377// These instruction only exist on SI and CI 1378let SubtargetPredicate = isSICI in { 1379 1380let SchedRW = [WriteQuarterRate32] in { 1381 1382defm V_MOV_FED_B32 : VOP1InstSI <vop1<0x9>, "v_mov_fed_b32", VOP_I32_I32>; 1383defm V_LOG_CLAMP_F32 : VOP1InstSI <vop1<0x26>, "v_log_clamp_f32", 1384 VOP_F32_F32, int_amdgcn_log_clamp>; 1385defm V_RCP_CLAMP_F32 : VOP1InstSI <vop1<0x28>, "v_rcp_clamp_f32", VOP_F32_F32>; 1386defm V_RCP_LEGACY_F32 : VOP1InstSI <vop1<0x29>, "v_rcp_legacy_f32", VOP_F32_F32>; 1387defm V_RSQ_CLAMP_F32 : VOP1InstSI <vop1<0x2c>, "v_rsq_clamp_f32", 1388 VOP_F32_F32, AMDGPUrsq_clamp 1389>; 1390defm V_RSQ_LEGACY_F32 : VOP1InstSI <vop1<0x2d>, "v_rsq_legacy_f32", 1391 VOP_F32_F32, AMDGPUrsq_legacy 1392>; 1393 1394} // End SchedRW = [WriteQuarterRate32] 1395 1396let SchedRW = [WriteDouble] in { 1397 1398defm V_RCP_CLAMP_F64 : VOP1InstSI <vop1<0x30>, "v_rcp_clamp_f64", VOP_F64_F64>; 1399defm V_RSQ_CLAMP_F64 : VOP1InstSI <vop1<0x32>, "v_rsq_clamp_f64", 1400 VOP_F64_F64, AMDGPUrsq_clamp 1401>; 1402 1403} // End SchedRW = [WriteDouble] 1404 1405} // End SubtargetPredicate = isSICI 1406 1407//===----------------------------------------------------------------------===// 1408// VINTRP Instructions 1409//===----------------------------------------------------------------------===// 1410 1411let Uses = [M0, EXEC] in { 1412 1413// FIXME: Specify SchedRW for VINTRP insturctions. 1414 1415multiclass V_INTERP_P1_F32_m : VINTRP_m < 1416 0x00000000, 1417 (outs VGPR_32:$dst), 1418 (ins VGPR_32:$i, i32imm:$attr_chan, i32imm:$attr), 1419 "v_interp_p1_f32 $dst, $i, $attr_chan, $attr, [m0]", 1420 [(set f32:$dst, (AMDGPUinterp_p1 i32:$i, (i32 imm:$attr_chan), 1421 (i32 imm:$attr)))] 1422>; 1423 1424let OtherPredicates = [has32BankLDS] in { 1425 1426defm V_INTERP_P1_F32 : V_INTERP_P1_F32_m; 1427 1428} // End OtherPredicates = [has32BankLDS] 1429 1430let OtherPredicates = [has16BankLDS], Constraints = "@earlyclobber $dst", isAsmParserOnly=1 in { 1431 1432defm V_INTERP_P1_F32_16bank : V_INTERP_P1_F32_m; 1433 1434} // End OtherPredicates = [has32BankLDS], Constraints = "@earlyclobber $dst", isAsmParserOnly=1 1435 1436let DisableEncoding = "$src0", Constraints = "$src0 = $dst" in { 1437 1438defm V_INTERP_P2_F32 : VINTRP_m < 1439 0x00000001, 1440 (outs VGPR_32:$dst), 1441 (ins VGPR_32:$src0, VGPR_32:$j, i32imm:$attr_chan, i32imm:$attr), 1442 "v_interp_p2_f32 $dst, [$src0], $j, $attr_chan, $attr, [m0]", 1443 [(set f32:$dst, (AMDGPUinterp_p2 f32:$src0, i32:$j, (i32 imm:$attr_chan), 1444 (i32 imm:$attr)))]>; 1445 1446} // End DisableEncoding = "$src0", Constraints = "$src0 = $dst" 1447 1448defm V_INTERP_MOV_F32 : VINTRP_m < 1449 0x00000002, 1450 (outs VGPR_32:$dst), 1451 (ins InterpSlot:$src0, i32imm:$attr_chan, i32imm:$attr), 1452 "v_interp_mov_f32 $dst, $src0, $attr_chan, $attr, [m0]", 1453 [(set f32:$dst, (AMDGPUinterp_mov (i32 imm:$src0), (i32 imm:$attr_chan), 1454 (i32 imm:$attr)))]>; 1455 1456} // End Uses = [M0, EXEC] 1457 1458//===----------------------------------------------------------------------===// 1459// VOP2 Instructions 1460//===----------------------------------------------------------------------===// 1461 1462multiclass V_CNDMASK <vop2 op, string name> { 1463 defm _e32 : VOP2_m <op, name, VOP_CNDMASK, [], name>; 1464 1465 defm _e64 : VOP3_m < 1466 op, VOP_CNDMASK.Outs, VOP_CNDMASK.Ins64, 1467 name#!cast<string>(VOP_CNDMASK.Asm64), [], name, 3, 0>; 1468} 1469 1470defm V_CNDMASK_B32 : V_CNDMASK<vop2<0x0>, "v_cndmask_b32">; 1471 1472let isCommutable = 1 in { 1473defm V_ADD_F32 : VOP2Inst <vop2<0x3, 0x1>, "v_add_f32", 1474 VOP_F32_F32_F32, fadd 1475>; 1476 1477defm V_SUB_F32 : VOP2Inst <vop2<0x4, 0x2>, "v_sub_f32", VOP_F32_F32_F32, fsub>; 1478defm V_SUBREV_F32 : VOP2Inst <vop2<0x5, 0x3>, "v_subrev_f32", 1479 VOP_F32_F32_F32, null_frag, "v_sub_f32" 1480>; 1481} // End isCommutable = 1 1482 1483let isCommutable = 1 in { 1484 1485defm V_MUL_LEGACY_F32 : VOP2Inst <vop2<0x7, 0x4>, "v_mul_legacy_f32", 1486 VOP_F32_F32_F32 1487>; 1488 1489defm V_MUL_F32 : VOP2Inst <vop2<0x8, 0x5>, "v_mul_f32", 1490 VOP_F32_F32_F32, fmul 1491>; 1492 1493defm V_MUL_I32_I24 : VOP2Inst <vop2<0x9, 0x6>, "v_mul_i32_i24", 1494 VOP_I32_I32_I32, AMDGPUmul_i24 1495>; 1496 1497defm V_MUL_HI_I32_I24 : VOP2Inst <vop2<0xa,0x7>, "v_mul_hi_i32_i24", 1498 VOP_I32_I32_I32 1499>; 1500 1501defm V_MUL_U32_U24 : VOP2Inst <vop2<0xb, 0x8>, "v_mul_u32_u24", 1502 VOP_I32_I32_I32, AMDGPUmul_u24 1503>; 1504 1505defm V_MUL_HI_U32_U24 : VOP2Inst <vop2<0xc,0x9>, "v_mul_hi_u32_u24", 1506 VOP_I32_I32_I32 1507>; 1508 1509defm V_MIN_F32 : VOP2Inst <vop2<0xf, 0xa>, "v_min_f32", VOP_F32_F32_F32, 1510 fminnum>; 1511defm V_MAX_F32 : VOP2Inst <vop2<0x10, 0xb>, "v_max_f32", VOP_F32_F32_F32, 1512 fmaxnum>; 1513defm V_MIN_I32 : VOP2Inst <vop2<0x11, 0xc>, "v_min_i32", VOP_I32_I32_I32>; 1514defm V_MAX_I32 : VOP2Inst <vop2<0x12, 0xd>, "v_max_i32", VOP_I32_I32_I32>; 1515defm V_MIN_U32 : VOP2Inst <vop2<0x13, 0xe>, "v_min_u32", VOP_I32_I32_I32>; 1516defm V_MAX_U32 : VOP2Inst <vop2<0x14, 0xf>, "v_max_u32", VOP_I32_I32_I32>; 1517 1518defm V_LSHRREV_B32 : VOP2Inst < 1519 vop2<0x16, 0x10>, "v_lshrrev_b32", VOP_I32_I32_I32, null_frag, 1520 "v_lshr_b32" 1521>; 1522 1523defm V_ASHRREV_I32 : VOP2Inst < 1524 vop2<0x18, 0x11>, "v_ashrrev_i32", VOP_I32_I32_I32, null_frag, 1525 "v_ashr_i32" 1526>; 1527 1528defm V_LSHLREV_B32 : VOP2Inst < 1529 vop2<0x1a, 0x12>, "v_lshlrev_b32", VOP_I32_I32_I32, null_frag, 1530 "v_lshl_b32" 1531>; 1532 1533defm V_AND_B32 : VOP2Inst <vop2<0x1b, 0x13>, "v_and_b32", VOP_I32_I32_I32>; 1534defm V_OR_B32 : VOP2Inst <vop2<0x1c, 0x14>, "v_or_b32", VOP_I32_I32_I32>; 1535defm V_XOR_B32 : VOP2Inst <vop2<0x1d, 0x15>, "v_xor_b32", VOP_I32_I32_I32>; 1536 1537let Constraints = "$vdst = $src2", DisableEncoding="$src2", 1538 isConvertibleToThreeAddress = 1 in { 1539defm V_MAC_F32 : VOP2Inst <vop2<0x1f, 0x16>, "v_mac_f32", VOP_MAC>; 1540} 1541} // End isCommutable = 1 1542 1543defm V_MADMK_F32 : VOP2MADK <vop2<0x20, 0x17>, "v_madmk_f32", VOP_MADMK>; 1544 1545let isCommutable = 1 in { 1546defm V_MADAK_F32 : VOP2MADK <vop2<0x21, 0x18>, "v_madak_f32", VOP_MADAK>; 1547} // End isCommutable = 1 1548 1549let isCommutable = 1 in { 1550// No patterns so that the scalar instructions are always selected. 1551// The scalar versions will be replaced with vector when needed later. 1552 1553// V_ADD_I32, V_SUB_I32, and V_SUBREV_I32 where renamed to *_U32 in VI, 1554// but the VI instructions behave the same as the SI versions. 1555defm V_ADD_I32 : VOP2bInst <vop2<0x25, 0x19>, "v_add_i32", 1556 VOP2b_I32_I1_I32_I32 1557>; 1558defm V_SUB_I32 : VOP2bInst <vop2<0x26, 0x1a>, "v_sub_i32", VOP2b_I32_I1_I32_I32>; 1559 1560defm V_SUBREV_I32 : VOP2bInst <vop2<0x27, 0x1b>, "v_subrev_i32", 1561 VOP2b_I32_I1_I32_I32, null_frag, "v_sub_i32" 1562>; 1563 1564defm V_ADDC_U32 : VOP2bInst <vop2<0x28, 0x1c>, "v_addc_u32", 1565 VOP2b_I32_I1_I32_I32_I1 1566>; 1567defm V_SUBB_U32 : VOP2bInst <vop2<0x29, 0x1d>, "v_subb_u32", 1568 VOP2b_I32_I1_I32_I32_I1 1569>; 1570defm V_SUBBREV_U32 : VOP2bInst <vop2<0x2a, 0x1e>, "v_subbrev_u32", 1571 VOP2b_I32_I1_I32_I32_I1, null_frag, "v_subb_u32" 1572>; 1573 1574} // End isCommutable = 1 1575 1576defm V_READLANE_B32 : VOP2SI_3VI_m < 1577 vop3 <0x001, 0x289>, 1578 "v_readlane_b32", 1579 (outs SReg_32:$vdst), 1580 (ins VGPR_32:$src0, SCSrc_32:$src1), 1581 "v_readlane_b32 $vdst, $src0, $src1" 1582>; 1583 1584defm V_WRITELANE_B32 : VOP2SI_3VI_m < 1585 vop3 <0x002, 0x28a>, 1586 "v_writelane_b32", 1587 (outs VGPR_32:$vdst), 1588 (ins SReg_32:$src0, SCSrc_32:$src1), 1589 "v_writelane_b32 $vdst, $src0, $src1" 1590>; 1591 1592// These instructions only exist on SI and CI 1593let SubtargetPredicate = isSICI in { 1594 1595let isCommutable = 1 in { 1596defm V_MAC_LEGACY_F32 : VOP2InstSI <vop2<0x6>, "v_mac_legacy_f32", 1597 VOP_F32_F32_F32 1598>; 1599} // End isCommutable = 1 1600 1601defm V_MIN_LEGACY_F32 : VOP2InstSI <vop2<0xd>, "v_min_legacy_f32", 1602 VOP_F32_F32_F32, AMDGPUfmin_legacy 1603>; 1604defm V_MAX_LEGACY_F32 : VOP2InstSI <vop2<0xe>, "v_max_legacy_f32", 1605 VOP_F32_F32_F32, AMDGPUfmax_legacy 1606>; 1607 1608let isCommutable = 1 in { 1609defm V_LSHR_B32 : VOP2InstSI <vop2<0x15>, "v_lshr_b32", VOP_I32_I32_I32>; 1610defm V_ASHR_I32 : VOP2InstSI <vop2<0x17>, "v_ashr_i32", VOP_I32_I32_I32>; 1611defm V_LSHL_B32 : VOP2InstSI <vop2<0x19>, "v_lshl_b32", VOP_I32_I32_I32>; 1612} // End isCommutable = 1 1613} // End let SubtargetPredicate = SICI 1614 1615defm V_BFM_B32 : VOP2_VI3_Inst <vop23<0x1e, 0x293>, "v_bfm_b32", 1616 VOP_I32_I32_I32 1617>; 1618defm V_BCNT_U32_B32 : VOP2_VI3_Inst <vop23<0x22, 0x28b>, "v_bcnt_u32_b32", 1619 VOP_I32_I32_I32 1620>; 1621defm V_MBCNT_LO_U32_B32 : VOP2_VI3_Inst <vop23<0x23, 0x28c>, "v_mbcnt_lo_u32_b32", 1622 VOP_I32_I32_I32, int_amdgcn_mbcnt_lo 1623>; 1624defm V_MBCNT_HI_U32_B32 : VOP2_VI3_Inst <vop23<0x24, 0x28d>, "v_mbcnt_hi_u32_b32", 1625 VOP_I32_I32_I32, int_amdgcn_mbcnt_hi 1626>; 1627defm V_LDEXP_F32 : VOP2_VI3_Inst <vop23<0x2b, 0x288>, "v_ldexp_f32", 1628 VOP_F32_F32_I32, AMDGPUldexp 1629>; 1630 1631defm V_CVT_PKACCUM_U8_F32 : VOP2_VI3_Inst <vop23<0x2c, 0x1f0>, "v_cvt_pkaccum_u8_f32", 1632 VOP_I32_F32_I32>; // TODO: set "Uses = dst" 1633 1634defm V_CVT_PKNORM_I16_F32 : VOP2_VI3_Inst <vop23<0x2d, 0x294>, "v_cvt_pknorm_i16_f32", 1635 VOP_I32_F32_F32 1636>; 1637defm V_CVT_PKNORM_U16_F32 : VOP2_VI3_Inst <vop23<0x2e, 0x295>, "v_cvt_pknorm_u16_f32", 1638 VOP_I32_F32_F32 1639>; 1640defm V_CVT_PKRTZ_F16_F32 : VOP2_VI3_Inst <vop23<0x2f, 0x296>, "v_cvt_pkrtz_f16_f32", 1641 VOP_I32_F32_F32, int_SI_packf16 1642>; 1643defm V_CVT_PK_U16_U32 : VOP2_VI3_Inst <vop23<0x30, 0x297>, "v_cvt_pk_u16_u32", 1644 VOP_I32_I32_I32 1645>; 1646defm V_CVT_PK_I16_I32 : VOP2_VI3_Inst <vop23<0x31, 0x298>, "v_cvt_pk_i16_i32", 1647 VOP_I32_I32_I32 1648>; 1649 1650//===----------------------------------------------------------------------===// 1651// VOP3 Instructions 1652//===----------------------------------------------------------------------===// 1653 1654let isCommutable = 1 in { 1655defm V_MAD_LEGACY_F32 : VOP3Inst <vop3<0x140, 0x1c0>, "v_mad_legacy_f32", 1656 VOP_F32_F32_F32_F32 1657>; 1658 1659defm V_MAD_F32 : VOP3Inst <vop3<0x141, 0x1c1>, "v_mad_f32", 1660 VOP_F32_F32_F32_F32, fmad 1661>; 1662 1663defm V_MAD_I32_I24 : VOP3Inst <vop3<0x142, 0x1c2>, "v_mad_i32_i24", 1664 VOP_I32_I32_I32_I32, AMDGPUmad_i24 1665>; 1666defm V_MAD_U32_U24 : VOP3Inst <vop3<0x143, 0x1c3>, "v_mad_u32_u24", 1667 VOP_I32_I32_I32_I32, AMDGPUmad_u24 1668>; 1669} // End isCommutable = 1 1670 1671defm V_CUBEID_F32 : VOP3Inst <vop3<0x144, 0x1c4>, "v_cubeid_f32", 1672 VOP_F32_F32_F32_F32, int_amdgcn_cubeid 1673>; 1674defm V_CUBESC_F32 : VOP3Inst <vop3<0x145, 0x1c5>, "v_cubesc_f32", 1675 VOP_F32_F32_F32_F32, int_amdgcn_cubesc 1676>; 1677defm V_CUBETC_F32 : VOP3Inst <vop3<0x146, 0x1c6>, "v_cubetc_f32", 1678 VOP_F32_F32_F32_F32, int_amdgcn_cubetc 1679>; 1680defm V_CUBEMA_F32 : VOP3Inst <vop3<0x147, 0x1c7>, "v_cubema_f32", 1681 VOP_F32_F32_F32_F32, int_amdgcn_cubema 1682>; 1683 1684defm V_BFE_U32 : VOP3Inst <vop3<0x148, 0x1c8>, "v_bfe_u32", 1685 VOP_I32_I32_I32_I32, AMDGPUbfe_u32 1686>; 1687defm V_BFE_I32 : VOP3Inst <vop3<0x149, 0x1c9>, "v_bfe_i32", 1688 VOP_I32_I32_I32_I32, AMDGPUbfe_i32 1689>; 1690 1691defm V_BFI_B32 : VOP3Inst <vop3<0x14a, 0x1ca>, "v_bfi_b32", 1692 VOP_I32_I32_I32_I32, AMDGPUbfi 1693>; 1694 1695let isCommutable = 1 in { 1696defm V_FMA_F32 : VOP3Inst <vop3<0x14b, 0x1cb>, "v_fma_f32", 1697 VOP_F32_F32_F32_F32, fma 1698>; 1699defm V_FMA_F64 : VOP3Inst <vop3<0x14c, 0x1cc>, "v_fma_f64", 1700 VOP_F64_F64_F64_F64, fma 1701>; 1702} // End isCommutable = 1 1703 1704//def V_LERP_U8 : VOP3_U8 <0x0000014d, "v_lerp_u8", []>; 1705defm V_ALIGNBIT_B32 : VOP3Inst <vop3<0x14e, 0x1ce>, "v_alignbit_b32", 1706 VOP_I32_I32_I32_I32 1707>; 1708defm V_ALIGNBYTE_B32 : VOP3Inst <vop3<0x14f, 0x1cf>, "v_alignbyte_b32", 1709 VOP_I32_I32_I32_I32 1710>; 1711 1712defm V_MIN3_F32 : VOP3Inst <vop3<0x151, 0x1d0>, "v_min3_f32", 1713 VOP_F32_F32_F32_F32, AMDGPUfmin3>; 1714 1715defm V_MIN3_I32 : VOP3Inst <vop3<0x152, 0x1d1>, "v_min3_i32", 1716 VOP_I32_I32_I32_I32, AMDGPUsmin3 1717>; 1718defm V_MIN3_U32 : VOP3Inst <vop3<0x153, 0x1d2>, "v_min3_u32", 1719 VOP_I32_I32_I32_I32, AMDGPUumin3 1720>; 1721defm V_MAX3_F32 : VOP3Inst <vop3<0x154, 0x1d3>, "v_max3_f32", 1722 VOP_F32_F32_F32_F32, AMDGPUfmax3 1723>; 1724defm V_MAX3_I32 : VOP3Inst <vop3<0x155, 0x1d4>, "v_max3_i32", 1725 VOP_I32_I32_I32_I32, AMDGPUsmax3 1726>; 1727defm V_MAX3_U32 : VOP3Inst <vop3<0x156, 0x1d5>, "v_max3_u32", 1728 VOP_I32_I32_I32_I32, AMDGPUumax3 1729>; 1730defm V_MED3_F32 : VOP3Inst <vop3<0x157, 0x1d6>, "v_med3_f32", 1731 VOP_F32_F32_F32_F32, AMDGPUfmed3 1732>; 1733defm V_MED3_I32 : VOP3Inst <vop3<0x158, 0x1d7>, "v_med3_i32", 1734 VOP_I32_I32_I32_I32, AMDGPUsmed3 1735>; 1736defm V_MED3_U32 : VOP3Inst <vop3<0x159, 0x1d8>, "v_med3_u32", 1737 VOP_I32_I32_I32_I32, AMDGPUumed3 1738>; 1739 1740//def V_SAD_U8 : VOP3_U8 <0x0000015a, "v_sad_u8", []>; 1741//def V_SAD_HI_U8 : VOP3_U8 <0x0000015b, "v_sad_hi_u8", []>; 1742//def V_SAD_U16 : VOP3_U16 <0x0000015c, "v_sad_u16", []>; 1743defm V_SAD_U32 : VOP3Inst <vop3<0x15d, 0x1dc>, "v_sad_u32", 1744 VOP_I32_I32_I32_I32 1745>; 1746//def V_CVT_PK_U8_F32 : VOP3_U8 <0x0000015e, "v_cvt_pk_u8_f32", []>; 1747defm V_DIV_FIXUP_F32 : VOP3Inst < 1748 vop3<0x15f, 0x1de>, "v_div_fixup_f32", VOP_F32_F32_F32_F32, AMDGPUdiv_fixup 1749>; 1750 1751let SchedRW = [WriteDoubleAdd] in { 1752 1753defm V_DIV_FIXUP_F64 : VOP3Inst < 1754 vop3<0x160, 0x1df>, "v_div_fixup_f64", VOP_F64_F64_F64_F64, AMDGPUdiv_fixup 1755>; 1756 1757} // End SchedRW = [WriteDouble] 1758 1759let SchedRW = [WriteDoubleAdd] in { 1760let isCommutable = 1 in { 1761 1762defm V_ADD_F64 : VOP3Inst <vop3<0x164, 0x280>, "v_add_f64", 1763 VOP_F64_F64_F64, fadd, 1 1764>; 1765defm V_MUL_F64 : VOP3Inst <vop3<0x165, 0x281>, "v_mul_f64", 1766 VOP_F64_F64_F64, fmul, 1 1767>; 1768 1769defm V_MIN_F64 : VOP3Inst <vop3<0x166, 0x282>, "v_min_f64", 1770 VOP_F64_F64_F64, fminnum, 1 1771>; 1772defm V_MAX_F64 : VOP3Inst <vop3<0x167, 0x283>, "v_max_f64", 1773 VOP_F64_F64_F64, fmaxnum, 1 1774>; 1775 1776} // End isCommutable = 1 1777 1778defm V_LDEXP_F64 : VOP3Inst <vop3<0x168, 0x284>, "v_ldexp_f64", 1779 VOP_F64_F64_I32, AMDGPUldexp, 1 1780>; 1781 1782} // End let SchedRW = [WriteDoubleAdd] 1783 1784let isCommutable = 1, SchedRW = [WriteQuarterRate32] in { 1785 1786defm V_MUL_LO_U32 : VOP3Inst <vop3<0x169, 0x285>, "v_mul_lo_u32", 1787 VOP_I32_I32_I32 1788>; 1789defm V_MUL_HI_U32 : VOP3Inst <vop3<0x16a, 0x286>, "v_mul_hi_u32", 1790 VOP_I32_I32_I32, mulhu 1791>; 1792 1793let DisableVIDecoder=1 in { // removed from VI as identical to V_MUL_LO_U32 1794defm V_MUL_LO_I32 : VOP3Inst <vop3<0x16b, 0x285>, "v_mul_lo_i32", 1795 VOP_I32_I32_I32 1796>; 1797} 1798 1799defm V_MUL_HI_I32 : VOP3Inst <vop3<0x16c, 0x287>, "v_mul_hi_i32", 1800 VOP_I32_I32_I32, mulhs 1801>; 1802 1803} // End isCommutable = 1, SchedRW = [WriteQuarterRate32] 1804 1805let SchedRW = [WriteFloatFMA, WriteSALU] in { 1806defm V_DIV_SCALE_F32 : VOP3bInst <vop3<0x16d, 0x1e0>, "v_div_scale_f32", 1807 VOP3b_F32_I1_F32_F32_F32, [], 1 1808>; 1809} 1810 1811let SchedRW = [WriteDouble, WriteSALU] in { 1812// Double precision division pre-scale. 1813defm V_DIV_SCALE_F64 : VOP3bInst <vop3<0x16e, 0x1e1>, "v_div_scale_f64", 1814 VOP3b_F64_I1_F64_F64_F64, [], 1 1815>; 1816} // End SchedRW = [WriteDouble] 1817 1818let isCommutable = 1, Uses = [VCC, EXEC] in { 1819 1820let SchedRW = [WriteFloatFMA] in { 1821// v_div_fmas_f32: 1822// result = src0 * src1 + src2 1823// if (vcc) 1824// result *= 2^32 1825// 1826defm V_DIV_FMAS_F32 : VOP3_VCC_Inst <vop3<0x16f, 0x1e2>, "v_div_fmas_f32", 1827 VOP_F32_F32_F32_F32, AMDGPUdiv_fmas 1828>; 1829} 1830 1831let SchedRW = [WriteDouble] in { 1832// v_div_fmas_f64: 1833// result = src0 * src1 + src2 1834// if (vcc) 1835// result *= 2^64 1836// 1837defm V_DIV_FMAS_F64 : VOP3_VCC_Inst <vop3<0x170, 0x1e3>, "v_div_fmas_f64", 1838 VOP_F64_F64_F64_F64, AMDGPUdiv_fmas 1839>; 1840 1841} // End SchedRW = [WriteDouble] 1842} // End isCommutable = 1, Uses = [VCC, EXEC] 1843 1844//def V_MSAD_U8 : VOP3_U8 <0x00000171, "v_msad_u8", []>; 1845//def V_QSAD_U8 : VOP3_U8 <0x00000172, "v_qsad_u8", []>; 1846//def V_MQSAD_U8 : VOP3_U8 <0x00000173, "v_mqsad_u8", []>; 1847 1848let SchedRW = [WriteDouble] in { 1849defm V_TRIG_PREOP_F64 : VOP3Inst < 1850 vop3<0x174, 0x292>, "v_trig_preop_f64", VOP_F64_F64_I32, AMDGPUtrig_preop 1851>; 1852 1853} // End SchedRW = [WriteDouble] 1854 1855// These instructions only exist on SI and CI 1856let SubtargetPredicate = isSICI in { 1857 1858defm V_LSHL_B64 : VOP3Inst <vop3<0x161>, "v_lshl_b64", VOP_I64_I64_I32>; 1859defm V_LSHR_B64 : VOP3Inst <vop3<0x162>, "v_lshr_b64", VOP_I64_I64_I32>; 1860defm V_ASHR_I64 : VOP3Inst <vop3<0x163>, "v_ashr_i64", VOP_I64_I64_I32>; 1861 1862defm V_MULLIT_F32 : VOP3Inst <vop3<0x150>, "v_mullit_f32", 1863 VOP_F32_F32_F32_F32>; 1864 1865} // End SubtargetPredicate = isSICI 1866 1867let SubtargetPredicate = isVI, DisableSIDecoder = 1 in { 1868 1869defm V_LSHLREV_B64 : VOP3Inst <vop3<0, 0x28f>, "v_lshlrev_b64", 1870 VOP_I64_I32_I64 1871>; 1872defm V_LSHRREV_B64 : VOP3Inst <vop3<0, 0x290>, "v_lshrrev_b64", 1873 VOP_I64_I32_I64 1874>; 1875defm V_ASHRREV_I64 : VOP3Inst <vop3<0, 0x291>, "v_ashrrev_i64", 1876 VOP_I64_I32_I64 1877>; 1878 1879} // End SubtargetPredicate = isVI 1880 1881//===----------------------------------------------------------------------===// 1882// Pseudo Instructions 1883//===----------------------------------------------------------------------===// 1884let isCodeGenOnly = 1, isPseudo = 1 in { 1885 1886// For use in patterns 1887def V_CNDMASK_B64_PSEUDO : VOP3Common <(outs VReg_64:$vdst), 1888 (ins VSrc_64:$src0, VSrc_64:$src1, SSrc_64:$src2), "", [] 1889>; 1890 1891let hasSideEffects = 0, mayLoad = 0, mayStore = 0, Uses = [EXEC] in { 1892// 64-bit vector move instruction. This is mainly used by the SIFoldOperands 1893// pass to enable folding of inline immediates. 1894def V_MOV_B64_PSEUDO : InstSI <(outs VReg_64:$vdst), (ins VSrc_64:$src0), "", []>; 1895} // End let hasSideEffects = 0, mayLoad = 0, mayStore = 0 1896 1897let hasSideEffects = 1, SALU = 1 in { 1898def SGPR_USE : InstSI <(outs),(ins), "", []>; 1899} 1900 1901let usesCustomInserter = 1, SALU = 1 in { 1902def GET_GROUPSTATICSIZE : InstSI <(outs SReg_32:$sdst), (ins), "", 1903 [(set SReg_32:$sdst, (int_amdgcn_groupstaticsize))]>; 1904} // End let usesCustomInserter = 1, SALU = 1 1905 1906// SI pseudo instructions. These are used by the CFG structurizer pass 1907// and should be lowered to ISA instructions prior to codegen. 1908 1909let mayLoad = 1, mayStore = 1, hasSideEffects = 1 in { 1910let Uses = [EXEC], Defs = [EXEC] in { 1911 1912let isBranch = 1, isTerminator = 1 in { 1913 1914def SI_IF: InstSI < 1915 (outs SReg_64:$dst), 1916 (ins SReg_64:$vcc, brtarget:$target), 1917 "", 1918 [(set i64:$dst, (int_amdgcn_if i1:$vcc, bb:$target))] 1919>; 1920 1921def SI_ELSE : InstSI < 1922 (outs SReg_64:$dst), 1923 (ins SReg_64:$src, brtarget:$target), 1924 "", 1925 [(set i64:$dst, (int_amdgcn_else i64:$src, bb:$target))] 1926> { 1927 let Constraints = "$src = $dst"; 1928} 1929 1930def SI_LOOP : InstSI < 1931 (outs), 1932 (ins SReg_64:$saved, brtarget:$target), 1933 "si_loop $saved, $target", 1934 [(int_amdgcn_loop i64:$saved, bb:$target)] 1935>; 1936 1937} // End isBranch = 1, isTerminator = 1 1938 1939def SI_BREAK : InstSI < 1940 (outs SReg_64:$dst), 1941 (ins SReg_64:$src), 1942 "si_else $dst, $src", 1943 [(set i64:$dst, (int_amdgcn_break i64:$src))] 1944>; 1945 1946def SI_IF_BREAK : InstSI < 1947 (outs SReg_64:$dst), 1948 (ins SReg_64:$vcc, SReg_64:$src), 1949 "si_if_break $dst, $vcc, $src", 1950 [(set i64:$dst, (int_amdgcn_if_break i1:$vcc, i64:$src))] 1951>; 1952 1953def SI_ELSE_BREAK : InstSI < 1954 (outs SReg_64:$dst), 1955 (ins SReg_64:$src0, SReg_64:$src1), 1956 "si_else_break $dst, $src0, $src1", 1957 [(set i64:$dst, (int_amdgcn_else_break i64:$src0, i64:$src1))] 1958>; 1959 1960def SI_END_CF : InstSI < 1961 (outs), 1962 (ins SReg_64:$saved), 1963 "si_end_cf $saved", 1964 [(int_amdgcn_end_cf i64:$saved)] 1965>; 1966 1967} // End Uses = [EXEC], Defs = [EXEC] 1968 1969let Uses = [EXEC], Defs = [EXEC,VCC] in { 1970def SI_KILL : InstSI < 1971 (outs), 1972 (ins VSrc_32:$src), 1973 "si_kill $src", 1974 [(int_AMDGPU_kill f32:$src)] 1975>; 1976} // End Uses = [EXEC], Defs = [EXEC,VCC] 1977 1978} // End mayLoad = 1, mayStore = 1, hasSideEffects = 1 1979 1980let Uses = [EXEC], Defs = [EXEC,VCC,M0] in { 1981 1982class SI_INDIRECT_SRC<RegisterClass rc> : InstSI < 1983 (outs VGPR_32:$dst, SReg_64:$temp), 1984 (ins rc:$src, VSrc_32:$idx, i32imm:$off), 1985 "si_indirect_src $dst, $temp, $src, $idx, $off", 1986 [] 1987>; 1988 1989class SI_INDIRECT_DST<RegisterClass rc> : InstSI < 1990 (outs rc:$dst, SReg_64:$temp), 1991 (ins unknown:$src, VSrc_32:$idx, i32imm:$off, VGPR_32:$val), 1992 "si_indirect_dst $dst, $temp, $src, $idx, $off, $val", 1993 [] 1994> { 1995 let Constraints = "$src = $dst"; 1996} 1997 1998// TODO: We can support indirect SGPR access. 1999def SI_INDIRECT_SRC_V1 : SI_INDIRECT_SRC<VGPR_32>; 2000def SI_INDIRECT_SRC_V2 : SI_INDIRECT_SRC<VReg_64>; 2001def SI_INDIRECT_SRC_V4 : SI_INDIRECT_SRC<VReg_128>; 2002def SI_INDIRECT_SRC_V8 : SI_INDIRECT_SRC<VReg_256>; 2003def SI_INDIRECT_SRC_V16 : SI_INDIRECT_SRC<VReg_512>; 2004 2005def SI_INDIRECT_DST_V1 : SI_INDIRECT_DST<VGPR_32>; 2006def SI_INDIRECT_DST_V2 : SI_INDIRECT_DST<VReg_64>; 2007def SI_INDIRECT_DST_V4 : SI_INDIRECT_DST<VReg_128>; 2008def SI_INDIRECT_DST_V8 : SI_INDIRECT_DST<VReg_256>; 2009def SI_INDIRECT_DST_V16 : SI_INDIRECT_DST<VReg_512>; 2010 2011} // End Uses = [EXEC], Defs = [EXEC,VCC,M0] 2012 2013multiclass SI_SPILL_SGPR <RegisterClass sgpr_class> { 2014 2015 let UseNamedOperandTable = 1, Uses = [EXEC] in { 2016 def _SAVE : InstSI < 2017 (outs), 2018 (ins sgpr_class:$src, i32imm:$frame_idx), 2019 "", []> { 2020 let mayStore = 1; 2021 let mayLoad = 0; 2022 } 2023 2024 def _RESTORE : InstSI < 2025 (outs sgpr_class:$dst), 2026 (ins i32imm:$frame_idx), 2027 "", []> { 2028 let mayStore = 0; 2029 let mayLoad = 1; 2030 } 2031 } // End UseNamedOperandTable = 1 2032} 2033 2034// It's unclear whether you can use M0 as the output of v_readlane_b32 2035// instructions, so use SGPR_32 register class for spills to prevent 2036// this from happening. 2037defm SI_SPILL_S32 : SI_SPILL_SGPR <SGPR_32>; 2038defm SI_SPILL_S64 : SI_SPILL_SGPR <SReg_64>; 2039defm SI_SPILL_S128 : SI_SPILL_SGPR <SReg_128>; 2040defm SI_SPILL_S256 : SI_SPILL_SGPR <SReg_256>; 2041defm SI_SPILL_S512 : SI_SPILL_SGPR <SReg_512>; 2042 2043multiclass SI_SPILL_VGPR <RegisterClass vgpr_class> { 2044 let UseNamedOperandTable = 1, VGPRSpill = 1, Uses = [EXEC] in { 2045 def _SAVE : InstSI < 2046 (outs), 2047 (ins vgpr_class:$src, i32imm:$frame_idx, SReg_128:$scratch_rsrc, 2048 SReg_32:$scratch_offset, i32imm:$offset), 2049 "", []> { 2050 let mayStore = 1; 2051 let mayLoad = 0; 2052 } 2053 2054 def _RESTORE : InstSI < 2055 (outs vgpr_class:$dst), 2056 (ins i32imm:$frame_idx, SReg_128:$scratch_rsrc, SReg_32:$scratch_offset, 2057 i32imm:$offset), 2058 "", []> { 2059 let mayStore = 0; 2060 let mayLoad = 1; 2061 } 2062 } // End UseNamedOperandTable = 1, VGPRSpill = 1 2063} 2064 2065defm SI_SPILL_V32 : SI_SPILL_VGPR <VGPR_32>; 2066defm SI_SPILL_V64 : SI_SPILL_VGPR <VReg_64>; 2067defm SI_SPILL_V96 : SI_SPILL_VGPR <VReg_96>; 2068defm SI_SPILL_V128 : SI_SPILL_VGPR <VReg_128>; 2069defm SI_SPILL_V256 : SI_SPILL_VGPR <VReg_256>; 2070defm SI_SPILL_V512 : SI_SPILL_VGPR <VReg_512>; 2071 2072let Defs = [SCC] in { 2073 2074def SI_CONSTDATA_PTR : InstSI < 2075 (outs SReg_64:$dst), 2076 (ins const_ga:$ptr), 2077 "", [(set SReg_64:$dst, (i64 (SIconstdata_ptr (tglobaladdr:$ptr))))] 2078> { 2079 let SALU = 1; 2080} 2081 2082} // End Defs = [SCC] 2083 2084} // End isCodeGenOnly, isPseudo 2085 2086} // End SubtargetPredicate = isGCN 2087 2088let Predicates = [isGCN] in { 2089 2090def : Pat < 2091 (int_AMDGPU_kilp), 2092 (SI_KILL 0xbf800000) 2093>; 2094 2095/* int_SI_vs_load_input */ 2096def : Pat< 2097 (SIload_input v4i32:$tlst, imm:$attr_offset, i32:$buf_idx_vgpr), 2098 (BUFFER_LOAD_FORMAT_XYZW_IDXEN $buf_idx_vgpr, $tlst, 0, imm:$attr_offset, 0, 0, 0) 2099>; 2100 2101def : Pat < 2102 (int_SI_export imm:$en, imm:$vm, imm:$done, imm:$tgt, imm:$compr, 2103 f32:$src0, f32:$src1, f32:$src2, f32:$src3), 2104 (EXP imm:$en, imm:$tgt, imm:$compr, imm:$done, imm:$vm, 2105 $src0, $src1, $src2, $src3) 2106>; 2107 2108//===----------------------------------------------------------------------===// 2109// buffer_load/store_format patterns 2110//===----------------------------------------------------------------------===// 2111 2112multiclass MUBUF_LoadIntrinsicPat<ValueType vt, string opcode> { 2113 def : Pat< 2114 (vt (int_amdgcn_buffer_load_format v4i32:$rsrc, 0, 2115 (MUBUFIntrinsicOffset i32:$soffset, 2116 i16:$offset), 2117 imm:$glc, imm:$slc)), 2118 (!cast<MUBUF>(opcode # _OFFSET) $rsrc, $soffset, (as_i16imm $offset), 2119 (as_i1imm $glc), (as_i1imm $slc), 0) 2120 >; 2121 2122 def : Pat< 2123 (vt (int_amdgcn_buffer_load_format v4i32:$rsrc, i32:$vindex, 2124 (MUBUFIntrinsicOffset i32:$soffset, 2125 i16:$offset), 2126 imm:$glc, imm:$slc)), 2127 (!cast<MUBUF>(opcode # _IDXEN) $vindex, $rsrc, $soffset, (as_i16imm $offset), 2128 (as_i1imm $glc), (as_i1imm $slc), 0) 2129 >; 2130 2131 def : Pat< 2132 (vt (int_amdgcn_buffer_load_format v4i32:$rsrc, 0, 2133 (MUBUFIntrinsicVOffset i32:$soffset, 2134 i16:$offset, 2135 i32:$voffset), 2136 imm:$glc, imm:$slc)), 2137 (!cast<MUBUF>(opcode # _OFFEN) $voffset, $rsrc, $soffset, (as_i16imm $offset), 2138 (as_i1imm $glc), (as_i1imm $slc), 0) 2139 >; 2140 2141 def : Pat< 2142 (vt (int_amdgcn_buffer_load_format v4i32:$rsrc, i32:$vindex, 2143 (MUBUFIntrinsicVOffset i32:$soffset, 2144 i16:$offset, 2145 i32:$voffset), 2146 imm:$glc, imm:$slc)), 2147 (!cast<MUBUF>(opcode # _BOTHEN) 2148 (REG_SEQUENCE VReg_64, $vindex, sub0, $voffset, sub1), 2149 $rsrc, $soffset, (as_i16imm $offset), 2150 (as_i1imm $glc), (as_i1imm $slc), 0) 2151 >; 2152} 2153 2154defm : MUBUF_LoadIntrinsicPat<f32, "BUFFER_LOAD_FORMAT_X">; 2155defm : MUBUF_LoadIntrinsicPat<v2f32, "BUFFER_LOAD_FORMAT_XY">; 2156defm : MUBUF_LoadIntrinsicPat<v4f32, "BUFFER_LOAD_FORMAT_XYZW">; 2157 2158def : Pat< 2159 (int_amdgcn_buffer_store_format v4f32:$vdata, v4i32:$rsrc, 0, 2160 (MUBUFIntrinsicOffset i32:$soffset, 2161 i16:$offset), 2162 imm:$glc, imm:$slc), 2163 (BUFFER_STORE_FORMAT_XYZW_OFFSET $vdata, $rsrc, $soffset, (as_i16imm $offset), 2164 (as_i1imm $glc), (as_i1imm $slc), 0) 2165>; 2166 2167def : Pat< 2168 (int_amdgcn_buffer_store_format v4f32:$vdata, v4i32:$rsrc, i32:$vindex, 2169 (MUBUFIntrinsicOffset i32:$soffset, 2170 i16:$offset), 2171 imm:$glc, imm:$slc), 2172 (BUFFER_STORE_FORMAT_XYZW_IDXEN $vdata, $vindex, $rsrc, $soffset, 2173 (as_i16imm $offset), (as_i1imm $glc), (as_i1imm $slc), 0) 2174>; 2175 2176def : Pat< 2177 (int_amdgcn_buffer_store_format v4f32:$vdata, v4i32:$rsrc, 0, 2178 (MUBUFIntrinsicVOffset i32:$soffset, 2179 i16:$offset, 2180 i32:$voffset), 2181 imm:$glc, imm:$slc), 2182 (BUFFER_STORE_FORMAT_XYZW_OFFEN $vdata, $voffset, $rsrc, $soffset, 2183 (as_i16imm $offset), (as_i1imm $glc), (as_i1imm $slc), 0) 2184>; 2185 2186def : Pat< 2187 (int_amdgcn_buffer_store_format v4f32:$vdata, v4i32:$rsrc, i32:$vindex, 2188 (MUBUFIntrinsicVOffset i32:$soffset, 2189 i16:$offset, 2190 i32:$voffset), 2191 imm:$glc, imm:$slc), 2192 (BUFFER_STORE_FORMAT_XYZW_BOTHEN 2193 $vdata, 2194 (REG_SEQUENCE VReg_64, $vindex, sub0, $voffset, sub1), 2195 $rsrc, $soffset, (as_i16imm $offset), 2196 (as_i1imm $glc), (as_i1imm $slc), 0) 2197>; 2198 2199//===----------------------------------------------------------------------===// 2200// buffer_atomic patterns 2201//===----------------------------------------------------------------------===// 2202multiclass BufferAtomicPatterns<SDPatternOperator name, string opcode> { 2203 def : Pat< 2204 (name i32:$vdata_in, v4i32:$rsrc, 0, 2205 (MUBUFIntrinsicOffset i32:$soffset, i16:$offset), 2206 imm:$slc), 2207 (!cast<MUBUF>(opcode # _RTN_OFFSET) $vdata_in, $rsrc, $soffset, 2208 (as_i16imm $offset), (as_i1imm $slc)) 2209 >; 2210 2211 def : Pat< 2212 (name i32:$vdata_in, v4i32:$rsrc, i32:$vindex, 2213 (MUBUFIntrinsicOffset i32:$soffset, i16:$offset), 2214 imm:$slc), 2215 (!cast<MUBUF>(opcode # _RTN_IDXEN) $vdata_in, $vindex, $rsrc, $soffset, 2216 (as_i16imm $offset), (as_i1imm $slc)) 2217 >; 2218 2219 def : Pat< 2220 (name i32:$vdata_in, v4i32:$rsrc, 0, 2221 (MUBUFIntrinsicVOffset i32:$soffset, i16:$offset, i32:$voffset), 2222 imm:$slc), 2223 (!cast<MUBUF>(opcode # _RTN_OFFEN) $vdata_in, $voffset, $rsrc, $soffset, 2224 (as_i16imm $offset), (as_i1imm $slc)) 2225 >; 2226 2227 def : Pat< 2228 (name i32:$vdata_in, v4i32:$rsrc, i32:$vindex, 2229 (MUBUFIntrinsicVOffset i32:$soffset, i16:$offset, i32:$voffset), 2230 imm:$slc), 2231 (!cast<MUBUF>(opcode # _RTN_BOTHEN) 2232 $vdata_in, 2233 (REG_SEQUENCE VReg_64, $vindex, sub0, $voffset, sub1), 2234 $rsrc, $soffset, (as_i16imm $offset), (as_i1imm $slc)) 2235 >; 2236} 2237 2238defm : BufferAtomicPatterns<int_amdgcn_buffer_atomic_swap, "BUFFER_ATOMIC_SWAP">; 2239defm : BufferAtomicPatterns<int_amdgcn_buffer_atomic_add, "BUFFER_ATOMIC_ADD">; 2240defm : BufferAtomicPatterns<int_amdgcn_buffer_atomic_sub, "BUFFER_ATOMIC_SUB">; 2241defm : BufferAtomicPatterns<int_amdgcn_buffer_atomic_smin, "BUFFER_ATOMIC_SMIN">; 2242defm : BufferAtomicPatterns<int_amdgcn_buffer_atomic_umin, "BUFFER_ATOMIC_UMIN">; 2243defm : BufferAtomicPatterns<int_amdgcn_buffer_atomic_smax, "BUFFER_ATOMIC_SMAX">; 2244defm : BufferAtomicPatterns<int_amdgcn_buffer_atomic_umax, "BUFFER_ATOMIC_UMAX">; 2245defm : BufferAtomicPatterns<int_amdgcn_buffer_atomic_and, "BUFFER_ATOMIC_AND">; 2246defm : BufferAtomicPatterns<int_amdgcn_buffer_atomic_or, "BUFFER_ATOMIC_OR">; 2247defm : BufferAtomicPatterns<int_amdgcn_buffer_atomic_xor, "BUFFER_ATOMIC_XOR">; 2248 2249def : Pat< 2250 (int_amdgcn_buffer_atomic_cmpswap 2251 i32:$data, i32:$cmp, v4i32:$rsrc, 0, 2252 (MUBUFIntrinsicOffset i32:$soffset, i16:$offset), 2253 imm:$slc), 2254 (EXTRACT_SUBREG 2255 (BUFFER_ATOMIC_CMPSWAP_RTN_OFFSET 2256 (REG_SEQUENCE VReg_64, $data, sub0, $cmp, sub1), 2257 $rsrc, $soffset, (as_i16imm $offset), (as_i1imm $slc)), 2258 sub0) 2259>; 2260 2261def : Pat< 2262 (int_amdgcn_buffer_atomic_cmpswap 2263 i32:$data, i32:$cmp, v4i32:$rsrc, i32:$vindex, 2264 (MUBUFIntrinsicOffset i32:$soffset, i16:$offset), 2265 imm:$slc), 2266 (EXTRACT_SUBREG 2267 (BUFFER_ATOMIC_CMPSWAP_RTN_IDXEN 2268 (REG_SEQUENCE VReg_64, $data, sub0, $cmp, sub1), 2269 $vindex, $rsrc, $soffset, (as_i16imm $offset), (as_i1imm $slc)), 2270 sub0) 2271>; 2272 2273def : Pat< 2274 (int_amdgcn_buffer_atomic_cmpswap 2275 i32:$data, i32:$cmp, v4i32:$rsrc, 0, 2276 (MUBUFIntrinsicVOffset i32:$soffset, i16:$offset, i32:$voffset), 2277 imm:$slc), 2278 (EXTRACT_SUBREG 2279 (BUFFER_ATOMIC_CMPSWAP_RTN_OFFEN 2280 (REG_SEQUENCE VReg_64, $data, sub0, $cmp, sub1), 2281 $voffset, $rsrc, $soffset, (as_i16imm $offset), (as_i1imm $slc)), 2282 sub0) 2283>; 2284 2285def : Pat< 2286 (int_amdgcn_buffer_atomic_cmpswap 2287 i32:$data, i32:$cmp, v4i32:$rsrc, i32:$vindex, 2288 (MUBUFIntrinsicVOffset i32:$soffset, i16:$offset, i32:$voffset), 2289 imm:$slc), 2290 (EXTRACT_SUBREG 2291 (BUFFER_ATOMIC_CMPSWAP_RTN_BOTHEN 2292 (REG_SEQUENCE VReg_64, $data, sub0, $cmp, sub1), 2293 (REG_SEQUENCE VReg_64, $vindex, sub0, $voffset, sub1), 2294 $rsrc, $soffset, (as_i16imm $offset), (as_i1imm $slc)), 2295 sub0) 2296>; 2297 2298 2299//===----------------------------------------------------------------------===// 2300// S_GETREG_B32 Intrinsic Pattern. 2301//===----------------------------------------------------------------------===// 2302def : Pat < 2303 (int_amdgcn_s_getreg imm:$simm16), 2304 (S_GETREG_B32 (as_i16imm $simm16)) 2305>; 2306 2307//===----------------------------------------------------------------------===// 2308// SMRD Patterns 2309//===----------------------------------------------------------------------===// 2310 2311multiclass SMRD_Pattern <string Instr, ValueType vt> { 2312 2313 // 1. IMM offset 2314 def : Pat < 2315 (smrd_load (SMRDImm i64:$sbase, i32:$offset)), 2316 (vt (!cast<SMRD>(Instr#"_IMM") $sbase, $offset)) 2317 >; 2318 2319 // 2. SGPR offset 2320 def : Pat < 2321 (smrd_load (SMRDSgpr i64:$sbase, i32:$offset)), 2322 (vt (!cast<SMRD>(Instr#"_SGPR") $sbase, $offset)) 2323 >; 2324 2325 def : Pat < 2326 (smrd_load (SMRDImm32 i64:$sbase, i32:$offset)), 2327 (vt (!cast<SMRD>(Instr#"_IMM_ci") $sbase, $offset)) 2328 > { 2329 let Predicates = [isCIOnly]; 2330 } 2331} 2332 2333// Global and constant loads can be selected to either MUBUF or SMRD 2334// instructions, but SMRD instructions are faster so we want the instruction 2335// selector to prefer those. 2336let AddedComplexity = 100 in { 2337 2338defm : SMRD_Pattern <"S_LOAD_DWORD", i32>; 2339defm : SMRD_Pattern <"S_LOAD_DWORDX2", v2i32>; 2340defm : SMRD_Pattern <"S_LOAD_DWORDX4", v4i32>; 2341defm : SMRD_Pattern <"S_LOAD_DWORDX8", v8i32>; 2342defm : SMRD_Pattern <"S_LOAD_DWORDX16", v16i32>; 2343 2344// 1. Offset as an immediate 2345def : Pat < 2346 (SIload_constant v4i32:$sbase, (SMRDBufferImm i32:$offset)), 2347 (S_BUFFER_LOAD_DWORD_IMM $sbase, $offset) 2348>; 2349 2350// 2. Offset loaded in an 32bit SGPR 2351def : Pat < 2352 (SIload_constant v4i32:$sbase, (SMRDBufferSgpr i32:$offset)), 2353 (S_BUFFER_LOAD_DWORD_SGPR $sbase, $offset) 2354>; 2355 2356let Predicates = [isCI] in { 2357 2358def : Pat < 2359 (SIload_constant v4i32:$sbase, (SMRDBufferImm32 i32:$offset)), 2360 (S_BUFFER_LOAD_DWORD_IMM_ci $sbase, $offset) 2361>; 2362 2363} // End Predicates = [isCI] 2364 2365} // End let AddedComplexity = 10000 2366 2367//===----------------------------------------------------------------------===// 2368// SOP1 Patterns 2369//===----------------------------------------------------------------------===// 2370 2371def : Pat < 2372 (i64 (ctpop i64:$src)), 2373 (i64 (REG_SEQUENCE SReg_64, 2374 (i32 (COPY_TO_REGCLASS (S_BCNT1_I32_B64 $src), SReg_32)), sub0, 2375 (S_MOV_B32 0), sub1)) 2376>; 2377 2378def : Pat < 2379 (i32 (smax i32:$x, (i32 (ineg i32:$x)))), 2380 (S_ABS_I32 $x) 2381>; 2382 2383//===----------------------------------------------------------------------===// 2384// SOP2 Patterns 2385//===----------------------------------------------------------------------===// 2386 2387// V_ADD_I32_e32/S_ADD_U32 produces carry in VCC/SCC. For the vector 2388// case, the sgpr-copies pass will fix this to use the vector version. 2389def : Pat < 2390 (i32 (addc i32:$src0, i32:$src1)), 2391 (S_ADD_U32 $src0, $src1) 2392>; 2393 2394//===----------------------------------------------------------------------===// 2395// SOPP Patterns 2396//===----------------------------------------------------------------------===// 2397 2398// FIXME: These should be removed eventually 2399def : Pat < 2400 (int_AMDGPU_barrier_global), 2401 (S_BARRIER) 2402>; 2403 2404def : Pat < 2405 (int_AMDGPU_barrier_local), 2406 (S_BARRIER) 2407>; 2408 2409//===----------------------------------------------------------------------===// 2410// VOP1 Patterns 2411//===----------------------------------------------------------------------===// 2412 2413let Predicates = [UnsafeFPMath] in { 2414 2415//def : RcpPat<V_RCP_F64_e32, f64>; 2416//defm : RsqPat<V_RSQ_F64_e32, f64>; 2417//defm : RsqPat<V_RSQ_F32_e32, f32>; 2418 2419def : RsqPat<V_RSQ_F32_e32, f32>; 2420def : RsqPat<V_RSQ_F64_e32, f64>; 2421} 2422 2423//===----------------------------------------------------------------------===// 2424// VOP2 Patterns 2425//===----------------------------------------------------------------------===// 2426 2427def : Pat < 2428 (i32 (add (i32 (ctpop i32:$popcnt)), i32:$val)), 2429 (V_BCNT_U32_B32_e64 $popcnt, $val) 2430>; 2431 2432def : Pat < 2433 (i32 (select i1:$src0, i32:$src1, i32:$src2)), 2434 (V_CNDMASK_B32_e64 $src2, $src1, $src0) 2435>; 2436 2437// Pattern for V_MAC_F32 2438def : Pat < 2439 (fmad (VOP3NoMods0 f32:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod), 2440 (VOP3NoMods f32:$src1, i32:$src1_modifiers), 2441 (VOP3NoMods f32:$src2, i32:$src2_modifiers)), 2442 (V_MAC_F32_e64 $src0_modifiers, $src0, $src1_modifiers, $src1, 2443 $src2_modifiers, $src2, $clamp, $omod) 2444>; 2445 2446/********** ======================= **********/ 2447/********** Image sampling patterns **********/ 2448/********** ======================= **********/ 2449 2450// Image + sampler 2451class SampleRawPattern<SDPatternOperator name, MIMG opcode, ValueType vt> : Pat < 2452 (name vt:$addr, v8i32:$rsrc, v4i32:$sampler, i32:$dmask, i32:$unorm, 2453 i32:$r128, i32:$da, i32:$glc, i32:$slc, i32:$tfe, i32:$lwe), 2454 (opcode $addr, $rsrc, $sampler, 2455 (as_i32imm $dmask), (as_i1imm $unorm), (as_i1imm $glc), (as_i1imm $slc), 2456 (as_i1imm $r128), (as_i1imm $tfe), (as_i1imm $lwe), (as_i1imm $da)) 2457>; 2458 2459multiclass SampleRawPatterns<SDPatternOperator name, string opcode> { 2460 def : SampleRawPattern<name, !cast<MIMG>(opcode # _V4_V1), i32>; 2461 def : SampleRawPattern<name, !cast<MIMG>(opcode # _V4_V2), v2i32>; 2462 def : SampleRawPattern<name, !cast<MIMG>(opcode # _V4_V4), v4i32>; 2463 def : SampleRawPattern<name, !cast<MIMG>(opcode # _V4_V8), v8i32>; 2464 def : SampleRawPattern<name, !cast<MIMG>(opcode # _V4_V16), v16i32>; 2465} 2466 2467// Image only 2468class ImagePattern<SDPatternOperator name, MIMG opcode, ValueType vt> : Pat < 2469 (name vt:$addr, v8i32:$rsrc, imm:$dmask, imm:$unorm, 2470 imm:$r128, imm:$da, imm:$glc, imm:$slc, imm:$tfe, imm:$lwe), 2471 (opcode $addr, $rsrc, 2472 (as_i32imm $dmask), (as_i1imm $unorm), (as_i1imm $glc), (as_i1imm $slc), 2473 (as_i1imm $r128), (as_i1imm $tfe), (as_i1imm $lwe), (as_i1imm $da)) 2474>; 2475 2476multiclass ImagePatterns<SDPatternOperator name, string opcode> { 2477 def : ImagePattern<name, !cast<MIMG>(opcode # _V4_V1), i32>; 2478 def : ImagePattern<name, !cast<MIMG>(opcode # _V4_V2), v2i32>; 2479 def : ImagePattern<name, !cast<MIMG>(opcode # _V4_V4), v4i32>; 2480} 2481 2482class ImageLoadPattern<SDPatternOperator name, MIMG opcode, ValueType vt> : Pat < 2483 (name vt:$addr, v8i32:$rsrc, imm:$dmask, imm:$r128, imm:$da, imm:$glc, 2484 imm:$slc), 2485 (opcode $addr, $rsrc, 2486 (as_i32imm $dmask), 1, (as_i1imm $glc), (as_i1imm $slc), 2487 (as_i1imm $r128), 0, 0, (as_i1imm $da)) 2488>; 2489 2490multiclass ImageLoadPatterns<SDPatternOperator name, string opcode> { 2491 def : ImageLoadPattern<name, !cast<MIMG>(opcode # _V4_V1), i32>; 2492 def : ImageLoadPattern<name, !cast<MIMG>(opcode # _V4_V2), v2i32>; 2493 def : ImageLoadPattern<name, !cast<MIMG>(opcode # _V4_V4), v4i32>; 2494} 2495 2496class ImageStorePattern<SDPatternOperator name, MIMG opcode, ValueType vt> : Pat < 2497 (name v4f32:$data, vt:$addr, v8i32:$rsrc, i32:$dmask, imm:$r128, imm:$da, 2498 imm:$glc, imm:$slc), 2499 (opcode $data, $addr, $rsrc, 2500 (as_i32imm $dmask), 1, (as_i1imm $glc), (as_i1imm $slc), 2501 (as_i1imm $r128), 0, 0, (as_i1imm $da)) 2502>; 2503 2504multiclass ImageStorePatterns<SDPatternOperator name, string opcode> { 2505 def : ImageStorePattern<name, !cast<MIMG>(opcode # _V4_V1), i32>; 2506 def : ImageStorePattern<name, !cast<MIMG>(opcode # _V4_V2), v2i32>; 2507 def : ImageStorePattern<name, !cast<MIMG>(opcode # _V4_V4), v4i32>; 2508} 2509 2510class ImageAtomicPattern<SDPatternOperator name, MIMG opcode, ValueType vt> : Pat < 2511 (name i32:$vdata, vt:$addr, v8i32:$rsrc, imm:$r128, imm:$da, imm:$slc), 2512 (opcode $vdata, $addr, $rsrc, 1, 1, 1, (as_i1imm $slc), (as_i1imm $r128), 0, 0, (as_i1imm $da)) 2513>; 2514 2515multiclass ImageAtomicPatterns<SDPatternOperator name, string opcode> { 2516 def : ImageAtomicPattern<name, !cast<MIMG>(opcode # _V1), i32>; 2517 def : ImageAtomicPattern<name, !cast<MIMG>(opcode # _V2), v2i32>; 2518 def : ImageAtomicPattern<name, !cast<MIMG>(opcode # _V4), v4i32>; 2519} 2520 2521class ImageAtomicCmpSwapPattern<MIMG opcode, ValueType vt> : Pat < 2522 (int_amdgcn_image_atomic_cmpswap i32:$vsrc, i32:$vcmp, vt:$addr, v8i32:$rsrc, 2523 imm:$r128, imm:$da, imm:$slc), 2524 (EXTRACT_SUBREG 2525 (opcode (REG_SEQUENCE VReg_64, $vsrc, sub0, $vcmp, sub1), 2526 $addr, $rsrc, 3, 1, 1, (as_i1imm $slc), (as_i1imm $r128), 0, 0, (as_i1imm $da)), 2527 sub0) 2528>; 2529 2530// Basic sample 2531defm : SampleRawPatterns<int_SI_image_sample, "IMAGE_SAMPLE">; 2532defm : SampleRawPatterns<int_SI_image_sample_cl, "IMAGE_SAMPLE_CL">; 2533defm : SampleRawPatterns<int_SI_image_sample_d, "IMAGE_SAMPLE_D">; 2534defm : SampleRawPatterns<int_SI_image_sample_d_cl, "IMAGE_SAMPLE_D_CL">; 2535defm : SampleRawPatterns<int_SI_image_sample_l, "IMAGE_SAMPLE_L">; 2536defm : SampleRawPatterns<int_SI_image_sample_b, "IMAGE_SAMPLE_B">; 2537defm : SampleRawPatterns<int_SI_image_sample_b_cl, "IMAGE_SAMPLE_B_CL">; 2538defm : SampleRawPatterns<int_SI_image_sample_lz, "IMAGE_SAMPLE_LZ">; 2539defm : SampleRawPatterns<int_SI_image_sample_cd, "IMAGE_SAMPLE_CD">; 2540defm : SampleRawPatterns<int_SI_image_sample_cd_cl, "IMAGE_SAMPLE_CD_CL">; 2541 2542// Sample with comparison 2543defm : SampleRawPatterns<int_SI_image_sample_c, "IMAGE_SAMPLE_C">; 2544defm : SampleRawPatterns<int_SI_image_sample_c_cl, "IMAGE_SAMPLE_C_CL">; 2545defm : SampleRawPatterns<int_SI_image_sample_c_d, "IMAGE_SAMPLE_C_D">; 2546defm : SampleRawPatterns<int_SI_image_sample_c_d_cl, "IMAGE_SAMPLE_C_D_CL">; 2547defm : SampleRawPatterns<int_SI_image_sample_c_l, "IMAGE_SAMPLE_C_L">; 2548defm : SampleRawPatterns<int_SI_image_sample_c_b, "IMAGE_SAMPLE_C_B">; 2549defm : SampleRawPatterns<int_SI_image_sample_c_b_cl, "IMAGE_SAMPLE_C_B_CL">; 2550defm : SampleRawPatterns<int_SI_image_sample_c_lz, "IMAGE_SAMPLE_C_LZ">; 2551defm : SampleRawPatterns<int_SI_image_sample_c_cd, "IMAGE_SAMPLE_C_CD">; 2552defm : SampleRawPatterns<int_SI_image_sample_c_cd_cl, "IMAGE_SAMPLE_C_CD_CL">; 2553 2554// Sample with offsets 2555defm : SampleRawPatterns<int_SI_image_sample_o, "IMAGE_SAMPLE_O">; 2556defm : SampleRawPatterns<int_SI_image_sample_cl_o, "IMAGE_SAMPLE_CL_O">; 2557defm : SampleRawPatterns<int_SI_image_sample_d_o, "IMAGE_SAMPLE_D_O">; 2558defm : SampleRawPatterns<int_SI_image_sample_d_cl_o, "IMAGE_SAMPLE_D_CL_O">; 2559defm : SampleRawPatterns<int_SI_image_sample_l_o, "IMAGE_SAMPLE_L_O">; 2560defm : SampleRawPatterns<int_SI_image_sample_b_o, "IMAGE_SAMPLE_B_O">; 2561defm : SampleRawPatterns<int_SI_image_sample_b_cl_o, "IMAGE_SAMPLE_B_CL_O">; 2562defm : SampleRawPatterns<int_SI_image_sample_lz_o, "IMAGE_SAMPLE_LZ_O">; 2563defm : SampleRawPatterns<int_SI_image_sample_cd_o, "IMAGE_SAMPLE_CD_O">; 2564defm : SampleRawPatterns<int_SI_image_sample_cd_cl_o, "IMAGE_SAMPLE_CD_CL_O">; 2565 2566// Sample with comparison and offsets 2567defm : SampleRawPatterns<int_SI_image_sample_c_o, "IMAGE_SAMPLE_C_O">; 2568defm : SampleRawPatterns<int_SI_image_sample_c_cl_o, "IMAGE_SAMPLE_C_CL_O">; 2569defm : SampleRawPatterns<int_SI_image_sample_c_d_o, "IMAGE_SAMPLE_C_D_O">; 2570defm : SampleRawPatterns<int_SI_image_sample_c_d_cl_o, "IMAGE_SAMPLE_C_D_CL_O">; 2571defm : SampleRawPatterns<int_SI_image_sample_c_l_o, "IMAGE_SAMPLE_C_L_O">; 2572defm : SampleRawPatterns<int_SI_image_sample_c_b_o, "IMAGE_SAMPLE_C_B_O">; 2573defm : SampleRawPatterns<int_SI_image_sample_c_b_cl_o, "IMAGE_SAMPLE_C_B_CL_O">; 2574defm : SampleRawPatterns<int_SI_image_sample_c_lz_o, "IMAGE_SAMPLE_C_LZ_O">; 2575defm : SampleRawPatterns<int_SI_image_sample_c_cd_o, "IMAGE_SAMPLE_C_CD_O">; 2576defm : SampleRawPatterns<int_SI_image_sample_c_cd_cl_o, "IMAGE_SAMPLE_C_CD_CL_O">; 2577 2578// Gather opcodes 2579// Only the variants which make sense are defined. 2580def : SampleRawPattern<int_SI_gather4, IMAGE_GATHER4_V4_V2, v2i32>; 2581def : SampleRawPattern<int_SI_gather4, IMAGE_GATHER4_V4_V4, v4i32>; 2582def : SampleRawPattern<int_SI_gather4_cl, IMAGE_GATHER4_CL_V4_V4, v4i32>; 2583def : SampleRawPattern<int_SI_gather4_l, IMAGE_GATHER4_L_V4_V4, v4i32>; 2584def : SampleRawPattern<int_SI_gather4_b, IMAGE_GATHER4_B_V4_V4, v4i32>; 2585def : SampleRawPattern<int_SI_gather4_b_cl, IMAGE_GATHER4_B_CL_V4_V4, v4i32>; 2586def : SampleRawPattern<int_SI_gather4_b_cl, IMAGE_GATHER4_B_CL_V4_V8, v8i32>; 2587def : SampleRawPattern<int_SI_gather4_lz, IMAGE_GATHER4_LZ_V4_V2, v2i32>; 2588def : SampleRawPattern<int_SI_gather4_lz, IMAGE_GATHER4_LZ_V4_V4, v4i32>; 2589 2590def : SampleRawPattern<int_SI_gather4_c, IMAGE_GATHER4_C_V4_V4, v4i32>; 2591def : SampleRawPattern<int_SI_gather4_c_cl, IMAGE_GATHER4_C_CL_V4_V4, v4i32>; 2592def : SampleRawPattern<int_SI_gather4_c_cl, IMAGE_GATHER4_C_CL_V4_V8, v8i32>; 2593def : SampleRawPattern<int_SI_gather4_c_l, IMAGE_GATHER4_C_L_V4_V4, v4i32>; 2594def : SampleRawPattern<int_SI_gather4_c_l, IMAGE_GATHER4_C_L_V4_V8, v8i32>; 2595def : SampleRawPattern<int_SI_gather4_c_b, IMAGE_GATHER4_C_B_V4_V4, v4i32>; 2596def : SampleRawPattern<int_SI_gather4_c_b, IMAGE_GATHER4_C_B_V4_V8, v8i32>; 2597def : SampleRawPattern<int_SI_gather4_c_b_cl, IMAGE_GATHER4_C_B_CL_V4_V8, v8i32>; 2598def : SampleRawPattern<int_SI_gather4_c_lz, IMAGE_GATHER4_C_LZ_V4_V4, v4i32>; 2599 2600def : SampleRawPattern<int_SI_gather4_o, IMAGE_GATHER4_O_V4_V4, v4i32>; 2601def : SampleRawPattern<int_SI_gather4_cl_o, IMAGE_GATHER4_CL_O_V4_V4, v4i32>; 2602def : SampleRawPattern<int_SI_gather4_cl_o, IMAGE_GATHER4_CL_O_V4_V8, v8i32>; 2603def : SampleRawPattern<int_SI_gather4_l_o, IMAGE_GATHER4_L_O_V4_V4, v4i32>; 2604def : SampleRawPattern<int_SI_gather4_l_o, IMAGE_GATHER4_L_O_V4_V8, v8i32>; 2605def : SampleRawPattern<int_SI_gather4_b_o, IMAGE_GATHER4_B_O_V4_V4, v4i32>; 2606def : SampleRawPattern<int_SI_gather4_b_o, IMAGE_GATHER4_B_O_V4_V8, v8i32>; 2607def : SampleRawPattern<int_SI_gather4_b_cl_o, IMAGE_GATHER4_B_CL_O_V4_V8, v8i32>; 2608def : SampleRawPattern<int_SI_gather4_lz_o, IMAGE_GATHER4_LZ_O_V4_V4, v4i32>; 2609 2610def : SampleRawPattern<int_SI_gather4_c_o, IMAGE_GATHER4_C_O_V4_V4, v4i32>; 2611def : SampleRawPattern<int_SI_gather4_c_o, IMAGE_GATHER4_C_O_V4_V8, v8i32>; 2612def : SampleRawPattern<int_SI_gather4_c_cl_o, IMAGE_GATHER4_C_CL_O_V4_V8, v8i32>; 2613def : SampleRawPattern<int_SI_gather4_c_l_o, IMAGE_GATHER4_C_L_O_V4_V8, v8i32>; 2614def : SampleRawPattern<int_SI_gather4_c_b_o, IMAGE_GATHER4_C_B_O_V4_V8, v8i32>; 2615def : SampleRawPattern<int_SI_gather4_c_b_cl_o, IMAGE_GATHER4_C_B_CL_O_V4_V8, v8i32>; 2616def : SampleRawPattern<int_SI_gather4_c_lz_o, IMAGE_GATHER4_C_LZ_O_V4_V4, v4i32>; 2617def : SampleRawPattern<int_SI_gather4_c_lz_o, IMAGE_GATHER4_C_LZ_O_V4_V8, v8i32>; 2618 2619def : SampleRawPattern<int_SI_getlod, IMAGE_GET_LOD_V4_V1, i32>; 2620def : SampleRawPattern<int_SI_getlod, IMAGE_GET_LOD_V4_V2, v2i32>; 2621def : SampleRawPattern<int_SI_getlod, IMAGE_GET_LOD_V4_V4, v4i32>; 2622 2623def : ImagePattern<int_SI_getresinfo, IMAGE_GET_RESINFO_V4_V1, i32>; 2624defm : ImagePatterns<int_SI_image_load, "IMAGE_LOAD">; 2625defm : ImagePatterns<int_SI_image_load_mip, "IMAGE_LOAD_MIP">; 2626defm : ImageLoadPatterns<int_amdgcn_image_load, "IMAGE_LOAD">; 2627defm : ImageLoadPatterns<int_amdgcn_image_load_mip, "IMAGE_LOAD_MIP">; 2628defm : ImageStorePatterns<int_amdgcn_image_store, "IMAGE_STORE">; 2629defm : ImageStorePatterns<int_amdgcn_image_store_mip, "IMAGE_STORE_MIP">; 2630defm : ImageAtomicPatterns<int_amdgcn_image_atomic_swap, "IMAGE_ATOMIC_SWAP">; 2631def : ImageAtomicCmpSwapPattern<IMAGE_ATOMIC_CMPSWAP_V1, i32>; 2632def : ImageAtomicCmpSwapPattern<IMAGE_ATOMIC_CMPSWAP_V2, v2i32>; 2633def : ImageAtomicCmpSwapPattern<IMAGE_ATOMIC_CMPSWAP_V4, v4i32>; 2634defm : ImageAtomicPatterns<int_amdgcn_image_atomic_add, "IMAGE_ATOMIC_ADD">; 2635defm : ImageAtomicPatterns<int_amdgcn_image_atomic_sub, "IMAGE_ATOMIC_SUB">; 2636defm : ImageAtomicPatterns<int_amdgcn_image_atomic_smin, "IMAGE_ATOMIC_SMIN">; 2637defm : ImageAtomicPatterns<int_amdgcn_image_atomic_umin, "IMAGE_ATOMIC_UMIN">; 2638defm : ImageAtomicPatterns<int_amdgcn_image_atomic_smax, "IMAGE_ATOMIC_SMAX">; 2639defm : ImageAtomicPatterns<int_amdgcn_image_atomic_umax, "IMAGE_ATOMIC_UMAX">; 2640defm : ImageAtomicPatterns<int_amdgcn_image_atomic_and, "IMAGE_ATOMIC_AND">; 2641defm : ImageAtomicPatterns<int_amdgcn_image_atomic_or, "IMAGE_ATOMIC_OR">; 2642defm : ImageAtomicPatterns<int_amdgcn_image_atomic_xor, "IMAGE_ATOMIC_XOR">; 2643defm : ImageAtomicPatterns<int_amdgcn_image_atomic_inc, "IMAGE_ATOMIC_INC">; 2644defm : ImageAtomicPatterns<int_amdgcn_image_atomic_dec, "IMAGE_ATOMIC_DEC">; 2645 2646/* SIsample for simple 1D texture lookup */ 2647def : Pat < 2648 (SIsample i32:$addr, v8i32:$rsrc, v4i32:$sampler, imm), 2649 (IMAGE_SAMPLE_V4_V1 $addr, $rsrc, $sampler, 0xf, 0, 0, 0, 0, 0, 0, 0) 2650>; 2651 2652class SamplePattern<SDNode name, MIMG opcode, ValueType vt> : Pat < 2653 (name vt:$addr, v8i32:$rsrc, v4i32:$sampler, imm), 2654 (opcode $addr, $rsrc, $sampler, 0xf, 0, 0, 0, 0, 0, 0, 0) 2655>; 2656 2657class SampleRectPattern<SDNode name, MIMG opcode, ValueType vt> : Pat < 2658 (name vt:$addr, v8i32:$rsrc, v4i32:$sampler, TEX_RECT), 2659 (opcode $addr, $rsrc, $sampler, 0xf, 1, 0, 0, 0, 0, 0, 0) 2660>; 2661 2662class SampleArrayPattern<SDNode name, MIMG opcode, ValueType vt> : Pat < 2663 (name vt:$addr, v8i32:$rsrc, v4i32:$sampler, TEX_ARRAY), 2664 (opcode $addr, $rsrc, $sampler, 0xf, 0, 0, 0, 0, 0, 0, 1) 2665>; 2666 2667class SampleShadowPattern<SDNode name, MIMG opcode, 2668 ValueType vt> : Pat < 2669 (name vt:$addr, v8i32:$rsrc, v4i32:$sampler, TEX_SHADOW), 2670 (opcode $addr, $rsrc, $sampler, 0xf, 0, 0, 0, 0, 0, 0, 0) 2671>; 2672 2673class SampleShadowArrayPattern<SDNode name, MIMG opcode, 2674 ValueType vt> : Pat < 2675 (name vt:$addr, v8i32:$rsrc, v4i32:$sampler, TEX_SHADOW_ARRAY), 2676 (opcode $addr, $rsrc, $sampler, 0xf, 0, 0, 0, 0, 0, 0, 1) 2677>; 2678 2679/* SIsample* for texture lookups consuming more address parameters */ 2680multiclass SamplePatterns<MIMG sample, MIMG sample_c, MIMG sample_l, 2681 MIMG sample_c_l, MIMG sample_b, MIMG sample_c_b, 2682MIMG sample_d, MIMG sample_c_d, ValueType addr_type> { 2683 def : SamplePattern <SIsample, sample, addr_type>; 2684 def : SampleRectPattern <SIsample, sample, addr_type>; 2685 def : SampleArrayPattern <SIsample, sample, addr_type>; 2686 def : SampleShadowPattern <SIsample, sample_c, addr_type>; 2687 def : SampleShadowArrayPattern <SIsample, sample_c, addr_type>; 2688 2689 def : SamplePattern <SIsamplel, sample_l, addr_type>; 2690 def : SampleArrayPattern <SIsamplel, sample_l, addr_type>; 2691 def : SampleShadowPattern <SIsamplel, sample_c_l, addr_type>; 2692 def : SampleShadowArrayPattern <SIsamplel, sample_c_l, addr_type>; 2693 2694 def : SamplePattern <SIsampleb, sample_b, addr_type>; 2695 def : SampleArrayPattern <SIsampleb, sample_b, addr_type>; 2696 def : SampleShadowPattern <SIsampleb, sample_c_b, addr_type>; 2697 def : SampleShadowArrayPattern <SIsampleb, sample_c_b, addr_type>; 2698 2699 def : SamplePattern <SIsampled, sample_d, addr_type>; 2700 def : SampleArrayPattern <SIsampled, sample_d, addr_type>; 2701 def : SampleShadowPattern <SIsampled, sample_c_d, addr_type>; 2702 def : SampleShadowArrayPattern <SIsampled, sample_c_d, addr_type>; 2703} 2704 2705defm : SamplePatterns<IMAGE_SAMPLE_V4_V2, IMAGE_SAMPLE_C_V4_V2, 2706 IMAGE_SAMPLE_L_V4_V2, IMAGE_SAMPLE_C_L_V4_V2, 2707 IMAGE_SAMPLE_B_V4_V2, IMAGE_SAMPLE_C_B_V4_V2, 2708 IMAGE_SAMPLE_D_V4_V2, IMAGE_SAMPLE_C_D_V4_V2, 2709 v2i32>; 2710defm : SamplePatterns<IMAGE_SAMPLE_V4_V4, IMAGE_SAMPLE_C_V4_V4, 2711 IMAGE_SAMPLE_L_V4_V4, IMAGE_SAMPLE_C_L_V4_V4, 2712 IMAGE_SAMPLE_B_V4_V4, IMAGE_SAMPLE_C_B_V4_V4, 2713 IMAGE_SAMPLE_D_V4_V4, IMAGE_SAMPLE_C_D_V4_V4, 2714 v4i32>; 2715defm : SamplePatterns<IMAGE_SAMPLE_V4_V8, IMAGE_SAMPLE_C_V4_V8, 2716 IMAGE_SAMPLE_L_V4_V8, IMAGE_SAMPLE_C_L_V4_V8, 2717 IMAGE_SAMPLE_B_V4_V8, IMAGE_SAMPLE_C_B_V4_V8, 2718 IMAGE_SAMPLE_D_V4_V8, IMAGE_SAMPLE_C_D_V4_V8, 2719 v8i32>; 2720defm : SamplePatterns<IMAGE_SAMPLE_V4_V16, IMAGE_SAMPLE_C_V4_V16, 2721 IMAGE_SAMPLE_L_V4_V16, IMAGE_SAMPLE_C_L_V4_V16, 2722 IMAGE_SAMPLE_B_V4_V16, IMAGE_SAMPLE_C_B_V4_V16, 2723 IMAGE_SAMPLE_D_V4_V16, IMAGE_SAMPLE_C_D_V4_V16, 2724 v16i32>; 2725 2726/********** ============================================ **********/ 2727/********** Extraction, Insertion, Building and Casting **********/ 2728/********** ============================================ **********/ 2729 2730foreach Index = 0-2 in { 2731 def Extract_Element_v2i32_#Index : Extract_Element < 2732 i32, v2i32, Index, !cast<SubRegIndex>(sub#Index) 2733 >; 2734 def Insert_Element_v2i32_#Index : Insert_Element < 2735 i32, v2i32, Index, !cast<SubRegIndex>(sub#Index) 2736 >; 2737 2738 def Extract_Element_v2f32_#Index : Extract_Element < 2739 f32, v2f32, Index, !cast<SubRegIndex>(sub#Index) 2740 >; 2741 def Insert_Element_v2f32_#Index : Insert_Element < 2742 f32, v2f32, Index, !cast<SubRegIndex>(sub#Index) 2743 >; 2744} 2745 2746foreach Index = 0-3 in { 2747 def Extract_Element_v4i32_#Index : Extract_Element < 2748 i32, v4i32, Index, !cast<SubRegIndex>(sub#Index) 2749 >; 2750 def Insert_Element_v4i32_#Index : Insert_Element < 2751 i32, v4i32, Index, !cast<SubRegIndex>(sub#Index) 2752 >; 2753 2754 def Extract_Element_v4f32_#Index : Extract_Element < 2755 f32, v4f32, Index, !cast<SubRegIndex>(sub#Index) 2756 >; 2757 def Insert_Element_v4f32_#Index : Insert_Element < 2758 f32, v4f32, Index, !cast<SubRegIndex>(sub#Index) 2759 >; 2760} 2761 2762foreach Index = 0-7 in { 2763 def Extract_Element_v8i32_#Index : Extract_Element < 2764 i32, v8i32, Index, !cast<SubRegIndex>(sub#Index) 2765 >; 2766 def Insert_Element_v8i32_#Index : Insert_Element < 2767 i32, v8i32, Index, !cast<SubRegIndex>(sub#Index) 2768 >; 2769 2770 def Extract_Element_v8f32_#Index : Extract_Element < 2771 f32, v8f32, Index, !cast<SubRegIndex>(sub#Index) 2772 >; 2773 def Insert_Element_v8f32_#Index : Insert_Element < 2774 f32, v8f32, Index, !cast<SubRegIndex>(sub#Index) 2775 >; 2776} 2777 2778foreach Index = 0-15 in { 2779 def Extract_Element_v16i32_#Index : Extract_Element < 2780 i32, v16i32, Index, !cast<SubRegIndex>(sub#Index) 2781 >; 2782 def Insert_Element_v16i32_#Index : Insert_Element < 2783 i32, v16i32, Index, !cast<SubRegIndex>(sub#Index) 2784 >; 2785 2786 def Extract_Element_v16f32_#Index : Extract_Element < 2787 f32, v16f32, Index, !cast<SubRegIndex>(sub#Index) 2788 >; 2789 def Insert_Element_v16f32_#Index : Insert_Element < 2790 f32, v16f32, Index, !cast<SubRegIndex>(sub#Index) 2791 >; 2792} 2793 2794// FIXME: Why do only some of these type combinations for SReg and 2795// VReg? 2796// 32-bit bitcast 2797def : BitConvert <i32, f32, VGPR_32>; 2798def : BitConvert <f32, i32, VGPR_32>; 2799def : BitConvert <i32, f32, SReg_32>; 2800def : BitConvert <f32, i32, SReg_32>; 2801 2802// 64-bit bitcast 2803def : BitConvert <i64, f64, VReg_64>; 2804def : BitConvert <f64, i64, VReg_64>; 2805def : BitConvert <v2i32, v2f32, VReg_64>; 2806def : BitConvert <v2f32, v2i32, VReg_64>; 2807def : BitConvert <i64, v2i32, VReg_64>; 2808def : BitConvert <v2i32, i64, VReg_64>; 2809def : BitConvert <i64, v2f32, VReg_64>; 2810def : BitConvert <v2f32, i64, VReg_64>; 2811def : BitConvert <f64, v2f32, VReg_64>; 2812def : BitConvert <v2f32, f64, VReg_64>; 2813def : BitConvert <f64, v2i32, VReg_64>; 2814def : BitConvert <v2i32, f64, VReg_64>; 2815def : BitConvert <v4i32, v4f32, VReg_128>; 2816def : BitConvert <v4f32, v4i32, VReg_128>; 2817 2818// 128-bit bitcast 2819def : BitConvert <v2i64, v4i32, SReg_128>; 2820def : BitConvert <v4i32, v2i64, SReg_128>; 2821def : BitConvert <v2f64, v4f32, VReg_128>; 2822def : BitConvert <v2f64, v4i32, VReg_128>; 2823def : BitConvert <v4f32, v2f64, VReg_128>; 2824def : BitConvert <v4i32, v2f64, VReg_128>; 2825 2826// 256-bit bitcast 2827def : BitConvert <v8i32, v8f32, SReg_256>; 2828def : BitConvert <v8f32, v8i32, SReg_256>; 2829def : BitConvert <v8i32, v8f32, VReg_256>; 2830def : BitConvert <v8f32, v8i32, VReg_256>; 2831 2832// 512-bit bitcast 2833def : BitConvert <v16i32, v16f32, VReg_512>; 2834def : BitConvert <v16f32, v16i32, VReg_512>; 2835 2836/********** =================== **********/ 2837/********** Src & Dst modifiers **********/ 2838/********** =================== **********/ 2839 2840def : Pat < 2841 (AMDGPUclamp (VOP3Mods0Clamp f32:$src0, i32:$src0_modifiers, i32:$omod), 2842 (f32 FP_ZERO), (f32 FP_ONE)), 2843 (V_ADD_F32_e64 $src0_modifiers, $src0, 0, 0, 1, $omod) 2844>; 2845 2846/********** ================================ **********/ 2847/********** Floating point absolute/negative **********/ 2848/********** ================================ **********/ 2849 2850// Prevent expanding both fneg and fabs. 2851 2852def : Pat < 2853 (fneg (fabs f32:$src)), 2854 (S_OR_B32 $src, 0x80000000) // Set sign bit 2855>; 2856 2857// FIXME: Should use S_OR_B32 2858def : Pat < 2859 (fneg (fabs f64:$src)), 2860 (REG_SEQUENCE VReg_64, 2861 (i32 (EXTRACT_SUBREG f64:$src, sub0)), 2862 sub0, 2863 (V_OR_B32_e32 (EXTRACT_SUBREG f64:$src, sub1), 2864 (V_MOV_B32_e32 0x80000000)), // Set sign bit. 2865 sub1) 2866>; 2867 2868def : Pat < 2869 (fabs f32:$src), 2870 (V_AND_B32_e32 $src, (V_MOV_B32_e32 0x7fffffff)) 2871>; 2872 2873def : Pat < 2874 (fneg f32:$src), 2875 (V_XOR_B32_e32 $src, (V_MOV_B32_e32 0x80000000)) 2876>; 2877 2878def : Pat < 2879 (fabs f64:$src), 2880 (REG_SEQUENCE VReg_64, 2881 (i32 (EXTRACT_SUBREG f64:$src, sub0)), 2882 sub0, 2883 (V_AND_B32_e32 (EXTRACT_SUBREG f64:$src, sub1), 2884 (V_MOV_B32_e32 0x7fffffff)), // Set sign bit. 2885 sub1) 2886>; 2887 2888def : Pat < 2889 (fneg f64:$src), 2890 (REG_SEQUENCE VReg_64, 2891 (i32 (EXTRACT_SUBREG f64:$src, sub0)), 2892 sub0, 2893 (V_XOR_B32_e32 (EXTRACT_SUBREG f64:$src, sub1), 2894 (V_MOV_B32_e32 0x80000000)), 2895 sub1) 2896>; 2897 2898/********** ================== **********/ 2899/********** Immediate Patterns **********/ 2900/********** ================== **********/ 2901 2902def : Pat < 2903 (SGPRImm<(i32 imm)>:$imm), 2904 (S_MOV_B32 imm:$imm) 2905>; 2906 2907def : Pat < 2908 (SGPRImm<(f32 fpimm)>:$imm), 2909 (S_MOV_B32 (f32 (bitcast_fpimm_to_i32 $imm))) 2910>; 2911 2912def : Pat < 2913 (i32 imm:$imm), 2914 (V_MOV_B32_e32 imm:$imm) 2915>; 2916 2917def : Pat < 2918 (f32 fpimm:$imm), 2919 (V_MOV_B32_e32 (f32 (bitcast_fpimm_to_i32 $imm))) 2920>; 2921 2922def : Pat < 2923 (i64 InlineImm<i64>:$imm), 2924 (S_MOV_B64 InlineImm<i64>:$imm) 2925>; 2926 2927// XXX - Should this use a s_cmp to set SCC? 2928 2929// Set to sign-extended 64-bit value (true = -1, false = 0) 2930def : Pat < 2931 (i1 imm:$imm), 2932 (S_MOV_B64 (i64 (as_i64imm $imm))) 2933>; 2934 2935def : Pat < 2936 (f64 InlineFPImm<f64>:$imm), 2937 (S_MOV_B64 (f64 (bitcast_fpimm_to_i64 InlineFPImm<f64>:$imm))) 2938>; 2939 2940/********** ================== **********/ 2941/********** Intrinsic Patterns **********/ 2942/********** ================== **********/ 2943 2944def : POW_Common <V_LOG_F32_e32, V_EXP_F32_e32, V_MUL_LEGACY_F32_e32>; 2945 2946def : Pat < 2947 (int_AMDGPU_cube v4f32:$src), 2948 (REG_SEQUENCE VReg_128, 2949 (V_CUBETC_F32 0 /* src0_modifiers */, (EXTRACT_SUBREG $src, sub0), 2950 0 /* src1_modifiers */, (EXTRACT_SUBREG $src, sub1), 2951 0 /* src2_modifiers */, (EXTRACT_SUBREG $src, sub2), 2952 0 /* clamp */, 0 /* omod */), sub0, 2953 (V_CUBESC_F32 0 /* src0_modifiers */, (EXTRACT_SUBREG $src, sub0), 2954 0 /* src1_modifiers */,(EXTRACT_SUBREG $src, sub1), 2955 0 /* src2_modifiers */,(EXTRACT_SUBREG $src, sub2), 2956 0 /* clamp */, 0 /* omod */), sub1, 2957 (V_CUBEMA_F32 0 /* src1_modifiers */,(EXTRACT_SUBREG $src, sub0), 2958 0 /* src1_modifiers */,(EXTRACT_SUBREG $src, sub1), 2959 0 /* src1_modifiers */,(EXTRACT_SUBREG $src, sub2), 2960 0 /* clamp */, 0 /* omod */), sub2, 2961 (V_CUBEID_F32 0 /* src1_modifiers */,(EXTRACT_SUBREG $src, sub0), 2962 0 /* src1_modifiers */,(EXTRACT_SUBREG $src, sub1), 2963 0 /* src1_modifiers */,(EXTRACT_SUBREG $src, sub2), 2964 0 /* clamp */, 0 /* omod */), sub3) 2965>; 2966 2967def : Pat < 2968 (i32 (sext i1:$src0)), 2969 (V_CNDMASK_B32_e64 (i32 0), (i32 -1), $src0) 2970>; 2971 2972class Ext32Pat <SDNode ext> : Pat < 2973 (i32 (ext i1:$src0)), 2974 (V_CNDMASK_B32_e64 (i32 0), (i32 1), $src0) 2975>; 2976 2977def : Ext32Pat <zext>; 2978def : Ext32Pat <anyext>; 2979 2980// Offset in an 32-bit VGPR 2981def : Pat < 2982 (SIload_constant v4i32:$sbase, i32:$voff), 2983 (BUFFER_LOAD_DWORD_OFFEN $voff, $sbase, 0, 0, 0, 0, 0) 2984>; 2985 2986// The multiplication scales from [0,1] to the unsigned integer range 2987def : Pat < 2988 (AMDGPUurecip i32:$src0), 2989 (V_CVT_U32_F32_e32 2990 (V_MUL_F32_e32 CONST.FP_UINT_MAX_PLUS_1, 2991 (V_RCP_IFLAG_F32_e32 (V_CVT_F32_U32_e32 $src0)))) 2992>; 2993 2994def : Pat < 2995 (int_SI_tid), 2996 (V_MBCNT_HI_U32_B32_e64 0xffffffff, 2997 (V_MBCNT_LO_U32_B32_e64 0xffffffff, 0)) 2998>; 2999 3000//===----------------------------------------------------------------------===// 3001// VOP3 Patterns 3002//===----------------------------------------------------------------------===// 3003 3004def : IMad24Pat<V_MAD_I32_I24>; 3005def : UMad24Pat<V_MAD_U32_U24>; 3006 3007defm : BFIPatterns <V_BFI_B32, S_MOV_B32, SReg_64>; 3008def : ROTRPattern <V_ALIGNBIT_B32>; 3009 3010/********** ======================= **********/ 3011/********** Load/Store Patterns **********/ 3012/********** ======================= **********/ 3013 3014class DSReadPat <DS inst, ValueType vt, PatFrag frag> : Pat < 3015 (vt (frag (DS1Addr1Offset i32:$ptr, i32:$offset))), 3016 (inst $ptr, (as_i16imm $offset), (i1 0)) 3017>; 3018 3019def : DSReadPat <DS_READ_I8, i32, si_sextload_local_i8>; 3020def : DSReadPat <DS_READ_U8, i32, si_az_extload_local_i8>; 3021def : DSReadPat <DS_READ_I16, i32, si_sextload_local_i16>; 3022def : DSReadPat <DS_READ_U16, i32, si_az_extload_local_i16>; 3023def : DSReadPat <DS_READ_B32, i32, si_load_local>; 3024 3025let AddedComplexity = 100 in { 3026 3027def : DSReadPat <DS_READ_B64, v2i32, si_load_local_align8>; 3028 3029} // End AddedComplexity = 100 3030 3031def : Pat < 3032 (v2i32 (si_load_local (DS64Bit4ByteAligned i32:$ptr, i8:$offset0, 3033 i8:$offset1))), 3034 (DS_READ2_B32 $ptr, $offset0, $offset1, (i1 0)) 3035>; 3036 3037class DSWritePat <DS inst, ValueType vt, PatFrag frag> : Pat < 3038 (frag vt:$value, (DS1Addr1Offset i32:$ptr, i32:$offset)), 3039 (inst $ptr, $value, (as_i16imm $offset), (i1 0)) 3040>; 3041 3042def : DSWritePat <DS_WRITE_B8, i32, si_truncstore_local_i8>; 3043def : DSWritePat <DS_WRITE_B16, i32, si_truncstore_local_i16>; 3044def : DSWritePat <DS_WRITE_B32, i32, si_store_local>; 3045 3046let AddedComplexity = 100 in { 3047 3048def : DSWritePat <DS_WRITE_B64, v2i32, si_store_local_align8>; 3049} // End AddedComplexity = 100 3050 3051def : Pat < 3052 (si_store_local v2i32:$value, (DS64Bit4ByteAligned i32:$ptr, i8:$offset0, 3053 i8:$offset1)), 3054 (DS_WRITE2_B32 $ptr, (EXTRACT_SUBREG $value, sub0), 3055 (EXTRACT_SUBREG $value, sub1), $offset0, $offset1, 3056 (i1 0)) 3057>; 3058 3059class DSAtomicRetPat<DS inst, ValueType vt, PatFrag frag> : Pat < 3060 (frag (DS1Addr1Offset i32:$ptr, i32:$offset), vt:$value), 3061 (inst $ptr, $value, (as_i16imm $offset), (i1 0)) 3062>; 3063 3064class DSAtomicCmpXChg <DS inst, ValueType vt, PatFrag frag> : Pat < 3065 (frag (DS1Addr1Offset i32:$ptr, i32:$offset), vt:$cmp, vt:$swap), 3066 (inst $ptr, $cmp, $swap, (as_i16imm $offset), (i1 0)) 3067>; 3068 3069 3070// 32-bit atomics. 3071def : DSAtomicRetPat<DS_WRXCHG_RTN_B32, i32, si_atomic_swap_local>; 3072def : DSAtomicRetPat<DS_ADD_RTN_U32, i32, si_atomic_load_add_local>; 3073def : DSAtomicRetPat<DS_SUB_RTN_U32, i32, si_atomic_load_sub_local>; 3074def : DSAtomicRetPat<DS_AND_RTN_B32, i32, si_atomic_load_and_local>; 3075def : DSAtomicRetPat<DS_OR_RTN_B32, i32, si_atomic_load_or_local>; 3076def : DSAtomicRetPat<DS_XOR_RTN_B32, i32, si_atomic_load_xor_local>; 3077def : DSAtomicRetPat<DS_MIN_RTN_I32, i32, si_atomic_load_min_local>; 3078def : DSAtomicRetPat<DS_MAX_RTN_I32, i32, si_atomic_load_max_local>; 3079def : DSAtomicRetPat<DS_MIN_RTN_U32, i32, si_atomic_load_umin_local>; 3080def : DSAtomicRetPat<DS_MAX_RTN_U32, i32, si_atomic_load_umax_local>; 3081 3082def : DSAtomicCmpXChg<DS_CMPST_RTN_B32, i32, si_atomic_cmp_swap_32_local>; 3083 3084// 64-bit atomics. 3085def : DSAtomicRetPat<DS_WRXCHG_RTN_B64, i64, si_atomic_swap_local>; 3086def : DSAtomicRetPat<DS_ADD_RTN_U64, i64, si_atomic_load_add_local>; 3087def : DSAtomicRetPat<DS_SUB_RTN_U64, i64, si_atomic_load_sub_local>; 3088def : DSAtomicRetPat<DS_AND_RTN_B64, i64, si_atomic_load_and_local>; 3089def : DSAtomicRetPat<DS_OR_RTN_B64, i64, si_atomic_load_or_local>; 3090def : DSAtomicRetPat<DS_XOR_RTN_B64, i64, si_atomic_load_xor_local>; 3091def : DSAtomicRetPat<DS_MIN_RTN_I64, i64, si_atomic_load_min_local>; 3092def : DSAtomicRetPat<DS_MAX_RTN_I64, i64, si_atomic_load_max_local>; 3093def : DSAtomicRetPat<DS_MIN_RTN_U64, i64, si_atomic_load_umin_local>; 3094def : DSAtomicRetPat<DS_MAX_RTN_U64, i64, si_atomic_load_umax_local>; 3095 3096def : DSAtomicCmpXChg<DS_CMPST_RTN_B64, i64, si_atomic_cmp_swap_64_local>; 3097 3098 3099//===----------------------------------------------------------------------===// 3100// MUBUF Patterns 3101//===----------------------------------------------------------------------===// 3102 3103multiclass MUBUFLoad_Pattern <MUBUF Instr_ADDR64, ValueType vt, 3104 PatFrag constant_ld> { 3105 def : Pat < 3106 (vt (constant_ld (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr, i32:$soffset, 3107 i16:$offset, i1:$glc, i1:$slc, i1:$tfe))), 3108 (Instr_ADDR64 $vaddr, $srsrc, $soffset, $offset, $glc, $slc, $tfe) 3109 >; 3110} 3111 3112let Predicates = [isSICI] in { 3113defm : MUBUFLoad_Pattern <BUFFER_LOAD_SBYTE_ADDR64, i32, sextloadi8_constant>; 3114defm : MUBUFLoad_Pattern <BUFFER_LOAD_UBYTE_ADDR64, i32, az_extloadi8_constant>; 3115defm : MUBUFLoad_Pattern <BUFFER_LOAD_SSHORT_ADDR64, i32, sextloadi16_constant>; 3116defm : MUBUFLoad_Pattern <BUFFER_LOAD_USHORT_ADDR64, i32, az_extloadi16_constant>; 3117} // End Predicates = [isSICI] 3118 3119class MUBUFScratchLoadPat <MUBUF Instr, ValueType vt, PatFrag ld> : Pat < 3120 (vt (ld (MUBUFScratch v4i32:$srsrc, i32:$vaddr, 3121 i32:$soffset, u16imm:$offset))), 3122 (Instr $vaddr, $srsrc, $soffset, $offset, 0, 0, 0) 3123>; 3124 3125def : MUBUFScratchLoadPat <BUFFER_LOAD_SBYTE_OFFEN, i32, sextloadi8_private>; 3126def : MUBUFScratchLoadPat <BUFFER_LOAD_UBYTE_OFFEN, i32, extloadi8_private>; 3127def : MUBUFScratchLoadPat <BUFFER_LOAD_SSHORT_OFFEN, i32, sextloadi16_private>; 3128def : MUBUFScratchLoadPat <BUFFER_LOAD_USHORT_OFFEN, i32, extloadi16_private>; 3129def : MUBUFScratchLoadPat <BUFFER_LOAD_DWORD_OFFEN, i32, load_private>; 3130def : MUBUFScratchLoadPat <BUFFER_LOAD_DWORDX2_OFFEN, v2i32, load_private>; 3131def : MUBUFScratchLoadPat <BUFFER_LOAD_DWORDX4_OFFEN, v4i32, load_private>; 3132 3133// BUFFER_LOAD_DWORD*, addr64=0 3134multiclass MUBUF_Load_Dword <ValueType vt, MUBUF offset, MUBUF offen, MUBUF idxen, 3135 MUBUF bothen> { 3136 3137 def : Pat < 3138 (vt (int_SI_buffer_load_dword v4i32:$rsrc, (i32 imm), i32:$soffset, 3139 imm:$offset, 0, 0, imm:$glc, imm:$slc, 3140 imm:$tfe)), 3141 (offset $rsrc, $soffset, (as_i16imm $offset), (as_i1imm $glc), 3142 (as_i1imm $slc), (as_i1imm $tfe)) 3143 >; 3144 3145 def : Pat < 3146 (vt (int_SI_buffer_load_dword v4i32:$rsrc, i32:$vaddr, i32:$soffset, 3147 imm:$offset, 1, 0, imm:$glc, imm:$slc, 3148 imm:$tfe)), 3149 (offen $vaddr, $rsrc, $soffset, (as_i16imm $offset), (as_i1imm $glc), (as_i1imm $slc), 3150 (as_i1imm $tfe)) 3151 >; 3152 3153 def : Pat < 3154 (vt (int_SI_buffer_load_dword v4i32:$rsrc, i32:$vaddr, i32:$soffset, 3155 imm:$offset, 0, 1, imm:$glc, imm:$slc, 3156 imm:$tfe)), 3157 (idxen $vaddr, $rsrc, $soffset, (as_i16imm $offset), (as_i1imm $glc), 3158 (as_i1imm $slc), (as_i1imm $tfe)) 3159 >; 3160 3161 def : Pat < 3162 (vt (int_SI_buffer_load_dword v4i32:$rsrc, v2i32:$vaddr, i32:$soffset, 3163 imm:$offset, 1, 1, imm:$glc, imm:$slc, 3164 imm:$tfe)), 3165 (bothen $vaddr, $rsrc, $soffset, (as_i16imm $offset), (as_i1imm $glc), (as_i1imm $slc), 3166 (as_i1imm $tfe)) 3167 >; 3168} 3169 3170defm : MUBUF_Load_Dword <i32, BUFFER_LOAD_DWORD_OFFSET, BUFFER_LOAD_DWORD_OFFEN, 3171 BUFFER_LOAD_DWORD_IDXEN, BUFFER_LOAD_DWORD_BOTHEN>; 3172defm : MUBUF_Load_Dword <v2i32, BUFFER_LOAD_DWORDX2_OFFSET, BUFFER_LOAD_DWORDX2_OFFEN, 3173 BUFFER_LOAD_DWORDX2_IDXEN, BUFFER_LOAD_DWORDX2_BOTHEN>; 3174defm : MUBUF_Load_Dword <v4i32, BUFFER_LOAD_DWORDX4_OFFSET, BUFFER_LOAD_DWORDX4_OFFEN, 3175 BUFFER_LOAD_DWORDX4_IDXEN, BUFFER_LOAD_DWORDX4_BOTHEN>; 3176 3177class MUBUFScratchStorePat <MUBUF Instr, ValueType vt, PatFrag st> : Pat < 3178 (st vt:$value, (MUBUFScratch v4i32:$srsrc, i32:$vaddr, i32:$soffset, 3179 u16imm:$offset)), 3180 (Instr $value, $vaddr, $srsrc, $soffset, $offset, 0, 0, 0) 3181>; 3182 3183def : MUBUFScratchStorePat <BUFFER_STORE_BYTE_OFFEN, i32, truncstorei8_private>; 3184def : MUBUFScratchStorePat <BUFFER_STORE_SHORT_OFFEN, i32, truncstorei16_private>; 3185def : MUBUFScratchStorePat <BUFFER_STORE_DWORD_OFFEN, i32, store_private>; 3186def : MUBUFScratchStorePat <BUFFER_STORE_DWORDX2_OFFEN, v2i32, store_private>; 3187def : MUBUFScratchStorePat <BUFFER_STORE_DWORDX4_OFFEN, v4i32, store_private>; 3188 3189//===----------------------------------------------------------------------===// 3190// MTBUF Patterns 3191//===----------------------------------------------------------------------===// 3192 3193// TBUFFER_STORE_FORMAT_*, addr64=0 3194class MTBUF_StoreResource <ValueType vt, int num_channels, MTBUF opcode> : Pat< 3195 (SItbuffer_store v4i32:$rsrc, vt:$vdata, num_channels, i32:$vaddr, 3196 i32:$soffset, imm:$inst_offset, imm:$dfmt, 3197 imm:$nfmt, imm:$offen, imm:$idxen, 3198 imm:$glc, imm:$slc, imm:$tfe), 3199 (opcode 3200 $vdata, (as_i16imm $inst_offset), (as_i1imm $offen), (as_i1imm $idxen), 3201 (as_i1imm $glc), 0, (as_i8imm $dfmt), (as_i8imm $nfmt), $vaddr, $rsrc, 3202 (as_i1imm $slc), (as_i1imm $tfe), $soffset) 3203>; 3204 3205def : MTBUF_StoreResource <i32, 1, TBUFFER_STORE_FORMAT_X>; 3206def : MTBUF_StoreResource <v2i32, 2, TBUFFER_STORE_FORMAT_XY>; 3207def : MTBUF_StoreResource <v4i32, 3, TBUFFER_STORE_FORMAT_XYZ>; 3208def : MTBUF_StoreResource <v4i32, 4, TBUFFER_STORE_FORMAT_XYZW>; 3209 3210/********** ====================== **********/ 3211/********** Indirect adressing **********/ 3212/********** ====================== **********/ 3213 3214multiclass SI_INDIRECT_Pattern <ValueType vt, ValueType eltvt, string VecSize> { 3215 3216 // 1. Extract with offset 3217 def : Pat< 3218 (eltvt (extractelt vt:$vec, (add i32:$idx, imm:$off))), 3219 (!cast<Instruction>("SI_INDIRECT_SRC_"#VecSize) $vec, $idx, imm:$off) 3220 >; 3221 3222 // 2. Extract without offset 3223 def : Pat< 3224 (eltvt (extractelt vt:$vec, i32:$idx)), 3225 (!cast<Instruction>("SI_INDIRECT_SRC_"#VecSize) $vec, $idx, 0) 3226 >; 3227 3228 // 3. Insert with offset 3229 def : Pat< 3230 (insertelt vt:$vec, eltvt:$val, (add i32:$idx, imm:$off)), 3231 (!cast<Instruction>("SI_INDIRECT_DST_"#VecSize) $vec, $idx, imm:$off, $val) 3232 >; 3233 3234 // 4. Insert without offset 3235 def : Pat< 3236 (insertelt vt:$vec, eltvt:$val, i32:$idx), 3237 (!cast<Instruction>("SI_INDIRECT_DST_"#VecSize) $vec, $idx, 0, $val) 3238 >; 3239} 3240 3241defm : SI_INDIRECT_Pattern <v2f32, f32, "V2">; 3242defm : SI_INDIRECT_Pattern <v4f32, f32, "V4">; 3243defm : SI_INDIRECT_Pattern <v8f32, f32, "V8">; 3244defm : SI_INDIRECT_Pattern <v16f32, f32, "V16">; 3245 3246defm : SI_INDIRECT_Pattern <v2i32, i32, "V2">; 3247defm : SI_INDIRECT_Pattern <v4i32, i32, "V4">; 3248defm : SI_INDIRECT_Pattern <v8i32, i32, "V8">; 3249defm : SI_INDIRECT_Pattern <v16i32, i32, "V16">; 3250 3251//===----------------------------------------------------------------------===// 3252// Conversion Patterns 3253//===----------------------------------------------------------------------===// 3254 3255def : Pat<(i32 (sext_inreg i32:$src, i1)), 3256 (S_BFE_I32 i32:$src, 65536)>; // 0 | 1 << 16 3257 3258// Handle sext_inreg in i64 3259def : Pat < 3260 (i64 (sext_inreg i64:$src, i1)), 3261 (S_BFE_I64 i64:$src, 0x10000) // 0 | 1 << 16 3262>; 3263 3264def : Pat < 3265 (i64 (sext_inreg i64:$src, i8)), 3266 (S_BFE_I64 i64:$src, 0x80000) // 0 | 8 << 16 3267>; 3268 3269def : Pat < 3270 (i64 (sext_inreg i64:$src, i16)), 3271 (S_BFE_I64 i64:$src, 0x100000) // 0 | 16 << 16 3272>; 3273 3274def : Pat < 3275 (i64 (sext_inreg i64:$src, i32)), 3276 (S_BFE_I64 i64:$src, 0x200000) // 0 | 32 << 16 3277>; 3278 3279class ZExt_i64_i32_Pat <SDNode ext> : Pat < 3280 (i64 (ext i32:$src)), 3281 (REG_SEQUENCE SReg_64, $src, sub0, (S_MOV_B32 0), sub1) 3282>; 3283 3284class ZExt_i64_i1_Pat <SDNode ext> : Pat < 3285 (i64 (ext i1:$src)), 3286 (REG_SEQUENCE VReg_64, 3287 (V_CNDMASK_B32_e64 (i32 0), (i32 1), $src), sub0, 3288 (S_MOV_B32 0), sub1) 3289>; 3290 3291 3292def : ZExt_i64_i32_Pat<zext>; 3293def : ZExt_i64_i32_Pat<anyext>; 3294def : ZExt_i64_i1_Pat<zext>; 3295def : ZExt_i64_i1_Pat<anyext>; 3296 3297// FIXME: We need to use COPY_TO_REGCLASS to work-around the fact that 3298// REG_SEQUENCE patterns don't support instructions with multiple outputs. 3299def : Pat < 3300 (i64 (sext i32:$src)), 3301 (REG_SEQUENCE SReg_64, $src, sub0, 3302 (i32 (COPY_TO_REGCLASS (S_ASHR_I32 $src, 31), SGPR_32)), sub1) 3303>; 3304 3305def : Pat < 3306 (i64 (sext i1:$src)), 3307 (REG_SEQUENCE VReg_64, 3308 (V_CNDMASK_B32_e64 0, -1, $src), sub0, 3309 (V_CNDMASK_B32_e64 0, -1, $src), sub1) 3310>; 3311 3312// If we need to perform a logical operation on i1 values, we need to 3313// use vector comparisons since there is only one SCC register. Vector 3314// comparisions still write to a pair of SGPRs, so treat these as 3315// 64-bit comparisons. When legalizing SGPR copies, instructions 3316// resulting in the copies from SCC to these instructions will be 3317// moved to the VALU. 3318def : Pat < 3319 (i1 (and i1:$src0, i1:$src1)), 3320 (S_AND_B64 $src0, $src1) 3321>; 3322 3323def : Pat < 3324 (i1 (or i1:$src0, i1:$src1)), 3325 (S_OR_B64 $src0, $src1) 3326>; 3327 3328def : Pat < 3329 (i1 (xor i1:$src0, i1:$src1)), 3330 (S_XOR_B64 $src0, $src1) 3331>; 3332 3333def : Pat < 3334 (f32 (sint_to_fp i1:$src)), 3335 (V_CNDMASK_B32_e64 (i32 0), CONST.FP32_NEG_ONE, $src) 3336>; 3337 3338def : Pat < 3339 (f32 (uint_to_fp i1:$src)), 3340 (V_CNDMASK_B32_e64 (i32 0), CONST.FP32_ONE, $src) 3341>; 3342 3343def : Pat < 3344 (f64 (sint_to_fp i1:$src)), 3345 (V_CVT_F64_I32_e32 (V_CNDMASK_B32_e64 (i32 0), (i32 -1), $src)) 3346>; 3347 3348def : Pat < 3349 (f64 (uint_to_fp i1:$src)), 3350 (V_CVT_F64_U32_e32 (V_CNDMASK_B32_e64 (i32 0), (i32 1), $src)) 3351>; 3352 3353//===----------------------------------------------------------------------===// 3354// Miscellaneous Patterns 3355//===----------------------------------------------------------------------===// 3356 3357def : Pat < 3358 (i32 (trunc i64:$a)), 3359 (EXTRACT_SUBREG $a, sub0) 3360>; 3361 3362def : Pat < 3363 (i1 (trunc i32:$a)), 3364 (V_CMP_EQ_I32_e64 (S_AND_B32 (i32 1), $a), 1) 3365>; 3366 3367def : Pat < 3368 (i1 (trunc i64:$a)), 3369 (V_CMP_EQ_I32_e64 (S_AND_B32 (i32 1), 3370 (EXTRACT_SUBREG $a, sub0)), 1) 3371>; 3372 3373def : Pat < 3374 (i32 (bswap i32:$a)), 3375 (V_BFI_B32 (S_MOV_B32 0x00ff00ff), 3376 (V_ALIGNBIT_B32 $a, $a, 24), 3377 (V_ALIGNBIT_B32 $a, $a, 8)) 3378>; 3379 3380def : Pat < 3381 (f32 (select i1:$src2, f32:$src1, f32:$src0)), 3382 (V_CNDMASK_B32_e64 $src0, $src1, $src2) 3383>; 3384 3385multiclass BFMPatterns <ValueType vt, InstSI BFM, InstSI MOV> { 3386 def : Pat < 3387 (vt (shl (vt (add (vt (shl 1, vt:$a)), -1)), vt:$b)), 3388 (BFM $a, $b) 3389 >; 3390 3391 def : Pat < 3392 (vt (add (vt (shl 1, vt:$a)), -1)), 3393 (BFM $a, (MOV 0)) 3394 >; 3395} 3396 3397defm : BFMPatterns <i32, S_BFM_B32, S_MOV_B32>; 3398// FIXME: defm : BFMPatterns <i64, S_BFM_B64, S_MOV_B64>; 3399 3400def : BFEPattern <V_BFE_U32, S_MOV_B32>; 3401 3402let Predicates = [isSICI] in { 3403def : Pat < 3404 (i64 (readcyclecounter)), 3405 (S_MEMTIME) 3406>; 3407} 3408 3409//===----------------------------------------------------------------------===// 3410// Fract Patterns 3411//===----------------------------------------------------------------------===// 3412 3413let Predicates = [isSI] in { 3414 3415// V_FRACT is buggy on SI, so the F32 version is never used and (x-floor(x)) is 3416// used instead. However, SI doesn't have V_FLOOR_F64, so the most efficient 3417// way to implement it is using V_FRACT_F64. 3418// The workaround for the V_FRACT bug is: 3419// fract(x) = isnan(x) ? x : min(V_FRACT(x), 0.99999999999999999) 3420 3421// Convert (x + (-floor(x)) to fract(x) 3422def : Pat < 3423 (f64 (fadd (f64 (VOP3Mods f64:$x, i32:$mods)), 3424 (f64 (fneg (f64 (ffloor (f64 (VOP3Mods f64:$x, i32:$mods)))))))), 3425 (V_CNDMASK_B64_PSEUDO 3426 (V_MIN_F64 3427 SRCMODS.NONE, 3428 (V_FRACT_F64_e64 $mods, $x, DSTCLAMP.NONE, DSTOMOD.NONE), 3429 SRCMODS.NONE, 3430 (V_MOV_B64_PSEUDO 0x3fefffffffffffff), 3431 DSTCLAMP.NONE, DSTOMOD.NONE), 3432 $x, 3433 (V_CMP_CLASS_F64_e64 SRCMODS.NONE, $x, 3/*NaN*/)) 3434>; 3435 3436// Convert floor(x) to (x - fract(x)) 3437def : Pat < 3438 (f64 (ffloor (f64 (VOP3Mods f64:$x, i32:$mods)))), 3439 (V_ADD_F64 3440 $mods, 3441 $x, 3442 SRCMODS.NEG, 3443 (V_CNDMASK_B64_PSEUDO 3444 (V_MIN_F64 3445 SRCMODS.NONE, 3446 (V_FRACT_F64_e64 $mods, $x, DSTCLAMP.NONE, DSTOMOD.NONE), 3447 SRCMODS.NONE, 3448 (V_MOV_B64_PSEUDO 0x3fefffffffffffff), 3449 DSTCLAMP.NONE, DSTOMOD.NONE), 3450 $x, 3451 (V_CMP_CLASS_F64_e64 SRCMODS.NONE, $x, 3/*NaN*/)), 3452 DSTCLAMP.NONE, DSTOMOD.NONE) 3453>; 3454 3455} // End Predicates = [isSI] 3456 3457//============================================================================// 3458// Miscellaneous Optimization Patterns 3459//============================================================================// 3460 3461def : SHA256MaPattern <V_BFI_B32, V_XOR_B32_e64>; 3462 3463def : IntMed3Pat<V_MED3_I32, smax, smax_oneuse, smin_oneuse>; 3464def : IntMed3Pat<V_MED3_U32, umax, umax_oneuse, umin_oneuse>; 3465 3466//============================================================================// 3467// Assembler aliases 3468//============================================================================// 3469 3470def : MnemonicAlias<"v_add_u32", "v_add_i32">; 3471def : MnemonicAlias<"v_sub_u32", "v_sub_i32">; 3472def : MnemonicAlias<"v_subrev_u32", "v_subrev_i32">; 3473 3474} // End isGCN predicate 3475