1//===-- SIInstructions.td - SI Instruction Defintions ---------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// This file was originally auto-generated from a GPU register header file and 10// all the instruction definitions were originally commented out. Instructions 11// that are not yet supported remain commented out. 12//===----------------------------------------------------------------------===// 13 14class InterpSlots { 15int P0 = 2; 16int P10 = 0; 17int P20 = 1; 18} 19def INTERP : InterpSlots; 20 21def InterpSlot : Operand<i32> { 22 let PrintMethod = "printInterpSlot"; 23} 24 25def SendMsgImm : Operand<i32> { 26 let PrintMethod = "printSendMsg"; 27} 28 29def isGCN : Predicate<"Subtarget->getGeneration() " 30 ">= AMDGPUSubtarget::SOUTHERN_ISLANDS">, 31 AssemblerPredicate<"FeatureGCN">; 32def isSI : Predicate<"Subtarget->getGeneration() " 33 "== AMDGPUSubtarget::SOUTHERN_ISLANDS">, 34 AssemblerPredicate<"FeatureSouthernIslands">; 35 36 37def has16BankLDS : Predicate<"Subtarget->getLDSBankCount() == 16">; 38def has32BankLDS : Predicate<"Subtarget->getLDSBankCount() == 32">; 39 40def SWaitMatchClass : AsmOperandClass { 41 let Name = "SWaitCnt"; 42 let RenderMethod = "addImmOperands"; 43 let ParserMethod = "parseSWaitCntOps"; 44} 45 46def WAIT_FLAG : Operand <i32> { 47 let ParserMatchClass = SWaitMatchClass; 48 let PrintMethod = "printWaitFlag"; 49} 50 51let SubtargetPredicate = isGCN in { 52 53//===----------------------------------------------------------------------===// 54// EXP Instructions 55//===----------------------------------------------------------------------===// 56 57defm EXP : EXP_m; 58 59//===----------------------------------------------------------------------===// 60// SMRD Instructions 61//===----------------------------------------------------------------------===// 62 63// We are using the SGPR_32 and not the SReg_32 register class for 32-bit 64// SMRD instructions, because the SGPR_32 register class does not include M0 65// and writing to M0 from an SMRD instruction will hang the GPU. 66defm S_LOAD_DWORD : SMRD_Helper <smrd<0x00>, "s_load_dword", SReg_64, SGPR_32>; 67defm S_LOAD_DWORDX2 : SMRD_Helper <smrd<0x01>, "s_load_dwordx2", SReg_64, SReg_64>; 68defm S_LOAD_DWORDX4 : SMRD_Helper <smrd<0x02>, "s_load_dwordx4", SReg_64, SReg_128>; 69defm S_LOAD_DWORDX8 : SMRD_Helper <smrd<0x03>, "s_load_dwordx8", SReg_64, SReg_256>; 70defm S_LOAD_DWORDX16 : SMRD_Helper <smrd<0x04>, "s_load_dwordx16", SReg_64, SReg_512>; 71 72defm S_BUFFER_LOAD_DWORD : SMRD_Helper < 73 smrd<0x08>, "s_buffer_load_dword", SReg_128, SGPR_32 74>; 75 76defm S_BUFFER_LOAD_DWORDX2 : SMRD_Helper < 77 smrd<0x09>, "s_buffer_load_dwordx2", SReg_128, SReg_64 78>; 79 80defm S_BUFFER_LOAD_DWORDX4 : SMRD_Helper < 81 smrd<0x0a>, "s_buffer_load_dwordx4", SReg_128, SReg_128 82>; 83 84defm S_BUFFER_LOAD_DWORDX8 : SMRD_Helper < 85 smrd<0x0b>, "s_buffer_load_dwordx8", SReg_128, SReg_256 86>; 87 88defm S_BUFFER_LOAD_DWORDX16 : SMRD_Helper < 89 smrd<0x0c>, "s_buffer_load_dwordx16", SReg_128, SReg_512 90>; 91 92let mayStore = ? in { 93// FIXME: mayStore = ? is a workaround for tablegen bug for different 94// inferred mayStore flags for the instruction pattern vs. standalone 95// Pat. Each considers the other contradictory. 96 97defm S_MEMTIME : SMRD_Special <smrd<0x1e, 0x24>, "s_memtime", 98 (outs SReg_64:$sdst), ?, " $sdst", [(set i64:$sdst, (int_amdgcn_s_memtime))] 99>; 100} 101 102defm S_DCACHE_INV : SMRD_Inval <smrd<0x1f, 0x20>, "s_dcache_inv", 103 int_amdgcn_s_dcache_inv>; 104 105//===----------------------------------------------------------------------===// 106// SOP1 Instructions 107//===----------------------------------------------------------------------===// 108 109let isMoveImm = 1 in { 110 let isReMaterializable = 1, isAsCheapAsAMove = 1 in { 111 defm S_MOV_B32 : SOP1_32 <sop1<0x03, 0x00>, "s_mov_b32", []>; 112 defm S_MOV_B64 : SOP1_64 <sop1<0x04, 0x01>, "s_mov_b64", []>; 113 } // End isRematerializeable = 1 114 115 let Uses = [SCC] in { 116 defm S_CMOV_B32 : SOP1_32 <sop1<0x05, 0x02>, "s_cmov_b32", []>; 117 defm S_CMOV_B64 : SOP1_64 <sop1<0x06, 0x03>, "s_cmov_b64", []>; 118 } // End Uses = [SCC] 119} // End isMoveImm = 1 120 121let Defs = [SCC] in { 122 defm S_NOT_B32 : SOP1_32 <sop1<0x07, 0x04>, "s_not_b32", 123 [(set i32:$sdst, (not i32:$src0))] 124 >; 125 126 defm S_NOT_B64 : SOP1_64 <sop1<0x08, 0x05>, "s_not_b64", 127 [(set i64:$sdst, (not i64:$src0))] 128 >; 129 defm S_WQM_B32 : SOP1_32 <sop1<0x09, 0x06>, "s_wqm_b32", []>; 130 defm S_WQM_B64 : SOP1_64 <sop1<0x0a, 0x07>, "s_wqm_b64", []>; 131} // End Defs = [SCC] 132 133 134defm S_BREV_B32 : SOP1_32 <sop1<0x0b, 0x08>, "s_brev_b32", 135 [(set i32:$sdst, (bitreverse i32:$src0))] 136>; 137defm S_BREV_B64 : SOP1_64 <sop1<0x0c, 0x09>, "s_brev_b64", []>; 138 139let Defs = [SCC] in { 140 defm S_BCNT0_I32_B32 : SOP1_32 <sop1<0x0d, 0x0a>, "s_bcnt0_i32_b32", []>; 141 defm S_BCNT0_I32_B64 : SOP1_32_64 <sop1<0x0e, 0x0b>, "s_bcnt0_i32_b64", []>; 142 defm S_BCNT1_I32_B32 : SOP1_32 <sop1<0x0f, 0x0c>, "s_bcnt1_i32_b32", 143 [(set i32:$sdst, (ctpop i32:$src0))] 144 >; 145 defm S_BCNT1_I32_B64 : SOP1_32_64 <sop1<0x10, 0x0d>, "s_bcnt1_i32_b64", []>; 146} // End Defs = [SCC] 147 148defm S_FF0_I32_B32 : SOP1_32 <sop1<0x11, 0x0e>, "s_ff0_i32_b32", []>; 149defm S_FF0_I32_B64 : SOP1_32_64 <sop1<0x12, 0x0f>, "s_ff0_i32_b64", []>; 150defm S_FF1_I32_B32 : SOP1_32 <sop1<0x13, 0x10>, "s_ff1_i32_b32", 151 [(set i32:$sdst, (cttz_zero_undef i32:$src0))] 152>; 153defm S_FF1_I32_B64 : SOP1_32_64 <sop1<0x14, 0x11>, "s_ff1_i32_b64", []>; 154 155defm S_FLBIT_I32_B32 : SOP1_32 <sop1<0x15, 0x12>, "s_flbit_i32_b32", 156 [(set i32:$sdst, (AMDGPUffbh_u32 i32:$src0))] 157>; 158 159defm S_FLBIT_I32_B64 : SOP1_32_64 <sop1<0x16, 0x13>, "s_flbit_i32_b64", []>; 160defm S_FLBIT_I32 : SOP1_32 <sop1<0x17, 0x14>, "s_flbit_i32", 161 [(set i32:$sdst, (int_AMDGPU_flbit_i32 i32:$src0))] 162>; 163defm S_FLBIT_I32_I64 : SOP1_32_64 <sop1<0x18, 0x15>, "s_flbit_i32_i64", []>; 164defm S_SEXT_I32_I8 : SOP1_32 <sop1<0x19, 0x16>, "s_sext_i32_i8", 165 [(set i32:$sdst, (sext_inreg i32:$src0, i8))] 166>; 167defm S_SEXT_I32_I16 : SOP1_32 <sop1<0x1a, 0x17>, "s_sext_i32_i16", 168 [(set i32:$sdst, (sext_inreg i32:$src0, i16))] 169>; 170 171defm S_BITSET0_B32 : SOP1_32 <sop1<0x1b, 0x18>, "s_bitset0_b32", []>; 172defm S_BITSET0_B64 : SOP1_64_32 <sop1<0x1c, 0x19>, "s_bitset0_b64", []>; 173defm S_BITSET1_B32 : SOP1_32 <sop1<0x1d, 0x1a>, "s_bitset1_b32", []>; 174defm S_BITSET1_B64 : SOP1_64_32 <sop1<0x1e, 0x1b>, "s_bitset1_b64", []>; 175defm S_GETPC_B64 : SOP1_64_0 <sop1<0x1f, 0x1c>, "s_getpc_b64", []>; 176defm S_SETPC_B64 : SOP1_1 <sop1<0x20, 0x1d>, "s_setpc_b64", []>; 177defm S_SWAPPC_B64 : SOP1_64 <sop1<0x21, 0x1e>, "s_swappc_b64", []>; 178defm S_RFE_B64 : SOP1_1 <sop1<0x22, 0x1f>, "s_rfe_b64", []>; 179 180let hasSideEffects = 1, Uses = [EXEC], Defs = [EXEC, SCC] in { 181 182defm S_AND_SAVEEXEC_B64 : SOP1_64 <sop1<0x24, 0x20>, "s_and_saveexec_b64", []>; 183defm S_OR_SAVEEXEC_B64 : SOP1_64 <sop1<0x25, 0x21>, "s_or_saveexec_b64", []>; 184defm S_XOR_SAVEEXEC_B64 : SOP1_64 <sop1<0x26, 0x22>, "s_xor_saveexec_b64", []>; 185defm S_ANDN2_SAVEEXEC_B64 : SOP1_64 <sop1<0x27, 0x23>, "s_andn2_saveexec_b64", []>; 186defm S_ORN2_SAVEEXEC_B64 : SOP1_64 <sop1<0x28, 0x24>, "s_orn2_saveexec_b64", []>; 187defm S_NAND_SAVEEXEC_B64 : SOP1_64 <sop1<0x29, 0x25>, "s_nand_saveexec_b64", []>; 188defm S_NOR_SAVEEXEC_B64 : SOP1_64 <sop1<0x2a, 0x26>, "s_nor_saveexec_b64", []>; 189defm S_XNOR_SAVEEXEC_B64 : SOP1_64 <sop1<0x2b, 0x27>, "s_xnor_saveexec_b64", []>; 190 191} // End hasSideEffects = 1, Uses = [EXEC], Defs = [EXEC, SCC] 192 193defm S_QUADMASK_B32 : SOP1_32 <sop1<0x2c, 0x28>, "s_quadmask_b32", []>; 194defm S_QUADMASK_B64 : SOP1_64 <sop1<0x2d, 0x29>, "s_quadmask_b64", []>; 195 196let Uses = [M0] in { 197defm S_MOVRELS_B32 : SOP1_32 <sop1<0x2e, 0x2a>, "s_movrels_b32", []>; 198defm S_MOVRELS_B64 : SOP1_64 <sop1<0x2f, 0x2b>, "s_movrels_b64", []>; 199defm S_MOVRELD_B32 : SOP1_32 <sop1<0x30, 0x2c>, "s_movreld_b32", []>; 200defm S_MOVRELD_B64 : SOP1_64 <sop1<0x31, 0x2d>, "s_movreld_b64", []>; 201} // End Uses = [M0] 202 203defm S_CBRANCH_JOIN : SOP1_1 <sop1<0x32, 0x2e>, "s_cbranch_join", []>; 204defm S_MOV_REGRD_B32 : SOP1_32 <sop1<0x33, 0x2f>, "s_mov_regrd_b32", []>; 205let Defs = [SCC] in { 206 defm S_ABS_I32 : SOP1_32 <sop1<0x34, 0x30>, "s_abs_i32", []>; 207} // End Defs = [SCC] 208defm S_MOV_FED_B32 : SOP1_32 <sop1<0x35, 0x31>, "s_mov_fed_b32", []>; 209 210//===----------------------------------------------------------------------===// 211// SOP2 Instructions 212//===----------------------------------------------------------------------===// 213 214let Defs = [SCC] in { // Carry out goes to SCC 215let isCommutable = 1 in { 216defm S_ADD_U32 : SOP2_32 <sop2<0x00>, "s_add_u32", []>; 217defm S_ADD_I32 : SOP2_32 <sop2<0x02>, "s_add_i32", 218 [(set i32:$sdst, (add SSrc_32:$src0, SSrc_32:$src1))] 219>; 220} // End isCommutable = 1 221 222defm S_SUB_U32 : SOP2_32 <sop2<0x01>, "s_sub_u32", []>; 223defm S_SUB_I32 : SOP2_32 <sop2<0x03>, "s_sub_i32", 224 [(set i32:$sdst, (sub SSrc_32:$src0, SSrc_32:$src1))] 225>; 226 227let Uses = [SCC] in { // Carry in comes from SCC 228let isCommutable = 1 in { 229defm S_ADDC_U32 : SOP2_32 <sop2<0x04>, "s_addc_u32", 230 [(set i32:$sdst, (adde (i32 SSrc_32:$src0), (i32 SSrc_32:$src1)))]>; 231} // End isCommutable = 1 232 233defm S_SUBB_U32 : SOP2_32 <sop2<0x05>, "s_subb_u32", 234 [(set i32:$sdst, (sube (i32 SSrc_32:$src0), (i32 SSrc_32:$src1)))]>; 235} // End Uses = [SCC] 236 237defm S_MIN_I32 : SOP2_32 <sop2<0x06>, "s_min_i32", 238 [(set i32:$sdst, (smin i32:$src0, i32:$src1))] 239>; 240defm S_MIN_U32 : SOP2_32 <sop2<0x07>, "s_min_u32", 241 [(set i32:$sdst, (umin i32:$src0, i32:$src1))] 242>; 243defm S_MAX_I32 : SOP2_32 <sop2<0x08>, "s_max_i32", 244 [(set i32:$sdst, (smax i32:$src0, i32:$src1))] 245>; 246defm S_MAX_U32 : SOP2_32 <sop2<0x09>, "s_max_u32", 247 [(set i32:$sdst, (umax i32:$src0, i32:$src1))] 248>; 249} // End Defs = [SCC] 250 251 252let Uses = [SCC] in { 253 defm S_CSELECT_B32 : SOP2_32 <sop2<0x0a>, "s_cselect_b32", []>; 254 defm S_CSELECT_B64 : SOP2_64 <sop2<0x0b>, "s_cselect_b64", []>; 255} // End Uses = [SCC] 256 257let Defs = [SCC] in { 258defm S_AND_B32 : SOP2_32 <sop2<0x0e, 0x0c>, "s_and_b32", 259 [(set i32:$sdst, (and i32:$src0, i32:$src1))] 260>; 261 262defm S_AND_B64 : SOP2_64 <sop2<0x0f, 0x0d>, "s_and_b64", 263 [(set i64:$sdst, (and i64:$src0, i64:$src1))] 264>; 265 266defm S_OR_B32 : SOP2_32 <sop2<0x10, 0x0e>, "s_or_b32", 267 [(set i32:$sdst, (or i32:$src0, i32:$src1))] 268>; 269 270defm S_OR_B64 : SOP2_64 <sop2<0x11, 0x0f>, "s_or_b64", 271 [(set i64:$sdst, (or i64:$src0, i64:$src1))] 272>; 273 274defm S_XOR_B32 : SOP2_32 <sop2<0x12, 0x10>, "s_xor_b32", 275 [(set i32:$sdst, (xor i32:$src0, i32:$src1))] 276>; 277 278defm S_XOR_B64 : SOP2_64 <sop2<0x13, 0x11>, "s_xor_b64", 279 [(set i64:$sdst, (xor i64:$src0, i64:$src1))] 280>; 281defm S_ANDN2_B32 : SOP2_32 <sop2<0x14, 0x12>, "s_andn2_b32", []>; 282defm S_ANDN2_B64 : SOP2_64 <sop2<0x15, 0x13>, "s_andn2_b64", []>; 283defm S_ORN2_B32 : SOP2_32 <sop2<0x16, 0x14>, "s_orn2_b32", []>; 284defm S_ORN2_B64 : SOP2_64 <sop2<0x17, 0x15>, "s_orn2_b64", []>; 285defm S_NAND_B32 : SOP2_32 <sop2<0x18, 0x16>, "s_nand_b32", []>; 286defm S_NAND_B64 : SOP2_64 <sop2<0x19, 0x17>, "s_nand_b64", []>; 287defm S_NOR_B32 : SOP2_32 <sop2<0x1a, 0x18>, "s_nor_b32", []>; 288defm S_NOR_B64 : SOP2_64 <sop2<0x1b, 0x19>, "s_nor_b64", []>; 289defm S_XNOR_B32 : SOP2_32 <sop2<0x1c, 0x1a>, "s_xnor_b32", []>; 290defm S_XNOR_B64 : SOP2_64 <sop2<0x1d, 0x1b>, "s_xnor_b64", []>; 291} // End Defs = [SCC] 292 293// Use added complexity so these patterns are preferred to the VALU patterns. 294let AddedComplexity = 1 in { 295let Defs = [SCC] in { 296 297defm S_LSHL_B32 : SOP2_32 <sop2<0x1e, 0x1c>, "s_lshl_b32", 298 [(set i32:$sdst, (shl i32:$src0, i32:$src1))] 299>; 300defm S_LSHL_B64 : SOP2_64_32 <sop2<0x1f, 0x1d>, "s_lshl_b64", 301 [(set i64:$sdst, (shl i64:$src0, i32:$src1))] 302>; 303defm S_LSHR_B32 : SOP2_32 <sop2<0x20, 0x1e>, "s_lshr_b32", 304 [(set i32:$sdst, (srl i32:$src0, i32:$src1))] 305>; 306defm S_LSHR_B64 : SOP2_64_32 <sop2<0x21, 0x1f>, "s_lshr_b64", 307 [(set i64:$sdst, (srl i64:$src0, i32:$src1))] 308>; 309defm S_ASHR_I32 : SOP2_32 <sop2<0x22, 0x20>, "s_ashr_i32", 310 [(set i32:$sdst, (sra i32:$src0, i32:$src1))] 311>; 312defm S_ASHR_I64 : SOP2_64_32 <sop2<0x23, 0x21>, "s_ashr_i64", 313 [(set i64:$sdst, (sra i64:$src0, i32:$src1))] 314>; 315} // End Defs = [SCC] 316 317defm S_BFM_B32 : SOP2_32 <sop2<0x24, 0x22>, "s_bfm_b32", 318 [(set i32:$sdst, (AMDGPUbfm i32:$src0, i32:$src1))]>; 319defm S_BFM_B64 : SOP2_64_32_32 <sop2<0x25, 0x23>, "s_bfm_b64", []>; 320defm S_MUL_I32 : SOP2_32 <sop2<0x26, 0x24>, "s_mul_i32", 321 [(set i32:$sdst, (mul i32:$src0, i32:$src1))] 322>; 323 324} // End AddedComplexity = 1 325 326let Defs = [SCC] in { 327defm S_BFE_U32 : SOP2_32 <sop2<0x27, 0x25>, "s_bfe_u32", []>; 328defm S_BFE_I32 : SOP2_32 <sop2<0x28, 0x26>, "s_bfe_i32", []>; 329defm S_BFE_U64 : SOP2_64_32 <sop2<0x29, 0x27>, "s_bfe_u64", []>; 330defm S_BFE_I64 : SOP2_64_32 <sop2<0x2a, 0x28>, "s_bfe_i64", []>; 331} // End Defs = [SCC] 332 333let sdst = 0 in { 334defm S_CBRANCH_G_FORK : SOP2_m < 335 sop2<0x2b, 0x29>, "s_cbranch_g_fork", (outs), 336 (ins SReg_64:$src0, SReg_64:$src1), "s_cbranch_g_fork $src0, $src1", [] 337>; 338} 339 340let Defs = [SCC] in { 341defm S_ABSDIFF_I32 : SOP2_32 <sop2<0x2c, 0x2a>, "s_absdiff_i32", []>; 342} // End Defs = [SCC] 343 344//===----------------------------------------------------------------------===// 345// SOPC Instructions 346//===----------------------------------------------------------------------===// 347 348def S_CMP_EQ_I32 : SOPC_CMP_32 <0x00000000, "s_cmp_eq_i32", COND_EQ>; 349def S_CMP_LG_I32 : SOPC_CMP_32 <0x00000001, "s_cmp_lg_i32", COND_NE>; 350def S_CMP_GT_I32 : SOPC_CMP_32 <0x00000002, "s_cmp_gt_i32", COND_SGT>; 351def S_CMP_GE_I32 : SOPC_CMP_32 <0x00000003, "s_cmp_ge_i32", COND_SGE>; 352def S_CMP_LT_I32 : SOPC_CMP_32 <0x00000004, "s_cmp_lt_i32", COND_SLT>; 353def S_CMP_LE_I32 : SOPC_CMP_32 <0x00000005, "s_cmp_le_i32", COND_SLE>; 354def S_CMP_EQ_U32 : SOPC_CMP_32 <0x00000006, "s_cmp_eq_u32", COND_EQ>; 355def S_CMP_LG_U32 : SOPC_CMP_32 <0x00000007, "s_cmp_lg_u32", COND_NE >; 356def S_CMP_GT_U32 : SOPC_CMP_32 <0x00000008, "s_cmp_gt_u32", COND_UGT>; 357def S_CMP_GE_U32 : SOPC_CMP_32 <0x00000009, "s_cmp_ge_u32", COND_UGE>; 358def S_CMP_LT_U32 : SOPC_CMP_32 <0x0000000a, "s_cmp_lt_u32", COND_ULT>; 359def S_CMP_LE_U32 : SOPC_CMP_32 <0x0000000b, "s_cmp_le_u32", COND_ULE>; 360def S_BITCMP0_B32 : SOPC_32 <0x0000000c, "s_bitcmp0_b32">; 361def S_BITCMP1_B32 : SOPC_32 <0x0000000d, "s_bitcmp1_b32">; 362def S_BITCMP0_B64 : SOPC_64_32 <0x0000000e, "s_bitcmp0_b64">; 363def S_BITCMP1_B64 : SOPC_64_32 <0x0000000f, "s_bitcmp1_b64">; 364def S_SETVSKIP : SOPC_32 <0x00000010, "s_setvskip">; 365 366//===----------------------------------------------------------------------===// 367// SOPK Instructions 368//===----------------------------------------------------------------------===// 369 370let isReMaterializable = 1, isMoveImm = 1 in { 371defm S_MOVK_I32 : SOPK_32 <sopk<0x00>, "s_movk_i32", []>; 372} // End isReMaterializable = 1 373let Uses = [SCC] in { 374 defm S_CMOVK_I32 : SOPK_32 <sopk<0x02, 0x01>, "s_cmovk_i32", []>; 375} 376 377let isCompare = 1 in { 378 379/* 380This instruction is disabled for now until we can figure out how to teach 381the instruction selector to correctly use the S_CMP* vs V_CMP* 382instructions. 383 384When this instruction is enabled the code generator sometimes produces this 385invalid sequence: 386 387SCC = S_CMPK_EQ_I32 SGPR0, imm 388VCC = COPY SCC 389VGPR0 = V_CNDMASK VCC, VGPR0, VGPR1 390 391defm S_CMPK_EQ_I32 : SOPK_SCC <sopk<0x03, 0x02>, "s_cmpk_eq_i32", 392 [(set i1:$dst, (setcc i32:$src0, imm:$src1, SETEQ))] 393>; 394*/ 395 396defm S_CMPK_EQ_I32 : SOPK_SCC <sopk<0x03, 0x02>, "s_cmpk_eq_i32", []>; 397defm S_CMPK_LG_I32 : SOPK_SCC <sopk<0x04, 0x03>, "s_cmpk_lg_i32", []>; 398defm S_CMPK_GT_I32 : SOPK_SCC <sopk<0x05, 0x04>, "s_cmpk_gt_i32", []>; 399defm S_CMPK_GE_I32 : SOPK_SCC <sopk<0x06, 0x05>, "s_cmpk_ge_i32", []>; 400defm S_CMPK_LT_I32 : SOPK_SCC <sopk<0x07, 0x06>, "s_cmpk_lt_i32", []>; 401defm S_CMPK_LE_I32 : SOPK_SCC <sopk<0x08, 0x07>, "s_cmpk_le_i32", []>; 402defm S_CMPK_EQ_U32 : SOPK_SCC <sopk<0x09, 0x08>, "s_cmpk_eq_u32", []>; 403defm S_CMPK_LG_U32 : SOPK_SCC <sopk<0x0a, 0x09>, "s_cmpk_lg_u32", []>; 404defm S_CMPK_GT_U32 : SOPK_SCC <sopk<0x0b, 0x0a>, "s_cmpk_gt_u32", []>; 405defm S_CMPK_GE_U32 : SOPK_SCC <sopk<0x0c, 0x0b>, "s_cmpk_ge_u32", []>; 406defm S_CMPK_LT_U32 : SOPK_SCC <sopk<0x0d, 0x0c>, "s_cmpk_lt_u32", []>; 407defm S_CMPK_LE_U32 : SOPK_SCC <sopk<0x0e, 0x0d>, "s_cmpk_le_u32", []>; 408} // End isCompare = 1 409 410let Defs = [SCC], isCommutable = 1, DisableEncoding = "$src0", 411 Constraints = "$sdst = $src0" in { 412 defm S_ADDK_I32 : SOPK_32TIE <sopk<0x0f, 0x0e>, "s_addk_i32", []>; 413 defm S_MULK_I32 : SOPK_32TIE <sopk<0x10, 0x0f>, "s_mulk_i32", []>; 414} 415 416defm S_CBRANCH_I_FORK : SOPK_m < 417 sopk<0x11, 0x10>, "s_cbranch_i_fork", (outs), 418 (ins SReg_64:$sdst, u16imm:$simm16), " $sdst, $simm16" 419>; 420 421let mayLoad = 1 in { 422defm S_GETREG_B32 : SOPK_m < 423 sopk<0x12, 0x11>, "s_getreg_b32", (outs SReg_32:$sdst), 424 (ins hwreg:$simm16), " $sdst, $simm16" 425>; 426} 427 428defm S_SETREG_B32 : SOPK_m < 429 sopk<0x13, 0x12>, "s_setreg_b32", (outs), 430 (ins SReg_32:$sdst, hwreg:$simm16), " $simm16, $sdst" 431>; 432// FIXME: Not on SI? 433//defm S_GETREG_REGRD_B32 : SOPK_32 <sopk<0x14, 0x13>, "s_getreg_regrd_b32", []>; 434defm S_SETREG_IMM32_B32 : SOPK_IMM32 < 435 sopk<0x15, 0x14>, "s_setreg_imm32_b32", (outs), 436 (ins i32imm:$imm, hwreg:$simm16), " $simm16, $imm" 437>; 438 439//===----------------------------------------------------------------------===// 440// SOPP Instructions 441//===----------------------------------------------------------------------===// 442 443def S_NOP : SOPP <0x00000000, (ins i16imm:$simm16), "s_nop $simm16">; 444 445let isTerminator = 1 in { 446 447def S_ENDPGM : SOPP <0x00000001, (ins), "s_endpgm", 448 [(IL_retflag)]> { 449 let simm16 = 0; 450 let isBarrier = 1; 451 let hasCtrlDep = 1; 452} 453 454let isBranch = 1 in { 455def S_BRANCH : SOPP < 456 0x00000002, (ins sopp_brtarget:$simm16), "s_branch $simm16", 457 [(br bb:$simm16)]> { 458 let isBarrier = 1; 459} 460 461let Uses = [SCC] in { 462def S_CBRANCH_SCC0 : SOPP < 463 0x00000004, (ins sopp_brtarget:$simm16), 464 "s_cbranch_scc0 $simm16" 465>; 466def S_CBRANCH_SCC1 : SOPP < 467 0x00000005, (ins sopp_brtarget:$simm16), 468 "s_cbranch_scc1 $simm16", 469 [(si_uniform_br_scc SCC, bb:$simm16)] 470>; 471} // End Uses = [SCC] 472 473let Uses = [VCC] in { 474def S_CBRANCH_VCCZ : SOPP < 475 0x00000006, (ins sopp_brtarget:$simm16), 476 "s_cbranch_vccz $simm16" 477>; 478def S_CBRANCH_VCCNZ : SOPP < 479 0x00000007, (ins sopp_brtarget:$simm16), 480 "s_cbranch_vccnz $simm16" 481>; 482} // End Uses = [VCC] 483 484let Uses = [EXEC] in { 485def S_CBRANCH_EXECZ : SOPP < 486 0x00000008, (ins sopp_brtarget:$simm16), 487 "s_cbranch_execz $simm16" 488>; 489def S_CBRANCH_EXECNZ : SOPP < 490 0x00000009, (ins sopp_brtarget:$simm16), 491 "s_cbranch_execnz $simm16" 492>; 493} // End Uses = [EXEC] 494 495 496} // End isBranch = 1 497} // End isTerminator = 1 498 499let hasSideEffects = 1 in { 500def S_BARRIER : SOPP <0x0000000a, (ins), "s_barrier", 501 [(int_amdgcn_s_barrier)] 502> { 503 let SchedRW = [WriteBarrier]; 504 let simm16 = 0; 505 let mayLoad = 1; 506 let mayStore = 1; 507 let isConvergent = 1; 508} 509 510let mayLoad = 1, mayStore = 1, hasSideEffects = 1 in 511def S_WAITCNT : SOPP <0x0000000c, (ins WAIT_FLAG:$simm16), "s_waitcnt $simm16">; 512def S_SETHALT : SOPP <0x0000000d, (ins i16imm:$simm16), "s_sethalt $simm16">; 513 514// On SI the documentation says sleep for approximately 64 * low 2 515// bits, consistent with the reported maximum of 448. On VI the 516// maximum reported is 960 cycles, so 960 / 64 = 15 max, so is the 517// maximum really 15 on VI? 518def S_SLEEP : SOPP <0x0000000e, (ins i32imm:$simm16), 519 "s_sleep $simm16", [(int_amdgcn_s_sleep SIMM16bit:$simm16)]> { 520 let hasSideEffects = 1; 521 let mayLoad = 1; 522 let mayStore = 1; 523} 524 525def S_SETPRIO : SOPP <0x0000000f, (ins i16imm:$simm16), "s_setprio $simm16">; 526 527let Uses = [EXEC, M0] in { 528 // FIXME: Should this be mayLoad+mayStore? 529 def S_SENDMSG : SOPP <0x00000010, (ins SendMsgImm:$simm16), "s_sendmsg $simm16", 530 [(AMDGPUsendmsg (i32 imm:$simm16))] 531 >; 532} // End Uses = [EXEC, M0] 533 534def S_SENDMSGHALT : SOPP <0x00000011, (ins i16imm:$simm16), "s_sendmsghalt $simm16">; 535def S_TRAP : SOPP <0x00000012, (ins i16imm:$simm16), "s_trap $simm16">; 536def S_ICACHE_INV : SOPP <0x00000013, (ins), "s_icache_inv"> { 537 let simm16 = 0; 538} 539def S_INCPERFLEVEL : SOPP <0x00000014, (ins i16imm:$simm16), "s_incperflevel $simm16">; 540def S_DECPERFLEVEL : SOPP <0x00000015, (ins i16imm:$simm16), "s_decperflevel $simm16">; 541def S_TTRACEDATA : SOPP <0x00000016, (ins), "s_ttracedata"> { 542 let simm16 = 0; 543} 544} // End hasSideEffects 545 546//===----------------------------------------------------------------------===// 547// VOPC Instructions 548//===----------------------------------------------------------------------===// 549 550let isCompare = 1, isCommutable = 1 in { 551 552defm V_CMP_F_F32 : VOPC_F32 <vopc<0x0, 0x40>, "v_cmp_f_f32">; 553defm V_CMP_LT_F32 : VOPC_F32 <vopc<0x1, 0x41>, "v_cmp_lt_f32", COND_OLT, "v_cmp_gt_f32">; 554defm V_CMP_EQ_F32 : VOPC_F32 <vopc<0x2, 0x42>, "v_cmp_eq_f32", COND_OEQ>; 555defm V_CMP_LE_F32 : VOPC_F32 <vopc<0x3, 0x43>, "v_cmp_le_f32", COND_OLE, "v_cmp_ge_f32">; 556defm V_CMP_GT_F32 : VOPC_F32 <vopc<0x4, 0x44>, "v_cmp_gt_f32", COND_OGT>; 557defm V_CMP_LG_F32 : VOPC_F32 <vopc<0x5, 0x45>, "v_cmp_lg_f32", COND_ONE>; 558defm V_CMP_GE_F32 : VOPC_F32 <vopc<0x6, 0x46>, "v_cmp_ge_f32", COND_OGE>; 559defm V_CMP_O_F32 : VOPC_F32 <vopc<0x7, 0x47>, "v_cmp_o_f32", COND_O>; 560defm V_CMP_U_F32 : VOPC_F32 <vopc<0x8, 0x48>, "v_cmp_u_f32", COND_UO>; 561defm V_CMP_NGE_F32 : VOPC_F32 <vopc<0x9, 0x49>, "v_cmp_nge_f32", COND_ULT, "v_cmp_nle_f32">; 562defm V_CMP_NLG_F32 : VOPC_F32 <vopc<0xa, 0x4a>, "v_cmp_nlg_f32", COND_UEQ>; 563defm V_CMP_NGT_F32 : VOPC_F32 <vopc<0xb, 0x4b>, "v_cmp_ngt_f32", COND_ULE, "v_cmp_nlt_f32">; 564defm V_CMP_NLE_F32 : VOPC_F32 <vopc<0xc, 0x4c>, "v_cmp_nle_f32", COND_UGT>; 565defm V_CMP_NEQ_F32 : VOPC_F32 <vopc<0xd, 0x4d>, "v_cmp_neq_f32", COND_UNE>; 566defm V_CMP_NLT_F32 : VOPC_F32 <vopc<0xe, 0x4e>, "v_cmp_nlt_f32", COND_UGE>; 567defm V_CMP_TRU_F32 : VOPC_F32 <vopc<0xf, 0x4f>, "v_cmp_tru_f32">; 568 569 570defm V_CMPX_F_F32 : VOPCX_F32 <vopc<0x10, 0x50>, "v_cmpx_f_f32">; 571defm V_CMPX_LT_F32 : VOPCX_F32 <vopc<0x11, 0x51>, "v_cmpx_lt_f32", "v_cmpx_gt_f32">; 572defm V_CMPX_EQ_F32 : VOPCX_F32 <vopc<0x12, 0x52>, "v_cmpx_eq_f32">; 573defm V_CMPX_LE_F32 : VOPCX_F32 <vopc<0x13, 0x53>, "v_cmpx_le_f32", "v_cmpx_ge_f32">; 574defm V_CMPX_GT_F32 : VOPCX_F32 <vopc<0x14, 0x54>, "v_cmpx_gt_f32">; 575defm V_CMPX_LG_F32 : VOPCX_F32 <vopc<0x15, 0x55>, "v_cmpx_lg_f32">; 576defm V_CMPX_GE_F32 : VOPCX_F32 <vopc<0x16, 0x56>, "v_cmpx_ge_f32">; 577defm V_CMPX_O_F32 : VOPCX_F32 <vopc<0x17, 0x57>, "v_cmpx_o_f32">; 578defm V_CMPX_U_F32 : VOPCX_F32 <vopc<0x18, 0x58>, "v_cmpx_u_f32">; 579defm V_CMPX_NGE_F32 : VOPCX_F32 <vopc<0x19, 0x59>, "v_cmpx_nge_f32">; 580defm V_CMPX_NLG_F32 : VOPCX_F32 <vopc<0x1a, 0x5a>, "v_cmpx_nlg_f32">; 581defm V_CMPX_NGT_F32 : VOPCX_F32 <vopc<0x1b, 0x5b>, "v_cmpx_ngt_f32">; 582defm V_CMPX_NLE_F32 : VOPCX_F32 <vopc<0x1c, 0x5c>, "v_cmpx_nle_f32">; 583defm V_CMPX_NEQ_F32 : VOPCX_F32 <vopc<0x1d, 0x5d>, "v_cmpx_neq_f32">; 584defm V_CMPX_NLT_F32 : VOPCX_F32 <vopc<0x1e, 0x5e>, "v_cmpx_nlt_f32">; 585defm V_CMPX_TRU_F32 : VOPCX_F32 <vopc<0x1f, 0x5f>, "v_cmpx_tru_f32">; 586 587 588defm V_CMP_F_F64 : VOPC_F64 <vopc<0x20, 0x60>, "v_cmp_f_f64">; 589defm V_CMP_LT_F64 : VOPC_F64 <vopc<0x21, 0x61>, "v_cmp_lt_f64", COND_OLT, "v_cmp_gt_f64">; 590defm V_CMP_EQ_F64 : VOPC_F64 <vopc<0x22, 0x62>, "v_cmp_eq_f64", COND_OEQ>; 591defm V_CMP_LE_F64 : VOPC_F64 <vopc<0x23, 0x63>, "v_cmp_le_f64", COND_OLE, "v_cmp_ge_f64">; 592defm V_CMP_GT_F64 : VOPC_F64 <vopc<0x24, 0x64>, "v_cmp_gt_f64", COND_OGT>; 593defm V_CMP_LG_F64 : VOPC_F64 <vopc<0x25, 0x65>, "v_cmp_lg_f64", COND_ONE>; 594defm V_CMP_GE_F64 : VOPC_F64 <vopc<0x26, 0x66>, "v_cmp_ge_f64", COND_OGE>; 595defm V_CMP_O_F64 : VOPC_F64 <vopc<0x27, 0x67>, "v_cmp_o_f64", COND_O>; 596defm V_CMP_U_F64 : VOPC_F64 <vopc<0x28, 0x68>, "v_cmp_u_f64", COND_UO>; 597defm V_CMP_NGE_F64 : VOPC_F64 <vopc<0x29, 0x69>, "v_cmp_nge_f64", COND_ULT, "v_cmp_nle_f64">; 598defm V_CMP_NLG_F64 : VOPC_F64 <vopc<0x2a, 0x6a>, "v_cmp_nlg_f64", COND_UEQ>; 599defm V_CMP_NGT_F64 : VOPC_F64 <vopc<0x2b, 0x6b>, "v_cmp_ngt_f64", COND_ULE, "v_cmp_nlt_f64">; 600defm V_CMP_NLE_F64 : VOPC_F64 <vopc<0x2c, 0x6c>, "v_cmp_nle_f64", COND_UGT>; 601defm V_CMP_NEQ_F64 : VOPC_F64 <vopc<0x2d, 0x6d>, "v_cmp_neq_f64", COND_UNE>; 602defm V_CMP_NLT_F64 : VOPC_F64 <vopc<0x2e, 0x6e>, "v_cmp_nlt_f64", COND_UGE>; 603defm V_CMP_TRU_F64 : VOPC_F64 <vopc<0x2f, 0x6f>, "v_cmp_tru_f64">; 604 605 606defm V_CMPX_F_F64 : VOPCX_F64 <vopc<0x30, 0x70>, "v_cmpx_f_f64">; 607defm V_CMPX_LT_F64 : VOPCX_F64 <vopc<0x31, 0x71>, "v_cmpx_lt_f64", "v_cmpx_gt_f64">; 608defm V_CMPX_EQ_F64 : VOPCX_F64 <vopc<0x32, 0x72>, "v_cmpx_eq_f64">; 609defm V_CMPX_LE_F64 : VOPCX_F64 <vopc<0x33, 0x73>, "v_cmpx_le_f64", "v_cmpx_ge_f64">; 610defm V_CMPX_GT_F64 : VOPCX_F64 <vopc<0x34, 0x74>, "v_cmpx_gt_f64">; 611defm V_CMPX_LG_F64 : VOPCX_F64 <vopc<0x35, 0x75>, "v_cmpx_lg_f64">; 612defm V_CMPX_GE_F64 : VOPCX_F64 <vopc<0x36, 0x76>, "v_cmpx_ge_f64">; 613defm V_CMPX_O_F64 : VOPCX_F64 <vopc<0x37, 0x77>, "v_cmpx_o_f64">; 614defm V_CMPX_U_F64 : VOPCX_F64 <vopc<0x38, 0x78>, "v_cmpx_u_f64">; 615defm V_CMPX_NGE_F64 : VOPCX_F64 <vopc<0x39, 0x79>, "v_cmpx_nge_f64", "v_cmpx_nle_f64">; 616defm V_CMPX_NLG_F64 : VOPCX_F64 <vopc<0x3a, 0x7a>, "v_cmpx_nlg_f64">; 617defm V_CMPX_NGT_F64 : VOPCX_F64 <vopc<0x3b, 0x7b>, "v_cmpx_ngt_f64", "v_cmpx_nlt_f64">; 618defm V_CMPX_NLE_F64 : VOPCX_F64 <vopc<0x3c, 0x7c>, "v_cmpx_nle_f64">; 619defm V_CMPX_NEQ_F64 : VOPCX_F64 <vopc<0x3d, 0x7d>, "v_cmpx_neq_f64">; 620defm V_CMPX_NLT_F64 : VOPCX_F64 <vopc<0x3e, 0x7e>, "v_cmpx_nlt_f64">; 621defm V_CMPX_TRU_F64 : VOPCX_F64 <vopc<0x3f, 0x7f>, "v_cmpx_tru_f64">; 622 623 624let SubtargetPredicate = isSICI in { 625 626defm V_CMPS_F_F32 : VOPC_F32 <vopc<0x40>, "v_cmps_f_f32">; 627defm V_CMPS_LT_F32 : VOPC_F32 <vopc<0x41>, "v_cmps_lt_f32", COND_NULL, "v_cmps_gt_f32">; 628defm V_CMPS_EQ_F32 : VOPC_F32 <vopc<0x42>, "v_cmps_eq_f32">; 629defm V_CMPS_LE_F32 : VOPC_F32 <vopc<0x43>, "v_cmps_le_f32", COND_NULL, "v_cmps_ge_f32">; 630defm V_CMPS_GT_F32 : VOPC_F32 <vopc<0x44>, "v_cmps_gt_f32">; 631defm V_CMPS_LG_F32 : VOPC_F32 <vopc<0x45>, "v_cmps_lg_f32">; 632defm V_CMPS_GE_F32 : VOPC_F32 <vopc<0x46>, "v_cmps_ge_f32">; 633defm V_CMPS_O_F32 : VOPC_F32 <vopc<0x47>, "v_cmps_o_f32">; 634defm V_CMPS_U_F32 : VOPC_F32 <vopc<0x48>, "v_cmps_u_f32">; 635defm V_CMPS_NGE_F32 : VOPC_F32 <vopc<0x49>, "v_cmps_nge_f32", COND_NULL, "v_cmps_nle_f32">; 636defm V_CMPS_NLG_F32 : VOPC_F32 <vopc<0x4a>, "v_cmps_nlg_f32">; 637defm V_CMPS_NGT_F32 : VOPC_F32 <vopc<0x4b>, "v_cmps_ngt_f32", COND_NULL, "v_cmps_nlt_f32">; 638defm V_CMPS_NLE_F32 : VOPC_F32 <vopc<0x4c>, "v_cmps_nle_f32">; 639defm V_CMPS_NEQ_F32 : VOPC_F32 <vopc<0x4d>, "v_cmps_neq_f32">; 640defm V_CMPS_NLT_F32 : VOPC_F32 <vopc<0x4e>, "v_cmps_nlt_f32">; 641defm V_CMPS_TRU_F32 : VOPC_F32 <vopc<0x4f>, "v_cmps_tru_f32">; 642 643 644defm V_CMPSX_F_F32 : VOPCX_F32 <vopc<0x50>, "v_cmpsx_f_f32">; 645defm V_CMPSX_LT_F32 : VOPCX_F32 <vopc<0x51>, "v_cmpsx_lt_f32", "v_cmpsx_gt_f32">; 646defm V_CMPSX_EQ_F32 : VOPCX_F32 <vopc<0x52>, "v_cmpsx_eq_f32">; 647defm V_CMPSX_LE_F32 : VOPCX_F32 <vopc<0x53>, "v_cmpsx_le_f32", "v_cmpsx_ge_f32">; 648defm V_CMPSX_GT_F32 : VOPCX_F32 <vopc<0x54>, "v_cmpsx_gt_f32">; 649defm V_CMPSX_LG_F32 : VOPCX_F32 <vopc<0x55>, "v_cmpsx_lg_f32">; 650defm V_CMPSX_GE_F32 : VOPCX_F32 <vopc<0x56>, "v_cmpsx_ge_f32">; 651defm V_CMPSX_O_F32 : VOPCX_F32 <vopc<0x57>, "v_cmpsx_o_f32">; 652defm V_CMPSX_U_F32 : VOPCX_F32 <vopc<0x58>, "v_cmpsx_u_f32">; 653defm V_CMPSX_NGE_F32 : VOPCX_F32 <vopc<0x59>, "v_cmpsx_nge_f32", "v_cmpsx_nle_f32">; 654defm V_CMPSX_NLG_F32 : VOPCX_F32 <vopc<0x5a>, "v_cmpsx_nlg_f32">; 655defm V_CMPSX_NGT_F32 : VOPCX_F32 <vopc<0x5b>, "v_cmpsx_ngt_f32", "v_cmpsx_nlt_f32">; 656defm V_CMPSX_NLE_F32 : VOPCX_F32 <vopc<0x5c>, "v_cmpsx_nle_f32">; 657defm V_CMPSX_NEQ_F32 : VOPCX_F32 <vopc<0x5d>, "v_cmpsx_neq_f32">; 658defm V_CMPSX_NLT_F32 : VOPCX_F32 <vopc<0x5e>, "v_cmpsx_nlt_f32">; 659defm V_CMPSX_TRU_F32 : VOPCX_F32 <vopc<0x5f>, "v_cmpsx_tru_f32">; 660 661 662defm V_CMPS_F_F64 : VOPC_F64 <vopc<0x60>, "v_cmps_f_f64">; 663defm V_CMPS_LT_F64 : VOPC_F64 <vopc<0x61>, "v_cmps_lt_f64", COND_NULL, "v_cmps_gt_f64">; 664defm V_CMPS_EQ_F64 : VOPC_F64 <vopc<0x62>, "v_cmps_eq_f64">; 665defm V_CMPS_LE_F64 : VOPC_F64 <vopc<0x63>, "v_cmps_le_f64", COND_NULL, "v_cmps_ge_f64">; 666defm V_CMPS_GT_F64 : VOPC_F64 <vopc<0x64>, "v_cmps_gt_f64">; 667defm V_CMPS_LG_F64 : VOPC_F64 <vopc<0x65>, "v_cmps_lg_f64">; 668defm V_CMPS_GE_F64 : VOPC_F64 <vopc<0x66>, "v_cmps_ge_f64">; 669defm V_CMPS_O_F64 : VOPC_F64 <vopc<0x67>, "v_cmps_o_f64">; 670defm V_CMPS_U_F64 : VOPC_F64 <vopc<0x68>, "v_cmps_u_f64">; 671defm V_CMPS_NGE_F64 : VOPC_F64 <vopc<0x69>, "v_cmps_nge_f64", COND_NULL, "v_cmps_nle_f64">; 672defm V_CMPS_NLG_F64 : VOPC_F64 <vopc<0x6a>, "v_cmps_nlg_f64">; 673defm V_CMPS_NGT_F64 : VOPC_F64 <vopc<0x6b>, "v_cmps_ngt_f64", COND_NULL, "v_cmps_nlt_f64">; 674defm V_CMPS_NLE_F64 : VOPC_F64 <vopc<0x6c>, "v_cmps_nle_f64">; 675defm V_CMPS_NEQ_F64 : VOPC_F64 <vopc<0x6d>, "v_cmps_neq_f64">; 676defm V_CMPS_NLT_F64 : VOPC_F64 <vopc<0x6e>, "v_cmps_nlt_f64">; 677defm V_CMPS_TRU_F64 : VOPC_F64 <vopc<0x6f>, "v_cmps_tru_f64">; 678 679 680defm V_CMPSX_F_F64 : VOPCX_F64 <vopc<0x70>, "v_cmpsx_f_f64">; 681defm V_CMPSX_LT_F64 : VOPCX_F64 <vopc<0x71>, "v_cmpsx_lt_f64", "v_cmpsx_gt_f64">; 682defm V_CMPSX_EQ_F64 : VOPCX_F64 <vopc<0x72>, "v_cmpsx_eq_f64">; 683defm V_CMPSX_LE_F64 : VOPCX_F64 <vopc<0x73>, "v_cmpsx_le_f64", "v_cmpsx_ge_f64">; 684defm V_CMPSX_GT_F64 : VOPCX_F64 <vopc<0x74>, "v_cmpsx_gt_f64">; 685defm V_CMPSX_LG_F64 : VOPCX_F64 <vopc<0x75>, "v_cmpsx_lg_f64">; 686defm V_CMPSX_GE_F64 : VOPCX_F64 <vopc<0x76>, "v_cmpsx_ge_f64">; 687defm V_CMPSX_O_F64 : VOPCX_F64 <vopc<0x77>, "v_cmpsx_o_f64">; 688defm V_CMPSX_U_F64 : VOPCX_F64 <vopc<0x78>, "v_cmpsx_u_f64">; 689defm V_CMPSX_NGE_F64 : VOPCX_F64 <vopc<0x79>, "v_cmpsx_nge_f64", "v_cmpsx_nle_f64">; 690defm V_CMPSX_NLG_F64 : VOPCX_F64 <vopc<0x7a>, "v_cmpsx_nlg_f64">; 691defm V_CMPSX_NGT_F64 : VOPCX_F64 <vopc<0x7b>, "v_cmpsx_ngt_f64", "v_cmpsx_nlt_f64">; 692defm V_CMPSX_NLE_F64 : VOPCX_F64 <vopc<0x7c>, "v_cmpsx_nle_f64">; 693defm V_CMPSX_NEQ_F64 : VOPCX_F64 <vopc<0x7d>, "v_cmpsx_neq_f64">; 694defm V_CMPSX_NLT_F64 : VOPCX_F64 <vopc<0x7e>, "v_cmpsx_nlt_f64">; 695defm V_CMPSX_TRU_F64 : VOPCX_F64 <vopc<0x7f>, "v_cmpsx_tru_f64">; 696 697} // End SubtargetPredicate = isSICI 698 699defm V_CMP_F_I32 : VOPC_I32 <vopc<0x80, 0xc0>, "v_cmp_f_i32">; 700defm V_CMP_LT_I32 : VOPC_I32 <vopc<0x81, 0xc1>, "v_cmp_lt_i32", COND_SLT, "v_cmp_gt_i32">; 701defm V_CMP_EQ_I32 : VOPC_I32 <vopc<0x82, 0xc2>, "v_cmp_eq_i32", COND_EQ>; 702defm V_CMP_LE_I32 : VOPC_I32 <vopc<0x83, 0xc3>, "v_cmp_le_i32", COND_SLE, "v_cmp_ge_i32">; 703defm V_CMP_GT_I32 : VOPC_I32 <vopc<0x84, 0xc4>, "v_cmp_gt_i32", COND_SGT>; 704defm V_CMP_NE_I32 : VOPC_I32 <vopc<0x85, 0xc5>, "v_cmp_ne_i32", COND_NE>; 705defm V_CMP_GE_I32 : VOPC_I32 <vopc<0x86, 0xc6>, "v_cmp_ge_i32", COND_SGE>; 706defm V_CMP_T_I32 : VOPC_I32 <vopc<0x87, 0xc7>, "v_cmp_t_i32">; 707 708 709defm V_CMPX_F_I32 : VOPCX_I32 <vopc<0x90, 0xd0>, "v_cmpx_f_i32">; 710defm V_CMPX_LT_I32 : VOPCX_I32 <vopc<0x91, 0xd1>, "v_cmpx_lt_i32", "v_cmpx_gt_i32">; 711defm V_CMPX_EQ_I32 : VOPCX_I32 <vopc<0x92, 0xd2>, "v_cmpx_eq_i32">; 712defm V_CMPX_LE_I32 : VOPCX_I32 <vopc<0x93, 0xd3>, "v_cmpx_le_i32", "v_cmpx_ge_i32">; 713defm V_CMPX_GT_I32 : VOPCX_I32 <vopc<0x94, 0xd4>, "v_cmpx_gt_i32">; 714defm V_CMPX_NE_I32 : VOPCX_I32 <vopc<0x95, 0xd5>, "v_cmpx_ne_i32">; 715defm V_CMPX_GE_I32 : VOPCX_I32 <vopc<0x96, 0xd6>, "v_cmpx_ge_i32">; 716defm V_CMPX_T_I32 : VOPCX_I32 <vopc<0x97, 0xd7>, "v_cmpx_t_i32">; 717 718 719defm V_CMP_F_I64 : VOPC_I64 <vopc<0xa0, 0xe0>, "v_cmp_f_i64">; 720defm V_CMP_LT_I64 : VOPC_I64 <vopc<0xa1, 0xe1>, "v_cmp_lt_i64", COND_SLT, "v_cmp_gt_i64">; 721defm V_CMP_EQ_I64 : VOPC_I64 <vopc<0xa2, 0xe2>, "v_cmp_eq_i64", COND_EQ>; 722defm V_CMP_LE_I64 : VOPC_I64 <vopc<0xa3, 0xe3>, "v_cmp_le_i64", COND_SLE, "v_cmp_ge_i64">; 723defm V_CMP_GT_I64 : VOPC_I64 <vopc<0xa4, 0xe4>, "v_cmp_gt_i64", COND_SGT>; 724defm V_CMP_NE_I64 : VOPC_I64 <vopc<0xa5, 0xe5>, "v_cmp_ne_i64", COND_NE>; 725defm V_CMP_GE_I64 : VOPC_I64 <vopc<0xa6, 0xe6>, "v_cmp_ge_i64", COND_SGE>; 726defm V_CMP_T_I64 : VOPC_I64 <vopc<0xa7, 0xe7>, "v_cmp_t_i64">; 727 728 729defm V_CMPX_F_I64 : VOPCX_I64 <vopc<0xb0, 0xf0>, "v_cmpx_f_i64">; 730defm V_CMPX_LT_I64 : VOPCX_I64 <vopc<0xb1, 0xf1>, "v_cmpx_lt_i64", "v_cmpx_gt_i64">; 731defm V_CMPX_EQ_I64 : VOPCX_I64 <vopc<0xb2, 0xf2>, "v_cmpx_eq_i64">; 732defm V_CMPX_LE_I64 : VOPCX_I64 <vopc<0xb3, 0xf3>, "v_cmpx_le_i64", "v_cmpx_ge_i64">; 733defm V_CMPX_GT_I64 : VOPCX_I64 <vopc<0xb4, 0xf4>, "v_cmpx_gt_i64">; 734defm V_CMPX_NE_I64 : VOPCX_I64 <vopc<0xb5, 0xf5>, "v_cmpx_ne_i64">; 735defm V_CMPX_GE_I64 : VOPCX_I64 <vopc<0xb6, 0xf6>, "v_cmpx_ge_i64">; 736defm V_CMPX_T_I64 : VOPCX_I64 <vopc<0xb7, 0xf7>, "v_cmpx_t_i64">; 737 738 739defm V_CMP_F_U32 : VOPC_I32 <vopc<0xc0, 0xc8>, "v_cmp_f_u32">; 740defm V_CMP_LT_U32 : VOPC_I32 <vopc<0xc1, 0xc9>, "v_cmp_lt_u32", COND_ULT, "v_cmp_gt_u32">; 741defm V_CMP_EQ_U32 : VOPC_I32 <vopc<0xc2, 0xca>, "v_cmp_eq_u32", COND_EQ>; 742defm V_CMP_LE_U32 : VOPC_I32 <vopc<0xc3, 0xcb>, "v_cmp_le_u32", COND_ULE, "v_cmp_ge_u32">; 743defm V_CMP_GT_U32 : VOPC_I32 <vopc<0xc4, 0xcc>, "v_cmp_gt_u32", COND_UGT>; 744defm V_CMP_NE_U32 : VOPC_I32 <vopc<0xc5, 0xcd>, "v_cmp_ne_u32", COND_NE>; 745defm V_CMP_GE_U32 : VOPC_I32 <vopc<0xc6, 0xce>, "v_cmp_ge_u32", COND_UGE>; 746defm V_CMP_T_U32 : VOPC_I32 <vopc<0xc7, 0xcf>, "v_cmp_t_u32">; 747 748 749defm V_CMPX_F_U32 : VOPCX_I32 <vopc<0xd0, 0xd8>, "v_cmpx_f_u32">; 750defm V_CMPX_LT_U32 : VOPCX_I32 <vopc<0xd1, 0xd9>, "v_cmpx_lt_u32", "v_cmpx_gt_u32">; 751defm V_CMPX_EQ_U32 : VOPCX_I32 <vopc<0xd2, 0xda>, "v_cmpx_eq_u32">; 752defm V_CMPX_LE_U32 : VOPCX_I32 <vopc<0xd3, 0xdb>, "v_cmpx_le_u32", "v_cmpx_le_u32">; 753defm V_CMPX_GT_U32 : VOPCX_I32 <vopc<0xd4, 0xdc>, "v_cmpx_gt_u32">; 754defm V_CMPX_NE_U32 : VOPCX_I32 <vopc<0xd5, 0xdd>, "v_cmpx_ne_u32">; 755defm V_CMPX_GE_U32 : VOPCX_I32 <vopc<0xd6, 0xde>, "v_cmpx_ge_u32">; 756defm V_CMPX_T_U32 : VOPCX_I32 <vopc<0xd7, 0xdf>, "v_cmpx_t_u32">; 757 758 759defm V_CMP_F_U64 : VOPC_I64 <vopc<0xe0, 0xe8>, "v_cmp_f_u64">; 760defm V_CMP_LT_U64 : VOPC_I64 <vopc<0xe1, 0xe9>, "v_cmp_lt_u64", COND_ULT, "v_cmp_gt_u64">; 761defm V_CMP_EQ_U64 : VOPC_I64 <vopc<0xe2, 0xea>, "v_cmp_eq_u64", COND_EQ>; 762defm V_CMP_LE_U64 : VOPC_I64 <vopc<0xe3, 0xeb>, "v_cmp_le_u64", COND_ULE, "v_cmp_ge_u64">; 763defm V_CMP_GT_U64 : VOPC_I64 <vopc<0xe4, 0xec>, "v_cmp_gt_u64", COND_UGT>; 764defm V_CMP_NE_U64 : VOPC_I64 <vopc<0xe5, 0xed>, "v_cmp_ne_u64", COND_NE>; 765defm V_CMP_GE_U64 : VOPC_I64 <vopc<0xe6, 0xee>, "v_cmp_ge_u64", COND_UGE>; 766defm V_CMP_T_U64 : VOPC_I64 <vopc<0xe7, 0xef>, "v_cmp_t_u64">; 767 768defm V_CMPX_F_U64 : VOPCX_I64 <vopc<0xf0, 0xf8>, "v_cmpx_f_u64">; 769defm V_CMPX_LT_U64 : VOPCX_I64 <vopc<0xf1, 0xf9>, "v_cmpx_lt_u64", "v_cmpx_gt_u64">; 770defm V_CMPX_EQ_U64 : VOPCX_I64 <vopc<0xf2, 0xfa>, "v_cmpx_eq_u64">; 771defm V_CMPX_LE_U64 : VOPCX_I64 <vopc<0xf3, 0xfb>, "v_cmpx_le_u64", "v_cmpx_ge_u64">; 772defm V_CMPX_GT_U64 : VOPCX_I64 <vopc<0xf4, 0xfc>, "v_cmpx_gt_u64">; 773defm V_CMPX_NE_U64 : VOPCX_I64 <vopc<0xf5, 0xfd>, "v_cmpx_ne_u64">; 774defm V_CMPX_GE_U64 : VOPCX_I64 <vopc<0xf6, 0xfe>, "v_cmpx_ge_u64">; 775defm V_CMPX_T_U64 : VOPCX_I64 <vopc<0xf7, 0xff>, "v_cmpx_t_u64">; 776 777} // End isCompare = 1, isCommutable = 1 778 779defm V_CMP_CLASS_F32 : VOPC_CLASS_F32 <vopc<0x88, 0x10>, "v_cmp_class_f32">; 780defm V_CMPX_CLASS_F32 : VOPCX_CLASS_F32 <vopc<0x98, 0x11>, "v_cmpx_class_f32">; 781defm V_CMP_CLASS_F64 : VOPC_CLASS_F64 <vopc<0xa8, 0x12>, "v_cmp_class_f64">; 782defm V_CMPX_CLASS_F64 : VOPCX_CLASS_F64 <vopc<0xb8, 0x13>, "v_cmpx_class_f64">; 783 784//===----------------------------------------------------------------------===// 785// DS Instructions 786//===----------------------------------------------------------------------===// 787 788defm DS_ADD_U32 : DS_1A1D_NORET <0x0, "ds_add_u32", VGPR_32>; 789defm DS_SUB_U32 : DS_1A1D_NORET <0x1, "ds_sub_u32", VGPR_32>; 790defm DS_RSUB_U32 : DS_1A1D_NORET <0x2, "ds_rsub_u32", VGPR_32>; 791defm DS_INC_U32 : DS_1A1D_NORET <0x3, "ds_inc_u32", VGPR_32>; 792defm DS_DEC_U32 : DS_1A1D_NORET <0x4, "ds_dec_u32", VGPR_32>; 793defm DS_MIN_I32 : DS_1A1D_NORET <0x5, "ds_min_i32", VGPR_32>; 794defm DS_MAX_I32 : DS_1A1D_NORET <0x6, "ds_max_i32", VGPR_32>; 795defm DS_MIN_U32 : DS_1A1D_NORET <0x7, "ds_min_u32", VGPR_32>; 796defm DS_MAX_U32 : DS_1A1D_NORET <0x8, "ds_max_u32", VGPR_32>; 797defm DS_AND_B32 : DS_1A1D_NORET <0x9, "ds_and_b32", VGPR_32>; 798defm DS_OR_B32 : DS_1A1D_NORET <0xa, "ds_or_b32", VGPR_32>; 799defm DS_XOR_B32 : DS_1A1D_NORET <0xb, "ds_xor_b32", VGPR_32>; 800defm DS_MSKOR_B32 : DS_1A2D_NORET <0xc, "ds_mskor_b32", VGPR_32>; 801let mayLoad = 0 in { 802defm DS_WRITE_B32 : DS_1A1D_NORET <0xd, "ds_write_b32", VGPR_32>; 803defm DS_WRITE2_B32 : DS_1A1D_Off8_NORET <0xe, "ds_write2_b32", VGPR_32>; 804defm DS_WRITE2ST64_B32 : DS_1A1D_Off8_NORET <0xf, "ds_write2st64_b32", VGPR_32>; 805} 806defm DS_CMPST_B32 : DS_1A2D_NORET <0x10, "ds_cmpst_b32", VGPR_32>; 807defm DS_CMPST_F32 : DS_1A2D_NORET <0x11, "ds_cmpst_f32", VGPR_32>; 808defm DS_MIN_F32 : DS_1A2D_NORET <0x12, "ds_min_f32", VGPR_32>; 809defm DS_MAX_F32 : DS_1A2D_NORET <0x13, "ds_max_f32", VGPR_32>; 810 811defm DS_GWS_INIT : DS_1A_GDS <0x19, "ds_gws_init">; 812defm DS_GWS_SEMA_V : DS_1A_GDS <0x1a, "ds_gws_sema_v">; 813defm DS_GWS_SEMA_BR : DS_1A_GDS <0x1b, "ds_gws_sema_br">; 814defm DS_GWS_SEMA_P : DS_1A_GDS <0x1c, "ds_gws_sema_p">; 815defm DS_GWS_BARRIER : DS_1A_GDS <0x1d, "ds_gws_barrier">; 816let mayLoad = 0 in { 817defm DS_WRITE_B8 : DS_1A1D_NORET <0x1e, "ds_write_b8", VGPR_32>; 818defm DS_WRITE_B16 : DS_1A1D_NORET <0x1f, "ds_write_b16", VGPR_32>; 819} 820defm DS_ADD_RTN_U32 : DS_1A1D_RET <0x20, "ds_add_rtn_u32", VGPR_32, "ds_add_u32">; 821defm DS_SUB_RTN_U32 : DS_1A1D_RET <0x21, "ds_sub_rtn_u32", VGPR_32, "ds_sub_u32">; 822defm DS_RSUB_RTN_U32 : DS_1A1D_RET <0x22, "ds_rsub_rtn_u32", VGPR_32, "ds_rsub_u32">; 823defm DS_INC_RTN_U32 : DS_1A1D_RET <0x23, "ds_inc_rtn_u32", VGPR_32, "ds_inc_u32">; 824defm DS_DEC_RTN_U32 : DS_1A1D_RET <0x24, "ds_dec_rtn_u32", VGPR_32, "ds_dec_u32">; 825defm DS_MIN_RTN_I32 : DS_1A1D_RET <0x25, "ds_min_rtn_i32", VGPR_32, "ds_min_i32">; 826defm DS_MAX_RTN_I32 : DS_1A1D_RET <0x26, "ds_max_rtn_i32", VGPR_32, "ds_max_i32">; 827defm DS_MIN_RTN_U32 : DS_1A1D_RET <0x27, "ds_min_rtn_u32", VGPR_32, "ds_min_u32">; 828defm DS_MAX_RTN_U32 : DS_1A1D_RET <0x28, "ds_max_rtn_u32", VGPR_32, "ds_max_u32">; 829defm DS_AND_RTN_B32 : DS_1A1D_RET <0x29, "ds_and_rtn_b32", VGPR_32, "ds_and_b32">; 830defm DS_OR_RTN_B32 : DS_1A1D_RET <0x2a, "ds_or_rtn_b32", VGPR_32, "ds_or_b32">; 831defm DS_XOR_RTN_B32 : DS_1A1D_RET <0x2b, "ds_xor_rtn_b32", VGPR_32, "ds_xor_b32">; 832defm DS_MSKOR_RTN_B32 : DS_1A2D_RET <0x2c, "ds_mskor_rtn_b32", VGPR_32, "ds_mskor_b32">; 833defm DS_WRXCHG_RTN_B32 : DS_1A1D_RET <0x2d, "ds_wrxchg_rtn_b32", VGPR_32>; 834defm DS_WRXCHG2_RTN_B32 : DS_1A2D_RET < 835 0x2e, "ds_wrxchg2_rtn_b32", VReg_64, "", VGPR_32 836>; 837defm DS_WRXCHG2ST64_RTN_B32 : DS_1A2D_RET < 838 0x2f, "ds_wrxchg2st64_rtn_b32", VReg_64, "", VGPR_32 839>; 840defm DS_CMPST_RTN_B32 : DS_1A2D_RET <0x30, "ds_cmpst_rtn_b32", VGPR_32, "ds_cmpst_b32">; 841defm DS_CMPST_RTN_F32 : DS_1A2D_RET <0x31, "ds_cmpst_rtn_f32", VGPR_32, "ds_cmpst_f32">; 842defm DS_MIN_RTN_F32 : DS_1A2D_RET <0x32, "ds_min_rtn_f32", VGPR_32, "ds_min_f32">; 843defm DS_MAX_RTN_F32 : DS_1A2D_RET <0x33, "ds_max_rtn_f32", VGPR_32, "ds_max_f32">; 844defm DS_SWIZZLE_B32 : DS_1A_RET <0x35, "ds_swizzle_b32", VGPR_32>; 845let mayStore = 0 in { 846defm DS_READ_B32 : DS_1A_RET <0x36, "ds_read_b32", VGPR_32>; 847defm DS_READ2_B32 : DS_1A_Off8_RET <0x37, "ds_read2_b32", VReg_64>; 848defm DS_READ2ST64_B32 : DS_1A_Off8_RET <0x38, "ds_read2st64_b32", VReg_64>; 849defm DS_READ_I8 : DS_1A_RET <0x39, "ds_read_i8", VGPR_32>; 850defm DS_READ_U8 : DS_1A_RET <0x3a, "ds_read_u8", VGPR_32>; 851defm DS_READ_I16 : DS_1A_RET <0x3b, "ds_read_i16", VGPR_32>; 852defm DS_READ_U16 : DS_1A_RET <0x3c, "ds_read_u16", VGPR_32>; 853} 854defm DS_CONSUME : DS_0A_RET <0x3d, "ds_consume">; 855defm DS_APPEND : DS_0A_RET <0x3e, "ds_append">; 856defm DS_ORDERED_COUNT : DS_1A_RET_GDS <0x3f, "ds_ordered_count">; 857defm DS_ADD_U64 : DS_1A1D_NORET <0x40, "ds_add_u64", VReg_64>; 858defm DS_SUB_U64 : DS_1A1D_NORET <0x41, "ds_sub_u64", VReg_64>; 859defm DS_RSUB_U64 : DS_1A1D_NORET <0x42, "ds_rsub_u64", VReg_64>; 860defm DS_INC_U64 : DS_1A1D_NORET <0x43, "ds_inc_u64", VReg_64>; 861defm DS_DEC_U64 : DS_1A1D_NORET <0x44, "ds_dec_u64", VReg_64>; 862defm DS_MIN_I64 : DS_1A1D_NORET <0x45, "ds_min_i64", VReg_64>; 863defm DS_MAX_I64 : DS_1A1D_NORET <0x46, "ds_max_i64", VReg_64>; 864defm DS_MIN_U64 : DS_1A1D_NORET <0x47, "ds_min_u64", VReg_64>; 865defm DS_MAX_U64 : DS_1A1D_NORET <0x48, "ds_max_u64", VReg_64>; 866defm DS_AND_B64 : DS_1A1D_NORET <0x49, "ds_and_b64", VReg_64>; 867defm DS_OR_B64 : DS_1A1D_NORET <0x4a, "ds_or_b64", VReg_64>; 868defm DS_XOR_B64 : DS_1A1D_NORET <0x4b, "ds_xor_b64", VReg_64>; 869defm DS_MSKOR_B64 : DS_1A2D_NORET <0x4c, "ds_mskor_b64", VReg_64>; 870let mayLoad = 0 in { 871defm DS_WRITE_B64 : DS_1A1D_NORET <0x4d, "ds_write_b64", VReg_64>; 872defm DS_WRITE2_B64 : DS_1A1D_Off8_NORET <0x4E, "ds_write2_b64", VReg_64>; 873defm DS_WRITE2ST64_B64 : DS_1A1D_Off8_NORET <0x4f, "ds_write2st64_b64", VReg_64>; 874} 875defm DS_CMPST_B64 : DS_1A2D_NORET <0x50, "ds_cmpst_b64", VReg_64>; 876defm DS_CMPST_F64 : DS_1A2D_NORET <0x51, "ds_cmpst_f64", VReg_64>; 877defm DS_MIN_F64 : DS_1A1D_NORET <0x52, "ds_min_f64", VReg_64>; 878defm DS_MAX_F64 : DS_1A1D_NORET <0x53, "ds_max_f64", VReg_64>; 879 880defm DS_ADD_RTN_U64 : DS_1A1D_RET <0x60, "ds_add_rtn_u64", VReg_64, "ds_add_u64">; 881defm DS_SUB_RTN_U64 : DS_1A1D_RET <0x61, "ds_sub_rtn_u64", VReg_64, "ds_sub_u64">; 882defm DS_RSUB_RTN_U64 : DS_1A1D_RET <0x62, "ds_rsub_rtn_u64", VReg_64, "ds_rsub_u64">; 883defm DS_INC_RTN_U64 : DS_1A1D_RET <0x63, "ds_inc_rtn_u64", VReg_64, "ds_inc_u64">; 884defm DS_DEC_RTN_U64 : DS_1A1D_RET <0x64, "ds_dec_rtn_u64", VReg_64, "ds_dec_u64">; 885defm DS_MIN_RTN_I64 : DS_1A1D_RET <0x65, "ds_min_rtn_i64", VReg_64, "ds_min_i64">; 886defm DS_MAX_RTN_I64 : DS_1A1D_RET <0x66, "ds_max_rtn_i64", VReg_64, "ds_max_i64">; 887defm DS_MIN_RTN_U64 : DS_1A1D_RET <0x67, "ds_min_rtn_u64", VReg_64, "ds_min_u64">; 888defm DS_MAX_RTN_U64 : DS_1A1D_RET <0x68, "ds_max_rtn_u64", VReg_64, "ds_max_u64">; 889defm DS_AND_RTN_B64 : DS_1A1D_RET <0x69, "ds_and_rtn_b64", VReg_64, "ds_and_b64">; 890defm DS_OR_RTN_B64 : DS_1A1D_RET <0x6a, "ds_or_rtn_b64", VReg_64, "ds_or_b64">; 891defm DS_XOR_RTN_B64 : DS_1A1D_RET <0x6b, "ds_xor_rtn_b64", VReg_64, "ds_xor_b64">; 892defm DS_MSKOR_RTN_B64 : DS_1A2D_RET <0x6c, "ds_mskor_rtn_b64", VReg_64, "ds_mskor_b64">; 893defm DS_WRXCHG_RTN_B64 : DS_1A1D_RET <0x6d, "ds_wrxchg_rtn_b64", VReg_64, "ds_wrxchg_b64">; 894defm DS_WRXCHG2_RTN_B64 : DS_1A2D_RET <0x6e, "ds_wrxchg2_rtn_b64", VReg_128, "ds_wrxchg2_b64", VReg_64>; 895defm DS_WRXCHG2ST64_RTN_B64 : DS_1A2D_RET <0x6f, "ds_wrxchg2st64_rtn_b64", VReg_128, "ds_wrxchg2st64_b64", VReg_64>; 896defm DS_CMPST_RTN_B64 : DS_1A2D_RET <0x70, "ds_cmpst_rtn_b64", VReg_64, "ds_cmpst_b64">; 897defm DS_CMPST_RTN_F64 : DS_1A2D_RET <0x71, "ds_cmpst_rtn_f64", VReg_64, "ds_cmpst_f64">; 898defm DS_MIN_RTN_F64 : DS_1A1D_RET <0x72, "ds_min_rtn_f64", VReg_64, "ds_min_f64">; 899defm DS_MAX_RTN_F64 : DS_1A1D_RET <0x73, "ds_max_rtn_f64", VReg_64, "ds_max_f64">; 900 901let mayStore = 0 in { 902defm DS_READ_B64 : DS_1A_RET <0x76, "ds_read_b64", VReg_64>; 903defm DS_READ2_B64 : DS_1A_Off8_RET <0x77, "ds_read2_b64", VReg_128>; 904defm DS_READ2ST64_B64 : DS_1A_Off8_RET <0x78, "ds_read2st64_b64", VReg_128>; 905} 906 907defm DS_ADD_SRC2_U32 : DS_1A <0x80, "ds_add_src2_u32">; 908defm DS_SUB_SRC2_U32 : DS_1A <0x81, "ds_sub_src2_u32">; 909defm DS_RSUB_SRC2_U32 : DS_1A <0x82, "ds_rsub_src2_u32">; 910defm DS_INC_SRC2_U32 : DS_1A <0x83, "ds_inc_src2_u32">; 911defm DS_DEC_SRC2_U32 : DS_1A <0x84, "ds_dec_src2_u32">; 912defm DS_MIN_SRC2_I32 : DS_1A <0x85, "ds_min_src2_i32">; 913defm DS_MAX_SRC2_I32 : DS_1A <0x86, "ds_max_src2_i32">; 914defm DS_MIN_SRC2_U32 : DS_1A <0x87, "ds_min_src2_u32">; 915defm DS_MAX_SRC2_U32 : DS_1A <0x88, "ds_max_src2_u32">; 916defm DS_AND_SRC2_B32 : DS_1A <0x89, "ds_and_src_b32">; 917defm DS_OR_SRC2_B32 : DS_1A <0x8a, "ds_or_src2_b32">; 918defm DS_XOR_SRC2_B32 : DS_1A <0x8b, "ds_xor_src2_b32">; 919defm DS_WRITE_SRC2_B32 : DS_1A <0x8c, "ds_write_src2_b32">; 920 921defm DS_MIN_SRC2_F32 : DS_1A <0x92, "ds_min_src2_f32">; 922defm DS_MAX_SRC2_F32 : DS_1A <0x93, "ds_max_src2_f32">; 923 924defm DS_ADD_SRC2_U64 : DS_1A <0xc0, "ds_add_src2_u64">; 925defm DS_SUB_SRC2_U64 : DS_1A <0xc1, "ds_sub_src2_u64">; 926defm DS_RSUB_SRC2_U64 : DS_1A <0xc2, "ds_rsub_src2_u64">; 927defm DS_INC_SRC2_U64 : DS_1A <0xc3, "ds_inc_src2_u64">; 928defm DS_DEC_SRC2_U64 : DS_1A <0xc4, "ds_dec_src2_u64">; 929defm DS_MIN_SRC2_I64 : DS_1A <0xc5, "ds_min_src2_i64">; 930defm DS_MAX_SRC2_I64 : DS_1A <0xc6, "ds_max_src2_i64">; 931defm DS_MIN_SRC2_U64 : DS_1A <0xc7, "ds_min_src2_u64">; 932defm DS_MAX_SRC2_U64 : DS_1A <0xc8, "ds_max_src2_u64">; 933defm DS_AND_SRC2_B64 : DS_1A <0xc9, "ds_and_src2_b64">; 934defm DS_OR_SRC2_B64 : DS_1A <0xca, "ds_or_src2_b64">; 935defm DS_XOR_SRC2_B64 : DS_1A <0xcb, "ds_xor_src2_b64">; 936defm DS_WRITE_SRC2_B64 : DS_1A <0xcc, "ds_write_src2_b64">; 937 938defm DS_MIN_SRC2_F64 : DS_1A <0xd2, "ds_min_src2_f64">; 939defm DS_MAX_SRC2_F64 : DS_1A <0xd3, "ds_max_src2_f64">; 940 941//===----------------------------------------------------------------------===// 942// MUBUF Instructions 943//===----------------------------------------------------------------------===// 944 945defm BUFFER_LOAD_FORMAT_X : MUBUF_Load_Helper < 946 mubuf<0x00>, "buffer_load_format_x", VGPR_32 947>; 948defm BUFFER_LOAD_FORMAT_XY : MUBUF_Load_Helper < 949 mubuf<0x01>, "buffer_load_format_xy", VReg_64 950>; 951defm BUFFER_LOAD_FORMAT_XYZ : MUBUF_Load_Helper < 952 mubuf<0x02>, "buffer_load_format_xyz", VReg_96 953>; 954defm BUFFER_LOAD_FORMAT_XYZW : MUBUF_Load_Helper < 955 mubuf<0x03>, "buffer_load_format_xyzw", VReg_128 956>; 957defm BUFFER_STORE_FORMAT_X : MUBUF_Store_Helper < 958 mubuf<0x04>, "buffer_store_format_x", VGPR_32 959>; 960defm BUFFER_STORE_FORMAT_XY : MUBUF_Store_Helper < 961 mubuf<0x05>, "buffer_store_format_xy", VReg_64 962>; 963defm BUFFER_STORE_FORMAT_XYZ : MUBUF_Store_Helper < 964 mubuf<0x06>, "buffer_store_format_xyz", VReg_96 965>; 966defm BUFFER_STORE_FORMAT_XYZW : MUBUF_Store_Helper < 967 mubuf<0x07>, "buffer_store_format_xyzw", VReg_128 968>; 969defm BUFFER_LOAD_UBYTE : MUBUF_Load_Helper < 970 mubuf<0x08, 0x10>, "buffer_load_ubyte", VGPR_32, i32, az_extloadi8_global 971>; 972defm BUFFER_LOAD_SBYTE : MUBUF_Load_Helper < 973 mubuf<0x09, 0x11>, "buffer_load_sbyte", VGPR_32, i32, sextloadi8_global 974>; 975defm BUFFER_LOAD_USHORT : MUBUF_Load_Helper < 976 mubuf<0x0a, 0x12>, "buffer_load_ushort", VGPR_32, i32, az_extloadi16_global 977>; 978defm BUFFER_LOAD_SSHORT : MUBUF_Load_Helper < 979 mubuf<0x0b, 0x13>, "buffer_load_sshort", VGPR_32, i32, sextloadi16_global 980>; 981defm BUFFER_LOAD_DWORD : MUBUF_Load_Helper < 982 mubuf<0x0c, 0x14>, "buffer_load_dword", VGPR_32, i32, mubuf_load 983>; 984defm BUFFER_LOAD_DWORDX2 : MUBUF_Load_Helper < 985 mubuf<0x0d, 0x15>, "buffer_load_dwordx2", VReg_64, v2i32, mubuf_load 986>; 987defm BUFFER_LOAD_DWORDX4 : MUBUF_Load_Helper < 988 mubuf<0x0e, 0x17>, "buffer_load_dwordx4", VReg_128, v4i32, mubuf_load 989>; 990 991defm BUFFER_STORE_BYTE : MUBUF_Store_Helper < 992 mubuf<0x18>, "buffer_store_byte", VGPR_32, i32, truncstorei8_global 993>; 994 995defm BUFFER_STORE_SHORT : MUBUF_Store_Helper < 996 mubuf<0x1a>, "buffer_store_short", VGPR_32, i32, truncstorei16_global 997>; 998 999defm BUFFER_STORE_DWORD : MUBUF_Store_Helper < 1000 mubuf<0x1c>, "buffer_store_dword", VGPR_32, i32, global_store 1001>; 1002 1003defm BUFFER_STORE_DWORDX2 : MUBUF_Store_Helper < 1004 mubuf<0x1d>, "buffer_store_dwordx2", VReg_64, v2i32, global_store 1005>; 1006 1007defm BUFFER_STORE_DWORDX4 : MUBUF_Store_Helper < 1008 mubuf<0x1e, 0x1f>, "buffer_store_dwordx4", VReg_128, v4i32, global_store 1009>; 1010 1011defm BUFFER_ATOMIC_SWAP : MUBUF_Atomic < 1012 mubuf<0x30, 0x40>, "buffer_atomic_swap", VGPR_32, i32, atomic_swap_global 1013>; 1014defm BUFFER_ATOMIC_CMPSWAP : MUBUF_Atomic < 1015 mubuf<0x31, 0x41>, "buffer_atomic_cmpswap", VReg_64, v2i32, null_frag 1016>; 1017defm BUFFER_ATOMIC_ADD : MUBUF_Atomic < 1018 mubuf<0x32, 0x42>, "buffer_atomic_add", VGPR_32, i32, atomic_add_global 1019>; 1020defm BUFFER_ATOMIC_SUB : MUBUF_Atomic < 1021 mubuf<0x33, 0x43>, "buffer_atomic_sub", VGPR_32, i32, atomic_sub_global 1022>; 1023//def BUFFER_ATOMIC_RSUB : MUBUF_ <mubuf<0x34>, "buffer_atomic_rsub", []>; // isn't on CI & VI 1024defm BUFFER_ATOMIC_SMIN : MUBUF_Atomic < 1025 mubuf<0x35, 0x44>, "buffer_atomic_smin", VGPR_32, i32, atomic_min_global 1026>; 1027defm BUFFER_ATOMIC_UMIN : MUBUF_Atomic < 1028 mubuf<0x36, 0x45>, "buffer_atomic_umin", VGPR_32, i32, atomic_umin_global 1029>; 1030defm BUFFER_ATOMIC_SMAX : MUBUF_Atomic < 1031 mubuf<0x37, 0x46>, "buffer_atomic_smax", VGPR_32, i32, atomic_max_global 1032>; 1033defm BUFFER_ATOMIC_UMAX : MUBUF_Atomic < 1034 mubuf<0x38, 0x47>, "buffer_atomic_umax", VGPR_32, i32, atomic_umax_global 1035>; 1036defm BUFFER_ATOMIC_AND : MUBUF_Atomic < 1037 mubuf<0x39, 0x48>, "buffer_atomic_and", VGPR_32, i32, atomic_and_global 1038>; 1039defm BUFFER_ATOMIC_OR : MUBUF_Atomic < 1040 mubuf<0x3a, 0x49>, "buffer_atomic_or", VGPR_32, i32, atomic_or_global 1041>; 1042defm BUFFER_ATOMIC_XOR : MUBUF_Atomic < 1043 mubuf<0x3b, 0x4a>, "buffer_atomic_xor", VGPR_32, i32, atomic_xor_global 1044>; 1045defm BUFFER_ATOMIC_INC : MUBUF_Atomic < 1046 mubuf<0x3c, 0x4b>, "buffer_atomic_inc", VGPR_32, i32, atomic_inc_global 1047>; 1048defm BUFFER_ATOMIC_DEC : MUBUF_Atomic < 1049 mubuf<0x3d, 0x4c>, "buffer_atomic_dec", VGPR_32, i32, atomic_dec_global 1050>; 1051 1052//def BUFFER_ATOMIC_FCMPSWAP : MUBUF_Atomic <mubuf<0x3e>, "buffer_atomic_fcmpswap", []>; // isn't on VI 1053//def BUFFER_ATOMIC_FMIN : MUBUF_Atomic <mubuf<0x3f>, "buffer_atomic_fmin", []>; // isn't on VI 1054//def BUFFER_ATOMIC_FMAX : MUBUF_Atomic <mubuf<0x40>, "buffer_atomic_fmax", []>; // isn't on VI 1055defm BUFFER_ATOMIC_SWAP_X2 : MUBUF_Atomic < 1056 mubuf<0x50, 0x60>, "buffer_atomic_swap_x2", VReg_64, i64, atomic_swap_global 1057>; 1058defm BUFFER_ATOMIC_CMPSWAP_X2 : MUBUF_Atomic < 1059 mubuf<0x51, 0x61>, "buffer_atomic_cmpswap_x2", VReg_128, v2i64, null_frag 1060>; 1061defm BUFFER_ATOMIC_ADD_X2 : MUBUF_Atomic < 1062 mubuf<0x52, 0x62>, "buffer_atomic_add_x2", VReg_64, i64, atomic_add_global 1063>; 1064defm BUFFER_ATOMIC_SUB_X2 : MUBUF_Atomic < 1065 mubuf<0x53, 0x63>, "buffer_atomic_sub_x2", VReg_64, i64, atomic_sub_global 1066>; 1067//defm BUFFER_ATOMIC_RSUB_X2 : MUBUF_Atomic <mubuf<0x54>, "buffer_atomic_rsub_x2", []>; // isn't on CI & VI 1068defm BUFFER_ATOMIC_SMIN_X2 : MUBUF_Atomic < 1069 mubuf<0x55, 0x64>, "buffer_atomic_smin_x2", VReg_64, i64, atomic_min_global 1070>; 1071defm BUFFER_ATOMIC_UMIN_X2 : MUBUF_Atomic < 1072 mubuf<0x56, 0x65>, "buffer_atomic_umin_x2", VReg_64, i64, atomic_umin_global 1073>; 1074defm BUFFER_ATOMIC_SMAX_X2 : MUBUF_Atomic < 1075 mubuf<0x57, 0x66>, "buffer_atomic_smax_x2", VReg_64, i64, atomic_max_global 1076>; 1077defm BUFFER_ATOMIC_UMAX_X2 : MUBUF_Atomic < 1078 mubuf<0x58, 0x67>, "buffer_atomic_umax_x2", VReg_64, i64, atomic_umax_global 1079>; 1080defm BUFFER_ATOMIC_AND_X2 : MUBUF_Atomic < 1081 mubuf<0x59, 0x68>, "buffer_atomic_and_x2", VReg_64, i64, atomic_and_global 1082>; 1083defm BUFFER_ATOMIC_OR_X2 : MUBUF_Atomic < 1084 mubuf<0x5a, 0x69>, "buffer_atomic_or_x2", VReg_64, i64, atomic_or_global 1085>; 1086defm BUFFER_ATOMIC_XOR_X2 : MUBUF_Atomic < 1087 mubuf<0x5b, 0x6a>, "buffer_atomic_xor_x2", VReg_64, i64, atomic_xor_global 1088>; 1089defm BUFFER_ATOMIC_INC_X2 : MUBUF_Atomic < 1090 mubuf<0x5c, 0x6b>, "buffer_atomic_inc_x2", VReg_64, i64, atomic_inc_global 1091>; 1092defm BUFFER_ATOMIC_DEC_X2 : MUBUF_Atomic < 1093 mubuf<0x5d, 0x6c>, "buffer_atomic_dec_x2", VReg_64, i64, atomic_dec_global 1094>; 1095//def BUFFER_ATOMIC_FCMPSWAP_X2 : MUBUF_X2 <mubuf<0x5e>, "buffer_atomic_fcmpswap_x2", []>; // isn't on VI 1096//def BUFFER_ATOMIC_FMIN_X2 : MUBUF_X2 <mubuf<0x5f>, "buffer_atomic_fmin_x2", []>; // isn't on VI 1097//def BUFFER_ATOMIC_FMAX_X2 : MUBUF_X2 <mubuf<0x60>, "buffer_atomic_fmax_x2", []>; // isn't on VI 1098 1099let SubtargetPredicate = isSI, DisableVIDecoder = 1 in { 1100defm BUFFER_WBINVL1_SC : MUBUF_Invalidate <mubuf<0x70>, "buffer_wbinvl1_sc", int_amdgcn_buffer_wbinvl1_sc>; // isn't on CI & VI 1101} 1102 1103defm BUFFER_WBINVL1 : MUBUF_Invalidate <mubuf<0x71, 0x3e>, "buffer_wbinvl1", int_amdgcn_buffer_wbinvl1>; 1104 1105//===----------------------------------------------------------------------===// 1106// MTBUF Instructions 1107//===----------------------------------------------------------------------===// 1108 1109//def TBUFFER_LOAD_FORMAT_X : MTBUF_ <0x00000000, "tbuffer_load_format_x", []>; 1110//def TBUFFER_LOAD_FORMAT_XY : MTBUF_ <0x00000001, "tbuffer_load_format_xy", []>; 1111//def TBUFFER_LOAD_FORMAT_XYZ : MTBUF_ <0x00000002, "tbuffer_load_format_xyz", []>; 1112defm TBUFFER_LOAD_FORMAT_XYZW : MTBUF_Load_Helper <0x00000003, "tbuffer_load_format_xyzw", VReg_128>; 1113defm TBUFFER_STORE_FORMAT_X : MTBUF_Store_Helper <0x00000004, "tbuffer_store_format_x", VGPR_32>; 1114defm TBUFFER_STORE_FORMAT_XY : MTBUF_Store_Helper <0x00000005, "tbuffer_store_format_xy", VReg_64>; 1115defm TBUFFER_STORE_FORMAT_XYZ : MTBUF_Store_Helper <0x00000006, "tbuffer_store_format_xyz", VReg_128>; 1116defm TBUFFER_STORE_FORMAT_XYZW : MTBUF_Store_Helper <0x00000007, "tbuffer_store_format_xyzw", VReg_128>; 1117 1118//===----------------------------------------------------------------------===// 1119// MIMG Instructions 1120//===----------------------------------------------------------------------===// 1121 1122defm IMAGE_LOAD : MIMG_NoSampler <0x00000000, "image_load">; 1123defm IMAGE_LOAD_MIP : MIMG_NoSampler <0x00000001, "image_load_mip">; 1124//def IMAGE_LOAD_PCK : MIMG_NoPattern_ <"image_load_pck", 0x00000002>; 1125//def IMAGE_LOAD_PCK_SGN : MIMG_NoPattern_ <"image_load_pck_sgn", 0x00000003>; 1126//def IMAGE_LOAD_MIP_PCK : MIMG_NoPattern_ <"image_load_mip_pck", 0x00000004>; 1127//def IMAGE_LOAD_MIP_PCK_SGN : MIMG_NoPattern_ <"image_load_mip_pck_sgn", 0x00000005>; 1128defm IMAGE_STORE : MIMG_Store <0x00000008, "image_store">; 1129defm IMAGE_STORE_MIP : MIMG_Store <0x00000009, "image_store_mip">; 1130//def IMAGE_STORE_PCK : MIMG_NoPattern_ <"image_store_pck", 0x0000000a>; 1131//def IMAGE_STORE_MIP_PCK : MIMG_NoPattern_ <"image_store_mip_pck", 0x0000000b>; 1132defm IMAGE_GET_RESINFO : MIMG_NoSampler <0x0000000e, "image_get_resinfo">; 1133defm IMAGE_ATOMIC_SWAP : MIMG_Atomic <mimg<0x0f, 0x10>, "image_atomic_swap">; 1134defm IMAGE_ATOMIC_CMPSWAP : MIMG_Atomic <mimg<0x10, 0x11>, "image_atomic_cmpswap", VReg_64>; 1135defm IMAGE_ATOMIC_ADD : MIMG_Atomic <mimg<0x11, 0x12>, "image_atomic_add">; 1136defm IMAGE_ATOMIC_SUB : MIMG_Atomic <mimg<0x12, 0x13>, "image_atomic_sub">; 1137//def IMAGE_ATOMIC_RSUB : MIMG_NoPattern_ <"image_atomic_rsub", 0x00000013>; -- not on VI 1138defm IMAGE_ATOMIC_SMIN : MIMG_Atomic <mimg<0x14>, "image_atomic_smin">; 1139defm IMAGE_ATOMIC_UMIN : MIMG_Atomic <mimg<0x15>, "image_atomic_umin">; 1140defm IMAGE_ATOMIC_SMAX : MIMG_Atomic <mimg<0x16>, "image_atomic_smax">; 1141defm IMAGE_ATOMIC_UMAX : MIMG_Atomic <mimg<0x17>, "image_atomic_umax">; 1142defm IMAGE_ATOMIC_AND : MIMG_Atomic <mimg<0x18>, "image_atomic_and">; 1143defm IMAGE_ATOMIC_OR : MIMG_Atomic <mimg<0x19>, "image_atomic_or">; 1144defm IMAGE_ATOMIC_XOR : MIMG_Atomic <mimg<0x1a>, "image_atomic_xor">; 1145defm IMAGE_ATOMIC_INC : MIMG_Atomic <mimg<0x1b>, "image_atomic_inc">; 1146defm IMAGE_ATOMIC_DEC : MIMG_Atomic <mimg<0x1c>, "image_atomic_dec">; 1147//def IMAGE_ATOMIC_FCMPSWAP : MIMG_NoPattern_ <"image_atomic_fcmpswap", 0x0000001d>; -- not on VI 1148//def IMAGE_ATOMIC_FMIN : MIMG_NoPattern_ <"image_atomic_fmin", 0x0000001e>; -- not on VI 1149//def IMAGE_ATOMIC_FMAX : MIMG_NoPattern_ <"image_atomic_fmax", 0x0000001f>; -- not on VI 1150defm IMAGE_SAMPLE : MIMG_Sampler_WQM <0x00000020, "image_sample">; 1151defm IMAGE_SAMPLE_CL : MIMG_Sampler_WQM <0x00000021, "image_sample_cl">; 1152defm IMAGE_SAMPLE_D : MIMG_Sampler <0x00000022, "image_sample_d">; 1153defm IMAGE_SAMPLE_D_CL : MIMG_Sampler <0x00000023, "image_sample_d_cl">; 1154defm IMAGE_SAMPLE_L : MIMG_Sampler <0x00000024, "image_sample_l">; 1155defm IMAGE_SAMPLE_B : MIMG_Sampler_WQM <0x00000025, "image_sample_b">; 1156defm IMAGE_SAMPLE_B_CL : MIMG_Sampler_WQM <0x00000026, "image_sample_b_cl">; 1157defm IMAGE_SAMPLE_LZ : MIMG_Sampler <0x00000027, "image_sample_lz">; 1158defm IMAGE_SAMPLE_C : MIMG_Sampler_WQM <0x00000028, "image_sample_c">; 1159defm IMAGE_SAMPLE_C_CL : MIMG_Sampler_WQM <0x00000029, "image_sample_c_cl">; 1160defm IMAGE_SAMPLE_C_D : MIMG_Sampler <0x0000002a, "image_sample_c_d">; 1161defm IMAGE_SAMPLE_C_D_CL : MIMG_Sampler <0x0000002b, "image_sample_c_d_cl">; 1162defm IMAGE_SAMPLE_C_L : MIMG_Sampler <0x0000002c, "image_sample_c_l">; 1163defm IMAGE_SAMPLE_C_B : MIMG_Sampler_WQM <0x0000002d, "image_sample_c_b">; 1164defm IMAGE_SAMPLE_C_B_CL : MIMG_Sampler_WQM <0x0000002e, "image_sample_c_b_cl">; 1165defm IMAGE_SAMPLE_C_LZ : MIMG_Sampler <0x0000002f, "image_sample_c_lz">; 1166defm IMAGE_SAMPLE_O : MIMG_Sampler_WQM <0x00000030, "image_sample_o">; 1167defm IMAGE_SAMPLE_CL_O : MIMG_Sampler_WQM <0x00000031, "image_sample_cl_o">; 1168defm IMAGE_SAMPLE_D_O : MIMG_Sampler <0x00000032, "image_sample_d_o">; 1169defm IMAGE_SAMPLE_D_CL_O : MIMG_Sampler <0x00000033, "image_sample_d_cl_o">; 1170defm IMAGE_SAMPLE_L_O : MIMG_Sampler <0x00000034, "image_sample_l_o">; 1171defm IMAGE_SAMPLE_B_O : MIMG_Sampler_WQM <0x00000035, "image_sample_b_o">; 1172defm IMAGE_SAMPLE_B_CL_O : MIMG_Sampler_WQM <0x00000036, "image_sample_b_cl_o">; 1173defm IMAGE_SAMPLE_LZ_O : MIMG_Sampler <0x00000037, "image_sample_lz_o">; 1174defm IMAGE_SAMPLE_C_O : MIMG_Sampler_WQM <0x00000038, "image_sample_c_o">; 1175defm IMAGE_SAMPLE_C_CL_O : MIMG_Sampler_WQM <0x00000039, "image_sample_c_cl_o">; 1176defm IMAGE_SAMPLE_C_D_O : MIMG_Sampler <0x0000003a, "image_sample_c_d_o">; 1177defm IMAGE_SAMPLE_C_D_CL_O : MIMG_Sampler <0x0000003b, "image_sample_c_d_cl_o">; 1178defm IMAGE_SAMPLE_C_L_O : MIMG_Sampler <0x0000003c, "image_sample_c_l_o">; 1179defm IMAGE_SAMPLE_C_B_O : MIMG_Sampler_WQM <0x0000003d, "image_sample_c_b_o">; 1180defm IMAGE_SAMPLE_C_B_CL_O : MIMG_Sampler_WQM <0x0000003e, "image_sample_c_b_cl_o">; 1181defm IMAGE_SAMPLE_C_LZ_O : MIMG_Sampler <0x0000003f, "image_sample_c_lz_o">; 1182defm IMAGE_GATHER4 : MIMG_Gather_WQM <0x00000040, "image_gather4">; 1183defm IMAGE_GATHER4_CL : MIMG_Gather_WQM <0x00000041, "image_gather4_cl">; 1184defm IMAGE_GATHER4_L : MIMG_Gather <0x00000044, "image_gather4_l">; 1185defm IMAGE_GATHER4_B : MIMG_Gather_WQM <0x00000045, "image_gather4_b">; 1186defm IMAGE_GATHER4_B_CL : MIMG_Gather_WQM <0x00000046, "image_gather4_b_cl">; 1187defm IMAGE_GATHER4_LZ : MIMG_Gather <0x00000047, "image_gather4_lz">; 1188defm IMAGE_GATHER4_C : MIMG_Gather_WQM <0x00000048, "image_gather4_c">; 1189defm IMAGE_GATHER4_C_CL : MIMG_Gather_WQM <0x00000049, "image_gather4_c_cl">; 1190defm IMAGE_GATHER4_C_L : MIMG_Gather <0x0000004c, "image_gather4_c_l">; 1191defm IMAGE_GATHER4_C_B : MIMG_Gather_WQM <0x0000004d, "image_gather4_c_b">; 1192defm IMAGE_GATHER4_C_B_CL : MIMG_Gather_WQM <0x0000004e, "image_gather4_c_b_cl">; 1193defm IMAGE_GATHER4_C_LZ : MIMG_Gather <0x0000004f, "image_gather4_c_lz">; 1194defm IMAGE_GATHER4_O : MIMG_Gather_WQM <0x00000050, "image_gather4_o">; 1195defm IMAGE_GATHER4_CL_O : MIMG_Gather_WQM <0x00000051, "image_gather4_cl_o">; 1196defm IMAGE_GATHER4_L_O : MIMG_Gather <0x00000054, "image_gather4_l_o">; 1197defm IMAGE_GATHER4_B_O : MIMG_Gather_WQM <0x00000055, "image_gather4_b_o">; 1198defm IMAGE_GATHER4_B_CL_O : MIMG_Gather <0x00000056, "image_gather4_b_cl_o">; 1199defm IMAGE_GATHER4_LZ_O : MIMG_Gather <0x00000057, "image_gather4_lz_o">; 1200defm IMAGE_GATHER4_C_O : MIMG_Gather_WQM <0x00000058, "image_gather4_c_o">; 1201defm IMAGE_GATHER4_C_CL_O : MIMG_Gather_WQM <0x00000059, "image_gather4_c_cl_o">; 1202defm IMAGE_GATHER4_C_L_O : MIMG_Gather <0x0000005c, "image_gather4_c_l_o">; 1203defm IMAGE_GATHER4_C_B_O : MIMG_Gather_WQM <0x0000005d, "image_gather4_c_b_o">; 1204defm IMAGE_GATHER4_C_B_CL_O : MIMG_Gather_WQM <0x0000005e, "image_gather4_c_b_cl_o">; 1205defm IMAGE_GATHER4_C_LZ_O : MIMG_Gather <0x0000005f, "image_gather4_c_lz_o">; 1206defm IMAGE_GET_LOD : MIMG_Sampler_WQM <0x00000060, "image_get_lod">; 1207defm IMAGE_SAMPLE_CD : MIMG_Sampler <0x00000068, "image_sample_cd">; 1208defm IMAGE_SAMPLE_CD_CL : MIMG_Sampler <0x00000069, "image_sample_cd_cl">; 1209defm IMAGE_SAMPLE_C_CD : MIMG_Sampler <0x0000006a, "image_sample_c_cd">; 1210defm IMAGE_SAMPLE_C_CD_CL : MIMG_Sampler <0x0000006b, "image_sample_c_cd_cl">; 1211defm IMAGE_SAMPLE_CD_O : MIMG_Sampler <0x0000006c, "image_sample_cd_o">; 1212defm IMAGE_SAMPLE_CD_CL_O : MIMG_Sampler <0x0000006d, "image_sample_cd_cl_o">; 1213defm IMAGE_SAMPLE_C_CD_O : MIMG_Sampler <0x0000006e, "image_sample_c_cd_o">; 1214defm IMAGE_SAMPLE_C_CD_CL_O : MIMG_Sampler <0x0000006f, "image_sample_c_cd_cl_o">; 1215//def IMAGE_RSRC256 : MIMG_NoPattern_RSRC256 <"image_rsrc256", 0x0000007e>; 1216//def IMAGE_SAMPLER : MIMG_NoPattern_ <"image_sampler", 0x0000007f>; 1217 1218//===----------------------------------------------------------------------===// 1219// VOP1 Instructions 1220//===----------------------------------------------------------------------===// 1221 1222let vdst = 0, src0 = 0, VOPAsmPrefer32Bit = 1 in { 1223defm V_NOP : VOP1Inst <vop1<0x0>, "v_nop", VOP_NONE>; 1224} 1225 1226let isMoveImm = 1, isReMaterializable = 1, isAsCheapAsAMove = 1 in { 1227defm V_MOV_B32 : VOP1Inst <vop1<0x1>, "v_mov_b32", VOP_I32_I32>; 1228} // End isMoveImm = 1 1229 1230let Uses = [EXEC] in { 1231 1232// FIXME: Specify SchedRW for READFIRSTLANE_B32 1233 1234def V_READFIRSTLANE_B32 : VOP1 < 1235 0x00000002, 1236 (outs SReg_32:$vdst), 1237 (ins VS_32:$src0), 1238 "v_readfirstlane_b32 $vdst, $src0", 1239 [] 1240>; 1241 1242} 1243 1244let SchedRW = [WriteQuarterRate32] in { 1245 1246defm V_CVT_I32_F64 : VOP1Inst <vop1<0x3>, "v_cvt_i32_f64", 1247 VOP_I32_F64, fp_to_sint 1248>; 1249defm V_CVT_F64_I32 : VOP1Inst <vop1<0x4>, "v_cvt_f64_i32", 1250 VOP_F64_I32, sint_to_fp 1251>; 1252defm V_CVT_F32_I32 : VOP1Inst <vop1<0x5>, "v_cvt_f32_i32", 1253 VOP_F32_I32, sint_to_fp 1254>; 1255defm V_CVT_F32_U32 : VOP1Inst <vop1<0x6>, "v_cvt_f32_u32", 1256 VOP_F32_I32, uint_to_fp 1257>; 1258defm V_CVT_U32_F32 : VOP1Inst <vop1<0x7>, "v_cvt_u32_f32", 1259 VOP_I32_F32, fp_to_uint 1260>; 1261defm V_CVT_I32_F32 : VOP1Inst <vop1<0x8>, "v_cvt_i32_f32", 1262 VOP_I32_F32, fp_to_sint 1263>; 1264defm V_CVT_F16_F32 : VOP1Inst <vop1<0xa>, "v_cvt_f16_f32", 1265 VOP_I32_F32, fp_to_f16 1266>; 1267defm V_CVT_F32_F16 : VOP1Inst <vop1<0xb>, "v_cvt_f32_f16", 1268 VOP_F32_I32, f16_to_fp 1269>; 1270defm V_CVT_RPI_I32_F32 : VOP1Inst <vop1<0xc>, "v_cvt_rpi_i32_f32", 1271 VOP_I32_F32, cvt_rpi_i32_f32>; 1272defm V_CVT_FLR_I32_F32 : VOP1Inst <vop1<0xd>, "v_cvt_flr_i32_f32", 1273 VOP_I32_F32, cvt_flr_i32_f32>; 1274defm V_CVT_OFF_F32_I4 : VOP1Inst <vop1<0x0e>, "v_cvt_off_f32_i4", VOP_F32_I32>; 1275defm V_CVT_F32_F64 : VOP1Inst <vop1<0xf>, "v_cvt_f32_f64", 1276 VOP_F32_F64, fround 1277>; 1278defm V_CVT_F64_F32 : VOP1Inst <vop1<0x10>, "v_cvt_f64_f32", 1279 VOP_F64_F32, fextend 1280>; 1281defm V_CVT_F32_UBYTE0 : VOP1Inst <vop1<0x11>, "v_cvt_f32_ubyte0", 1282 VOP_F32_I32, AMDGPUcvt_f32_ubyte0 1283>; 1284defm V_CVT_F32_UBYTE1 : VOP1Inst <vop1<0x12>, "v_cvt_f32_ubyte1", 1285 VOP_F32_I32, AMDGPUcvt_f32_ubyte1 1286>; 1287defm V_CVT_F32_UBYTE2 : VOP1Inst <vop1<0x13>, "v_cvt_f32_ubyte2", 1288 VOP_F32_I32, AMDGPUcvt_f32_ubyte2 1289>; 1290defm V_CVT_F32_UBYTE3 : VOP1Inst <vop1<0x14>, "v_cvt_f32_ubyte3", 1291 VOP_F32_I32, AMDGPUcvt_f32_ubyte3 1292>; 1293defm V_CVT_U32_F64 : VOP1Inst <vop1<0x15>, "v_cvt_u32_f64", 1294 VOP_I32_F64, fp_to_uint 1295>; 1296defm V_CVT_F64_U32 : VOP1Inst <vop1<0x16>, "v_cvt_f64_u32", 1297 VOP_F64_I32, uint_to_fp 1298>; 1299 1300} // End SchedRW = [WriteQuarterRate32] 1301 1302defm V_FRACT_F32 : VOP1Inst <vop1<0x20, 0x1b>, "v_fract_f32", 1303 VOP_F32_F32, AMDGPUfract 1304>; 1305defm V_TRUNC_F32 : VOP1Inst <vop1<0x21, 0x1c>, "v_trunc_f32", 1306 VOP_F32_F32, ftrunc 1307>; 1308defm V_CEIL_F32 : VOP1Inst <vop1<0x22, 0x1d>, "v_ceil_f32", 1309 VOP_F32_F32, fceil 1310>; 1311defm V_RNDNE_F32 : VOP1Inst <vop1<0x23, 0x1e>, "v_rndne_f32", 1312 VOP_F32_F32, frint 1313>; 1314defm V_FLOOR_F32 : VOP1Inst <vop1<0x24, 0x1f>, "v_floor_f32", 1315 VOP_F32_F32, ffloor 1316>; 1317defm V_EXP_F32 : VOP1Inst <vop1<0x25, 0x20>, "v_exp_f32", 1318 VOP_F32_F32, fexp2 1319>; 1320 1321let SchedRW = [WriteQuarterRate32] in { 1322 1323defm V_LOG_F32 : VOP1Inst <vop1<0x27, 0x21>, "v_log_f32", 1324 VOP_F32_F32, flog2 1325>; 1326defm V_RCP_F32 : VOP1Inst <vop1<0x2a, 0x22>, "v_rcp_f32", 1327 VOP_F32_F32, AMDGPUrcp 1328>; 1329defm V_RCP_IFLAG_F32 : VOP1Inst <vop1<0x2b, 0x23>, "v_rcp_iflag_f32", 1330 VOP_F32_F32 1331>; 1332defm V_RSQ_F32 : VOP1Inst <vop1<0x2e, 0x24>, "v_rsq_f32", 1333 VOP_F32_F32, AMDGPUrsq 1334>; 1335 1336} // End SchedRW = [WriteQuarterRate32] 1337 1338let SchedRW = [WriteDouble] in { 1339 1340defm V_RCP_F64 : VOP1Inst <vop1<0x2f, 0x25>, "v_rcp_f64", 1341 VOP_F64_F64, AMDGPUrcp 1342>; 1343defm V_RSQ_F64 : VOP1Inst <vop1<0x31, 0x26>, "v_rsq_f64", 1344 VOP_F64_F64, AMDGPUrsq 1345>; 1346 1347} // End SchedRW = [WriteDouble]; 1348 1349defm V_SQRT_F32 : VOP1Inst <vop1<0x33, 0x27>, "v_sqrt_f32", 1350 VOP_F32_F32, fsqrt 1351>; 1352 1353let SchedRW = [WriteDouble] in { 1354 1355defm V_SQRT_F64 : VOP1Inst <vop1<0x34, 0x28>, "v_sqrt_f64", 1356 VOP_F64_F64, fsqrt 1357>; 1358 1359} // End SchedRW = [WriteDouble] 1360 1361let SchedRW = [WriteQuarterRate32] in { 1362 1363defm V_SIN_F32 : VOP1Inst <vop1<0x35, 0x29>, "v_sin_f32", 1364 VOP_F32_F32, AMDGPUsin 1365>; 1366defm V_COS_F32 : VOP1Inst <vop1<0x36, 0x2a>, "v_cos_f32", 1367 VOP_F32_F32, AMDGPUcos 1368>; 1369 1370} // End SchedRW = [WriteQuarterRate32] 1371 1372defm V_NOT_B32 : VOP1Inst <vop1<0x37, 0x2b>, "v_not_b32", VOP_I32_I32>; 1373defm V_BFREV_B32 : VOP1Inst <vop1<0x38, 0x2c>, "v_bfrev_b32", VOP_I32_I32>; 1374defm V_FFBH_U32 : VOP1Inst <vop1<0x39, 0x2d>, "v_ffbh_u32", VOP_I32_I32>; 1375defm V_FFBL_B32 : VOP1Inst <vop1<0x3a, 0x2e>, "v_ffbl_b32", VOP_I32_I32>; 1376defm V_FFBH_I32 : VOP1Inst <vop1<0x3b, 0x2f>, "v_ffbh_i32", VOP_I32_I32>; 1377defm V_FREXP_EXP_I32_F64 : VOP1Inst <vop1<0x3c,0x30>, "v_frexp_exp_i32_f64", 1378 VOP_I32_F64, int_amdgcn_frexp_exp 1379>; 1380 1381let SchedRW = [WriteDoubleAdd] in { 1382defm V_FREXP_MANT_F64 : VOP1Inst <vop1<0x3d, 0x31>, "v_frexp_mant_f64", 1383 VOP_F64_F64, int_amdgcn_frexp_mant 1384>; 1385 1386defm V_FRACT_F64 : VOP1Inst <vop1<0x3e, 0x32>, "v_fract_f64", 1387 VOP_F64_F64 1388>; 1389} // End SchedRW = [WriteDoubleAdd] 1390 1391 1392defm V_FREXP_EXP_I32_F32 : VOP1Inst <vop1<0x3f, 0x33>, "v_frexp_exp_i32_f32", 1393 VOP_I32_F32, int_amdgcn_frexp_exp 1394>; 1395defm V_FREXP_MANT_F32 : VOP1Inst <vop1<0x40, 0x34>, "v_frexp_mant_f32", 1396 VOP_F32_F32, int_amdgcn_frexp_mant 1397>; 1398let vdst = 0, src0 = 0, VOPAsmPrefer32Bit = 1 in { 1399defm V_CLREXCP : VOP1Inst <vop1<0x41,0x35>, "v_clrexcp", VOP_NO_EXT<VOP_NONE>>; 1400} 1401 1402let Uses = [M0, EXEC] in { 1403defm V_MOVRELD_B32 : VOP1Inst <vop1<0x42, 0x36>, "v_movreld_b32", VOP_NO_EXT<VOP_I32_I32>>; 1404defm V_MOVRELS_B32 : VOP1Inst <vop1<0x43, 0x37>, "v_movrels_b32", VOP_NO_EXT<VOP_I32_I32>>; 1405defm V_MOVRELSD_B32 : VOP1Inst <vop1<0x44, 0x38>, "v_movrelsd_b32", VOP_NO_EXT<VOP_I32_I32>>; 1406} // End Uses = [M0, EXEC] 1407 1408// These instruction only exist on SI and CI 1409let SubtargetPredicate = isSICI in { 1410 1411let SchedRW = [WriteQuarterRate32] in { 1412 1413defm V_MOV_FED_B32 : VOP1InstSI <vop1<0x9>, "v_mov_fed_b32", VOP_I32_I32>; 1414defm V_LOG_CLAMP_F32 : VOP1InstSI <vop1<0x26>, "v_log_clamp_f32", 1415 VOP_F32_F32, int_amdgcn_log_clamp>; 1416defm V_RCP_CLAMP_F32 : VOP1InstSI <vop1<0x28>, "v_rcp_clamp_f32", VOP_F32_F32>; 1417defm V_RCP_LEGACY_F32 : VOP1InstSI <vop1<0x29>, "v_rcp_legacy_f32", VOP_F32_F32>; 1418defm V_RSQ_CLAMP_F32 : VOP1InstSI <vop1<0x2c>, "v_rsq_clamp_f32", 1419 VOP_F32_F32, AMDGPUrsq_clamp 1420>; 1421defm V_RSQ_LEGACY_F32 : VOP1InstSI <vop1<0x2d>, "v_rsq_legacy_f32", 1422 VOP_F32_F32, AMDGPUrsq_legacy 1423>; 1424 1425} // End SchedRW = [WriteQuarterRate32] 1426 1427let SchedRW = [WriteDouble] in { 1428 1429defm V_RCP_CLAMP_F64 : VOP1InstSI <vop1<0x30>, "v_rcp_clamp_f64", VOP_F64_F64>; 1430defm V_RSQ_CLAMP_F64 : VOP1InstSI <vop1<0x32>, "v_rsq_clamp_f64", 1431 VOP_F64_F64, AMDGPUrsq_clamp 1432>; 1433 1434} // End SchedRW = [WriteDouble] 1435 1436} // End SubtargetPredicate = isSICI 1437 1438//===----------------------------------------------------------------------===// 1439// VINTRP Instructions 1440//===----------------------------------------------------------------------===// 1441 1442let Uses = [M0, EXEC] in { 1443 1444// FIXME: Specify SchedRW for VINTRP insturctions. 1445 1446multiclass V_INTERP_P1_F32_m : VINTRP_m < 1447 0x00000000, 1448 (outs VGPR_32:$dst), 1449 (ins VGPR_32:$i, i32imm:$attr_chan, i32imm:$attr), 1450 "v_interp_p1_f32 $dst, $i, $attr_chan, $attr, [m0]", 1451 [(set f32:$dst, (AMDGPUinterp_p1 i32:$i, (i32 imm:$attr_chan), 1452 (i32 imm:$attr)))] 1453>; 1454 1455let OtherPredicates = [has32BankLDS] in { 1456 1457defm V_INTERP_P1_F32 : V_INTERP_P1_F32_m; 1458 1459} // End OtherPredicates = [has32BankLDS] 1460 1461let OtherPredicates = [has16BankLDS], Constraints = "@earlyclobber $dst", isAsmParserOnly=1 in { 1462 1463defm V_INTERP_P1_F32_16bank : V_INTERP_P1_F32_m; 1464 1465} // End OtherPredicates = [has32BankLDS], Constraints = "@earlyclobber $dst", isAsmParserOnly=1 1466 1467let DisableEncoding = "$src0", Constraints = "$src0 = $dst" in { 1468 1469defm V_INTERP_P2_F32 : VINTRP_m < 1470 0x00000001, 1471 (outs VGPR_32:$dst), 1472 (ins VGPR_32:$src0, VGPR_32:$j, i32imm:$attr_chan, i32imm:$attr), 1473 "v_interp_p2_f32 $dst, [$src0], $j, $attr_chan, $attr, [m0]", 1474 [(set f32:$dst, (AMDGPUinterp_p2 f32:$src0, i32:$j, (i32 imm:$attr_chan), 1475 (i32 imm:$attr)))]>; 1476 1477} // End DisableEncoding = "$src0", Constraints = "$src0 = $dst" 1478 1479defm V_INTERP_MOV_F32 : VINTRP_m < 1480 0x00000002, 1481 (outs VGPR_32:$dst), 1482 (ins InterpSlot:$src0, i32imm:$attr_chan, i32imm:$attr), 1483 "v_interp_mov_f32 $dst, $src0, $attr_chan, $attr, [m0]", 1484 [(set f32:$dst, (AMDGPUinterp_mov (i32 imm:$src0), (i32 imm:$attr_chan), 1485 (i32 imm:$attr)))]>; 1486 1487} // End Uses = [M0, EXEC] 1488 1489//===----------------------------------------------------------------------===// 1490// VOP2 Instructions 1491//===----------------------------------------------------------------------===// 1492 1493multiclass V_CNDMASK <vop2 op, string name> { 1494 defm _e32 : VOP2_m <op, name, VOP_CNDMASK, [], name>; 1495 1496 defm _e64 : VOP3_m < 1497 op, VOP_CNDMASK.Outs, VOP_CNDMASK.Ins64, 1498 name#!cast<string>(VOP_CNDMASK.Asm64), [], name, 3, 0>; 1499} 1500 1501defm V_CNDMASK_B32 : V_CNDMASK<vop2<0x0>, "v_cndmask_b32">; 1502 1503let isCommutable = 1 in { 1504defm V_ADD_F32 : VOP2Inst <vop2<0x3, 0x1>, "v_add_f32", 1505 VOP_F32_F32_F32, fadd 1506>; 1507 1508defm V_SUB_F32 : VOP2Inst <vop2<0x4, 0x2>, "v_sub_f32", VOP_F32_F32_F32, fsub>; 1509defm V_SUBREV_F32 : VOP2Inst <vop2<0x5, 0x3>, "v_subrev_f32", 1510 VOP_F32_F32_F32, null_frag, "v_sub_f32" 1511>; 1512} // End isCommutable = 1 1513 1514let isCommutable = 1 in { 1515 1516defm V_MUL_LEGACY_F32 : VOP2Inst <vop2<0x7, 0x4>, "v_mul_legacy_f32", 1517 VOP_F32_F32_F32 1518>; 1519 1520defm V_MUL_F32 : VOP2Inst <vop2<0x8, 0x5>, "v_mul_f32", 1521 VOP_F32_F32_F32, fmul 1522>; 1523 1524defm V_MUL_I32_I24 : VOP2Inst <vop2<0x9, 0x6>, "v_mul_i32_i24", 1525 VOP_I32_I32_I32, AMDGPUmul_i24 1526>; 1527 1528defm V_MUL_HI_I32_I24 : VOP2Inst <vop2<0xa,0x7>, "v_mul_hi_i32_i24", 1529 VOP_I32_I32_I32 1530>; 1531 1532defm V_MUL_U32_U24 : VOP2Inst <vop2<0xb, 0x8>, "v_mul_u32_u24", 1533 VOP_I32_I32_I32, AMDGPUmul_u24 1534>; 1535 1536defm V_MUL_HI_U32_U24 : VOP2Inst <vop2<0xc,0x9>, "v_mul_hi_u32_u24", 1537 VOP_I32_I32_I32 1538>; 1539 1540defm V_MIN_F32 : VOP2Inst <vop2<0xf, 0xa>, "v_min_f32", VOP_F32_F32_F32, 1541 fminnum>; 1542defm V_MAX_F32 : VOP2Inst <vop2<0x10, 0xb>, "v_max_f32", VOP_F32_F32_F32, 1543 fmaxnum>; 1544defm V_MIN_I32 : VOP2Inst <vop2<0x11, 0xc>, "v_min_i32", VOP_I32_I32_I32>; 1545defm V_MAX_I32 : VOP2Inst <vop2<0x12, 0xd>, "v_max_i32", VOP_I32_I32_I32>; 1546defm V_MIN_U32 : VOP2Inst <vop2<0x13, 0xe>, "v_min_u32", VOP_I32_I32_I32>; 1547defm V_MAX_U32 : VOP2Inst <vop2<0x14, 0xf>, "v_max_u32", VOP_I32_I32_I32>; 1548 1549defm V_LSHRREV_B32 : VOP2Inst < 1550 vop2<0x16, 0x10>, "v_lshrrev_b32", VOP_I32_I32_I32, null_frag, 1551 "v_lshr_b32" 1552>; 1553 1554defm V_ASHRREV_I32 : VOP2Inst < 1555 vop2<0x18, 0x11>, "v_ashrrev_i32", VOP_I32_I32_I32, null_frag, 1556 "v_ashr_i32" 1557>; 1558 1559defm V_LSHLREV_B32 : VOP2Inst < 1560 vop2<0x1a, 0x12>, "v_lshlrev_b32", VOP_I32_I32_I32, null_frag, 1561 "v_lshl_b32" 1562>; 1563 1564defm V_AND_B32 : VOP2Inst <vop2<0x1b, 0x13>, "v_and_b32", VOP_I32_I32_I32>; 1565defm V_OR_B32 : VOP2Inst <vop2<0x1c, 0x14>, "v_or_b32", VOP_I32_I32_I32>; 1566defm V_XOR_B32 : VOP2Inst <vop2<0x1d, 0x15>, "v_xor_b32", VOP_I32_I32_I32>; 1567 1568let Constraints = "$vdst = $src2", DisableEncoding="$src2", 1569 isConvertibleToThreeAddress = 1 in { 1570defm V_MAC_F32 : VOP2Inst <vop2<0x1f, 0x16>, "v_mac_f32", VOP_MAC>; 1571} 1572} // End isCommutable = 1 1573 1574defm V_MADMK_F32 : VOP2MADK <vop2<0x20, 0x17>, "v_madmk_f32", VOP_MADMK>; 1575 1576let isCommutable = 1 in { 1577defm V_MADAK_F32 : VOP2MADK <vop2<0x21, 0x18>, "v_madak_f32", VOP_MADAK>; 1578} // End isCommutable = 1 1579 1580let isCommutable = 1 in { 1581// No patterns so that the scalar instructions are always selected. 1582// The scalar versions will be replaced with vector when needed later. 1583 1584// V_ADD_I32, V_SUB_I32, and V_SUBREV_I32 where renamed to *_U32 in VI, 1585// but the VI instructions behave the same as the SI versions. 1586defm V_ADD_I32 : VOP2bInst <vop2<0x25, 0x19>, "v_add_i32", 1587 VOP2b_I32_I1_I32_I32 1588>; 1589defm V_SUB_I32 : VOP2bInst <vop2<0x26, 0x1a>, "v_sub_i32", VOP2b_I32_I1_I32_I32>; 1590 1591defm V_SUBREV_I32 : VOP2bInst <vop2<0x27, 0x1b>, "v_subrev_i32", 1592 VOP2b_I32_I1_I32_I32, null_frag, "v_sub_i32" 1593>; 1594 1595defm V_ADDC_U32 : VOP2bInst <vop2<0x28, 0x1c>, "v_addc_u32", 1596 VOP2b_I32_I1_I32_I32_I1 1597>; 1598defm V_SUBB_U32 : VOP2bInst <vop2<0x29, 0x1d>, "v_subb_u32", 1599 VOP2b_I32_I1_I32_I32_I1 1600>; 1601defm V_SUBBREV_U32 : VOP2bInst <vop2<0x2a, 0x1e>, "v_subbrev_u32", 1602 VOP2b_I32_I1_I32_I32_I1, null_frag, "v_subb_u32" 1603>; 1604 1605} // End isCommutable = 1 1606 1607defm V_READLANE_B32 : VOP2SI_3VI_m < 1608 vop3 <0x001, 0x289>, 1609 "v_readlane_b32", 1610 (outs SReg_32:$vdst), 1611 (ins VS_32:$src0, SCSrc_32:$src1), 1612 "v_readlane_b32 $vdst, $src0, $src1" 1613>; 1614 1615defm V_WRITELANE_B32 : VOP2SI_3VI_m < 1616 vop3 <0x002, 0x28a>, 1617 "v_writelane_b32", 1618 (outs VGPR_32:$vdst), 1619 (ins SReg_32:$src0, SCSrc_32:$src1), 1620 "v_writelane_b32 $vdst, $src0, $src1" 1621>; 1622 1623// These instructions only exist on SI and CI 1624let SubtargetPredicate = isSICI in { 1625 1626let isCommutable = 1 in { 1627defm V_MAC_LEGACY_F32 : VOP2InstSI <vop2<0x6>, "v_mac_legacy_f32", 1628 VOP_F32_F32_F32 1629>; 1630} // End isCommutable = 1 1631 1632defm V_MIN_LEGACY_F32 : VOP2InstSI <vop2<0xd>, "v_min_legacy_f32", 1633 VOP_F32_F32_F32, AMDGPUfmin_legacy 1634>; 1635defm V_MAX_LEGACY_F32 : VOP2InstSI <vop2<0xe>, "v_max_legacy_f32", 1636 VOP_F32_F32_F32, AMDGPUfmax_legacy 1637>; 1638 1639let isCommutable = 1 in { 1640defm V_LSHR_B32 : VOP2InstSI <vop2<0x15>, "v_lshr_b32", VOP_I32_I32_I32>; 1641defm V_ASHR_I32 : VOP2InstSI <vop2<0x17>, "v_ashr_i32", VOP_I32_I32_I32>; 1642defm V_LSHL_B32 : VOP2InstSI <vop2<0x19>, "v_lshl_b32", VOP_I32_I32_I32>; 1643} // End isCommutable = 1 1644} // End let SubtargetPredicate = SICI 1645 1646defm V_BFM_B32 : VOP2_VI3_Inst <vop23<0x1e, 0x293>, "v_bfm_b32", 1647 VOP_I32_I32_I32 1648>; 1649defm V_BCNT_U32_B32 : VOP2_VI3_Inst <vop23<0x22, 0x28b>, "v_bcnt_u32_b32", 1650 VOP_I32_I32_I32 1651>; 1652defm V_MBCNT_LO_U32_B32 : VOP2_VI3_Inst <vop23<0x23, 0x28c>, "v_mbcnt_lo_u32_b32", 1653 VOP_I32_I32_I32, int_amdgcn_mbcnt_lo 1654>; 1655defm V_MBCNT_HI_U32_B32 : VOP2_VI3_Inst <vop23<0x24, 0x28d>, "v_mbcnt_hi_u32_b32", 1656 VOP_I32_I32_I32, int_amdgcn_mbcnt_hi 1657>; 1658defm V_LDEXP_F32 : VOP2_VI3_Inst <vop23<0x2b, 0x288>, "v_ldexp_f32", 1659 VOP_F32_F32_I32, AMDGPUldexp 1660>; 1661 1662defm V_CVT_PKACCUM_U8_F32 : VOP2_VI3_Inst <vop23<0x2c, 0x1f0>, "v_cvt_pkaccum_u8_f32", 1663 VOP_I32_F32_I32>; // TODO: set "Uses = dst" 1664 1665defm V_CVT_PKNORM_I16_F32 : VOP2_VI3_Inst <vop23<0x2d, 0x294>, "v_cvt_pknorm_i16_f32", 1666 VOP_I32_F32_F32 1667>; 1668defm V_CVT_PKNORM_U16_F32 : VOP2_VI3_Inst <vop23<0x2e, 0x295>, "v_cvt_pknorm_u16_f32", 1669 VOP_I32_F32_F32 1670>; 1671defm V_CVT_PKRTZ_F16_F32 : VOP2_VI3_Inst <vop23<0x2f, 0x296>, "v_cvt_pkrtz_f16_f32", 1672 VOP_I32_F32_F32, int_SI_packf16 1673>; 1674defm V_CVT_PK_U16_U32 : VOP2_VI3_Inst <vop23<0x30, 0x297>, "v_cvt_pk_u16_u32", 1675 VOP_I32_I32_I32 1676>; 1677defm V_CVT_PK_I16_I32 : VOP2_VI3_Inst <vop23<0x31, 0x298>, "v_cvt_pk_i16_i32", 1678 VOP_I32_I32_I32 1679>; 1680 1681//===----------------------------------------------------------------------===// 1682// VOP3 Instructions 1683//===----------------------------------------------------------------------===// 1684 1685let isCommutable = 1 in { 1686defm V_MAD_LEGACY_F32 : VOP3Inst <vop3<0x140, 0x1c0>, "v_mad_legacy_f32", 1687 VOP_F32_F32_F32_F32 1688>; 1689 1690defm V_MAD_F32 : VOP3Inst <vop3<0x141, 0x1c1>, "v_mad_f32", 1691 VOP_F32_F32_F32_F32, fmad 1692>; 1693 1694defm V_MAD_I32_I24 : VOP3Inst <vop3<0x142, 0x1c2>, "v_mad_i32_i24", 1695 VOP_I32_I32_I32_I32, AMDGPUmad_i24 1696>; 1697defm V_MAD_U32_U24 : VOP3Inst <vop3<0x143, 0x1c3>, "v_mad_u32_u24", 1698 VOP_I32_I32_I32_I32, AMDGPUmad_u24 1699>; 1700} // End isCommutable = 1 1701 1702defm V_CUBEID_F32 : VOP3Inst <vop3<0x144, 0x1c4>, "v_cubeid_f32", 1703 VOP_F32_F32_F32_F32, int_amdgcn_cubeid 1704>; 1705defm V_CUBESC_F32 : VOP3Inst <vop3<0x145, 0x1c5>, "v_cubesc_f32", 1706 VOP_F32_F32_F32_F32, int_amdgcn_cubesc 1707>; 1708defm V_CUBETC_F32 : VOP3Inst <vop3<0x146, 0x1c6>, "v_cubetc_f32", 1709 VOP_F32_F32_F32_F32, int_amdgcn_cubetc 1710>; 1711defm V_CUBEMA_F32 : VOP3Inst <vop3<0x147, 0x1c7>, "v_cubema_f32", 1712 VOP_F32_F32_F32_F32, int_amdgcn_cubema 1713>; 1714 1715defm V_BFE_U32 : VOP3Inst <vop3<0x148, 0x1c8>, "v_bfe_u32", 1716 VOP_I32_I32_I32_I32, AMDGPUbfe_u32 1717>; 1718defm V_BFE_I32 : VOP3Inst <vop3<0x149, 0x1c9>, "v_bfe_i32", 1719 VOP_I32_I32_I32_I32, AMDGPUbfe_i32 1720>; 1721 1722defm V_BFI_B32 : VOP3Inst <vop3<0x14a, 0x1ca>, "v_bfi_b32", 1723 VOP_I32_I32_I32_I32, AMDGPUbfi 1724>; 1725 1726let isCommutable = 1 in { 1727defm V_FMA_F32 : VOP3Inst <vop3<0x14b, 0x1cb>, "v_fma_f32", 1728 VOP_F32_F32_F32_F32, fma 1729>; 1730defm V_FMA_F64 : VOP3Inst <vop3<0x14c, 0x1cc>, "v_fma_f64", 1731 VOP_F64_F64_F64_F64, fma 1732>; 1733} // End isCommutable = 1 1734 1735//def V_LERP_U8 : VOP3_U8 <0x0000014d, "v_lerp_u8", []>; 1736defm V_ALIGNBIT_B32 : VOP3Inst <vop3<0x14e, 0x1ce>, "v_alignbit_b32", 1737 VOP_I32_I32_I32_I32 1738>; 1739defm V_ALIGNBYTE_B32 : VOP3Inst <vop3<0x14f, 0x1cf>, "v_alignbyte_b32", 1740 VOP_I32_I32_I32_I32 1741>; 1742 1743defm V_MIN3_F32 : VOP3Inst <vop3<0x151, 0x1d0>, "v_min3_f32", 1744 VOP_F32_F32_F32_F32, AMDGPUfmin3>; 1745 1746defm V_MIN3_I32 : VOP3Inst <vop3<0x152, 0x1d1>, "v_min3_i32", 1747 VOP_I32_I32_I32_I32, AMDGPUsmin3 1748>; 1749defm V_MIN3_U32 : VOP3Inst <vop3<0x153, 0x1d2>, "v_min3_u32", 1750 VOP_I32_I32_I32_I32, AMDGPUumin3 1751>; 1752defm V_MAX3_F32 : VOP3Inst <vop3<0x154, 0x1d3>, "v_max3_f32", 1753 VOP_F32_F32_F32_F32, AMDGPUfmax3 1754>; 1755defm V_MAX3_I32 : VOP3Inst <vop3<0x155, 0x1d4>, "v_max3_i32", 1756 VOP_I32_I32_I32_I32, AMDGPUsmax3 1757>; 1758defm V_MAX3_U32 : VOP3Inst <vop3<0x156, 0x1d5>, "v_max3_u32", 1759 VOP_I32_I32_I32_I32, AMDGPUumax3 1760>; 1761defm V_MED3_F32 : VOP3Inst <vop3<0x157, 0x1d6>, "v_med3_f32", 1762 VOP_F32_F32_F32_F32, AMDGPUfmed3 1763>; 1764defm V_MED3_I32 : VOP3Inst <vop3<0x158, 0x1d7>, "v_med3_i32", 1765 VOP_I32_I32_I32_I32, AMDGPUsmed3 1766>; 1767defm V_MED3_U32 : VOP3Inst <vop3<0x159, 0x1d8>, "v_med3_u32", 1768 VOP_I32_I32_I32_I32, AMDGPUumed3 1769>; 1770 1771//def V_SAD_U8 : VOP3_U8 <0x0000015a, "v_sad_u8", []>; 1772//def V_SAD_HI_U8 : VOP3_U8 <0x0000015b, "v_sad_hi_u8", []>; 1773//def V_SAD_U16 : VOP3_U16 <0x0000015c, "v_sad_u16", []>; 1774defm V_SAD_U32 : VOP3Inst <vop3<0x15d, 0x1dc>, "v_sad_u32", 1775 VOP_I32_I32_I32_I32 1776>; 1777//def V_CVT_PK_U8_F32 : VOP3_U8 <0x0000015e, "v_cvt_pk_u8_f32", []>; 1778defm V_DIV_FIXUP_F32 : VOP3Inst < 1779 vop3<0x15f, 0x1de>, "v_div_fixup_f32", VOP_F32_F32_F32_F32, AMDGPUdiv_fixup 1780>; 1781 1782let SchedRW = [WriteDoubleAdd] in { 1783 1784defm V_DIV_FIXUP_F64 : VOP3Inst < 1785 vop3<0x160, 0x1df>, "v_div_fixup_f64", VOP_F64_F64_F64_F64, AMDGPUdiv_fixup 1786>; 1787 1788} // End SchedRW = [WriteDouble] 1789 1790let SchedRW = [WriteDoubleAdd] in { 1791let isCommutable = 1 in { 1792 1793defm V_ADD_F64 : VOP3Inst <vop3<0x164, 0x280>, "v_add_f64", 1794 VOP_F64_F64_F64, fadd, 1 1795>; 1796defm V_MUL_F64 : VOP3Inst <vop3<0x165, 0x281>, "v_mul_f64", 1797 VOP_F64_F64_F64, fmul, 1 1798>; 1799 1800defm V_MIN_F64 : VOP3Inst <vop3<0x166, 0x282>, "v_min_f64", 1801 VOP_F64_F64_F64, fminnum, 1 1802>; 1803defm V_MAX_F64 : VOP3Inst <vop3<0x167, 0x283>, "v_max_f64", 1804 VOP_F64_F64_F64, fmaxnum, 1 1805>; 1806 1807} // End isCommutable = 1 1808 1809defm V_LDEXP_F64 : VOP3Inst <vop3<0x168, 0x284>, "v_ldexp_f64", 1810 VOP_F64_F64_I32, AMDGPUldexp, 1 1811>; 1812 1813} // End let SchedRW = [WriteDoubleAdd] 1814 1815let isCommutable = 1, SchedRW = [WriteQuarterRate32] in { 1816 1817defm V_MUL_LO_U32 : VOP3Inst <vop3<0x169, 0x285>, "v_mul_lo_u32", 1818 VOP_I32_I32_I32 1819>; 1820defm V_MUL_HI_U32 : VOP3Inst <vop3<0x16a, 0x286>, "v_mul_hi_u32", 1821 VOP_I32_I32_I32, mulhu 1822>; 1823 1824let DisableVIDecoder=1 in { // removed from VI as identical to V_MUL_LO_U32 1825defm V_MUL_LO_I32 : VOP3Inst <vop3<0x16b, 0x285>, "v_mul_lo_i32", 1826 VOP_I32_I32_I32 1827>; 1828} 1829 1830defm V_MUL_HI_I32 : VOP3Inst <vop3<0x16c, 0x287>, "v_mul_hi_i32", 1831 VOP_I32_I32_I32, mulhs 1832>; 1833 1834} // End isCommutable = 1, SchedRW = [WriteQuarterRate32] 1835 1836let SchedRW = [WriteFloatFMA, WriteSALU] in { 1837defm V_DIV_SCALE_F32 : VOP3bInst <vop3<0x16d, 0x1e0>, "v_div_scale_f32", 1838 VOP3b_F32_I1_F32_F32_F32, [], 1 1839>; 1840} 1841 1842let SchedRW = [WriteDouble, WriteSALU] in { 1843// Double precision division pre-scale. 1844defm V_DIV_SCALE_F64 : VOP3bInst <vop3<0x16e, 0x1e1>, "v_div_scale_f64", 1845 VOP3b_F64_I1_F64_F64_F64, [], 1 1846>; 1847} // End SchedRW = [WriteDouble] 1848 1849let isCommutable = 1, Uses = [VCC, EXEC] in { 1850 1851let SchedRW = [WriteFloatFMA] in { 1852// v_div_fmas_f32: 1853// result = src0 * src1 + src2 1854// if (vcc) 1855// result *= 2^32 1856// 1857defm V_DIV_FMAS_F32 : VOP3_VCC_Inst <vop3<0x16f, 0x1e2>, "v_div_fmas_f32", 1858 VOP_F32_F32_F32_F32, AMDGPUdiv_fmas 1859>; 1860} 1861 1862let SchedRW = [WriteDouble] in { 1863// v_div_fmas_f64: 1864// result = src0 * src1 + src2 1865// if (vcc) 1866// result *= 2^64 1867// 1868defm V_DIV_FMAS_F64 : VOP3_VCC_Inst <vop3<0x170, 0x1e3>, "v_div_fmas_f64", 1869 VOP_F64_F64_F64_F64, AMDGPUdiv_fmas 1870>; 1871 1872} // End SchedRW = [WriteDouble] 1873} // End isCommutable = 1, Uses = [VCC, EXEC] 1874 1875//def V_MSAD_U8 : VOP3_U8 <0x00000171, "v_msad_u8", []>; 1876//def V_QSAD_U8 : VOP3_U8 <0x00000172, "v_qsad_u8", []>; 1877//def V_MQSAD_U8 : VOP3_U8 <0x00000173, "v_mqsad_u8", []>; 1878 1879let SchedRW = [WriteDouble] in { 1880defm V_TRIG_PREOP_F64 : VOP3Inst < 1881 vop3<0x174, 0x292>, "v_trig_preop_f64", VOP_F64_F64_I32, AMDGPUtrig_preop 1882>; 1883 1884} // End SchedRW = [WriteDouble] 1885 1886// These instructions only exist on SI and CI 1887let SubtargetPredicate = isSICI in { 1888 1889defm V_LSHL_B64 : VOP3Inst <vop3<0x161>, "v_lshl_b64", VOP_I64_I64_I32>; 1890defm V_LSHR_B64 : VOP3Inst <vop3<0x162>, "v_lshr_b64", VOP_I64_I64_I32>; 1891defm V_ASHR_I64 : VOP3Inst <vop3<0x163>, "v_ashr_i64", VOP_I64_I64_I32>; 1892 1893defm V_MULLIT_F32 : VOP3Inst <vop3<0x150>, "v_mullit_f32", 1894 VOP_F32_F32_F32_F32>; 1895 1896} // End SubtargetPredicate = isSICI 1897 1898let SubtargetPredicate = isVI, DisableSIDecoder = 1 in { 1899 1900defm V_LSHLREV_B64 : VOP3Inst <vop3<0, 0x28f>, "v_lshlrev_b64", 1901 VOP_I64_I32_I64 1902>; 1903defm V_LSHRREV_B64 : VOP3Inst <vop3<0, 0x290>, "v_lshrrev_b64", 1904 VOP_I64_I32_I64 1905>; 1906defm V_ASHRREV_I64 : VOP3Inst <vop3<0, 0x291>, "v_ashrrev_i64", 1907 VOP_I64_I32_I64 1908>; 1909 1910} // End SubtargetPredicate = isVI 1911 1912//===----------------------------------------------------------------------===// 1913// Pseudo Instructions 1914//===----------------------------------------------------------------------===// 1915let isCodeGenOnly = 1, isPseudo = 1 in { 1916 1917// For use in patterns 1918def V_CNDMASK_B64_PSEUDO : VOP3Common <(outs VReg_64:$vdst), 1919 (ins VSrc_64:$src0, VSrc_64:$src1, SSrc_64:$src2), "", [] 1920>; 1921 1922let hasSideEffects = 0, mayLoad = 0, mayStore = 0, Uses = [EXEC] in { 1923// 64-bit vector move instruction. This is mainly used by the SIFoldOperands 1924// pass to enable folding of inline immediates. 1925def V_MOV_B64_PSEUDO : InstSI <(outs VReg_64:$vdst), (ins VSrc_64:$src0), "", []>; 1926} // End let hasSideEffects = 0, mayLoad = 0, mayStore = 0 1927 1928let hasSideEffects = 1, SALU = 1 in { 1929def SGPR_USE : InstSI <(outs),(ins), "", []>; 1930} 1931 1932let usesCustomInserter = 1, SALU = 1 in { 1933def GET_GROUPSTATICSIZE : InstSI <(outs SReg_32:$sdst), (ins), "", 1934 [(set SReg_32:$sdst, (int_amdgcn_groupstaticsize))]>; 1935} // End let usesCustomInserter = 1, SALU = 1 1936 1937// SI pseudo instructions. These are used by the CFG structurizer pass 1938// and should be lowered to ISA instructions prior to codegen. 1939 1940let mayLoad = 1, mayStore = 1, hasSideEffects = 1 in { 1941let Uses = [EXEC], Defs = [EXEC] in { 1942 1943let isBranch = 1, isTerminator = 1 in { 1944 1945def SI_IF: InstSI < 1946 (outs SReg_64:$dst), 1947 (ins SReg_64:$vcc, brtarget:$target), 1948 "", 1949 [(set i64:$dst, (int_amdgcn_if i1:$vcc, bb:$target))] 1950>; 1951 1952def SI_ELSE : InstSI < 1953 (outs SReg_64:$dst), 1954 (ins SReg_64:$src, brtarget:$target), 1955 "", 1956 [(set i64:$dst, (int_amdgcn_else i64:$src, bb:$target))] 1957> { 1958 let Constraints = "$src = $dst"; 1959} 1960 1961def SI_LOOP : InstSI < 1962 (outs), 1963 (ins SReg_64:$saved, brtarget:$target), 1964 "si_loop $saved, $target", 1965 [(int_amdgcn_loop i64:$saved, bb:$target)] 1966>; 1967 1968} // End isBranch = 1, isTerminator = 1 1969 1970def SI_BREAK : InstSI < 1971 (outs SReg_64:$dst), 1972 (ins SReg_64:$src), 1973 "si_else $dst, $src", 1974 [(set i64:$dst, (int_amdgcn_break i64:$src))] 1975>; 1976 1977def SI_IF_BREAK : InstSI < 1978 (outs SReg_64:$dst), 1979 (ins SReg_64:$vcc, SReg_64:$src), 1980 "si_if_break $dst, $vcc, $src", 1981 [(set i64:$dst, (int_amdgcn_if_break i1:$vcc, i64:$src))] 1982>; 1983 1984def SI_ELSE_BREAK : InstSI < 1985 (outs SReg_64:$dst), 1986 (ins SReg_64:$src0, SReg_64:$src1), 1987 "si_else_break $dst, $src0, $src1", 1988 [(set i64:$dst, (int_amdgcn_else_break i64:$src0, i64:$src1))] 1989>; 1990 1991def SI_END_CF : InstSI < 1992 (outs), 1993 (ins SReg_64:$saved), 1994 "si_end_cf $saved", 1995 [(int_amdgcn_end_cf i64:$saved)] 1996>; 1997 1998} // End Uses = [EXEC], Defs = [EXEC] 1999 2000let Uses = [EXEC], Defs = [EXEC,VCC] in { 2001def SI_KILL : InstSI < 2002 (outs), 2003 (ins VSrc_32:$src), 2004 "si_kill $src", 2005 [(int_AMDGPU_kill f32:$src)] 2006>; 2007} // End Uses = [EXEC], Defs = [EXEC,VCC] 2008 2009} // End mayLoad = 1, mayStore = 1, hasSideEffects = 1 2010 2011let SALU = 1 in 2012def SI_PS_LIVE : InstSI < 2013 (outs SReg_64:$dst), 2014 (ins), 2015 "si_ps_live $dst", 2016 [(set i1:$dst, (int_amdgcn_ps_live))] 2017>; 2018 2019// Used as an isel pseudo to directly emit initialization with an 2020// s_mov_b32 rather than a copy of another initialized 2021// register. MachineCSE skips copies, and we don't want to have to 2022// fold operands before it runs. 2023def SI_INIT_M0 : InstSI < 2024 (outs), 2025 (ins SSrc_32:$src), "", []> { 2026 let Defs = [M0]; 2027 let usesCustomInserter = 1; 2028 let isPseudo = 1; 2029 let isCodeGenOnly = 1; 2030 let isAsCheapAsAMove = 1; 2031 let SALU = 1; 2032 let isReMaterializable = 1; 2033} 2034 2035let Uses = [EXEC], Defs = [EXEC, VCC, M0] in { 2036 2037class SI_INDIRECT_SRC<RegisterClass rc> : InstSI < 2038 (outs VGPR_32:$dst, SReg_64:$temp), 2039 (ins rc:$src, VSrc_32:$idx, i32imm:$off), 2040 "si_indirect_src $dst, $temp, $src, $idx, $off", 2041 [] 2042>; 2043 2044class SI_INDIRECT_DST<RegisterClass rc> : InstSI < 2045 (outs rc:$dst, SReg_64:$temp), 2046 (ins unknown:$src, VSrc_32:$idx, i32imm:$off, VGPR_32:$val), 2047 "si_indirect_dst $dst, $temp, $src, $idx, $off, $val", 2048 [] 2049> { 2050 let Constraints = "$src = $dst"; 2051} 2052 2053// TODO: We can support indirect SGPR access. 2054def SI_INDIRECT_SRC_V1 : SI_INDIRECT_SRC<VGPR_32>; 2055def SI_INDIRECT_SRC_V2 : SI_INDIRECT_SRC<VReg_64>; 2056def SI_INDIRECT_SRC_V4 : SI_INDIRECT_SRC<VReg_128>; 2057def SI_INDIRECT_SRC_V8 : SI_INDIRECT_SRC<VReg_256>; 2058def SI_INDIRECT_SRC_V16 : SI_INDIRECT_SRC<VReg_512>; 2059 2060def SI_INDIRECT_DST_V1 : SI_INDIRECT_DST<VGPR_32>; 2061def SI_INDIRECT_DST_V2 : SI_INDIRECT_DST<VReg_64>; 2062def SI_INDIRECT_DST_V4 : SI_INDIRECT_DST<VReg_128>; 2063def SI_INDIRECT_DST_V8 : SI_INDIRECT_DST<VReg_256>; 2064def SI_INDIRECT_DST_V16 : SI_INDIRECT_DST<VReg_512>; 2065 2066} // End Uses = [EXEC], Defs = [EXEC,VCC,M0] 2067 2068multiclass SI_SPILL_SGPR <RegisterClass sgpr_class> { 2069 2070 let UseNamedOperandTable = 1, Uses = [EXEC] in { 2071 def _SAVE : InstSI < 2072 (outs), 2073 (ins sgpr_class:$src, i32imm:$frame_idx), 2074 "", []> { 2075 let mayStore = 1; 2076 let mayLoad = 0; 2077 } 2078 2079 def _RESTORE : InstSI < 2080 (outs sgpr_class:$dst), 2081 (ins i32imm:$frame_idx), 2082 "", []> { 2083 let mayStore = 0; 2084 let mayLoad = 1; 2085 } 2086 } // End UseNamedOperandTable = 1 2087} 2088 2089// It's unclear whether you can use M0 as the output of v_readlane_b32 2090// instructions, so use SGPR_32 register class for spills to prevent 2091// this from happening. 2092defm SI_SPILL_S32 : SI_SPILL_SGPR <SGPR_32>; 2093defm SI_SPILL_S64 : SI_SPILL_SGPR <SReg_64>; 2094defm SI_SPILL_S128 : SI_SPILL_SGPR <SReg_128>; 2095defm SI_SPILL_S256 : SI_SPILL_SGPR <SReg_256>; 2096defm SI_SPILL_S512 : SI_SPILL_SGPR <SReg_512>; 2097 2098multiclass SI_SPILL_VGPR <RegisterClass vgpr_class> { 2099 let UseNamedOperandTable = 1, VGPRSpill = 1, Uses = [EXEC] in { 2100 def _SAVE : InstSI < 2101 (outs), 2102 (ins vgpr_class:$src, i32imm:$frame_idx, SReg_128:$scratch_rsrc, 2103 SReg_32:$scratch_offset, i32imm:$offset), 2104 "", []> { 2105 let mayStore = 1; 2106 let mayLoad = 0; 2107 } 2108 2109 def _RESTORE : InstSI < 2110 (outs vgpr_class:$dst), 2111 (ins i32imm:$frame_idx, SReg_128:$scratch_rsrc, SReg_32:$scratch_offset, 2112 i32imm:$offset), 2113 "", []> { 2114 let mayStore = 0; 2115 let mayLoad = 1; 2116 } 2117 } // End UseNamedOperandTable = 1, VGPRSpill = 1 2118} 2119 2120defm SI_SPILL_V32 : SI_SPILL_VGPR <VGPR_32>; 2121defm SI_SPILL_V64 : SI_SPILL_VGPR <VReg_64>; 2122defm SI_SPILL_V96 : SI_SPILL_VGPR <VReg_96>; 2123defm SI_SPILL_V128 : SI_SPILL_VGPR <VReg_128>; 2124defm SI_SPILL_V256 : SI_SPILL_VGPR <VReg_256>; 2125defm SI_SPILL_V512 : SI_SPILL_VGPR <VReg_512>; 2126 2127let Defs = [SCC] in { 2128 2129def SI_CONSTDATA_PTR : InstSI < 2130 (outs SReg_64:$dst), 2131 (ins const_ga:$ptr), 2132 "", [(set SReg_64:$dst, (i64 (SIconstdata_ptr (tglobaladdr:$ptr))))] 2133> { 2134 let SALU = 1; 2135} 2136 2137} // End Defs = [SCC] 2138 2139} // End isCodeGenOnly, isPseudo 2140 2141} // End SubtargetPredicate = isGCN 2142 2143let Predicates = [isGCN] in { 2144 2145def : Pat < 2146 (int_AMDGPU_kilp), 2147 (SI_KILL 0xbf800000) 2148>; 2149 2150/* int_SI_vs_load_input */ 2151def : Pat< 2152 (SIload_input v4i32:$tlst, imm:$attr_offset, i32:$buf_idx_vgpr), 2153 (BUFFER_LOAD_FORMAT_XYZW_IDXEN $buf_idx_vgpr, $tlst, 0, imm:$attr_offset, 0, 0, 0) 2154>; 2155 2156def : Pat < 2157 (int_SI_export imm:$en, imm:$vm, imm:$done, imm:$tgt, imm:$compr, 2158 f32:$src0, f32:$src1, f32:$src2, f32:$src3), 2159 (EXP imm:$en, imm:$tgt, imm:$compr, imm:$done, imm:$vm, 2160 $src0, $src1, $src2, $src3) 2161>; 2162 2163//===----------------------------------------------------------------------===// 2164// buffer_load/store_format patterns 2165//===----------------------------------------------------------------------===// 2166 2167multiclass MUBUF_LoadIntrinsicPat<SDPatternOperator name, ValueType vt, 2168 string opcode> { 2169 def : Pat< 2170 (vt (name v4i32:$rsrc, 0, 2171 (MUBUFIntrinsicOffset i32:$soffset, i16:$offset), 2172 imm:$glc, imm:$slc)), 2173 (!cast<MUBUF>(opcode # _OFFSET) $rsrc, $soffset, (as_i16imm $offset), 2174 (as_i1imm $glc), (as_i1imm $slc), 0) 2175 >; 2176 2177 def : Pat< 2178 (vt (name v4i32:$rsrc, i32:$vindex, 2179 (MUBUFIntrinsicOffset i32:$soffset, i16:$offset), 2180 imm:$glc, imm:$slc)), 2181 (!cast<MUBUF>(opcode # _IDXEN) $vindex, $rsrc, $soffset, (as_i16imm $offset), 2182 (as_i1imm $glc), (as_i1imm $slc), 0) 2183 >; 2184 2185 def : Pat< 2186 (vt (name v4i32:$rsrc, 0, 2187 (MUBUFIntrinsicVOffset i32:$soffset, i16:$offset, i32:$voffset), 2188 imm:$glc, imm:$slc)), 2189 (!cast<MUBUF>(opcode # _OFFEN) $voffset, $rsrc, $soffset, (as_i16imm $offset), 2190 (as_i1imm $glc), (as_i1imm $slc), 0) 2191 >; 2192 2193 def : Pat< 2194 (vt (name v4i32:$rsrc, i32:$vindex, 2195 (MUBUFIntrinsicVOffset i32:$soffset, i16:$offset, i32:$voffset), 2196 imm:$glc, imm:$slc)), 2197 (!cast<MUBUF>(opcode # _BOTHEN) 2198 (REG_SEQUENCE VReg_64, $vindex, sub0, $voffset, sub1), 2199 $rsrc, $soffset, (as_i16imm $offset), 2200 (as_i1imm $glc), (as_i1imm $slc), 0) 2201 >; 2202} 2203 2204defm : MUBUF_LoadIntrinsicPat<int_amdgcn_buffer_load_format, f32, "BUFFER_LOAD_FORMAT_X">; 2205defm : MUBUF_LoadIntrinsicPat<int_amdgcn_buffer_load_format, v2f32, "BUFFER_LOAD_FORMAT_XY">; 2206defm : MUBUF_LoadIntrinsicPat<int_amdgcn_buffer_load_format, v4f32, "BUFFER_LOAD_FORMAT_XYZW">; 2207defm : MUBUF_LoadIntrinsicPat<int_amdgcn_buffer_load, f32, "BUFFER_LOAD_DWORD">; 2208defm : MUBUF_LoadIntrinsicPat<int_amdgcn_buffer_load, v2f32, "BUFFER_LOAD_DWORDX2">; 2209defm : MUBUF_LoadIntrinsicPat<int_amdgcn_buffer_load, v4f32, "BUFFER_LOAD_DWORDX4">; 2210 2211multiclass MUBUF_StoreIntrinsicPat<SDPatternOperator name, ValueType vt, 2212 string opcode> { 2213 def : Pat< 2214 (name vt:$vdata, v4i32:$rsrc, 0, 2215 (MUBUFIntrinsicOffset i32:$soffset, i16:$offset), 2216 imm:$glc, imm:$slc), 2217 (!cast<MUBUF>(opcode # _OFFSET) $vdata, $rsrc, $soffset, (as_i16imm $offset), 2218 (as_i1imm $glc), (as_i1imm $slc), 0) 2219 >; 2220 2221 def : Pat< 2222 (name vt:$vdata, v4i32:$rsrc, i32:$vindex, 2223 (MUBUFIntrinsicOffset i32:$soffset, i16:$offset), 2224 imm:$glc, imm:$slc), 2225 (!cast<MUBUF>(opcode # _IDXEN) $vdata, $vindex, $rsrc, $soffset, 2226 (as_i16imm $offset), (as_i1imm $glc), 2227 (as_i1imm $slc), 0) 2228 >; 2229 2230 def : Pat< 2231 (name vt:$vdata, v4i32:$rsrc, 0, 2232 (MUBUFIntrinsicVOffset i32:$soffset, i16:$offset, i32:$voffset), 2233 imm:$glc, imm:$slc), 2234 (!cast<MUBUF>(opcode # _OFFEN) $vdata, $voffset, $rsrc, $soffset, 2235 (as_i16imm $offset), (as_i1imm $glc), 2236 (as_i1imm $slc), 0) 2237 >; 2238 2239 def : Pat< 2240 (name vt:$vdata, v4i32:$rsrc, i32:$vindex, 2241 (MUBUFIntrinsicVOffset i32:$soffset, i16:$offset, i32:$voffset), 2242 imm:$glc, imm:$slc), 2243 (!cast<MUBUF>(opcode # _BOTHEN) 2244 $vdata, 2245 (REG_SEQUENCE VReg_64, $vindex, sub0, $voffset, sub1), 2246 $rsrc, $soffset, (as_i16imm $offset), 2247 (as_i1imm $glc), (as_i1imm $slc), 0) 2248 >; 2249} 2250 2251defm : MUBUF_StoreIntrinsicPat<int_amdgcn_buffer_store_format, f32, "BUFFER_STORE_FORMAT_X">; 2252defm : MUBUF_StoreIntrinsicPat<int_amdgcn_buffer_store_format, v2f32, "BUFFER_STORE_FORMAT_XY">; 2253defm : MUBUF_StoreIntrinsicPat<int_amdgcn_buffer_store_format, v4f32, "BUFFER_STORE_FORMAT_XYZW">; 2254defm : MUBUF_StoreIntrinsicPat<int_amdgcn_buffer_store, f32, "BUFFER_STORE_DWORD">; 2255defm : MUBUF_StoreIntrinsicPat<int_amdgcn_buffer_store, v2f32, "BUFFER_STORE_DWORDX2">; 2256defm : MUBUF_StoreIntrinsicPat<int_amdgcn_buffer_store, v4f32, "BUFFER_STORE_DWORDX4">; 2257 2258//===----------------------------------------------------------------------===// 2259// buffer_atomic patterns 2260//===----------------------------------------------------------------------===// 2261multiclass BufferAtomicPatterns<SDPatternOperator name, string opcode> { 2262 def : Pat< 2263 (name i32:$vdata_in, v4i32:$rsrc, 0, 2264 (MUBUFIntrinsicOffset i32:$soffset, i16:$offset), 2265 imm:$slc), 2266 (!cast<MUBUF>(opcode # _RTN_OFFSET) $vdata_in, $rsrc, $soffset, 2267 (as_i16imm $offset), (as_i1imm $slc)) 2268 >; 2269 2270 def : Pat< 2271 (name i32:$vdata_in, v4i32:$rsrc, i32:$vindex, 2272 (MUBUFIntrinsicOffset i32:$soffset, i16:$offset), 2273 imm:$slc), 2274 (!cast<MUBUF>(opcode # _RTN_IDXEN) $vdata_in, $vindex, $rsrc, $soffset, 2275 (as_i16imm $offset), (as_i1imm $slc)) 2276 >; 2277 2278 def : Pat< 2279 (name i32:$vdata_in, v4i32:$rsrc, 0, 2280 (MUBUFIntrinsicVOffset i32:$soffset, i16:$offset, i32:$voffset), 2281 imm:$slc), 2282 (!cast<MUBUF>(opcode # _RTN_OFFEN) $vdata_in, $voffset, $rsrc, $soffset, 2283 (as_i16imm $offset), (as_i1imm $slc)) 2284 >; 2285 2286 def : Pat< 2287 (name i32:$vdata_in, v4i32:$rsrc, i32:$vindex, 2288 (MUBUFIntrinsicVOffset i32:$soffset, i16:$offset, i32:$voffset), 2289 imm:$slc), 2290 (!cast<MUBUF>(opcode # _RTN_BOTHEN) 2291 $vdata_in, 2292 (REG_SEQUENCE VReg_64, $vindex, sub0, $voffset, sub1), 2293 $rsrc, $soffset, (as_i16imm $offset), (as_i1imm $slc)) 2294 >; 2295} 2296 2297defm : BufferAtomicPatterns<int_amdgcn_buffer_atomic_swap, "BUFFER_ATOMIC_SWAP">; 2298defm : BufferAtomicPatterns<int_amdgcn_buffer_atomic_add, "BUFFER_ATOMIC_ADD">; 2299defm : BufferAtomicPatterns<int_amdgcn_buffer_atomic_sub, "BUFFER_ATOMIC_SUB">; 2300defm : BufferAtomicPatterns<int_amdgcn_buffer_atomic_smin, "BUFFER_ATOMIC_SMIN">; 2301defm : BufferAtomicPatterns<int_amdgcn_buffer_atomic_umin, "BUFFER_ATOMIC_UMIN">; 2302defm : BufferAtomicPatterns<int_amdgcn_buffer_atomic_smax, "BUFFER_ATOMIC_SMAX">; 2303defm : BufferAtomicPatterns<int_amdgcn_buffer_atomic_umax, "BUFFER_ATOMIC_UMAX">; 2304defm : BufferAtomicPatterns<int_amdgcn_buffer_atomic_and, "BUFFER_ATOMIC_AND">; 2305defm : BufferAtomicPatterns<int_amdgcn_buffer_atomic_or, "BUFFER_ATOMIC_OR">; 2306defm : BufferAtomicPatterns<int_amdgcn_buffer_atomic_xor, "BUFFER_ATOMIC_XOR">; 2307 2308def : Pat< 2309 (int_amdgcn_buffer_atomic_cmpswap 2310 i32:$data, i32:$cmp, v4i32:$rsrc, 0, 2311 (MUBUFIntrinsicOffset i32:$soffset, i16:$offset), 2312 imm:$slc), 2313 (EXTRACT_SUBREG 2314 (BUFFER_ATOMIC_CMPSWAP_RTN_OFFSET 2315 (REG_SEQUENCE VReg_64, $data, sub0, $cmp, sub1), 2316 $rsrc, $soffset, (as_i16imm $offset), (as_i1imm $slc)), 2317 sub0) 2318>; 2319 2320def : Pat< 2321 (int_amdgcn_buffer_atomic_cmpswap 2322 i32:$data, i32:$cmp, v4i32:$rsrc, i32:$vindex, 2323 (MUBUFIntrinsicOffset i32:$soffset, i16:$offset), 2324 imm:$slc), 2325 (EXTRACT_SUBREG 2326 (BUFFER_ATOMIC_CMPSWAP_RTN_IDXEN 2327 (REG_SEQUENCE VReg_64, $data, sub0, $cmp, sub1), 2328 $vindex, $rsrc, $soffset, (as_i16imm $offset), (as_i1imm $slc)), 2329 sub0) 2330>; 2331 2332def : Pat< 2333 (int_amdgcn_buffer_atomic_cmpswap 2334 i32:$data, i32:$cmp, v4i32:$rsrc, 0, 2335 (MUBUFIntrinsicVOffset i32:$soffset, i16:$offset, i32:$voffset), 2336 imm:$slc), 2337 (EXTRACT_SUBREG 2338 (BUFFER_ATOMIC_CMPSWAP_RTN_OFFEN 2339 (REG_SEQUENCE VReg_64, $data, sub0, $cmp, sub1), 2340 $voffset, $rsrc, $soffset, (as_i16imm $offset), (as_i1imm $slc)), 2341 sub0) 2342>; 2343 2344def : Pat< 2345 (int_amdgcn_buffer_atomic_cmpswap 2346 i32:$data, i32:$cmp, v4i32:$rsrc, i32:$vindex, 2347 (MUBUFIntrinsicVOffset i32:$soffset, i16:$offset, i32:$voffset), 2348 imm:$slc), 2349 (EXTRACT_SUBREG 2350 (BUFFER_ATOMIC_CMPSWAP_RTN_BOTHEN 2351 (REG_SEQUENCE VReg_64, $data, sub0, $cmp, sub1), 2352 (REG_SEQUENCE VReg_64, $vindex, sub0, $voffset, sub1), 2353 $rsrc, $soffset, (as_i16imm $offset), (as_i1imm $slc)), 2354 sub0) 2355>; 2356 2357 2358//===----------------------------------------------------------------------===// 2359// S_GETREG_B32 Intrinsic Pattern. 2360//===----------------------------------------------------------------------===// 2361def : Pat < 2362 (int_amdgcn_s_getreg imm:$simm16), 2363 (S_GETREG_B32 (as_i16imm $simm16)) 2364>; 2365 2366//===----------------------------------------------------------------------===// 2367// SMRD Patterns 2368//===----------------------------------------------------------------------===// 2369 2370multiclass SMRD_Pattern <string Instr, ValueType vt> { 2371 2372 // 1. IMM offset 2373 def : Pat < 2374 (smrd_load (SMRDImm i64:$sbase, i32:$offset)), 2375 (vt (!cast<SMRD>(Instr#"_IMM") $sbase, $offset)) 2376 >; 2377 2378 // 2. SGPR offset 2379 def : Pat < 2380 (smrd_load (SMRDSgpr i64:$sbase, i32:$offset)), 2381 (vt (!cast<SMRD>(Instr#"_SGPR") $sbase, $offset)) 2382 >; 2383 2384 def : Pat < 2385 (smrd_load (SMRDImm32 i64:$sbase, i32:$offset)), 2386 (vt (!cast<SMRD>(Instr#"_IMM_ci") $sbase, $offset)) 2387 > { 2388 let Predicates = [isCIOnly]; 2389 } 2390} 2391 2392// Global and constant loads can be selected to either MUBUF or SMRD 2393// instructions, but SMRD instructions are faster so we want the instruction 2394// selector to prefer those. 2395let AddedComplexity = 100 in { 2396 2397defm : SMRD_Pattern <"S_LOAD_DWORD", i32>; 2398defm : SMRD_Pattern <"S_LOAD_DWORDX2", v2i32>; 2399defm : SMRD_Pattern <"S_LOAD_DWORDX4", v4i32>; 2400defm : SMRD_Pattern <"S_LOAD_DWORDX8", v8i32>; 2401defm : SMRD_Pattern <"S_LOAD_DWORDX16", v16i32>; 2402 2403// 1. Offset as an immediate 2404def : Pat < 2405 (SIload_constant v4i32:$sbase, (SMRDBufferImm i32:$offset)), 2406 (S_BUFFER_LOAD_DWORD_IMM $sbase, $offset) 2407>; 2408 2409// 2. Offset loaded in an 32bit SGPR 2410def : Pat < 2411 (SIload_constant v4i32:$sbase, (SMRDBufferSgpr i32:$offset)), 2412 (S_BUFFER_LOAD_DWORD_SGPR $sbase, $offset) 2413>; 2414 2415let Predicates = [isCI] in { 2416 2417def : Pat < 2418 (SIload_constant v4i32:$sbase, (SMRDBufferImm32 i32:$offset)), 2419 (S_BUFFER_LOAD_DWORD_IMM_ci $sbase, $offset) 2420>; 2421 2422} // End Predicates = [isCI] 2423 2424} // End let AddedComplexity = 10000 2425 2426//===----------------------------------------------------------------------===// 2427// SOP1 Patterns 2428//===----------------------------------------------------------------------===// 2429 2430def : Pat < 2431 (i64 (ctpop i64:$src)), 2432 (i64 (REG_SEQUENCE SReg_64, 2433 (i32 (COPY_TO_REGCLASS (S_BCNT1_I32_B64 $src), SReg_32)), sub0, 2434 (S_MOV_B32 0), sub1)) 2435>; 2436 2437def : Pat < 2438 (i32 (smax i32:$x, (i32 (ineg i32:$x)))), 2439 (S_ABS_I32 $x) 2440>; 2441 2442//===----------------------------------------------------------------------===// 2443// SOP2 Patterns 2444//===----------------------------------------------------------------------===// 2445 2446// V_ADD_I32_e32/S_ADD_U32 produces carry in VCC/SCC. For the vector 2447// case, the sgpr-copies pass will fix this to use the vector version. 2448def : Pat < 2449 (i32 (addc i32:$src0, i32:$src1)), 2450 (S_ADD_U32 $src0, $src1) 2451>; 2452 2453//===----------------------------------------------------------------------===// 2454// SOPP Patterns 2455//===----------------------------------------------------------------------===// 2456 2457def : Pat < 2458 (int_amdgcn_s_waitcnt i32:$simm16), 2459 (S_WAITCNT (as_i16imm $simm16)) 2460>; 2461 2462// FIXME: These should be removed eventually 2463def : Pat < 2464 (int_AMDGPU_barrier_global), 2465 (S_BARRIER) 2466>; 2467 2468def : Pat < 2469 (int_AMDGPU_barrier_local), 2470 (S_BARRIER) 2471>; 2472 2473//===----------------------------------------------------------------------===// 2474// VOP1 Patterns 2475//===----------------------------------------------------------------------===// 2476 2477let Predicates = [UnsafeFPMath] in { 2478 2479//def : RcpPat<V_RCP_F64_e32, f64>; 2480//defm : RsqPat<V_RSQ_F64_e32, f64>; 2481//defm : RsqPat<V_RSQ_F32_e32, f32>; 2482 2483def : RsqPat<V_RSQ_F32_e32, f32>; 2484def : RsqPat<V_RSQ_F64_e32, f64>; 2485} 2486 2487//===----------------------------------------------------------------------===// 2488// VOP2 Patterns 2489//===----------------------------------------------------------------------===// 2490 2491def : Pat < 2492 (i32 (add (i32 (ctpop i32:$popcnt)), i32:$val)), 2493 (V_BCNT_U32_B32_e64 $popcnt, $val) 2494>; 2495 2496def : Pat < 2497 (i32 (select i1:$src0, i32:$src1, i32:$src2)), 2498 (V_CNDMASK_B32_e64 $src2, $src1, $src0) 2499>; 2500 2501// Pattern for V_MAC_F32 2502def : Pat < 2503 (fmad (VOP3NoMods0 f32:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod), 2504 (VOP3NoMods f32:$src1, i32:$src1_modifiers), 2505 (VOP3NoMods f32:$src2, i32:$src2_modifiers)), 2506 (V_MAC_F32_e64 $src0_modifiers, $src0, $src1_modifiers, $src1, 2507 $src2_modifiers, $src2, $clamp, $omod) 2508>; 2509 2510/********** ======================= **********/ 2511/********** Image sampling patterns **********/ 2512/********** ======================= **********/ 2513 2514// Image + sampler 2515class SampleRawPattern<SDPatternOperator name, MIMG opcode, ValueType vt> : Pat < 2516 (name vt:$addr, v8i32:$rsrc, v4i32:$sampler, i32:$dmask, i32:$unorm, 2517 i32:$r128, i32:$da, i32:$glc, i32:$slc, i32:$tfe, i32:$lwe), 2518 (opcode $addr, $rsrc, $sampler, 2519 (as_i32imm $dmask), (as_i1imm $unorm), (as_i1imm $glc), (as_i1imm $slc), 2520 (as_i1imm $r128), (as_i1imm $tfe), (as_i1imm $lwe), (as_i1imm $da)) 2521>; 2522 2523multiclass SampleRawPatterns<SDPatternOperator name, string opcode> { 2524 def : SampleRawPattern<name, !cast<MIMG>(opcode # _V4_V1), i32>; 2525 def : SampleRawPattern<name, !cast<MIMG>(opcode # _V4_V2), v2i32>; 2526 def : SampleRawPattern<name, !cast<MIMG>(opcode # _V4_V4), v4i32>; 2527 def : SampleRawPattern<name, !cast<MIMG>(opcode # _V4_V8), v8i32>; 2528 def : SampleRawPattern<name, !cast<MIMG>(opcode # _V4_V16), v16i32>; 2529} 2530 2531// Image only 2532class ImagePattern<SDPatternOperator name, MIMG opcode, ValueType vt> : Pat < 2533 (name vt:$addr, v8i32:$rsrc, imm:$dmask, imm:$unorm, 2534 imm:$r128, imm:$da, imm:$glc, imm:$slc, imm:$tfe, imm:$lwe), 2535 (opcode $addr, $rsrc, 2536 (as_i32imm $dmask), (as_i1imm $unorm), (as_i1imm $glc), (as_i1imm $slc), 2537 (as_i1imm $r128), (as_i1imm $tfe), (as_i1imm $lwe), (as_i1imm $da)) 2538>; 2539 2540multiclass ImagePatterns<SDPatternOperator name, string opcode> { 2541 def : ImagePattern<name, !cast<MIMG>(opcode # _V4_V1), i32>; 2542 def : ImagePattern<name, !cast<MIMG>(opcode # _V4_V2), v2i32>; 2543 def : ImagePattern<name, !cast<MIMG>(opcode # _V4_V4), v4i32>; 2544} 2545 2546class ImageLoadPattern<SDPatternOperator name, MIMG opcode, ValueType vt> : Pat < 2547 (name vt:$addr, v8i32:$rsrc, imm:$dmask, imm:$r128, imm:$da, imm:$glc, 2548 imm:$slc), 2549 (opcode $addr, $rsrc, 2550 (as_i32imm $dmask), 1, (as_i1imm $glc), (as_i1imm $slc), 2551 (as_i1imm $r128), 0, 0, (as_i1imm $da)) 2552>; 2553 2554multiclass ImageLoadPatterns<SDPatternOperator name, string opcode> { 2555 def : ImageLoadPattern<name, !cast<MIMG>(opcode # _V4_V1), i32>; 2556 def : ImageLoadPattern<name, !cast<MIMG>(opcode # _V4_V2), v2i32>; 2557 def : ImageLoadPattern<name, !cast<MIMG>(opcode # _V4_V4), v4i32>; 2558} 2559 2560class ImageStorePattern<SDPatternOperator name, MIMG opcode, ValueType vt> : Pat < 2561 (name v4f32:$data, vt:$addr, v8i32:$rsrc, i32:$dmask, imm:$r128, imm:$da, 2562 imm:$glc, imm:$slc), 2563 (opcode $data, $addr, $rsrc, 2564 (as_i32imm $dmask), 1, (as_i1imm $glc), (as_i1imm $slc), 2565 (as_i1imm $r128), 0, 0, (as_i1imm $da)) 2566>; 2567 2568multiclass ImageStorePatterns<SDPatternOperator name, string opcode> { 2569 def : ImageStorePattern<name, !cast<MIMG>(opcode # _V4_V1), i32>; 2570 def : ImageStorePattern<name, !cast<MIMG>(opcode # _V4_V2), v2i32>; 2571 def : ImageStorePattern<name, !cast<MIMG>(opcode # _V4_V4), v4i32>; 2572} 2573 2574class ImageAtomicPattern<SDPatternOperator name, MIMG opcode, ValueType vt> : Pat < 2575 (name i32:$vdata, vt:$addr, v8i32:$rsrc, imm:$r128, imm:$da, imm:$slc), 2576 (opcode $vdata, $addr, $rsrc, 1, 1, 1, (as_i1imm $slc), (as_i1imm $r128), 0, 0, (as_i1imm $da)) 2577>; 2578 2579multiclass ImageAtomicPatterns<SDPatternOperator name, string opcode> { 2580 def : ImageAtomicPattern<name, !cast<MIMG>(opcode # _V1), i32>; 2581 def : ImageAtomicPattern<name, !cast<MIMG>(opcode # _V2), v2i32>; 2582 def : ImageAtomicPattern<name, !cast<MIMG>(opcode # _V4), v4i32>; 2583} 2584 2585class ImageAtomicCmpSwapPattern<MIMG opcode, ValueType vt> : Pat < 2586 (int_amdgcn_image_atomic_cmpswap i32:$vsrc, i32:$vcmp, vt:$addr, v8i32:$rsrc, 2587 imm:$r128, imm:$da, imm:$slc), 2588 (EXTRACT_SUBREG 2589 (opcode (REG_SEQUENCE VReg_64, $vsrc, sub0, $vcmp, sub1), 2590 $addr, $rsrc, 3, 1, 1, (as_i1imm $slc), (as_i1imm $r128), 0, 0, (as_i1imm $da)), 2591 sub0) 2592>; 2593 2594// Basic sample 2595defm : SampleRawPatterns<int_SI_image_sample, "IMAGE_SAMPLE">; 2596defm : SampleRawPatterns<int_SI_image_sample_cl, "IMAGE_SAMPLE_CL">; 2597defm : SampleRawPatterns<int_SI_image_sample_d, "IMAGE_SAMPLE_D">; 2598defm : SampleRawPatterns<int_SI_image_sample_d_cl, "IMAGE_SAMPLE_D_CL">; 2599defm : SampleRawPatterns<int_SI_image_sample_l, "IMAGE_SAMPLE_L">; 2600defm : SampleRawPatterns<int_SI_image_sample_b, "IMAGE_SAMPLE_B">; 2601defm : SampleRawPatterns<int_SI_image_sample_b_cl, "IMAGE_SAMPLE_B_CL">; 2602defm : SampleRawPatterns<int_SI_image_sample_lz, "IMAGE_SAMPLE_LZ">; 2603defm : SampleRawPatterns<int_SI_image_sample_cd, "IMAGE_SAMPLE_CD">; 2604defm : SampleRawPatterns<int_SI_image_sample_cd_cl, "IMAGE_SAMPLE_CD_CL">; 2605 2606// Sample with comparison 2607defm : SampleRawPatterns<int_SI_image_sample_c, "IMAGE_SAMPLE_C">; 2608defm : SampleRawPatterns<int_SI_image_sample_c_cl, "IMAGE_SAMPLE_C_CL">; 2609defm : SampleRawPatterns<int_SI_image_sample_c_d, "IMAGE_SAMPLE_C_D">; 2610defm : SampleRawPatterns<int_SI_image_sample_c_d_cl, "IMAGE_SAMPLE_C_D_CL">; 2611defm : SampleRawPatterns<int_SI_image_sample_c_l, "IMAGE_SAMPLE_C_L">; 2612defm : SampleRawPatterns<int_SI_image_sample_c_b, "IMAGE_SAMPLE_C_B">; 2613defm : SampleRawPatterns<int_SI_image_sample_c_b_cl, "IMAGE_SAMPLE_C_B_CL">; 2614defm : SampleRawPatterns<int_SI_image_sample_c_lz, "IMAGE_SAMPLE_C_LZ">; 2615defm : SampleRawPatterns<int_SI_image_sample_c_cd, "IMAGE_SAMPLE_C_CD">; 2616defm : SampleRawPatterns<int_SI_image_sample_c_cd_cl, "IMAGE_SAMPLE_C_CD_CL">; 2617 2618// Sample with offsets 2619defm : SampleRawPatterns<int_SI_image_sample_o, "IMAGE_SAMPLE_O">; 2620defm : SampleRawPatterns<int_SI_image_sample_cl_o, "IMAGE_SAMPLE_CL_O">; 2621defm : SampleRawPatterns<int_SI_image_sample_d_o, "IMAGE_SAMPLE_D_O">; 2622defm : SampleRawPatterns<int_SI_image_sample_d_cl_o, "IMAGE_SAMPLE_D_CL_O">; 2623defm : SampleRawPatterns<int_SI_image_sample_l_o, "IMAGE_SAMPLE_L_O">; 2624defm : SampleRawPatterns<int_SI_image_sample_b_o, "IMAGE_SAMPLE_B_O">; 2625defm : SampleRawPatterns<int_SI_image_sample_b_cl_o, "IMAGE_SAMPLE_B_CL_O">; 2626defm : SampleRawPatterns<int_SI_image_sample_lz_o, "IMAGE_SAMPLE_LZ_O">; 2627defm : SampleRawPatterns<int_SI_image_sample_cd_o, "IMAGE_SAMPLE_CD_O">; 2628defm : SampleRawPatterns<int_SI_image_sample_cd_cl_o, "IMAGE_SAMPLE_CD_CL_O">; 2629 2630// Sample with comparison and offsets 2631defm : SampleRawPatterns<int_SI_image_sample_c_o, "IMAGE_SAMPLE_C_O">; 2632defm : SampleRawPatterns<int_SI_image_sample_c_cl_o, "IMAGE_SAMPLE_C_CL_O">; 2633defm : SampleRawPatterns<int_SI_image_sample_c_d_o, "IMAGE_SAMPLE_C_D_O">; 2634defm : SampleRawPatterns<int_SI_image_sample_c_d_cl_o, "IMAGE_SAMPLE_C_D_CL_O">; 2635defm : SampleRawPatterns<int_SI_image_sample_c_l_o, "IMAGE_SAMPLE_C_L_O">; 2636defm : SampleRawPatterns<int_SI_image_sample_c_b_o, "IMAGE_SAMPLE_C_B_O">; 2637defm : SampleRawPatterns<int_SI_image_sample_c_b_cl_o, "IMAGE_SAMPLE_C_B_CL_O">; 2638defm : SampleRawPatterns<int_SI_image_sample_c_lz_o, "IMAGE_SAMPLE_C_LZ_O">; 2639defm : SampleRawPatterns<int_SI_image_sample_c_cd_o, "IMAGE_SAMPLE_C_CD_O">; 2640defm : SampleRawPatterns<int_SI_image_sample_c_cd_cl_o, "IMAGE_SAMPLE_C_CD_CL_O">; 2641 2642// Gather opcodes 2643// Only the variants which make sense are defined. 2644def : SampleRawPattern<int_SI_gather4, IMAGE_GATHER4_V4_V2, v2i32>; 2645def : SampleRawPattern<int_SI_gather4, IMAGE_GATHER4_V4_V4, v4i32>; 2646def : SampleRawPattern<int_SI_gather4_cl, IMAGE_GATHER4_CL_V4_V4, v4i32>; 2647def : SampleRawPattern<int_SI_gather4_l, IMAGE_GATHER4_L_V4_V4, v4i32>; 2648def : SampleRawPattern<int_SI_gather4_b, IMAGE_GATHER4_B_V4_V4, v4i32>; 2649def : SampleRawPattern<int_SI_gather4_b_cl, IMAGE_GATHER4_B_CL_V4_V4, v4i32>; 2650def : SampleRawPattern<int_SI_gather4_b_cl, IMAGE_GATHER4_B_CL_V4_V8, v8i32>; 2651def : SampleRawPattern<int_SI_gather4_lz, IMAGE_GATHER4_LZ_V4_V2, v2i32>; 2652def : SampleRawPattern<int_SI_gather4_lz, IMAGE_GATHER4_LZ_V4_V4, v4i32>; 2653 2654def : SampleRawPattern<int_SI_gather4_c, IMAGE_GATHER4_C_V4_V4, v4i32>; 2655def : SampleRawPattern<int_SI_gather4_c_cl, IMAGE_GATHER4_C_CL_V4_V4, v4i32>; 2656def : SampleRawPattern<int_SI_gather4_c_cl, IMAGE_GATHER4_C_CL_V4_V8, v8i32>; 2657def : SampleRawPattern<int_SI_gather4_c_l, IMAGE_GATHER4_C_L_V4_V4, v4i32>; 2658def : SampleRawPattern<int_SI_gather4_c_l, IMAGE_GATHER4_C_L_V4_V8, v8i32>; 2659def : SampleRawPattern<int_SI_gather4_c_b, IMAGE_GATHER4_C_B_V4_V4, v4i32>; 2660def : SampleRawPattern<int_SI_gather4_c_b, IMAGE_GATHER4_C_B_V4_V8, v8i32>; 2661def : SampleRawPattern<int_SI_gather4_c_b_cl, IMAGE_GATHER4_C_B_CL_V4_V8, v8i32>; 2662def : SampleRawPattern<int_SI_gather4_c_lz, IMAGE_GATHER4_C_LZ_V4_V4, v4i32>; 2663 2664def : SampleRawPattern<int_SI_gather4_o, IMAGE_GATHER4_O_V4_V4, v4i32>; 2665def : SampleRawPattern<int_SI_gather4_cl_o, IMAGE_GATHER4_CL_O_V4_V4, v4i32>; 2666def : SampleRawPattern<int_SI_gather4_cl_o, IMAGE_GATHER4_CL_O_V4_V8, v8i32>; 2667def : SampleRawPattern<int_SI_gather4_l_o, IMAGE_GATHER4_L_O_V4_V4, v4i32>; 2668def : SampleRawPattern<int_SI_gather4_l_o, IMAGE_GATHER4_L_O_V4_V8, v8i32>; 2669def : SampleRawPattern<int_SI_gather4_b_o, IMAGE_GATHER4_B_O_V4_V4, v4i32>; 2670def : SampleRawPattern<int_SI_gather4_b_o, IMAGE_GATHER4_B_O_V4_V8, v8i32>; 2671def : SampleRawPattern<int_SI_gather4_b_cl_o, IMAGE_GATHER4_B_CL_O_V4_V8, v8i32>; 2672def : SampleRawPattern<int_SI_gather4_lz_o, IMAGE_GATHER4_LZ_O_V4_V4, v4i32>; 2673 2674def : SampleRawPattern<int_SI_gather4_c_o, IMAGE_GATHER4_C_O_V4_V4, v4i32>; 2675def : SampleRawPattern<int_SI_gather4_c_o, IMAGE_GATHER4_C_O_V4_V8, v8i32>; 2676def : SampleRawPattern<int_SI_gather4_c_cl_o, IMAGE_GATHER4_C_CL_O_V4_V8, v8i32>; 2677def : SampleRawPattern<int_SI_gather4_c_l_o, IMAGE_GATHER4_C_L_O_V4_V8, v8i32>; 2678def : SampleRawPattern<int_SI_gather4_c_b_o, IMAGE_GATHER4_C_B_O_V4_V8, v8i32>; 2679def : SampleRawPattern<int_SI_gather4_c_b_cl_o, IMAGE_GATHER4_C_B_CL_O_V4_V8, v8i32>; 2680def : SampleRawPattern<int_SI_gather4_c_lz_o, IMAGE_GATHER4_C_LZ_O_V4_V4, v4i32>; 2681def : SampleRawPattern<int_SI_gather4_c_lz_o, IMAGE_GATHER4_C_LZ_O_V4_V8, v8i32>; 2682 2683def : SampleRawPattern<int_SI_getlod, IMAGE_GET_LOD_V4_V1, i32>; 2684def : SampleRawPattern<int_SI_getlod, IMAGE_GET_LOD_V4_V2, v2i32>; 2685def : SampleRawPattern<int_SI_getlod, IMAGE_GET_LOD_V4_V4, v4i32>; 2686 2687def : ImagePattern<int_SI_getresinfo, IMAGE_GET_RESINFO_V4_V1, i32>; 2688defm : ImagePatterns<int_SI_image_load, "IMAGE_LOAD">; 2689defm : ImagePatterns<int_SI_image_load_mip, "IMAGE_LOAD_MIP">; 2690defm : ImageLoadPatterns<int_amdgcn_image_load, "IMAGE_LOAD">; 2691defm : ImageLoadPatterns<int_amdgcn_image_load_mip, "IMAGE_LOAD_MIP">; 2692defm : ImageStorePatterns<int_amdgcn_image_store, "IMAGE_STORE">; 2693defm : ImageStorePatterns<int_amdgcn_image_store_mip, "IMAGE_STORE_MIP">; 2694defm : ImageAtomicPatterns<int_amdgcn_image_atomic_swap, "IMAGE_ATOMIC_SWAP">; 2695def : ImageAtomicCmpSwapPattern<IMAGE_ATOMIC_CMPSWAP_V1, i32>; 2696def : ImageAtomicCmpSwapPattern<IMAGE_ATOMIC_CMPSWAP_V2, v2i32>; 2697def : ImageAtomicCmpSwapPattern<IMAGE_ATOMIC_CMPSWAP_V4, v4i32>; 2698defm : ImageAtomicPatterns<int_amdgcn_image_atomic_add, "IMAGE_ATOMIC_ADD">; 2699defm : ImageAtomicPatterns<int_amdgcn_image_atomic_sub, "IMAGE_ATOMIC_SUB">; 2700defm : ImageAtomicPatterns<int_amdgcn_image_atomic_smin, "IMAGE_ATOMIC_SMIN">; 2701defm : ImageAtomicPatterns<int_amdgcn_image_atomic_umin, "IMAGE_ATOMIC_UMIN">; 2702defm : ImageAtomicPatterns<int_amdgcn_image_atomic_smax, "IMAGE_ATOMIC_SMAX">; 2703defm : ImageAtomicPatterns<int_amdgcn_image_atomic_umax, "IMAGE_ATOMIC_UMAX">; 2704defm : ImageAtomicPatterns<int_amdgcn_image_atomic_and, "IMAGE_ATOMIC_AND">; 2705defm : ImageAtomicPatterns<int_amdgcn_image_atomic_or, "IMAGE_ATOMIC_OR">; 2706defm : ImageAtomicPatterns<int_amdgcn_image_atomic_xor, "IMAGE_ATOMIC_XOR">; 2707defm : ImageAtomicPatterns<int_amdgcn_image_atomic_inc, "IMAGE_ATOMIC_INC">; 2708defm : ImageAtomicPatterns<int_amdgcn_image_atomic_dec, "IMAGE_ATOMIC_DEC">; 2709 2710/* SIsample for simple 1D texture lookup */ 2711def : Pat < 2712 (SIsample i32:$addr, v8i32:$rsrc, v4i32:$sampler, imm), 2713 (IMAGE_SAMPLE_V4_V1 $addr, $rsrc, $sampler, 0xf, 0, 0, 0, 0, 0, 0, 0) 2714>; 2715 2716class SamplePattern<SDNode name, MIMG opcode, ValueType vt> : Pat < 2717 (name vt:$addr, v8i32:$rsrc, v4i32:$sampler, imm), 2718 (opcode $addr, $rsrc, $sampler, 0xf, 0, 0, 0, 0, 0, 0, 0) 2719>; 2720 2721class SampleRectPattern<SDNode name, MIMG opcode, ValueType vt> : Pat < 2722 (name vt:$addr, v8i32:$rsrc, v4i32:$sampler, TEX_RECT), 2723 (opcode $addr, $rsrc, $sampler, 0xf, 1, 0, 0, 0, 0, 0, 0) 2724>; 2725 2726class SampleArrayPattern<SDNode name, MIMG opcode, ValueType vt> : Pat < 2727 (name vt:$addr, v8i32:$rsrc, v4i32:$sampler, TEX_ARRAY), 2728 (opcode $addr, $rsrc, $sampler, 0xf, 0, 0, 0, 0, 0, 0, 1) 2729>; 2730 2731class SampleShadowPattern<SDNode name, MIMG opcode, 2732 ValueType vt> : Pat < 2733 (name vt:$addr, v8i32:$rsrc, v4i32:$sampler, TEX_SHADOW), 2734 (opcode $addr, $rsrc, $sampler, 0xf, 0, 0, 0, 0, 0, 0, 0) 2735>; 2736 2737class SampleShadowArrayPattern<SDNode name, MIMG opcode, 2738 ValueType vt> : Pat < 2739 (name vt:$addr, v8i32:$rsrc, v4i32:$sampler, TEX_SHADOW_ARRAY), 2740 (opcode $addr, $rsrc, $sampler, 0xf, 0, 0, 0, 0, 0, 0, 1) 2741>; 2742 2743/* SIsample* for texture lookups consuming more address parameters */ 2744multiclass SamplePatterns<MIMG sample, MIMG sample_c, MIMG sample_l, 2745 MIMG sample_c_l, MIMG sample_b, MIMG sample_c_b, 2746MIMG sample_d, MIMG sample_c_d, ValueType addr_type> { 2747 def : SamplePattern <SIsample, sample, addr_type>; 2748 def : SampleRectPattern <SIsample, sample, addr_type>; 2749 def : SampleArrayPattern <SIsample, sample, addr_type>; 2750 def : SampleShadowPattern <SIsample, sample_c, addr_type>; 2751 def : SampleShadowArrayPattern <SIsample, sample_c, addr_type>; 2752 2753 def : SamplePattern <SIsamplel, sample_l, addr_type>; 2754 def : SampleArrayPattern <SIsamplel, sample_l, addr_type>; 2755 def : SampleShadowPattern <SIsamplel, sample_c_l, addr_type>; 2756 def : SampleShadowArrayPattern <SIsamplel, sample_c_l, addr_type>; 2757 2758 def : SamplePattern <SIsampleb, sample_b, addr_type>; 2759 def : SampleArrayPattern <SIsampleb, sample_b, addr_type>; 2760 def : SampleShadowPattern <SIsampleb, sample_c_b, addr_type>; 2761 def : SampleShadowArrayPattern <SIsampleb, sample_c_b, addr_type>; 2762 2763 def : SamplePattern <SIsampled, sample_d, addr_type>; 2764 def : SampleArrayPattern <SIsampled, sample_d, addr_type>; 2765 def : SampleShadowPattern <SIsampled, sample_c_d, addr_type>; 2766 def : SampleShadowArrayPattern <SIsampled, sample_c_d, addr_type>; 2767} 2768 2769defm : SamplePatterns<IMAGE_SAMPLE_V4_V2, IMAGE_SAMPLE_C_V4_V2, 2770 IMAGE_SAMPLE_L_V4_V2, IMAGE_SAMPLE_C_L_V4_V2, 2771 IMAGE_SAMPLE_B_V4_V2, IMAGE_SAMPLE_C_B_V4_V2, 2772 IMAGE_SAMPLE_D_V4_V2, IMAGE_SAMPLE_C_D_V4_V2, 2773 v2i32>; 2774defm : SamplePatterns<IMAGE_SAMPLE_V4_V4, IMAGE_SAMPLE_C_V4_V4, 2775 IMAGE_SAMPLE_L_V4_V4, IMAGE_SAMPLE_C_L_V4_V4, 2776 IMAGE_SAMPLE_B_V4_V4, IMAGE_SAMPLE_C_B_V4_V4, 2777 IMAGE_SAMPLE_D_V4_V4, IMAGE_SAMPLE_C_D_V4_V4, 2778 v4i32>; 2779defm : SamplePatterns<IMAGE_SAMPLE_V4_V8, IMAGE_SAMPLE_C_V4_V8, 2780 IMAGE_SAMPLE_L_V4_V8, IMAGE_SAMPLE_C_L_V4_V8, 2781 IMAGE_SAMPLE_B_V4_V8, IMAGE_SAMPLE_C_B_V4_V8, 2782 IMAGE_SAMPLE_D_V4_V8, IMAGE_SAMPLE_C_D_V4_V8, 2783 v8i32>; 2784defm : SamplePatterns<IMAGE_SAMPLE_V4_V16, IMAGE_SAMPLE_C_V4_V16, 2785 IMAGE_SAMPLE_L_V4_V16, IMAGE_SAMPLE_C_L_V4_V16, 2786 IMAGE_SAMPLE_B_V4_V16, IMAGE_SAMPLE_C_B_V4_V16, 2787 IMAGE_SAMPLE_D_V4_V16, IMAGE_SAMPLE_C_D_V4_V16, 2788 v16i32>; 2789 2790/********** ============================================ **********/ 2791/********** Extraction, Insertion, Building and Casting **********/ 2792/********** ============================================ **********/ 2793 2794foreach Index = 0-2 in { 2795 def Extract_Element_v2i32_#Index : Extract_Element < 2796 i32, v2i32, Index, !cast<SubRegIndex>(sub#Index) 2797 >; 2798 def Insert_Element_v2i32_#Index : Insert_Element < 2799 i32, v2i32, Index, !cast<SubRegIndex>(sub#Index) 2800 >; 2801 2802 def Extract_Element_v2f32_#Index : Extract_Element < 2803 f32, v2f32, Index, !cast<SubRegIndex>(sub#Index) 2804 >; 2805 def Insert_Element_v2f32_#Index : Insert_Element < 2806 f32, v2f32, Index, !cast<SubRegIndex>(sub#Index) 2807 >; 2808} 2809 2810foreach Index = 0-3 in { 2811 def Extract_Element_v4i32_#Index : Extract_Element < 2812 i32, v4i32, Index, !cast<SubRegIndex>(sub#Index) 2813 >; 2814 def Insert_Element_v4i32_#Index : Insert_Element < 2815 i32, v4i32, Index, !cast<SubRegIndex>(sub#Index) 2816 >; 2817 2818 def Extract_Element_v4f32_#Index : Extract_Element < 2819 f32, v4f32, Index, !cast<SubRegIndex>(sub#Index) 2820 >; 2821 def Insert_Element_v4f32_#Index : Insert_Element < 2822 f32, v4f32, Index, !cast<SubRegIndex>(sub#Index) 2823 >; 2824} 2825 2826foreach Index = 0-7 in { 2827 def Extract_Element_v8i32_#Index : Extract_Element < 2828 i32, v8i32, Index, !cast<SubRegIndex>(sub#Index) 2829 >; 2830 def Insert_Element_v8i32_#Index : Insert_Element < 2831 i32, v8i32, Index, !cast<SubRegIndex>(sub#Index) 2832 >; 2833 2834 def Extract_Element_v8f32_#Index : Extract_Element < 2835 f32, v8f32, Index, !cast<SubRegIndex>(sub#Index) 2836 >; 2837 def Insert_Element_v8f32_#Index : Insert_Element < 2838 f32, v8f32, Index, !cast<SubRegIndex>(sub#Index) 2839 >; 2840} 2841 2842foreach Index = 0-15 in { 2843 def Extract_Element_v16i32_#Index : Extract_Element < 2844 i32, v16i32, Index, !cast<SubRegIndex>(sub#Index) 2845 >; 2846 def Insert_Element_v16i32_#Index : Insert_Element < 2847 i32, v16i32, Index, !cast<SubRegIndex>(sub#Index) 2848 >; 2849 2850 def Extract_Element_v16f32_#Index : Extract_Element < 2851 f32, v16f32, Index, !cast<SubRegIndex>(sub#Index) 2852 >; 2853 def Insert_Element_v16f32_#Index : Insert_Element < 2854 f32, v16f32, Index, !cast<SubRegIndex>(sub#Index) 2855 >; 2856} 2857 2858// FIXME: Why do only some of these type combinations for SReg and 2859// VReg? 2860// 32-bit bitcast 2861def : BitConvert <i32, f32, VGPR_32>; 2862def : BitConvert <f32, i32, VGPR_32>; 2863def : BitConvert <i32, f32, SReg_32>; 2864def : BitConvert <f32, i32, SReg_32>; 2865 2866// 64-bit bitcast 2867def : BitConvert <i64, f64, VReg_64>; 2868def : BitConvert <f64, i64, VReg_64>; 2869def : BitConvert <v2i32, v2f32, VReg_64>; 2870def : BitConvert <v2f32, v2i32, VReg_64>; 2871def : BitConvert <i64, v2i32, VReg_64>; 2872def : BitConvert <v2i32, i64, VReg_64>; 2873def : BitConvert <i64, v2f32, VReg_64>; 2874def : BitConvert <v2f32, i64, VReg_64>; 2875def : BitConvert <f64, v2f32, VReg_64>; 2876def : BitConvert <v2f32, f64, VReg_64>; 2877def : BitConvert <f64, v2i32, VReg_64>; 2878def : BitConvert <v2i32, f64, VReg_64>; 2879def : BitConvert <v4i32, v4f32, VReg_128>; 2880def : BitConvert <v4f32, v4i32, VReg_128>; 2881 2882// 128-bit bitcast 2883def : BitConvert <v2i64, v4i32, SReg_128>; 2884def : BitConvert <v4i32, v2i64, SReg_128>; 2885def : BitConvert <v2f64, v4f32, VReg_128>; 2886def : BitConvert <v2f64, v4i32, VReg_128>; 2887def : BitConvert <v4f32, v2f64, VReg_128>; 2888def : BitConvert <v4i32, v2f64, VReg_128>; 2889 2890// 256-bit bitcast 2891def : BitConvert <v8i32, v8f32, SReg_256>; 2892def : BitConvert <v8f32, v8i32, SReg_256>; 2893def : BitConvert <v8i32, v8f32, VReg_256>; 2894def : BitConvert <v8f32, v8i32, VReg_256>; 2895 2896// 512-bit bitcast 2897def : BitConvert <v16i32, v16f32, VReg_512>; 2898def : BitConvert <v16f32, v16i32, VReg_512>; 2899 2900/********** =================== **********/ 2901/********** Src & Dst modifiers **********/ 2902/********** =================== **********/ 2903 2904def : Pat < 2905 (AMDGPUclamp (VOP3Mods0Clamp f32:$src0, i32:$src0_modifiers, i32:$omod), 2906 (f32 FP_ZERO), (f32 FP_ONE)), 2907 (V_ADD_F32_e64 $src0_modifiers, $src0, 0, 0, 1, $omod) 2908>; 2909 2910/********** ================================ **********/ 2911/********** Floating point absolute/negative **********/ 2912/********** ================================ **********/ 2913 2914// Prevent expanding both fneg and fabs. 2915 2916def : Pat < 2917 (fneg (fabs f32:$src)), 2918 (S_OR_B32 $src, 0x80000000) // Set sign bit 2919>; 2920 2921// FIXME: Should use S_OR_B32 2922def : Pat < 2923 (fneg (fabs f64:$src)), 2924 (REG_SEQUENCE VReg_64, 2925 (i32 (EXTRACT_SUBREG f64:$src, sub0)), 2926 sub0, 2927 (V_OR_B32_e32 (EXTRACT_SUBREG f64:$src, sub1), 2928 (V_MOV_B32_e32 0x80000000)), // Set sign bit. 2929 sub1) 2930>; 2931 2932def : Pat < 2933 (fabs f32:$src), 2934 (V_AND_B32_e32 $src, (V_MOV_B32_e32 0x7fffffff)) 2935>; 2936 2937def : Pat < 2938 (fneg f32:$src), 2939 (V_XOR_B32_e32 $src, (V_MOV_B32_e32 0x80000000)) 2940>; 2941 2942def : Pat < 2943 (fabs f64:$src), 2944 (REG_SEQUENCE VReg_64, 2945 (i32 (EXTRACT_SUBREG f64:$src, sub0)), 2946 sub0, 2947 (V_AND_B32_e32 (EXTRACT_SUBREG f64:$src, sub1), 2948 (V_MOV_B32_e32 0x7fffffff)), // Set sign bit. 2949 sub1) 2950>; 2951 2952def : Pat < 2953 (fneg f64:$src), 2954 (REG_SEQUENCE VReg_64, 2955 (i32 (EXTRACT_SUBREG f64:$src, sub0)), 2956 sub0, 2957 (V_XOR_B32_e32 (EXTRACT_SUBREG f64:$src, sub1), 2958 (V_MOV_B32_e32 0x80000000)), 2959 sub1) 2960>; 2961 2962/********** ================== **********/ 2963/********** Immediate Patterns **********/ 2964/********** ================== **********/ 2965 2966def : Pat < 2967 (SGPRImm<(i32 imm)>:$imm), 2968 (S_MOV_B32 imm:$imm) 2969>; 2970 2971def : Pat < 2972 (SGPRImm<(f32 fpimm)>:$imm), 2973 (S_MOV_B32 (f32 (bitcast_fpimm_to_i32 $imm))) 2974>; 2975 2976def : Pat < 2977 (i32 imm:$imm), 2978 (V_MOV_B32_e32 imm:$imm) 2979>; 2980 2981def : Pat < 2982 (f32 fpimm:$imm), 2983 (V_MOV_B32_e32 (f32 (bitcast_fpimm_to_i32 $imm))) 2984>; 2985 2986def : Pat < 2987 (i64 InlineImm<i64>:$imm), 2988 (S_MOV_B64 InlineImm<i64>:$imm) 2989>; 2990 2991// XXX - Should this use a s_cmp to set SCC? 2992 2993// Set to sign-extended 64-bit value (true = -1, false = 0) 2994def : Pat < 2995 (i1 imm:$imm), 2996 (S_MOV_B64 (i64 (as_i64imm $imm))) 2997>; 2998 2999def : Pat < 3000 (f64 InlineFPImm<f64>:$imm), 3001 (S_MOV_B64 (f64 (bitcast_fpimm_to_i64 InlineFPImm<f64>:$imm))) 3002>; 3003 3004/********** ================== **********/ 3005/********** Intrinsic Patterns **********/ 3006/********** ================== **********/ 3007 3008def : POW_Common <V_LOG_F32_e32, V_EXP_F32_e32, V_MUL_LEGACY_F32_e32>; 3009 3010def : Pat < 3011 (int_AMDGPU_cube v4f32:$src), 3012 (REG_SEQUENCE VReg_128, 3013 (V_CUBETC_F32 0 /* src0_modifiers */, (EXTRACT_SUBREG $src, sub0), 3014 0 /* src1_modifiers */, (EXTRACT_SUBREG $src, sub1), 3015 0 /* src2_modifiers */, (EXTRACT_SUBREG $src, sub2), 3016 0 /* clamp */, 0 /* omod */), sub0, 3017 (V_CUBESC_F32 0 /* src0_modifiers */, (EXTRACT_SUBREG $src, sub0), 3018 0 /* src1_modifiers */,(EXTRACT_SUBREG $src, sub1), 3019 0 /* src2_modifiers */,(EXTRACT_SUBREG $src, sub2), 3020 0 /* clamp */, 0 /* omod */), sub1, 3021 (V_CUBEMA_F32 0 /* src1_modifiers */,(EXTRACT_SUBREG $src, sub0), 3022 0 /* src1_modifiers */,(EXTRACT_SUBREG $src, sub1), 3023 0 /* src1_modifiers */,(EXTRACT_SUBREG $src, sub2), 3024 0 /* clamp */, 0 /* omod */), sub2, 3025 (V_CUBEID_F32 0 /* src1_modifiers */,(EXTRACT_SUBREG $src, sub0), 3026 0 /* src1_modifiers */,(EXTRACT_SUBREG $src, sub1), 3027 0 /* src1_modifiers */,(EXTRACT_SUBREG $src, sub2), 3028 0 /* clamp */, 0 /* omod */), sub3) 3029>; 3030 3031def : Pat < 3032 (i32 (sext i1:$src0)), 3033 (V_CNDMASK_B32_e64 (i32 0), (i32 -1), $src0) 3034>; 3035 3036class Ext32Pat <SDNode ext> : Pat < 3037 (i32 (ext i1:$src0)), 3038 (V_CNDMASK_B32_e64 (i32 0), (i32 1), $src0) 3039>; 3040 3041def : Ext32Pat <zext>; 3042def : Ext32Pat <anyext>; 3043 3044// Offset in an 32-bit VGPR 3045def : Pat < 3046 (SIload_constant v4i32:$sbase, i32:$voff), 3047 (BUFFER_LOAD_DWORD_OFFEN $voff, $sbase, 0, 0, 0, 0, 0) 3048>; 3049 3050// The multiplication scales from [0,1] to the unsigned integer range 3051def : Pat < 3052 (AMDGPUurecip i32:$src0), 3053 (V_CVT_U32_F32_e32 3054 (V_MUL_F32_e32 CONST.FP_UINT_MAX_PLUS_1, 3055 (V_RCP_IFLAG_F32_e32 (V_CVT_F32_U32_e32 $src0)))) 3056>; 3057 3058def : Pat < 3059 (int_SI_tid), 3060 (V_MBCNT_HI_U32_B32_e64 0xffffffff, 3061 (V_MBCNT_LO_U32_B32_e64 0xffffffff, 0)) 3062>; 3063 3064//===----------------------------------------------------------------------===// 3065// VOP3 Patterns 3066//===----------------------------------------------------------------------===// 3067 3068def : IMad24Pat<V_MAD_I32_I24>; 3069def : UMad24Pat<V_MAD_U32_U24>; 3070 3071defm : BFIPatterns <V_BFI_B32, S_MOV_B32, SReg_64>; 3072def : ROTRPattern <V_ALIGNBIT_B32>; 3073 3074/********** ======================= **********/ 3075/********** Load/Store Patterns **********/ 3076/********** ======================= **********/ 3077 3078class DSReadPat <DS inst, ValueType vt, PatFrag frag> : Pat < 3079 (vt (frag (DS1Addr1Offset i32:$ptr, i32:$offset))), 3080 (inst $ptr, (as_i16imm $offset), (i1 0)) 3081>; 3082 3083def : DSReadPat <DS_READ_I8, i32, si_sextload_local_i8>; 3084def : DSReadPat <DS_READ_U8, i32, si_az_extload_local_i8>; 3085def : DSReadPat <DS_READ_I16, i32, si_sextload_local_i16>; 3086def : DSReadPat <DS_READ_U16, i32, si_az_extload_local_i16>; 3087def : DSReadPat <DS_READ_B32, i32, si_load_local>; 3088 3089let AddedComplexity = 100 in { 3090 3091def : DSReadPat <DS_READ_B64, v2i32, si_load_local_align8>; 3092 3093} // End AddedComplexity = 100 3094 3095def : Pat < 3096 (v2i32 (si_load_local (DS64Bit4ByteAligned i32:$ptr, i8:$offset0, 3097 i8:$offset1))), 3098 (DS_READ2_B32 $ptr, $offset0, $offset1, (i1 0)) 3099>; 3100 3101class DSWritePat <DS inst, ValueType vt, PatFrag frag> : Pat < 3102 (frag vt:$value, (DS1Addr1Offset i32:$ptr, i32:$offset)), 3103 (inst $ptr, $value, (as_i16imm $offset), (i1 0)) 3104>; 3105 3106def : DSWritePat <DS_WRITE_B8, i32, si_truncstore_local_i8>; 3107def : DSWritePat <DS_WRITE_B16, i32, si_truncstore_local_i16>; 3108def : DSWritePat <DS_WRITE_B32, i32, si_store_local>; 3109 3110let AddedComplexity = 100 in { 3111 3112def : DSWritePat <DS_WRITE_B64, v2i32, si_store_local_align8>; 3113} // End AddedComplexity = 100 3114 3115def : Pat < 3116 (si_store_local v2i32:$value, (DS64Bit4ByteAligned i32:$ptr, i8:$offset0, 3117 i8:$offset1)), 3118 (DS_WRITE2_B32 $ptr, (EXTRACT_SUBREG $value, sub0), 3119 (EXTRACT_SUBREG $value, sub1), $offset0, $offset1, 3120 (i1 0)) 3121>; 3122 3123class DSAtomicRetPat<DS inst, ValueType vt, PatFrag frag> : Pat < 3124 (frag (DS1Addr1Offset i32:$ptr, i32:$offset), vt:$value), 3125 (inst $ptr, $value, (as_i16imm $offset), (i1 0)) 3126>; 3127 3128class DSAtomicCmpXChg <DS inst, ValueType vt, PatFrag frag> : Pat < 3129 (frag (DS1Addr1Offset i32:$ptr, i32:$offset), vt:$cmp, vt:$swap), 3130 (inst $ptr, $cmp, $swap, (as_i16imm $offset), (i1 0)) 3131>; 3132 3133 3134// 32-bit atomics. 3135def : DSAtomicRetPat<DS_WRXCHG_RTN_B32, i32, si_atomic_swap_local>; 3136def : DSAtomicRetPat<DS_ADD_RTN_U32, i32, si_atomic_load_add_local>; 3137def : DSAtomicRetPat<DS_SUB_RTN_U32, i32, si_atomic_load_sub_local>; 3138def : DSAtomicRetPat<DS_INC_RTN_U32, i32, si_atomic_inc_local>; 3139def : DSAtomicRetPat<DS_DEC_RTN_U32, i32, si_atomic_dec_local>; 3140def : DSAtomicRetPat<DS_AND_RTN_B32, i32, si_atomic_load_and_local>; 3141def : DSAtomicRetPat<DS_OR_RTN_B32, i32, si_atomic_load_or_local>; 3142def : DSAtomicRetPat<DS_XOR_RTN_B32, i32, si_atomic_load_xor_local>; 3143def : DSAtomicRetPat<DS_MIN_RTN_I32, i32, si_atomic_load_min_local>; 3144def : DSAtomicRetPat<DS_MAX_RTN_I32, i32, si_atomic_load_max_local>; 3145def : DSAtomicRetPat<DS_MIN_RTN_U32, i32, si_atomic_load_umin_local>; 3146def : DSAtomicRetPat<DS_MAX_RTN_U32, i32, si_atomic_load_umax_local>; 3147def : DSAtomicCmpXChg<DS_CMPST_RTN_B32, i32, si_atomic_cmp_swap_32_local>; 3148 3149// 64-bit atomics. 3150def : DSAtomicRetPat<DS_WRXCHG_RTN_B64, i64, si_atomic_swap_local>; 3151def : DSAtomicRetPat<DS_ADD_RTN_U64, i64, si_atomic_load_add_local>; 3152def : DSAtomicRetPat<DS_SUB_RTN_U64, i64, si_atomic_load_sub_local>; 3153def : DSAtomicRetPat<DS_INC_RTN_U64, i64, si_atomic_inc_local>; 3154def : DSAtomicRetPat<DS_DEC_RTN_U64, i64, si_atomic_dec_local>; 3155def : DSAtomicRetPat<DS_AND_RTN_B64, i64, si_atomic_load_and_local>; 3156def : DSAtomicRetPat<DS_OR_RTN_B64, i64, si_atomic_load_or_local>; 3157def : DSAtomicRetPat<DS_XOR_RTN_B64, i64, si_atomic_load_xor_local>; 3158def : DSAtomicRetPat<DS_MIN_RTN_I64, i64, si_atomic_load_min_local>; 3159def : DSAtomicRetPat<DS_MAX_RTN_I64, i64, si_atomic_load_max_local>; 3160def : DSAtomicRetPat<DS_MIN_RTN_U64, i64, si_atomic_load_umin_local>; 3161def : DSAtomicRetPat<DS_MAX_RTN_U64, i64, si_atomic_load_umax_local>; 3162 3163def : DSAtomicCmpXChg<DS_CMPST_RTN_B64, i64, si_atomic_cmp_swap_64_local>; 3164 3165 3166//===----------------------------------------------------------------------===// 3167// MUBUF Patterns 3168//===----------------------------------------------------------------------===// 3169 3170class MUBUFLoad_Pattern <MUBUF Instr_ADDR64, ValueType vt, 3171 PatFrag constant_ld> : Pat < 3172 (vt (constant_ld (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr, i32:$soffset, 3173 i16:$offset, i1:$glc, i1:$slc, i1:$tfe))), 3174 (Instr_ADDR64 $vaddr, $srsrc, $soffset, $offset, $glc, $slc, $tfe) 3175 >; 3176 3177multiclass MUBUFLoad_Atomic_Pattern <MUBUF Instr_ADDR64, MUBUF Instr_OFFSET, 3178 ValueType vt, PatFrag atomic_ld> { 3179 def : Pat < 3180 (vt (atomic_ld (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr, i32:$soffset, 3181 i16:$offset, i1:$slc))), 3182 (Instr_ADDR64 $vaddr, $srsrc, $soffset, $offset, 1, $slc, 0) 3183 >; 3184 3185 def : Pat < 3186 (vt (atomic_ld (MUBUFOffsetNoGLC v4i32:$rsrc, i32:$soffset, i16:$offset))), 3187 (Instr_OFFSET $rsrc, $soffset, (as_i16imm $offset), 1, 0, 0) 3188 >; 3189} 3190 3191let Predicates = [isSICI] in { 3192def : MUBUFLoad_Pattern <BUFFER_LOAD_SBYTE_ADDR64, i32, sextloadi8_constant>; 3193def : MUBUFLoad_Pattern <BUFFER_LOAD_UBYTE_ADDR64, i32, az_extloadi8_constant>; 3194def : MUBUFLoad_Pattern <BUFFER_LOAD_SSHORT_ADDR64, i32, sextloadi16_constant>; 3195def : MUBUFLoad_Pattern <BUFFER_LOAD_USHORT_ADDR64, i32, az_extloadi16_constant>; 3196 3197defm : MUBUFLoad_Atomic_Pattern <BUFFER_LOAD_DWORD_ADDR64, BUFFER_LOAD_DWORD_OFFSET, i32, mubuf_load_atomic>; 3198defm : MUBUFLoad_Atomic_Pattern <BUFFER_LOAD_DWORDX2_ADDR64, BUFFER_LOAD_DWORDX2_OFFSET, i64, mubuf_load_atomic>; 3199} // End Predicates = [isSICI] 3200 3201class MUBUFScratchLoadPat <MUBUF Instr, ValueType vt, PatFrag ld> : Pat < 3202 (vt (ld (MUBUFScratch v4i32:$srsrc, i32:$vaddr, 3203 i32:$soffset, u16imm:$offset))), 3204 (Instr $vaddr, $srsrc, $soffset, $offset, 0, 0, 0) 3205>; 3206 3207def : MUBUFScratchLoadPat <BUFFER_LOAD_SBYTE_OFFEN, i32, sextloadi8_private>; 3208def : MUBUFScratchLoadPat <BUFFER_LOAD_UBYTE_OFFEN, i32, extloadi8_private>; 3209def : MUBUFScratchLoadPat <BUFFER_LOAD_SSHORT_OFFEN, i32, sextloadi16_private>; 3210def : MUBUFScratchLoadPat <BUFFER_LOAD_USHORT_OFFEN, i32, extloadi16_private>; 3211def : MUBUFScratchLoadPat <BUFFER_LOAD_DWORD_OFFEN, i32, load_private>; 3212def : MUBUFScratchLoadPat <BUFFER_LOAD_DWORDX2_OFFEN, v2i32, load_private>; 3213def : MUBUFScratchLoadPat <BUFFER_LOAD_DWORDX4_OFFEN, v4i32, load_private>; 3214 3215// BUFFER_LOAD_DWORD*, addr64=0 3216multiclass MUBUF_Load_Dword <ValueType vt, MUBUF offset, MUBUF offen, MUBUF idxen, 3217 MUBUF bothen> { 3218 3219 def : Pat < 3220 (vt (int_SI_buffer_load_dword v4i32:$rsrc, (i32 imm), i32:$soffset, 3221 imm:$offset, 0, 0, imm:$glc, imm:$slc, 3222 imm:$tfe)), 3223 (offset $rsrc, $soffset, (as_i16imm $offset), (as_i1imm $glc), 3224 (as_i1imm $slc), (as_i1imm $tfe)) 3225 >; 3226 3227 def : Pat < 3228 (vt (int_SI_buffer_load_dword v4i32:$rsrc, i32:$vaddr, i32:$soffset, 3229 imm:$offset, 1, 0, imm:$glc, imm:$slc, 3230 imm:$tfe)), 3231 (offen $vaddr, $rsrc, $soffset, (as_i16imm $offset), (as_i1imm $glc), (as_i1imm $slc), 3232 (as_i1imm $tfe)) 3233 >; 3234 3235 def : Pat < 3236 (vt (int_SI_buffer_load_dword v4i32:$rsrc, i32:$vaddr, i32:$soffset, 3237 imm:$offset, 0, 1, imm:$glc, imm:$slc, 3238 imm:$tfe)), 3239 (idxen $vaddr, $rsrc, $soffset, (as_i16imm $offset), (as_i1imm $glc), 3240 (as_i1imm $slc), (as_i1imm $tfe)) 3241 >; 3242 3243 def : Pat < 3244 (vt (int_SI_buffer_load_dword v4i32:$rsrc, v2i32:$vaddr, i32:$soffset, 3245 imm:$offset, 1, 1, imm:$glc, imm:$slc, 3246 imm:$tfe)), 3247 (bothen $vaddr, $rsrc, $soffset, (as_i16imm $offset), (as_i1imm $glc), (as_i1imm $slc), 3248 (as_i1imm $tfe)) 3249 >; 3250} 3251 3252defm : MUBUF_Load_Dword <i32, BUFFER_LOAD_DWORD_OFFSET, BUFFER_LOAD_DWORD_OFFEN, 3253 BUFFER_LOAD_DWORD_IDXEN, BUFFER_LOAD_DWORD_BOTHEN>; 3254defm : MUBUF_Load_Dword <v2i32, BUFFER_LOAD_DWORDX2_OFFSET, BUFFER_LOAD_DWORDX2_OFFEN, 3255 BUFFER_LOAD_DWORDX2_IDXEN, BUFFER_LOAD_DWORDX2_BOTHEN>; 3256defm : MUBUF_Load_Dword <v4i32, BUFFER_LOAD_DWORDX4_OFFSET, BUFFER_LOAD_DWORDX4_OFFEN, 3257 BUFFER_LOAD_DWORDX4_IDXEN, BUFFER_LOAD_DWORDX4_BOTHEN>; 3258 3259multiclass MUBUFStore_Atomic_Pattern <MUBUF Instr_ADDR64, MUBUF Instr_OFFSET, 3260 ValueType vt, PatFrag atomic_st> { 3261 // Store follows atomic op convention so address is forst 3262 def : Pat < 3263 (atomic_st (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr, i32:$soffset, 3264 i16:$offset, i1:$slc), vt:$val), 3265 (Instr_ADDR64 $val, $vaddr, $srsrc, $soffset, $offset, 1, $slc, 0) 3266 >; 3267 3268 def : Pat < 3269 (atomic_st (MUBUFOffsetNoGLC v4i32:$rsrc, i32:$soffset, i16:$offset), vt:$val), 3270 (Instr_OFFSET $val, $rsrc, $soffset, (as_i16imm $offset), 1, 0, 0) 3271 >; 3272} 3273let Predicates = [isSICI] in { 3274defm : MUBUFStore_Atomic_Pattern <BUFFER_STORE_DWORD_ADDR64, BUFFER_STORE_DWORD_OFFSET, i32, global_store_atomic>; 3275defm : MUBUFStore_Atomic_Pattern <BUFFER_STORE_DWORDX2_ADDR64, BUFFER_STORE_DWORDX2_OFFSET, i64, global_store_atomic>; 3276} // End Predicates = [isSICI] 3277 3278class MUBUFScratchStorePat <MUBUF Instr, ValueType vt, PatFrag st> : Pat < 3279 (st vt:$value, (MUBUFScratch v4i32:$srsrc, i32:$vaddr, i32:$soffset, 3280 u16imm:$offset)), 3281 (Instr $value, $vaddr, $srsrc, $soffset, $offset, 0, 0, 0) 3282>; 3283 3284def : MUBUFScratchStorePat <BUFFER_STORE_BYTE_OFFEN, i32, truncstorei8_private>; 3285def : MUBUFScratchStorePat <BUFFER_STORE_SHORT_OFFEN, i32, truncstorei16_private>; 3286def : MUBUFScratchStorePat <BUFFER_STORE_DWORD_OFFEN, i32, store_private>; 3287def : MUBUFScratchStorePat <BUFFER_STORE_DWORDX2_OFFEN, v2i32, store_private>; 3288def : MUBUFScratchStorePat <BUFFER_STORE_DWORDX4_OFFEN, v4i32, store_private>; 3289 3290 3291multiclass MUBUFCmpSwapPat <Instruction inst_addr64, Instruction inst_offset, 3292 SDPatternOperator node, ValueType data_vt, 3293 ValueType node_vt> { 3294 3295let Predicates = [isSI] in { 3296 def : Pat < 3297 (node_vt (node (MUBUFAddr64Atomic v4i32:$srsrc, i64:$vaddr, i32:$soffset, 3298 i16:$offset, i1:$slc), data_vt:$vdata_in)), 3299 (EXTRACT_SUBREG 3300 (inst_addr64 $vdata_in, $vaddr, $srsrc, $soffset, $offset, $slc), sub0) 3301 >; 3302 3303} 3304 3305 def : Pat < 3306 (node_vt (node (MUBUFOffsetAtomic v4i32:$srsrc, i32:$soffset, i16:$offset, 3307 i1:$slc), data_vt:$vdata_in)), 3308 (EXTRACT_SUBREG 3309 (inst_offset $vdata_in, $srsrc, $soffset, $offset, $slc), sub0) 3310 >; 3311} 3312 3313defm : MUBUFCmpSwapPat <BUFFER_ATOMIC_CMPSWAP_RTN_ADDR64, 3314 BUFFER_ATOMIC_CMPSWAP_RTN_OFFSET, 3315 atomic_cmp_swap_global, v2i32, i32>; 3316 3317defm : MUBUFCmpSwapPat <BUFFER_ATOMIC_CMPSWAP_X2_RTN_ADDR64, 3318 BUFFER_ATOMIC_CMPSWAP_X2_RTN_OFFSET, 3319 atomic_cmp_swap_global, v2i64, i64>; 3320 3321//===----------------------------------------------------------------------===// 3322// MTBUF Patterns 3323//===----------------------------------------------------------------------===// 3324 3325// TBUFFER_STORE_FORMAT_*, addr64=0 3326class MTBUF_StoreResource <ValueType vt, int num_channels, MTBUF opcode> : Pat< 3327 (SItbuffer_store v4i32:$rsrc, vt:$vdata, num_channels, i32:$vaddr, 3328 i32:$soffset, imm:$inst_offset, imm:$dfmt, 3329 imm:$nfmt, imm:$offen, imm:$idxen, 3330 imm:$glc, imm:$slc, imm:$tfe), 3331 (opcode 3332 $vdata, (as_i16imm $inst_offset), (as_i1imm $offen), (as_i1imm $idxen), 3333 (as_i1imm $glc), 0, (as_i8imm $dfmt), (as_i8imm $nfmt), $vaddr, $rsrc, 3334 (as_i1imm $slc), (as_i1imm $tfe), $soffset) 3335>; 3336 3337def : MTBUF_StoreResource <i32, 1, TBUFFER_STORE_FORMAT_X>; 3338def : MTBUF_StoreResource <v2i32, 2, TBUFFER_STORE_FORMAT_XY>; 3339def : MTBUF_StoreResource <v4i32, 3, TBUFFER_STORE_FORMAT_XYZ>; 3340def : MTBUF_StoreResource <v4i32, 4, TBUFFER_STORE_FORMAT_XYZW>; 3341 3342/********** ====================== **********/ 3343/********** Indirect adressing **********/ 3344/********** ====================== **********/ 3345 3346multiclass SI_INDIRECT_Pattern <ValueType vt, ValueType eltvt, string VecSize> { 3347 3348 // 1. Extract with offset 3349 def : Pat< 3350 (eltvt (extractelt vt:$vec, (add i32:$idx, imm:$off))), 3351 (!cast<Instruction>("SI_INDIRECT_SRC_"#VecSize) $vec, $idx, imm:$off) 3352 >; 3353 3354 // 2. Extract without offset 3355 def : Pat< 3356 (eltvt (extractelt vt:$vec, i32:$idx)), 3357 (!cast<Instruction>("SI_INDIRECT_SRC_"#VecSize) $vec, $idx, 0) 3358 >; 3359 3360 // 3. Insert with offset 3361 def : Pat< 3362 (insertelt vt:$vec, eltvt:$val, (add i32:$idx, imm:$off)), 3363 (!cast<Instruction>("SI_INDIRECT_DST_"#VecSize) $vec, $idx, imm:$off, $val) 3364 >; 3365 3366 // 4. Insert without offset 3367 def : Pat< 3368 (insertelt vt:$vec, eltvt:$val, i32:$idx), 3369 (!cast<Instruction>("SI_INDIRECT_DST_"#VecSize) $vec, $idx, 0, $val) 3370 >; 3371} 3372 3373defm : SI_INDIRECT_Pattern <v2f32, f32, "V2">; 3374defm : SI_INDIRECT_Pattern <v4f32, f32, "V4">; 3375defm : SI_INDIRECT_Pattern <v8f32, f32, "V8">; 3376defm : SI_INDIRECT_Pattern <v16f32, f32, "V16">; 3377 3378defm : SI_INDIRECT_Pattern <v2i32, i32, "V2">; 3379defm : SI_INDIRECT_Pattern <v4i32, i32, "V4">; 3380defm : SI_INDIRECT_Pattern <v8i32, i32, "V8">; 3381defm : SI_INDIRECT_Pattern <v16i32, i32, "V16">; 3382 3383//===----------------------------------------------------------------------===// 3384// Conversion Patterns 3385//===----------------------------------------------------------------------===// 3386 3387def : Pat<(i32 (sext_inreg i32:$src, i1)), 3388 (S_BFE_I32 i32:$src, 65536)>; // 0 | 1 << 16 3389 3390// Handle sext_inreg in i64 3391def : Pat < 3392 (i64 (sext_inreg i64:$src, i1)), 3393 (S_BFE_I64 i64:$src, 0x10000) // 0 | 1 << 16 3394>; 3395 3396def : Pat < 3397 (i64 (sext_inreg i64:$src, i8)), 3398 (S_BFE_I64 i64:$src, 0x80000) // 0 | 8 << 16 3399>; 3400 3401def : Pat < 3402 (i64 (sext_inreg i64:$src, i16)), 3403 (S_BFE_I64 i64:$src, 0x100000) // 0 | 16 << 16 3404>; 3405 3406def : Pat < 3407 (i64 (sext_inreg i64:$src, i32)), 3408 (S_BFE_I64 i64:$src, 0x200000) // 0 | 32 << 16 3409>; 3410 3411class ZExt_i64_i32_Pat <SDNode ext> : Pat < 3412 (i64 (ext i32:$src)), 3413 (REG_SEQUENCE SReg_64, $src, sub0, (S_MOV_B32 0), sub1) 3414>; 3415 3416class ZExt_i64_i1_Pat <SDNode ext> : Pat < 3417 (i64 (ext i1:$src)), 3418 (REG_SEQUENCE VReg_64, 3419 (V_CNDMASK_B32_e64 (i32 0), (i32 1), $src), sub0, 3420 (S_MOV_B32 0), sub1) 3421>; 3422 3423 3424def : ZExt_i64_i32_Pat<zext>; 3425def : ZExt_i64_i32_Pat<anyext>; 3426def : ZExt_i64_i1_Pat<zext>; 3427def : ZExt_i64_i1_Pat<anyext>; 3428 3429// FIXME: We need to use COPY_TO_REGCLASS to work-around the fact that 3430// REG_SEQUENCE patterns don't support instructions with multiple outputs. 3431def : Pat < 3432 (i64 (sext i32:$src)), 3433 (REG_SEQUENCE SReg_64, $src, sub0, 3434 (i32 (COPY_TO_REGCLASS (S_ASHR_I32 $src, 31), SGPR_32)), sub1) 3435>; 3436 3437def : Pat < 3438 (i64 (sext i1:$src)), 3439 (REG_SEQUENCE VReg_64, 3440 (V_CNDMASK_B32_e64 0, -1, $src), sub0, 3441 (V_CNDMASK_B32_e64 0, -1, $src), sub1) 3442>; 3443 3444// If we need to perform a logical operation on i1 values, we need to 3445// use vector comparisons since there is only one SCC register. Vector 3446// comparisions still write to a pair of SGPRs, so treat these as 3447// 64-bit comparisons. When legalizing SGPR copies, instructions 3448// resulting in the copies from SCC to these instructions will be 3449// moved to the VALU. 3450def : Pat < 3451 (i1 (and i1:$src0, i1:$src1)), 3452 (S_AND_B64 $src0, $src1) 3453>; 3454 3455def : Pat < 3456 (i1 (or i1:$src0, i1:$src1)), 3457 (S_OR_B64 $src0, $src1) 3458>; 3459 3460def : Pat < 3461 (i1 (xor i1:$src0, i1:$src1)), 3462 (S_XOR_B64 $src0, $src1) 3463>; 3464 3465def : Pat < 3466 (f32 (sint_to_fp i1:$src)), 3467 (V_CNDMASK_B32_e64 (i32 0), CONST.FP32_NEG_ONE, $src) 3468>; 3469 3470def : Pat < 3471 (f32 (uint_to_fp i1:$src)), 3472 (V_CNDMASK_B32_e64 (i32 0), CONST.FP32_ONE, $src) 3473>; 3474 3475def : Pat < 3476 (f64 (sint_to_fp i1:$src)), 3477 (V_CVT_F64_I32_e32 (V_CNDMASK_B32_e64 (i32 0), (i32 -1), $src)) 3478>; 3479 3480def : Pat < 3481 (f64 (uint_to_fp i1:$src)), 3482 (V_CVT_F64_U32_e32 (V_CNDMASK_B32_e64 (i32 0), (i32 1), $src)) 3483>; 3484 3485//===----------------------------------------------------------------------===// 3486// Miscellaneous Patterns 3487//===----------------------------------------------------------------------===// 3488 3489def : Pat < 3490 (i32 (trunc i64:$a)), 3491 (EXTRACT_SUBREG $a, sub0) 3492>; 3493 3494def : Pat < 3495 (i1 (trunc i32:$a)), 3496 (V_CMP_EQ_I32_e64 (S_AND_B32 (i32 1), $a), 1) 3497>; 3498 3499def : Pat < 3500 (i1 (trunc i64:$a)), 3501 (V_CMP_EQ_I32_e64 (S_AND_B32 (i32 1), 3502 (EXTRACT_SUBREG $a, sub0)), 1) 3503>; 3504 3505def : Pat < 3506 (i32 (bswap i32:$a)), 3507 (V_BFI_B32 (S_MOV_B32 0x00ff00ff), 3508 (V_ALIGNBIT_B32 $a, $a, 24), 3509 (V_ALIGNBIT_B32 $a, $a, 8)) 3510>; 3511 3512def : Pat < 3513 (f32 (select i1:$src2, f32:$src1, f32:$src0)), 3514 (V_CNDMASK_B32_e64 $src0, $src1, $src2) 3515>; 3516 3517multiclass BFMPatterns <ValueType vt, InstSI BFM, InstSI MOV> { 3518 def : Pat < 3519 (vt (shl (vt (add (vt (shl 1, vt:$a)), -1)), vt:$b)), 3520 (BFM $a, $b) 3521 >; 3522 3523 def : Pat < 3524 (vt (add (vt (shl 1, vt:$a)), -1)), 3525 (BFM $a, (MOV 0)) 3526 >; 3527} 3528 3529defm : BFMPatterns <i32, S_BFM_B32, S_MOV_B32>; 3530// FIXME: defm : BFMPatterns <i64, S_BFM_B64, S_MOV_B64>; 3531 3532def : BFEPattern <V_BFE_U32, S_MOV_B32>; 3533 3534let Predicates = [isSICI] in { 3535def : Pat < 3536 (i64 (readcyclecounter)), 3537 (S_MEMTIME) 3538>; 3539} 3540 3541def : Pat< 3542 (fcanonicalize f32:$src), 3543 (V_MUL_F32_e64 0, CONST.FP32_ONE, 0, $src, 0, 0) 3544>; 3545 3546def : Pat< 3547 (fcanonicalize f64:$src), 3548 (V_MUL_F64 0, CONST.FP64_ONE, 0, $src, 0, 0) 3549>; 3550 3551//===----------------------------------------------------------------------===// 3552// Fract Patterns 3553//===----------------------------------------------------------------------===// 3554 3555let Predicates = [isSI] in { 3556 3557// V_FRACT is buggy on SI, so the F32 version is never used and (x-floor(x)) is 3558// used instead. However, SI doesn't have V_FLOOR_F64, so the most efficient 3559// way to implement it is using V_FRACT_F64. 3560// The workaround for the V_FRACT bug is: 3561// fract(x) = isnan(x) ? x : min(V_FRACT(x), 0.99999999999999999) 3562 3563// Convert (x + (-floor(x)) to fract(x) 3564def : Pat < 3565 (f64 (fadd (f64 (VOP3Mods f64:$x, i32:$mods)), 3566 (f64 (fneg (f64 (ffloor (f64 (VOP3Mods f64:$x, i32:$mods)))))))), 3567 (V_CNDMASK_B64_PSEUDO 3568 (V_MIN_F64 3569 SRCMODS.NONE, 3570 (V_FRACT_F64_e64 $mods, $x, DSTCLAMP.NONE, DSTOMOD.NONE), 3571 SRCMODS.NONE, 3572 (V_MOV_B64_PSEUDO 0x3fefffffffffffff), 3573 DSTCLAMP.NONE, DSTOMOD.NONE), 3574 $x, 3575 (V_CMP_CLASS_F64_e64 SRCMODS.NONE, $x, 3/*NaN*/)) 3576>; 3577 3578// Convert floor(x) to (x - fract(x)) 3579def : Pat < 3580 (f64 (ffloor (f64 (VOP3Mods f64:$x, i32:$mods)))), 3581 (V_ADD_F64 3582 $mods, 3583 $x, 3584 SRCMODS.NEG, 3585 (V_CNDMASK_B64_PSEUDO 3586 (V_MIN_F64 3587 SRCMODS.NONE, 3588 (V_FRACT_F64_e64 $mods, $x, DSTCLAMP.NONE, DSTOMOD.NONE), 3589 SRCMODS.NONE, 3590 (V_MOV_B64_PSEUDO 0x3fefffffffffffff), 3591 DSTCLAMP.NONE, DSTOMOD.NONE), 3592 $x, 3593 (V_CMP_CLASS_F64_e64 SRCMODS.NONE, $x, 3/*NaN*/)), 3594 DSTCLAMP.NONE, DSTOMOD.NONE) 3595>; 3596 3597} // End Predicates = [isSI] 3598 3599//============================================================================// 3600// Miscellaneous Optimization Patterns 3601//============================================================================// 3602 3603def : SHA256MaPattern <V_BFI_B32, V_XOR_B32_e64>; 3604 3605def : IntMed3Pat<V_MED3_I32, smax, smax_oneuse, smin_oneuse>; 3606def : IntMed3Pat<V_MED3_U32, umax, umax_oneuse, umin_oneuse>; 3607 3608//============================================================================// 3609// Assembler aliases 3610//============================================================================// 3611 3612def : MnemonicAlias<"v_add_u32", "v_add_i32">; 3613def : MnemonicAlias<"v_sub_u32", "v_sub_i32">; 3614def : MnemonicAlias<"v_subrev_u32", "v_subrev_i32">; 3615 3616} // End isGCN predicate 3617