1//===-- SIInstructions.td - SI Instruction Defintions ---------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// This file was originally auto-generated from a GPU register header file and 10// all the instruction definitions were originally commented out. Instructions 11// that are not yet supported remain commented out. 12//===----------------------------------------------------------------------===// 13 14class InterpSlots { 15int P0 = 2; 16int P10 = 0; 17int P20 = 1; 18} 19def INTERP : InterpSlots; 20 21def InterpSlot : Operand<i32> { 22 let PrintMethod = "printInterpSlot"; 23} 24 25def SendMsgImm : Operand<i32> { 26 let PrintMethod = "printSendMsg"; 27} 28 29def isGCN : Predicate<"Subtarget->getGeneration() " 30 ">= AMDGPUSubtarget::SOUTHERN_ISLANDS">, 31 AssemblerPredicate<"FeatureGCN">; 32def isSI : Predicate<"Subtarget->getGeneration() " 33 "== AMDGPUSubtarget::SOUTHERN_ISLANDS">, 34 AssemblerPredicate<"FeatureSouthernIslands">; 35 36 37def has16BankLDS : Predicate<"Subtarget->getLDSBankCount() == 16">; 38def has32BankLDS : Predicate<"Subtarget->getLDSBankCount() == 32">; 39 40def SWaitMatchClass : AsmOperandClass { 41 let Name = "SWaitCnt"; 42 let RenderMethod = "addImmOperands"; 43 let ParserMethod = "parseSWaitCntOps"; 44} 45 46def WAIT_FLAG : InstFlag<"printWaitFlag"> { 47 let ParserMatchClass = SWaitMatchClass; 48} 49 50let SubtargetPredicate = isGCN in { 51 52//===----------------------------------------------------------------------===// 53// EXP Instructions 54//===----------------------------------------------------------------------===// 55 56defm EXP : EXP_m; 57 58//===----------------------------------------------------------------------===// 59// SMRD Instructions 60//===----------------------------------------------------------------------===// 61 62// We are using the SGPR_32 and not the SReg_32 register class for 32-bit 63// SMRD instructions, because the SGPR_32 register class does not include M0 64// and writing to M0 from an SMRD instruction will hang the GPU. 65defm S_LOAD_DWORD : SMRD_Helper <smrd<0x00>, "s_load_dword", SReg_64, SGPR_32>; 66defm S_LOAD_DWORDX2 : SMRD_Helper <smrd<0x01>, "s_load_dwordx2", SReg_64, SReg_64>; 67defm S_LOAD_DWORDX4 : SMRD_Helper <smrd<0x02>, "s_load_dwordx4", SReg_64, SReg_128>; 68defm S_LOAD_DWORDX8 : SMRD_Helper <smrd<0x03>, "s_load_dwordx8", SReg_64, SReg_256>; 69defm S_LOAD_DWORDX16 : SMRD_Helper <smrd<0x04>, "s_load_dwordx16", SReg_64, SReg_512>; 70 71defm S_BUFFER_LOAD_DWORD : SMRD_Helper < 72 smrd<0x08>, "s_buffer_load_dword", SReg_128, SGPR_32 73>; 74 75defm S_BUFFER_LOAD_DWORDX2 : SMRD_Helper < 76 smrd<0x09>, "s_buffer_load_dwordx2", SReg_128, SReg_64 77>; 78 79defm S_BUFFER_LOAD_DWORDX4 : SMRD_Helper < 80 smrd<0x0a>, "s_buffer_load_dwordx4", SReg_128, SReg_128 81>; 82 83defm S_BUFFER_LOAD_DWORDX8 : SMRD_Helper < 84 smrd<0x0b>, "s_buffer_load_dwordx8", SReg_128, SReg_256 85>; 86 87defm S_BUFFER_LOAD_DWORDX16 : SMRD_Helper < 88 smrd<0x0c>, "s_buffer_load_dwordx16", SReg_128, SReg_512 89>; 90 91let mayStore = ? in { 92// FIXME: mayStore = ? is a workaround for tablegen bug for different 93// inferred mayStore flags for the instruction pattern vs. standalone 94// Pat. Each considers the other contradictory. 95 96defm S_MEMTIME : SMRD_Special <smrd<0x1e, 0x24>, "s_memtime", 97 (outs SReg_64:$dst), " $dst", [(set i64:$dst, (int_amdgcn_s_memtime))] 98>; 99} 100 101defm S_DCACHE_INV : SMRD_Inval <smrd<0x1f, 0x20>, "s_dcache_inv", 102 int_amdgcn_s_dcache_inv>; 103 104//===----------------------------------------------------------------------===// 105// SOP1 Instructions 106//===----------------------------------------------------------------------===// 107 108let isMoveImm = 1 in { 109 let isReMaterializable = 1, isAsCheapAsAMove = 1 in { 110 defm S_MOV_B32 : SOP1_32 <sop1<0x03, 0x00>, "s_mov_b32", []>; 111 defm S_MOV_B64 : SOP1_64 <sop1<0x04, 0x01>, "s_mov_b64", []>; 112 } // End isRematerializeable = 1 113 114 let Uses = [SCC] in { 115 defm S_CMOV_B32 : SOP1_32 <sop1<0x05, 0x02>, "s_cmov_b32", []>; 116 defm S_CMOV_B64 : SOP1_64 <sop1<0x06, 0x03>, "s_cmov_b64", []>; 117 } // End Uses = [SCC] 118} // End isMoveImm = 1 119 120let Defs = [SCC] in { 121 defm S_NOT_B32 : SOP1_32 <sop1<0x07, 0x04>, "s_not_b32", 122 [(set i32:$dst, (not i32:$src0))] 123 >; 124 125 defm S_NOT_B64 : SOP1_64 <sop1<0x08, 0x05>, "s_not_b64", 126 [(set i64:$dst, (not i64:$src0))] 127 >; 128 defm S_WQM_B32 : SOP1_32 <sop1<0x09, 0x06>, "s_wqm_b32", []>; 129 defm S_WQM_B64 : SOP1_64 <sop1<0x0a, 0x07>, "s_wqm_b64", []>; 130} // End Defs = [SCC] 131 132 133defm S_BREV_B32 : SOP1_32 <sop1<0x0b, 0x08>, "s_brev_b32", 134 [(set i32:$dst, (bitreverse i32:$src0))] 135>; 136defm S_BREV_B64 : SOP1_64 <sop1<0x0c, 0x09>, "s_brev_b64", []>; 137 138let Defs = [SCC] in { 139 defm S_BCNT0_I32_B32 : SOP1_32 <sop1<0x0d, 0x0a>, "s_bcnt0_i32_b32", []>; 140 defm S_BCNT0_I32_B64 : SOP1_32_64 <sop1<0x0e, 0x0b>, "s_bcnt0_i32_b64", []>; 141 defm S_BCNT1_I32_B32 : SOP1_32 <sop1<0x0f, 0x0c>, "s_bcnt1_i32_b32", 142 [(set i32:$dst, (ctpop i32:$src0))] 143 >; 144 defm S_BCNT1_I32_B64 : SOP1_32_64 <sop1<0x10, 0x0d>, "s_bcnt1_i32_b64", []>; 145} // End Defs = [SCC] 146 147defm S_FF0_I32_B32 : SOP1_32 <sop1<0x11, 0x0e>, "s_ff0_i32_b32", []>; 148defm S_FF0_I32_B64 : SOP1_32_64 <sop1<0x12, 0x0f>, "s_ff0_i32_b64", []>; 149defm S_FF1_I32_B32 : SOP1_32 <sop1<0x13, 0x10>, "s_ff1_i32_b32", 150 [(set i32:$dst, (cttz_zero_undef i32:$src0))] 151>; 152defm S_FF1_I32_B64 : SOP1_32_64 <sop1<0x14, 0x11>, "s_ff1_i32_b64", []>; 153 154defm S_FLBIT_I32_B32 : SOP1_32 <sop1<0x15, 0x12>, "s_flbit_i32_b32", 155 [(set i32:$dst, (AMDGPUffbh_u32 i32:$src0))] 156>; 157 158defm S_FLBIT_I32_B64 : SOP1_32_64 <sop1<0x16, 0x13>, "s_flbit_i32_b64", []>; 159defm S_FLBIT_I32 : SOP1_32 <sop1<0x17, 0x14>, "s_flbit_i32", 160 [(set i32:$dst, (int_AMDGPU_flbit_i32 i32:$src0))] 161>; 162defm S_FLBIT_I32_I64 : SOP1_32_64 <sop1<0x18, 0x15>, "s_flbit_i32_i64", []>; 163defm S_SEXT_I32_I8 : SOP1_32 <sop1<0x19, 0x16>, "s_sext_i32_i8", 164 [(set i32:$dst, (sext_inreg i32:$src0, i8))] 165>; 166defm S_SEXT_I32_I16 : SOP1_32 <sop1<0x1a, 0x17>, "s_sext_i32_i16", 167 [(set i32:$dst, (sext_inreg i32:$src0, i16))] 168>; 169 170defm S_BITSET0_B32 : SOP1_32 <sop1<0x1b, 0x18>, "s_bitset0_b32", []>; 171defm S_BITSET0_B64 : SOP1_64 <sop1<0x1c, 0x19>, "s_bitset0_b64", []>; 172defm S_BITSET1_B32 : SOP1_32 <sop1<0x1d, 0x1a>, "s_bitset1_b32", []>; 173defm S_BITSET1_B64 : SOP1_64 <sop1<0x1e, 0x1b>, "s_bitset1_b64", []>; 174defm S_GETPC_B64 : SOP1_64_0 <sop1<0x1f, 0x1c>, "s_getpc_b64", []>; 175defm S_SETPC_B64 : SOP1_64 <sop1<0x20, 0x1d>, "s_setpc_b64", []>; 176defm S_SWAPPC_B64 : SOP1_64 <sop1<0x21, 0x1e>, "s_swappc_b64", []>; 177defm S_RFE_B64 : SOP1_64 <sop1<0x22, 0x1f>, "s_rfe_b64", []>; 178 179let hasSideEffects = 1, Uses = [EXEC], Defs = [EXEC, SCC] in { 180 181defm S_AND_SAVEEXEC_B64 : SOP1_64 <sop1<0x24, 0x20>, "s_and_saveexec_b64", []>; 182defm S_OR_SAVEEXEC_B64 : SOP1_64 <sop1<0x25, 0x21>, "s_or_saveexec_b64", []>; 183defm S_XOR_SAVEEXEC_B64 : SOP1_64 <sop1<0x26, 0x22>, "s_xor_saveexec_b64", []>; 184defm S_ANDN2_SAVEEXEC_B64 : SOP1_64 <sop1<0x27, 0x23>, "s_andn2_saveexec_b64", []>; 185defm S_ORN2_SAVEEXEC_B64 : SOP1_64 <sop1<0x28, 0x24>, "s_orn2_saveexec_b64", []>; 186defm S_NAND_SAVEEXEC_B64 : SOP1_64 <sop1<0x29, 0x25>, "s_nand_saveexec_b64", []>; 187defm S_NOR_SAVEEXEC_B64 : SOP1_64 <sop1<0x2a, 0x26>, "s_nor_saveexec_b64", []>; 188defm S_XNOR_SAVEEXEC_B64 : SOP1_64 <sop1<0x2b, 0x27>, "s_xnor_saveexec_b64", []>; 189 190} // End hasSideEffects = 1, Uses = [EXEC], Defs = [EXEC, SCC] 191 192defm S_QUADMASK_B32 : SOP1_32 <sop1<0x2c, 0x28>, "s_quadmask_b32", []>; 193defm S_QUADMASK_B64 : SOP1_64 <sop1<0x2d, 0x29>, "s_quadmask_b64", []>; 194 195let Uses = [M0] in { 196defm S_MOVRELS_B32 : SOP1_32 <sop1<0x2e, 0x2a>, "s_movrels_b32", []>; 197defm S_MOVRELS_B64 : SOP1_64 <sop1<0x2f, 0x2b>, "s_movrels_b64", []>; 198defm S_MOVRELD_B32 : SOP1_32 <sop1<0x30, 0x2c>, "s_movreld_b32", []>; 199defm S_MOVRELD_B64 : SOP1_64 <sop1<0x31, 0x2d>, "s_movreld_b64", []>; 200} // End Uses = [M0] 201 202defm S_CBRANCH_JOIN : SOP1_1 <sop1<0x32, 0x2e>, "s_cbranch_join", []>; 203defm S_MOV_REGRD_B32 : SOP1_32 <sop1<0x33, 0x2f>, "s_mov_regrd_b32", []>; 204let Defs = [SCC] in { 205 defm S_ABS_I32 : SOP1_32 <sop1<0x34, 0x30>, "s_abs_i32", []>; 206} // End Defs = [SCC] 207defm S_MOV_FED_B32 : SOP1_32 <sop1<0x35, 0x31>, "s_mov_fed_b32", []>; 208 209//===----------------------------------------------------------------------===// 210// SOP2 Instructions 211//===----------------------------------------------------------------------===// 212 213let Defs = [SCC] in { // Carry out goes to SCC 214let isCommutable = 1 in { 215defm S_ADD_U32 : SOP2_32 <sop2<0x00>, "s_add_u32", []>; 216defm S_ADD_I32 : SOP2_32 <sop2<0x02>, "s_add_i32", 217 [(set i32:$dst, (add SSrc_32:$src0, SSrc_32:$src1))] 218>; 219} // End isCommutable = 1 220 221defm S_SUB_U32 : SOP2_32 <sop2<0x01>, "s_sub_u32", []>; 222defm S_SUB_I32 : SOP2_32 <sop2<0x03>, "s_sub_i32", 223 [(set i32:$dst, (sub SSrc_32:$src0, SSrc_32:$src1))] 224>; 225 226let Uses = [SCC] in { // Carry in comes from SCC 227let isCommutable = 1 in { 228defm S_ADDC_U32 : SOP2_32 <sop2<0x04>, "s_addc_u32", 229 [(set i32:$dst, (adde (i32 SSrc_32:$src0), (i32 SSrc_32:$src1)))]>; 230} // End isCommutable = 1 231 232defm S_SUBB_U32 : SOP2_32 <sop2<0x05>, "s_subb_u32", 233 [(set i32:$dst, (sube (i32 SSrc_32:$src0), (i32 SSrc_32:$src1)))]>; 234} // End Uses = [SCC] 235 236defm S_MIN_I32 : SOP2_32 <sop2<0x06>, "s_min_i32", 237 [(set i32:$dst, (smin i32:$src0, i32:$src1))] 238>; 239defm S_MIN_U32 : SOP2_32 <sop2<0x07>, "s_min_u32", 240 [(set i32:$dst, (umin i32:$src0, i32:$src1))] 241>; 242defm S_MAX_I32 : SOP2_32 <sop2<0x08>, "s_max_i32", 243 [(set i32:$dst, (smax i32:$src0, i32:$src1))] 244>; 245defm S_MAX_U32 : SOP2_32 <sop2<0x09>, "s_max_u32", 246 [(set i32:$dst, (umax i32:$src0, i32:$src1))] 247>; 248} // End Defs = [SCC] 249 250 251let Uses = [SCC] in { 252 defm S_CSELECT_B32 : SOP2_32 <sop2<0x0a>, "s_cselect_b32", []>; 253 defm S_CSELECT_B64 : SOP2_64 <sop2<0x0b>, "s_cselect_b64", []>; 254} // End Uses = [SCC] 255 256let Defs = [SCC] in { 257defm S_AND_B32 : SOP2_32 <sop2<0x0e, 0x0c>, "s_and_b32", 258 [(set i32:$dst, (and i32:$src0, i32:$src1))] 259>; 260 261defm S_AND_B64 : SOP2_64 <sop2<0x0f, 0x0d>, "s_and_b64", 262 [(set i64:$dst, (and i64:$src0, i64:$src1))] 263>; 264 265defm S_OR_B32 : SOP2_32 <sop2<0x10, 0x0e>, "s_or_b32", 266 [(set i32:$dst, (or i32:$src0, i32:$src1))] 267>; 268 269defm S_OR_B64 : SOP2_64 <sop2<0x11, 0x0f>, "s_or_b64", 270 [(set i64:$dst, (or i64:$src0, i64:$src1))] 271>; 272 273defm S_XOR_B32 : SOP2_32 <sop2<0x12, 0x10>, "s_xor_b32", 274 [(set i32:$dst, (xor i32:$src0, i32:$src1))] 275>; 276 277defm S_XOR_B64 : SOP2_64 <sop2<0x13, 0x11>, "s_xor_b64", 278 [(set i64:$dst, (xor i64:$src0, i64:$src1))] 279>; 280defm S_ANDN2_B32 : SOP2_32 <sop2<0x14, 0x12>, "s_andn2_b32", []>; 281defm S_ANDN2_B64 : SOP2_64 <sop2<0x15, 0x13>, "s_andn2_b64", []>; 282defm S_ORN2_B32 : SOP2_32 <sop2<0x16, 0x14>, "s_orn2_b32", []>; 283defm S_ORN2_B64 : SOP2_64 <sop2<0x17, 0x15>, "s_orn2_b64", []>; 284defm S_NAND_B32 : SOP2_32 <sop2<0x18, 0x16>, "s_nand_b32", []>; 285defm S_NAND_B64 : SOP2_64 <sop2<0x19, 0x17>, "s_nand_b64", []>; 286defm S_NOR_B32 : SOP2_32 <sop2<0x1a, 0x18>, "s_nor_b32", []>; 287defm S_NOR_B64 : SOP2_64 <sop2<0x1b, 0x19>, "s_nor_b64", []>; 288defm S_XNOR_B32 : SOP2_32 <sop2<0x1c, 0x1a>, "s_xnor_b32", []>; 289defm S_XNOR_B64 : SOP2_64 <sop2<0x1d, 0x1b>, "s_xnor_b64", []>; 290} // End Defs = [SCC] 291 292// Use added complexity so these patterns are preferred to the VALU patterns. 293let AddedComplexity = 1 in { 294let Defs = [SCC] in { 295 296defm S_LSHL_B32 : SOP2_32 <sop2<0x1e, 0x1c>, "s_lshl_b32", 297 [(set i32:$dst, (shl i32:$src0, i32:$src1))] 298>; 299defm S_LSHL_B64 : SOP2_64_32 <sop2<0x1f, 0x1d>, "s_lshl_b64", 300 [(set i64:$dst, (shl i64:$src0, i32:$src1))] 301>; 302defm S_LSHR_B32 : SOP2_32 <sop2<0x20, 0x1e>, "s_lshr_b32", 303 [(set i32:$dst, (srl i32:$src0, i32:$src1))] 304>; 305defm S_LSHR_B64 : SOP2_64_32 <sop2<0x21, 0x1f>, "s_lshr_b64", 306 [(set i64:$dst, (srl i64:$src0, i32:$src1))] 307>; 308defm S_ASHR_I32 : SOP2_32 <sop2<0x22, 0x20>, "s_ashr_i32", 309 [(set i32:$dst, (sra i32:$src0, i32:$src1))] 310>; 311defm S_ASHR_I64 : SOP2_64_32 <sop2<0x23, 0x21>, "s_ashr_i64", 312 [(set i64:$dst, (sra i64:$src0, i32:$src1))] 313>; 314} // End Defs = [SCC] 315 316defm S_BFM_B32 : SOP2_32 <sop2<0x24, 0x22>, "s_bfm_b32", 317 [(set i32:$dst, (AMDGPUbfm i32:$src0, i32:$src1))]>; 318defm S_BFM_B64 : SOP2_64_32_32 <sop2<0x25, 0x23>, "s_bfm_b64", []>; 319defm S_MUL_I32 : SOP2_32 <sop2<0x26, 0x24>, "s_mul_i32", 320 [(set i32:$dst, (mul i32:$src0, i32:$src1))] 321>; 322 323} // End AddedComplexity = 1 324 325let Defs = [SCC] in { 326defm S_BFE_U32 : SOP2_32 <sop2<0x27, 0x25>, "s_bfe_u32", []>; 327defm S_BFE_I32 : SOP2_32 <sop2<0x28, 0x26>, "s_bfe_i32", []>; 328defm S_BFE_U64 : SOP2_64_32 <sop2<0x29, 0x27>, "s_bfe_u64", []>; 329defm S_BFE_I64 : SOP2_64_32 <sop2<0x2a, 0x28>, "s_bfe_i64", []>; 330} // End Defs = [SCC] 331 332let sdst = 0 in { 333defm S_CBRANCH_G_FORK : SOP2_m < 334 sop2<0x2b, 0x29>, "s_cbranch_g_fork", (outs), 335 (ins SReg_64:$src0, SReg_64:$src1), "s_cbranch_g_fork $src0, $src1", [] 336>; 337} 338 339let Defs = [SCC] in { 340defm S_ABSDIFF_I32 : SOP2_32 <sop2<0x2c, 0x2a>, "s_absdiff_i32", []>; 341} // End Defs = [SCC] 342 343//===----------------------------------------------------------------------===// 344// SOPC Instructions 345//===----------------------------------------------------------------------===// 346 347def S_CMP_EQ_I32 : SOPC_32 <0x00000000, "s_cmp_eq_i32", COND_EQ>; 348def S_CMP_LG_I32 : SOPC_32 <0x00000001, "s_cmp_lg_i32", COND_NE>; 349def S_CMP_GT_I32 : SOPC_32 <0x00000002, "s_cmp_gt_i32", COND_SGT>; 350def S_CMP_GE_I32 : SOPC_32 <0x00000003, "s_cmp_ge_i32", COND_SGE>; 351def S_CMP_LT_I32 : SOPC_32 <0x00000004, "s_cmp_lt_i32", COND_SLT>; 352def S_CMP_LE_I32 : SOPC_32 <0x00000005, "s_cmp_le_i32", COND_SLE>; 353def S_CMP_EQ_U32 : SOPC_32 <0x00000006, "s_cmp_eq_u32", COND_EQ>; 354def S_CMP_LG_U32 : SOPC_32 <0x00000007, "s_cmp_lg_u32", COND_NE >; 355def S_CMP_GT_U32 : SOPC_32 <0x00000008, "s_cmp_gt_u32", COND_UGT>; 356def S_CMP_GE_U32 : SOPC_32 <0x00000009, "s_cmp_ge_u32", COND_UGE>; 357def S_CMP_LT_U32 : SOPC_32 <0x0000000a, "s_cmp_lt_u32", COND_ULT>; 358def S_CMP_LE_U32 : SOPC_32 <0x0000000b, "s_cmp_le_u32", COND_ULE>; 359////def S_BITCMP0_B32 : SOPC_BITCMP0 <0x0000000c, "s_bitcmp0_b32", []>; 360////def S_BITCMP1_B32 : SOPC_BITCMP1 <0x0000000d, "s_bitcmp1_b32", []>; 361////def S_BITCMP0_B64 : SOPC_BITCMP0 <0x0000000e, "s_bitcmp0_b64", []>; 362////def S_BITCMP1_B64 : SOPC_BITCMP1 <0x0000000f, "s_bitcmp1_b64", []>; 363//def S_SETVSKIP : SOPC_ <0x00000010, "s_setvskip", []>; 364 365//===----------------------------------------------------------------------===// 366// SOPK Instructions 367//===----------------------------------------------------------------------===// 368 369let isReMaterializable = 1, isMoveImm = 1 in { 370defm S_MOVK_I32 : SOPK_32 <sopk<0x00>, "s_movk_i32", []>; 371} // End isReMaterializable = 1 372let Uses = [SCC] in { 373 defm S_CMOVK_I32 : SOPK_32 <sopk<0x02, 0x01>, "s_cmovk_i32", []>; 374} 375 376let isCompare = 1 in { 377 378/* 379This instruction is disabled for now until we can figure out how to teach 380the instruction selector to correctly use the S_CMP* vs V_CMP* 381instructions. 382 383When this instruction is enabled the code generator sometimes produces this 384invalid sequence: 385 386SCC = S_CMPK_EQ_I32 SGPR0, imm 387VCC = COPY SCC 388VGPR0 = V_CNDMASK VCC, VGPR0, VGPR1 389 390defm S_CMPK_EQ_I32 : SOPK_SCC <sopk<0x03, 0x02>, "s_cmpk_eq_i32", 391 [(set i1:$dst, (setcc i32:$src0, imm:$src1, SETEQ))] 392>; 393*/ 394 395defm S_CMPK_EQ_I32 : SOPK_SCC <sopk<0x03, 0x02>, "s_cmpk_eq_i32", []>; 396defm S_CMPK_LG_I32 : SOPK_SCC <sopk<0x04, 0x03>, "s_cmpk_lg_i32", []>; 397defm S_CMPK_GT_I32 : SOPK_SCC <sopk<0x05, 0x04>, "s_cmpk_gt_i32", []>; 398defm S_CMPK_GE_I32 : SOPK_SCC <sopk<0x06, 0x05>, "s_cmpk_ge_i32", []>; 399defm S_CMPK_LT_I32 : SOPK_SCC <sopk<0x07, 0x06>, "s_cmpk_lt_i32", []>; 400defm S_CMPK_LE_I32 : SOPK_SCC <sopk<0x08, 0x07>, "s_cmpk_le_i32", []>; 401defm S_CMPK_EQ_U32 : SOPK_SCC <sopk<0x09, 0x08>, "s_cmpk_eq_u32", []>; 402defm S_CMPK_LG_U32 : SOPK_SCC <sopk<0x0a, 0x09>, "s_cmpk_lg_u32", []>; 403defm S_CMPK_GT_U32 : SOPK_SCC <sopk<0x0b, 0x0a>, "s_cmpk_gt_u32", []>; 404defm S_CMPK_GE_U32 : SOPK_SCC <sopk<0x0c, 0x0b>, "s_cmpk_ge_u32", []>; 405defm S_CMPK_LT_U32 : SOPK_SCC <sopk<0x0d, 0x0c>, "s_cmpk_lt_u32", []>; 406defm S_CMPK_LE_U32 : SOPK_SCC <sopk<0x0e, 0x0d>, "s_cmpk_le_u32", []>; 407} // End isCompare = 1 408 409let Defs = [SCC], isCommutable = 1, DisableEncoding = "$src0", 410 Constraints = "$sdst = $src0" in { 411 defm S_ADDK_I32 : SOPK_32TIE <sopk<0x0f, 0x0e>, "s_addk_i32", []>; 412 defm S_MULK_I32 : SOPK_32TIE <sopk<0x10, 0x0f>, "s_mulk_i32", []>; 413} 414 415defm S_CBRANCH_I_FORK : SOPK_m < 416 sopk<0x11, 0x10>, "s_cbranch_i_fork", (outs), 417 (ins SReg_64:$sdst, u16imm:$simm16), " $sdst, $simm16" 418>; 419defm S_GETREG_B32 : SOPK_32 <sopk<0x12, 0x11>, "s_getreg_b32", []>; 420defm S_SETREG_B32 : SOPK_m < 421 sopk<0x13, 0x12>, "s_setreg_b32", (outs), 422 (ins SReg_32:$sdst, u16imm:$simm16), " $sdst, $simm16" 423>; 424// FIXME: Not on SI? 425//defm S_GETREG_REGRD_B32 : SOPK_32 <sopk<0x14, 0x13>, "s_getreg_regrd_b32", []>; 426defm S_SETREG_IMM32_B32 : SOPK_IMM32 < 427 sopk<0x15, 0x14>, "s_setreg_imm32_b32", (outs), 428 (ins i32imm:$imm, u16imm:$simm16), " $imm, $simm16" 429>; 430 431//===----------------------------------------------------------------------===// 432// SOPP Instructions 433//===----------------------------------------------------------------------===// 434 435def S_NOP : SOPP <0x00000000, (ins i16imm:$simm16), "s_nop $simm16">; 436 437let isTerminator = 1 in { 438 439def S_ENDPGM : SOPP <0x00000001, (ins), "s_endpgm", 440 [(IL_retflag)]> { 441 let simm16 = 0; 442 let isBarrier = 1; 443 let hasCtrlDep = 1; 444} 445 446let isBranch = 1 in { 447def S_BRANCH : SOPP < 448 0x00000002, (ins sopp_brtarget:$simm16), "s_branch $simm16", 449 [(br bb:$simm16)]> { 450 let isBarrier = 1; 451} 452 453let Uses = [SCC] in { 454def S_CBRANCH_SCC0 : SOPP < 455 0x00000004, (ins sopp_brtarget:$simm16), 456 "s_cbranch_scc0 $simm16" 457>; 458def S_CBRANCH_SCC1 : SOPP < 459 0x00000005, (ins sopp_brtarget:$simm16), 460 "s_cbranch_scc1 $simm16", 461 [(si_uniform_br_scc SCC, bb:$simm16)] 462>; 463} // End Uses = [SCC] 464 465let Uses = [VCC] in { 466def S_CBRANCH_VCCZ : SOPP < 467 0x00000006, (ins sopp_brtarget:$simm16), 468 "s_cbranch_vccz $simm16" 469>; 470def S_CBRANCH_VCCNZ : SOPP < 471 0x00000007, (ins sopp_brtarget:$simm16), 472 "s_cbranch_vccnz $simm16" 473>; 474} // End Uses = [VCC] 475 476let Uses = [EXEC] in { 477def S_CBRANCH_EXECZ : SOPP < 478 0x00000008, (ins sopp_brtarget:$simm16), 479 "s_cbranch_execz $simm16" 480>; 481def S_CBRANCH_EXECNZ : SOPP < 482 0x00000009, (ins sopp_brtarget:$simm16), 483 "s_cbranch_execnz $simm16" 484>; 485} // End Uses = [EXEC] 486 487 488} // End isBranch = 1 489} // End isTerminator = 1 490 491let hasSideEffects = 1 in { 492def S_BARRIER : SOPP <0x0000000a, (ins), "s_barrier", 493 [(int_amdgcn_s_barrier)] 494> { 495 let SchedRW = [WriteBarrier]; 496 let simm16 = 0; 497 let mayLoad = 1; 498 let mayStore = 1; 499 let isConvergent = 1; 500} 501 502def S_WAITCNT : SOPP <0x0000000c, (ins WAIT_FLAG:$simm16), "s_waitcnt $simm16">; 503def S_SETHALT : SOPP <0x0000000d, (ins i16imm:$simm16), "s_sethalt $simm16">; 504 505// On SI the documentation says sleep for approximately 64 * low 2 506// bits, consistent with the reported maximum of 448. On VI the 507// maximum reported is 960 cycles, so 960 / 64 = 15 max, so is the 508// maximum really 15 on VI? 509def S_SLEEP : SOPP <0x0000000e, (ins i32imm:$simm16), 510 "s_sleep $simm16", [(int_amdgcn_s_sleep SIMM16bit:$simm16)]> { 511 let hasSideEffects = 1; 512 let mayLoad = 1; 513 let mayStore = 1; 514} 515 516def S_SETPRIO : SOPP <0x0000000f, (ins i16imm:$sim16), "s_setprio $sim16">; 517 518let Uses = [EXEC, M0] in { 519 // FIXME: Should this be mayLoad+mayStore? 520 def S_SENDMSG : SOPP <0x00000010, (ins SendMsgImm:$simm16), "s_sendmsg $simm16", 521 [(AMDGPUsendmsg (i32 imm:$simm16))] 522 >; 523} // End Uses = [EXEC, M0] 524 525def S_SENDMSGHALT : SOPP <0x00000011, (ins i16imm:$simm16), "s_sendmsghalt $simm16">; 526def S_TRAP : SOPP <0x00000012, (ins i16imm:$simm16), "s_trap $simm16">; 527def S_ICACHE_INV : SOPP <0x00000013, (ins), "s_icache_inv"> { 528 let simm16 = 0; 529} 530def S_INCPERFLEVEL : SOPP <0x00000014, (ins i16imm:$simm16), "s_incperflevel $simm16">; 531def S_DECPERFLEVEL : SOPP <0x00000015, (ins i16imm:$simm16), "s_decperflevel $simm16">; 532def S_TTRACEDATA : SOPP <0x00000016, (ins), "s_ttracedata"> { 533 let simm16 = 0; 534} 535} // End hasSideEffects 536 537//===----------------------------------------------------------------------===// 538// VOPC Instructions 539//===----------------------------------------------------------------------===// 540 541let isCompare = 1, isCommutable = 1 in { 542 543defm V_CMP_F_F32 : VOPC_F32 <vopc<0x0, 0x40>, "v_cmp_f_f32">; 544defm V_CMP_LT_F32 : VOPC_F32 <vopc<0x1, 0x41>, "v_cmp_lt_f32", COND_OLT, "v_cmp_gt_f32">; 545defm V_CMP_EQ_F32 : VOPC_F32 <vopc<0x2, 0x42>, "v_cmp_eq_f32", COND_OEQ>; 546defm V_CMP_LE_F32 : VOPC_F32 <vopc<0x3, 0x43>, "v_cmp_le_f32", COND_OLE, "v_cmp_ge_f32">; 547defm V_CMP_GT_F32 : VOPC_F32 <vopc<0x4, 0x44>, "v_cmp_gt_f32", COND_OGT>; 548defm V_CMP_LG_F32 : VOPC_F32 <vopc<0x5, 0x45>, "v_cmp_lg_f32", COND_ONE>; 549defm V_CMP_GE_F32 : VOPC_F32 <vopc<0x6, 0x46>, "v_cmp_ge_f32", COND_OGE>; 550defm V_CMP_O_F32 : VOPC_F32 <vopc<0x7, 0x47>, "v_cmp_o_f32", COND_O>; 551defm V_CMP_U_F32 : VOPC_F32 <vopc<0x8, 0x48>, "v_cmp_u_f32", COND_UO>; 552defm V_CMP_NGE_F32 : VOPC_F32 <vopc<0x9, 0x49>, "v_cmp_nge_f32", COND_ULT, "v_cmp_nle_f32">; 553defm V_CMP_NLG_F32 : VOPC_F32 <vopc<0xa, 0x4a>, "v_cmp_nlg_f32", COND_UEQ>; 554defm V_CMP_NGT_F32 : VOPC_F32 <vopc<0xb, 0x4b>, "v_cmp_ngt_f32", COND_ULE, "v_cmp_nlt_f32">; 555defm V_CMP_NLE_F32 : VOPC_F32 <vopc<0xc, 0x4c>, "v_cmp_nle_f32", COND_UGT>; 556defm V_CMP_NEQ_F32 : VOPC_F32 <vopc<0xd, 0x4d>, "v_cmp_neq_f32", COND_UNE>; 557defm V_CMP_NLT_F32 : VOPC_F32 <vopc<0xe, 0x4e>, "v_cmp_nlt_f32", COND_UGE>; 558defm V_CMP_TRU_F32 : VOPC_F32 <vopc<0xf, 0x4f>, "v_cmp_tru_f32">; 559 560 561defm V_CMPX_F_F32 : VOPCX_F32 <vopc<0x10, 0x50>, "v_cmpx_f_f32">; 562defm V_CMPX_LT_F32 : VOPCX_F32 <vopc<0x11, 0x51>, "v_cmpx_lt_f32", "v_cmpx_gt_f32">; 563defm V_CMPX_EQ_F32 : VOPCX_F32 <vopc<0x12, 0x52>, "v_cmpx_eq_f32">; 564defm V_CMPX_LE_F32 : VOPCX_F32 <vopc<0x13, 0x53>, "v_cmpx_le_f32", "v_cmpx_ge_f32">; 565defm V_CMPX_GT_F32 : VOPCX_F32 <vopc<0x14, 0x54>, "v_cmpx_gt_f32">; 566defm V_CMPX_LG_F32 : VOPCX_F32 <vopc<0x15, 0x55>, "v_cmpx_lg_f32">; 567defm V_CMPX_GE_F32 : VOPCX_F32 <vopc<0x16, 0x56>, "v_cmpx_ge_f32">; 568defm V_CMPX_O_F32 : VOPCX_F32 <vopc<0x17, 0x57>, "v_cmpx_o_f32">; 569defm V_CMPX_U_F32 : VOPCX_F32 <vopc<0x18, 0x58>, "v_cmpx_u_f32">; 570defm V_CMPX_NGE_F32 : VOPCX_F32 <vopc<0x19, 0x59>, "v_cmpx_nge_f32">; 571defm V_CMPX_NLG_F32 : VOPCX_F32 <vopc<0x1a, 0x5a>, "v_cmpx_nlg_f32">; 572defm V_CMPX_NGT_F32 : VOPCX_F32 <vopc<0x1b, 0x5b>, "v_cmpx_ngt_f32">; 573defm V_CMPX_NLE_F32 : VOPCX_F32 <vopc<0x1c, 0x5c>, "v_cmpx_nle_f32">; 574defm V_CMPX_NEQ_F32 : VOPCX_F32 <vopc<0x1d, 0x5d>, "v_cmpx_neq_f32">; 575defm V_CMPX_NLT_F32 : VOPCX_F32 <vopc<0x1e, 0x5e>, "v_cmpx_nlt_f32">; 576defm V_CMPX_TRU_F32 : VOPCX_F32 <vopc<0x1f, 0x5f>, "v_cmpx_tru_f32">; 577 578 579defm V_CMP_F_F64 : VOPC_F64 <vopc<0x20, 0x60>, "v_cmp_f_f64">; 580defm V_CMP_LT_F64 : VOPC_F64 <vopc<0x21, 0x61>, "v_cmp_lt_f64", COND_OLT, "v_cmp_gt_f64">; 581defm V_CMP_EQ_F64 : VOPC_F64 <vopc<0x22, 0x62>, "v_cmp_eq_f64", COND_OEQ>; 582defm V_CMP_LE_F64 : VOPC_F64 <vopc<0x23, 0x63>, "v_cmp_le_f64", COND_OLE, "v_cmp_ge_f64">; 583defm V_CMP_GT_F64 : VOPC_F64 <vopc<0x24, 0x64>, "v_cmp_gt_f64", COND_OGT>; 584defm V_CMP_LG_F64 : VOPC_F64 <vopc<0x25, 0x65>, "v_cmp_lg_f64", COND_ONE>; 585defm V_CMP_GE_F64 : VOPC_F64 <vopc<0x26, 0x66>, "v_cmp_ge_f64", COND_OGE>; 586defm V_CMP_O_F64 : VOPC_F64 <vopc<0x27, 0x67>, "v_cmp_o_f64", COND_O>; 587defm V_CMP_U_F64 : VOPC_F64 <vopc<0x28, 0x68>, "v_cmp_u_f64", COND_UO>; 588defm V_CMP_NGE_F64 : VOPC_F64 <vopc<0x29, 0x69>, "v_cmp_nge_f64", COND_ULT, "v_cmp_nle_f64">; 589defm V_CMP_NLG_F64 : VOPC_F64 <vopc<0x2a, 0x6a>, "v_cmp_nlg_f64", COND_UEQ>; 590defm V_CMP_NGT_F64 : VOPC_F64 <vopc<0x2b, 0x6b>, "v_cmp_ngt_f64", COND_ULE, "v_cmp_nlt_f64">; 591defm V_CMP_NLE_F64 : VOPC_F64 <vopc<0x2c, 0x6c>, "v_cmp_nle_f64", COND_UGT>; 592defm V_CMP_NEQ_F64 : VOPC_F64 <vopc<0x2d, 0x6d>, "v_cmp_neq_f64", COND_UNE>; 593defm V_CMP_NLT_F64 : VOPC_F64 <vopc<0x2e, 0x6e>, "v_cmp_nlt_f64", COND_UGE>; 594defm V_CMP_TRU_F64 : VOPC_F64 <vopc<0x2f, 0x6f>, "v_cmp_tru_f64">; 595 596 597defm V_CMPX_F_F64 : VOPCX_F64 <vopc<0x30, 0x70>, "v_cmpx_f_f64">; 598defm V_CMPX_LT_F64 : VOPCX_F64 <vopc<0x31, 0x71>, "v_cmpx_lt_f64", "v_cmpx_gt_f64">; 599defm V_CMPX_EQ_F64 : VOPCX_F64 <vopc<0x32, 0x72>, "v_cmpx_eq_f64">; 600defm V_CMPX_LE_F64 : VOPCX_F64 <vopc<0x33, 0x73>, "v_cmpx_le_f64", "v_cmpx_ge_f64">; 601defm V_CMPX_GT_F64 : VOPCX_F64 <vopc<0x34, 0x74>, "v_cmpx_gt_f64">; 602defm V_CMPX_LG_F64 : VOPCX_F64 <vopc<0x35, 0x75>, "v_cmpx_lg_f64">; 603defm V_CMPX_GE_F64 : VOPCX_F64 <vopc<0x36, 0x76>, "v_cmpx_ge_f64">; 604defm V_CMPX_O_F64 : VOPCX_F64 <vopc<0x37, 0x77>, "v_cmpx_o_f64">; 605defm V_CMPX_U_F64 : VOPCX_F64 <vopc<0x38, 0x78>, "v_cmpx_u_f64">; 606defm V_CMPX_NGE_F64 : VOPCX_F64 <vopc<0x39, 0x79>, "v_cmpx_nge_f64", "v_cmpx_nle_f64">; 607defm V_CMPX_NLG_F64 : VOPCX_F64 <vopc<0x3a, 0x7a>, "v_cmpx_nlg_f64">; 608defm V_CMPX_NGT_F64 : VOPCX_F64 <vopc<0x3b, 0x7b>, "v_cmpx_ngt_f64", "v_cmpx_nlt_f64">; 609defm V_CMPX_NLE_F64 : VOPCX_F64 <vopc<0x3c, 0x7c>, "v_cmpx_nle_f64">; 610defm V_CMPX_NEQ_F64 : VOPCX_F64 <vopc<0x3d, 0x7d>, "v_cmpx_neq_f64">; 611defm V_CMPX_NLT_F64 : VOPCX_F64 <vopc<0x3e, 0x7e>, "v_cmpx_nlt_f64">; 612defm V_CMPX_TRU_F64 : VOPCX_F64 <vopc<0x3f, 0x7f>, "v_cmpx_tru_f64">; 613 614 615let SubtargetPredicate = isSICI in { 616 617defm V_CMPS_F_F32 : VOPC_F32 <vopc<0x40>, "v_cmps_f_f32">; 618defm V_CMPS_LT_F32 : VOPC_F32 <vopc<0x41>, "v_cmps_lt_f32", COND_NULL, "v_cmps_gt_f32">; 619defm V_CMPS_EQ_F32 : VOPC_F32 <vopc<0x42>, "v_cmps_eq_f32">; 620defm V_CMPS_LE_F32 : VOPC_F32 <vopc<0x43>, "v_cmps_le_f32", COND_NULL, "v_cmps_ge_f32">; 621defm V_CMPS_GT_F32 : VOPC_F32 <vopc<0x44>, "v_cmps_gt_f32">; 622defm V_CMPS_LG_F32 : VOPC_F32 <vopc<0x45>, "v_cmps_lg_f32">; 623defm V_CMPS_GE_F32 : VOPC_F32 <vopc<0x46>, "v_cmps_ge_f32">; 624defm V_CMPS_O_F32 : VOPC_F32 <vopc<0x47>, "v_cmps_o_f32">; 625defm V_CMPS_U_F32 : VOPC_F32 <vopc<0x48>, "v_cmps_u_f32">; 626defm V_CMPS_NGE_F32 : VOPC_F32 <vopc<0x49>, "v_cmps_nge_f32", COND_NULL, "v_cmps_nle_f32">; 627defm V_CMPS_NLG_F32 : VOPC_F32 <vopc<0x4a>, "v_cmps_nlg_f32">; 628defm V_CMPS_NGT_F32 : VOPC_F32 <vopc<0x4b>, "v_cmps_ngt_f32", COND_NULL, "v_cmps_nlt_f32">; 629defm V_CMPS_NLE_F32 : VOPC_F32 <vopc<0x4c>, "v_cmps_nle_f32">; 630defm V_CMPS_NEQ_F32 : VOPC_F32 <vopc<0x4d>, "v_cmps_neq_f32">; 631defm V_CMPS_NLT_F32 : VOPC_F32 <vopc<0x4e>, "v_cmps_nlt_f32">; 632defm V_CMPS_TRU_F32 : VOPC_F32 <vopc<0x4f>, "v_cmps_tru_f32">; 633 634 635defm V_CMPSX_F_F32 : VOPCX_F32 <vopc<0x50>, "v_cmpsx_f_f32">; 636defm V_CMPSX_LT_F32 : VOPCX_F32 <vopc<0x51>, "v_cmpsx_lt_f32", "v_cmpsx_gt_f32">; 637defm V_CMPSX_EQ_F32 : VOPCX_F32 <vopc<0x52>, "v_cmpsx_eq_f32">; 638defm V_CMPSX_LE_F32 : VOPCX_F32 <vopc<0x53>, "v_cmpsx_le_f32", "v_cmpsx_ge_f32">; 639defm V_CMPSX_GT_F32 : VOPCX_F32 <vopc<0x54>, "v_cmpsx_gt_f32">; 640defm V_CMPSX_LG_F32 : VOPCX_F32 <vopc<0x55>, "v_cmpsx_lg_f32">; 641defm V_CMPSX_GE_F32 : VOPCX_F32 <vopc<0x56>, "v_cmpsx_ge_f32">; 642defm V_CMPSX_O_F32 : VOPCX_F32 <vopc<0x57>, "v_cmpsx_o_f32">; 643defm V_CMPSX_U_F32 : VOPCX_F32 <vopc<0x58>, "v_cmpsx_u_f32">; 644defm V_CMPSX_NGE_F32 : VOPCX_F32 <vopc<0x59>, "v_cmpsx_nge_f32", "v_cmpsx_nle_f32">; 645defm V_CMPSX_NLG_F32 : VOPCX_F32 <vopc<0x5a>, "v_cmpsx_nlg_f32">; 646defm V_CMPSX_NGT_F32 : VOPCX_F32 <vopc<0x5b>, "v_cmpsx_ngt_f32", "v_cmpsx_nlt_f32">; 647defm V_CMPSX_NLE_F32 : VOPCX_F32 <vopc<0x5c>, "v_cmpsx_nle_f32">; 648defm V_CMPSX_NEQ_F32 : VOPCX_F32 <vopc<0x5d>, "v_cmpsx_neq_f32">; 649defm V_CMPSX_NLT_F32 : VOPCX_F32 <vopc<0x5e>, "v_cmpsx_nlt_f32">; 650defm V_CMPSX_TRU_F32 : VOPCX_F32 <vopc<0x5f>, "v_cmpsx_tru_f32">; 651 652 653defm V_CMPS_F_F64 : VOPC_F64 <vopc<0x60>, "v_cmps_f_f64">; 654defm V_CMPS_LT_F64 : VOPC_F64 <vopc<0x61>, "v_cmps_lt_f64", COND_NULL, "v_cmps_gt_f64">; 655defm V_CMPS_EQ_F64 : VOPC_F64 <vopc<0x62>, "v_cmps_eq_f64">; 656defm V_CMPS_LE_F64 : VOPC_F64 <vopc<0x63>, "v_cmps_le_f64", COND_NULL, "v_cmps_ge_f64">; 657defm V_CMPS_GT_F64 : VOPC_F64 <vopc<0x64>, "v_cmps_gt_f64">; 658defm V_CMPS_LG_F64 : VOPC_F64 <vopc<0x65>, "v_cmps_lg_f64">; 659defm V_CMPS_GE_F64 : VOPC_F64 <vopc<0x66>, "v_cmps_ge_f64">; 660defm V_CMPS_O_F64 : VOPC_F64 <vopc<0x67>, "v_cmps_o_f64">; 661defm V_CMPS_U_F64 : VOPC_F64 <vopc<0x68>, "v_cmps_u_f64">; 662defm V_CMPS_NGE_F64 : VOPC_F64 <vopc<0x69>, "v_cmps_nge_f64", COND_NULL, "v_cmps_nle_f64">; 663defm V_CMPS_NLG_F64 : VOPC_F64 <vopc<0x6a>, "v_cmps_nlg_f64">; 664defm V_CMPS_NGT_F64 : VOPC_F64 <vopc<0x6b>, "v_cmps_ngt_f64", COND_NULL, "v_cmps_nlt_f64">; 665defm V_CMPS_NLE_F64 : VOPC_F64 <vopc<0x6c>, "v_cmps_nle_f64">; 666defm V_CMPS_NEQ_F64 : VOPC_F64 <vopc<0x6d>, "v_cmps_neq_f64">; 667defm V_CMPS_NLT_F64 : VOPC_F64 <vopc<0x6e>, "v_cmps_nlt_f64">; 668defm V_CMPS_TRU_F64 : VOPC_F64 <vopc<0x6f>, "v_cmps_tru_f64">; 669 670 671defm V_CMPSX_F_F64 : VOPCX_F64 <vopc<0x70>, "v_cmpsx_f_f64">; 672defm V_CMPSX_LT_F64 : VOPCX_F64 <vopc<0x71>, "v_cmpsx_lt_f64", "v_cmpsx_gt_f64">; 673defm V_CMPSX_EQ_F64 : VOPCX_F64 <vopc<0x72>, "v_cmpsx_eq_f64">; 674defm V_CMPSX_LE_F64 : VOPCX_F64 <vopc<0x73>, "v_cmpsx_le_f64", "v_cmpsx_ge_f64">; 675defm V_CMPSX_GT_F64 : VOPCX_F64 <vopc<0x74>, "v_cmpsx_gt_f64">; 676defm V_CMPSX_LG_F64 : VOPCX_F64 <vopc<0x75>, "v_cmpsx_lg_f64">; 677defm V_CMPSX_GE_F64 : VOPCX_F64 <vopc<0x76>, "v_cmpsx_ge_f64">; 678defm V_CMPSX_O_F64 : VOPCX_F64 <vopc<0x77>, "v_cmpsx_o_f64">; 679defm V_CMPSX_U_F64 : VOPCX_F64 <vopc<0x78>, "v_cmpsx_u_f64">; 680defm V_CMPSX_NGE_F64 : VOPCX_F64 <vopc<0x79>, "v_cmpsx_nge_f64", "v_cmpsx_nle_f64">; 681defm V_CMPSX_NLG_F64 : VOPCX_F64 <vopc<0x7a>, "v_cmpsx_nlg_f64">; 682defm V_CMPSX_NGT_F64 : VOPCX_F64 <vopc<0x7b>, "v_cmpsx_ngt_f64", "v_cmpsx_nlt_f64">; 683defm V_CMPSX_NLE_F64 : VOPCX_F64 <vopc<0x7c>, "v_cmpsx_nle_f64">; 684defm V_CMPSX_NEQ_F64 : VOPCX_F64 <vopc<0x7d>, "v_cmpsx_neq_f64">; 685defm V_CMPSX_NLT_F64 : VOPCX_F64 <vopc<0x7e>, "v_cmpsx_nlt_f64">; 686defm V_CMPSX_TRU_F64 : VOPCX_F64 <vopc<0x7f>, "v_cmpsx_tru_f64">; 687 688} // End SubtargetPredicate = isSICI 689 690defm V_CMP_F_I32 : VOPC_I32 <vopc<0x80, 0xc0>, "v_cmp_f_i32">; 691defm V_CMP_LT_I32 : VOPC_I32 <vopc<0x81, 0xc1>, "v_cmp_lt_i32", COND_SLT, "v_cmp_gt_i32">; 692defm V_CMP_EQ_I32 : VOPC_I32 <vopc<0x82, 0xc2>, "v_cmp_eq_i32", COND_EQ>; 693defm V_CMP_LE_I32 : VOPC_I32 <vopc<0x83, 0xc3>, "v_cmp_le_i32", COND_SLE, "v_cmp_ge_i32">; 694defm V_CMP_GT_I32 : VOPC_I32 <vopc<0x84, 0xc4>, "v_cmp_gt_i32", COND_SGT>; 695defm V_CMP_NE_I32 : VOPC_I32 <vopc<0x85, 0xc5>, "v_cmp_ne_i32", COND_NE>; 696defm V_CMP_GE_I32 : VOPC_I32 <vopc<0x86, 0xc6>, "v_cmp_ge_i32", COND_SGE>; 697defm V_CMP_T_I32 : VOPC_I32 <vopc<0x87, 0xc7>, "v_cmp_t_i32">; 698 699 700defm V_CMPX_F_I32 : VOPCX_I32 <vopc<0x90, 0xd0>, "v_cmpx_f_i32">; 701defm V_CMPX_LT_I32 : VOPCX_I32 <vopc<0x91, 0xd1>, "v_cmpx_lt_i32", "v_cmpx_gt_i32">; 702defm V_CMPX_EQ_I32 : VOPCX_I32 <vopc<0x92, 0xd2>, "v_cmpx_eq_i32">; 703defm V_CMPX_LE_I32 : VOPCX_I32 <vopc<0x93, 0xd3>, "v_cmpx_le_i32", "v_cmpx_ge_i32">; 704defm V_CMPX_GT_I32 : VOPCX_I32 <vopc<0x94, 0xd4>, "v_cmpx_gt_i32">; 705defm V_CMPX_NE_I32 : VOPCX_I32 <vopc<0x95, 0xd5>, "v_cmpx_ne_i32">; 706defm V_CMPX_GE_I32 : VOPCX_I32 <vopc<0x96, 0xd6>, "v_cmpx_ge_i32">; 707defm V_CMPX_T_I32 : VOPCX_I32 <vopc<0x97, 0xd7>, "v_cmpx_t_i32">; 708 709 710defm V_CMP_F_I64 : VOPC_I64 <vopc<0xa0, 0xe0>, "v_cmp_f_i64">; 711defm V_CMP_LT_I64 : VOPC_I64 <vopc<0xa1, 0xe1>, "v_cmp_lt_i64", COND_SLT, "v_cmp_gt_i64">; 712defm V_CMP_EQ_I64 : VOPC_I64 <vopc<0xa2, 0xe2>, "v_cmp_eq_i64", COND_EQ>; 713defm V_CMP_LE_I64 : VOPC_I64 <vopc<0xa3, 0xe3>, "v_cmp_le_i64", COND_SLE, "v_cmp_ge_i64">; 714defm V_CMP_GT_I64 : VOPC_I64 <vopc<0xa4, 0xe4>, "v_cmp_gt_i64", COND_SGT>; 715defm V_CMP_NE_I64 : VOPC_I64 <vopc<0xa5, 0xe5>, "v_cmp_ne_i64", COND_NE>; 716defm V_CMP_GE_I64 : VOPC_I64 <vopc<0xa6, 0xe6>, "v_cmp_ge_i64", COND_SGE>; 717defm V_CMP_T_I64 : VOPC_I64 <vopc<0xa7, 0xe7>, "v_cmp_t_i64">; 718 719 720defm V_CMPX_F_I64 : VOPCX_I64 <vopc<0xb0, 0xf0>, "v_cmpx_f_i64">; 721defm V_CMPX_LT_I64 : VOPCX_I64 <vopc<0xb1, 0xf1>, "v_cmpx_lt_i64", "v_cmpx_gt_i64">; 722defm V_CMPX_EQ_I64 : VOPCX_I64 <vopc<0xb2, 0xf2>, "v_cmpx_eq_i64">; 723defm V_CMPX_LE_I64 : VOPCX_I64 <vopc<0xb3, 0xf3>, "v_cmpx_le_i64", "v_cmpx_ge_i64">; 724defm V_CMPX_GT_I64 : VOPCX_I64 <vopc<0xb4, 0xf4>, "v_cmpx_gt_i64">; 725defm V_CMPX_NE_I64 : VOPCX_I64 <vopc<0xb5, 0xf5>, "v_cmpx_ne_i64">; 726defm V_CMPX_GE_I64 : VOPCX_I64 <vopc<0xb6, 0xf6>, "v_cmpx_ge_i64">; 727defm V_CMPX_T_I64 : VOPCX_I64 <vopc<0xb7, 0xf7>, "v_cmpx_t_i64">; 728 729 730defm V_CMP_F_U32 : VOPC_I32 <vopc<0xc0, 0xc8>, "v_cmp_f_u32">; 731defm V_CMP_LT_U32 : VOPC_I32 <vopc<0xc1, 0xc9>, "v_cmp_lt_u32", COND_ULT, "v_cmp_gt_u32">; 732defm V_CMP_EQ_U32 : VOPC_I32 <vopc<0xc2, 0xca>, "v_cmp_eq_u32", COND_EQ>; 733defm V_CMP_LE_U32 : VOPC_I32 <vopc<0xc3, 0xcb>, "v_cmp_le_u32", COND_ULE, "v_cmp_ge_u32">; 734defm V_CMP_GT_U32 : VOPC_I32 <vopc<0xc4, 0xcc>, "v_cmp_gt_u32", COND_UGT>; 735defm V_CMP_NE_U32 : VOPC_I32 <vopc<0xc5, 0xcd>, "v_cmp_ne_u32", COND_NE>; 736defm V_CMP_GE_U32 : VOPC_I32 <vopc<0xc6, 0xce>, "v_cmp_ge_u32", COND_UGE>; 737defm V_CMP_T_U32 : VOPC_I32 <vopc<0xc7, 0xcf>, "v_cmp_t_u32">; 738 739 740defm V_CMPX_F_U32 : VOPCX_I32 <vopc<0xd0, 0xd8>, "v_cmpx_f_u32">; 741defm V_CMPX_LT_U32 : VOPCX_I32 <vopc<0xd1, 0xd9>, "v_cmpx_lt_u32", "v_cmpx_gt_u32">; 742defm V_CMPX_EQ_U32 : VOPCX_I32 <vopc<0xd2, 0xda>, "v_cmpx_eq_u32">; 743defm V_CMPX_LE_U32 : VOPCX_I32 <vopc<0xd3, 0xdb>, "v_cmpx_le_u32", "v_cmpx_le_u32">; 744defm V_CMPX_GT_U32 : VOPCX_I32 <vopc<0xd4, 0xdc>, "v_cmpx_gt_u32">; 745defm V_CMPX_NE_U32 : VOPCX_I32 <vopc<0xd5, 0xdd>, "v_cmpx_ne_u32">; 746defm V_CMPX_GE_U32 : VOPCX_I32 <vopc<0xd6, 0xde>, "v_cmpx_ge_u32">; 747defm V_CMPX_T_U32 : VOPCX_I32 <vopc<0xd7, 0xdf>, "v_cmpx_t_u32">; 748 749 750defm V_CMP_F_U64 : VOPC_I64 <vopc<0xe0, 0xe8>, "v_cmp_f_u64">; 751defm V_CMP_LT_U64 : VOPC_I64 <vopc<0xe1, 0xe9>, "v_cmp_lt_u64", COND_ULT, "v_cmp_gt_u64">; 752defm V_CMP_EQ_U64 : VOPC_I64 <vopc<0xe2, 0xea>, "v_cmp_eq_u64", COND_EQ>; 753defm V_CMP_LE_U64 : VOPC_I64 <vopc<0xe3, 0xeb>, "v_cmp_le_u64", COND_ULE, "v_cmp_ge_u64">; 754defm V_CMP_GT_U64 : VOPC_I64 <vopc<0xe4, 0xec>, "v_cmp_gt_u64", COND_UGT>; 755defm V_CMP_NE_U64 : VOPC_I64 <vopc<0xe5, 0xed>, "v_cmp_ne_u64", COND_NE>; 756defm V_CMP_GE_U64 : VOPC_I64 <vopc<0xe6, 0xee>, "v_cmp_ge_u64", COND_UGE>; 757defm V_CMP_T_U64 : VOPC_I64 <vopc<0xe7, 0xef>, "v_cmp_t_u64">; 758 759defm V_CMPX_F_U64 : VOPCX_I64 <vopc<0xf0, 0xf8>, "v_cmpx_f_u64">; 760defm V_CMPX_LT_U64 : VOPCX_I64 <vopc<0xf1, 0xf9>, "v_cmpx_lt_u64", "v_cmpx_gt_u64">; 761defm V_CMPX_EQ_U64 : VOPCX_I64 <vopc<0xf2, 0xfa>, "v_cmpx_eq_u64">; 762defm V_CMPX_LE_U64 : VOPCX_I64 <vopc<0xf3, 0xfb>, "v_cmpx_le_u64", "v_cmpx_ge_u64">; 763defm V_CMPX_GT_U64 : VOPCX_I64 <vopc<0xf4, 0xfc>, "v_cmpx_gt_u64">; 764defm V_CMPX_NE_U64 : VOPCX_I64 <vopc<0xf5, 0xfd>, "v_cmpx_ne_u64">; 765defm V_CMPX_GE_U64 : VOPCX_I64 <vopc<0xf6, 0xfe>, "v_cmpx_ge_u64">; 766defm V_CMPX_T_U64 : VOPCX_I64 <vopc<0xf7, 0xff>, "v_cmpx_t_u64">; 767 768} // End isCompare = 1, isCommutable = 1 769 770defm V_CMP_CLASS_F32 : VOPC_CLASS_F32 <vopc<0x88, 0x10>, "v_cmp_class_f32">; 771defm V_CMPX_CLASS_F32 : VOPCX_CLASS_F32 <vopc<0x98, 0x11>, "v_cmpx_class_f32">; 772defm V_CMP_CLASS_F64 : VOPC_CLASS_F64 <vopc<0xa8, 0x12>, "v_cmp_class_f64">; 773defm V_CMPX_CLASS_F64 : VOPCX_CLASS_F64 <vopc<0xb8, 0x13>, "v_cmpx_class_f64">; 774 775//===----------------------------------------------------------------------===// 776// DS Instructions 777//===----------------------------------------------------------------------===// 778 779defm DS_ADD_U32 : DS_1A1D_NORET <0x0, "ds_add_u32", VGPR_32>; 780defm DS_SUB_U32 : DS_1A1D_NORET <0x1, "ds_sub_u32", VGPR_32>; 781defm DS_RSUB_U32 : DS_1A1D_NORET <0x2, "ds_rsub_u32", VGPR_32>; 782defm DS_INC_U32 : DS_1A1D_NORET <0x3, "ds_inc_u32", VGPR_32>; 783defm DS_DEC_U32 : DS_1A1D_NORET <0x4, "ds_dec_u32", VGPR_32>; 784defm DS_MIN_I32 : DS_1A1D_NORET <0x5, "ds_min_i32", VGPR_32>; 785defm DS_MAX_I32 : DS_1A1D_NORET <0x6, "ds_max_i32", VGPR_32>; 786defm DS_MIN_U32 : DS_1A1D_NORET <0x7, "ds_min_u32", VGPR_32>; 787defm DS_MAX_U32 : DS_1A1D_NORET <0x8, "ds_max_u32", VGPR_32>; 788defm DS_AND_B32 : DS_1A1D_NORET <0x9, "ds_and_b32", VGPR_32>; 789defm DS_OR_B32 : DS_1A1D_NORET <0xa, "ds_or_b32", VGPR_32>; 790defm DS_XOR_B32 : DS_1A1D_NORET <0xb, "ds_xor_b32", VGPR_32>; 791defm DS_MSKOR_B32 : DS_1A2D_NORET <0xc, "ds_mskor_b32", VGPR_32>; 792let mayLoad = 0 in { 793defm DS_WRITE_B32 : DS_1A1D_NORET <0xd, "ds_write_b32", VGPR_32>; 794defm DS_WRITE2_B32 : DS_1A1D_Off8_NORET <0xe, "ds_write2_b32", VGPR_32>; 795defm DS_WRITE2ST64_B32 : DS_1A1D_Off8_NORET <0xf, "ds_write2st64_b32", VGPR_32>; 796} 797defm DS_CMPST_B32 : DS_1A2D_NORET <0x10, "ds_cmpst_b32", VGPR_32>; 798defm DS_CMPST_F32 : DS_1A2D_NORET <0x11, "ds_cmpst_f32", VGPR_32>; 799defm DS_MIN_F32 : DS_1A2D_NORET <0x12, "ds_min_f32", VGPR_32>; 800defm DS_MAX_F32 : DS_1A2D_NORET <0x13, "ds_max_f32", VGPR_32>; 801 802defm DS_GWS_INIT : DS_1A_GDS <0x19, "ds_gws_init">; 803defm DS_GWS_SEMA_V : DS_1A_GDS <0x1a, "ds_gws_sema_v">; 804defm DS_GWS_SEMA_BR : DS_1A_GDS <0x1b, "ds_gws_sema_br">; 805defm DS_GWS_SEMA_P : DS_1A_GDS <0x1c, "ds_gws_sema_p">; 806defm DS_GWS_BARRIER : DS_1A_GDS <0x1d, "ds_gws_barrier">; 807let mayLoad = 0 in { 808defm DS_WRITE_B8 : DS_1A1D_NORET <0x1e, "ds_write_b8", VGPR_32>; 809defm DS_WRITE_B16 : DS_1A1D_NORET <0x1f, "ds_write_b16", VGPR_32>; 810} 811defm DS_ADD_RTN_U32 : DS_1A1D_RET <0x20, "ds_add_rtn_u32", VGPR_32, "ds_add_u32">; 812defm DS_SUB_RTN_U32 : DS_1A1D_RET <0x21, "ds_sub_rtn_u32", VGPR_32, "ds_sub_u32">; 813defm DS_RSUB_RTN_U32 : DS_1A1D_RET <0x22, "ds_rsub_rtn_u32", VGPR_32, "ds_rsub_u32">; 814defm DS_INC_RTN_U32 : DS_1A1D_RET <0x23, "ds_inc_rtn_u32", VGPR_32, "ds_inc_u32">; 815defm DS_DEC_RTN_U32 : DS_1A1D_RET <0x24, "ds_dec_rtn_u32", VGPR_32, "ds_dec_u32">; 816defm DS_MIN_RTN_I32 : DS_1A1D_RET <0x25, "ds_min_rtn_i32", VGPR_32, "ds_min_i32">; 817defm DS_MAX_RTN_I32 : DS_1A1D_RET <0x26, "ds_max_rtn_i32", VGPR_32, "ds_max_i32">; 818defm DS_MIN_RTN_U32 : DS_1A1D_RET <0x27, "ds_min_rtn_u32", VGPR_32, "ds_min_u32">; 819defm DS_MAX_RTN_U32 : DS_1A1D_RET <0x28, "ds_max_rtn_u32", VGPR_32, "ds_max_u32">; 820defm DS_AND_RTN_B32 : DS_1A1D_RET <0x29, "ds_and_rtn_b32", VGPR_32, "ds_and_b32">; 821defm DS_OR_RTN_B32 : DS_1A1D_RET <0x2a, "ds_or_rtn_b32", VGPR_32, "ds_or_b32">; 822defm DS_XOR_RTN_B32 : DS_1A1D_RET <0x2b, "ds_xor_rtn_b32", VGPR_32, "ds_xor_b32">; 823defm DS_MSKOR_RTN_B32 : DS_1A2D_RET <0x2c, "ds_mskor_rtn_b32", VGPR_32, "ds_mskor_b32">; 824defm DS_WRXCHG_RTN_B32 : DS_1A1D_RET <0x2d, "ds_wrxchg_rtn_b32", VGPR_32>; 825defm DS_WRXCHG2_RTN_B32 : DS_1A2D_RET < 826 0x2e, "ds_wrxchg2_rtn_b32", VReg_64, "", VGPR_32 827>; 828defm DS_WRXCHG2ST64_RTN_B32 : DS_1A2D_RET < 829 0x2f, "ds_wrxchg2st64_rtn_b32", VReg_64, "", VGPR_32 830>; 831defm DS_CMPST_RTN_B32 : DS_1A2D_RET <0x30, "ds_cmpst_rtn_b32", VGPR_32, "ds_cmpst_b32">; 832defm DS_CMPST_RTN_F32 : DS_1A2D_RET <0x31, "ds_cmpst_rtn_f32", VGPR_32, "ds_cmpst_f32">; 833defm DS_MIN_RTN_F32 : DS_1A2D_RET <0x32, "ds_min_rtn_f32", VGPR_32, "ds_min_f32">; 834defm DS_MAX_RTN_F32 : DS_1A2D_RET <0x33, "ds_max_rtn_f32", VGPR_32, "ds_max_f32">; 835defm DS_SWIZZLE_B32 : DS_1A_RET <0x35, "ds_swizzle_b32", VGPR_32>; 836let mayStore = 0 in { 837defm DS_READ_B32 : DS_1A_RET <0x36, "ds_read_b32", VGPR_32>; 838defm DS_READ2_B32 : DS_1A_Off8_RET <0x37, "ds_read2_b32", VReg_64>; 839defm DS_READ2ST64_B32 : DS_1A_Off8_RET <0x38, "ds_read2st64_b32", VReg_64>; 840defm DS_READ_I8 : DS_1A_RET <0x39, "ds_read_i8", VGPR_32>; 841defm DS_READ_U8 : DS_1A_RET <0x3a, "ds_read_u8", VGPR_32>; 842defm DS_READ_I16 : DS_1A_RET <0x3b, "ds_read_i16", VGPR_32>; 843defm DS_READ_U16 : DS_1A_RET <0x3c, "ds_read_u16", VGPR_32>; 844} 845defm DS_CONSUME : DS_0A_RET <0x3d, "ds_consume">; 846defm DS_APPEND : DS_0A_RET <0x3e, "ds_append">; 847defm DS_ORDERED_COUNT : DS_1A_RET_GDS <0x3f, "ds_ordered_count">; 848defm DS_ADD_U64 : DS_1A1D_NORET <0x40, "ds_add_u64", VReg_64>; 849defm DS_SUB_U64 : DS_1A1D_NORET <0x41, "ds_sub_u64", VReg_64>; 850defm DS_RSUB_U64 : DS_1A1D_NORET <0x42, "ds_rsub_u64", VReg_64>; 851defm DS_INC_U64 : DS_1A1D_NORET <0x43, "ds_inc_u64", VReg_64>; 852defm DS_DEC_U64 : DS_1A1D_NORET <0x44, "ds_dec_u64", VReg_64>; 853defm DS_MIN_I64 : DS_1A1D_NORET <0x45, "ds_min_i64", VReg_64>; 854defm DS_MAX_I64 : DS_1A1D_NORET <0x46, "ds_max_i64", VReg_64>; 855defm DS_MIN_U64 : DS_1A1D_NORET <0x47, "ds_min_u64", VReg_64>; 856defm DS_MAX_U64 : DS_1A1D_NORET <0x48, "ds_max_u64", VReg_64>; 857defm DS_AND_B64 : DS_1A1D_NORET <0x49, "ds_and_b64", VReg_64>; 858defm DS_OR_B64 : DS_1A1D_NORET <0x4a, "ds_or_b64", VReg_64>; 859defm DS_XOR_B64 : DS_1A1D_NORET <0x4b, "ds_xor_b64", VReg_64>; 860defm DS_MSKOR_B64 : DS_1A2D_NORET <0x4c, "ds_mskor_b64", VReg_64>; 861let mayLoad = 0 in { 862defm DS_WRITE_B64 : DS_1A1D_NORET <0x4d, "ds_write_b64", VReg_64>; 863defm DS_WRITE2_B64 : DS_1A1D_Off8_NORET <0x4E, "ds_write2_b64", VReg_64>; 864defm DS_WRITE2ST64_B64 : DS_1A1D_Off8_NORET <0x4f, "ds_write2st64_b64", VReg_64>; 865} 866defm DS_CMPST_B64 : DS_1A2D_NORET <0x50, "ds_cmpst_b64", VReg_64>; 867defm DS_CMPST_F64 : DS_1A2D_NORET <0x51, "ds_cmpst_f64", VReg_64>; 868defm DS_MIN_F64 : DS_1A1D_NORET <0x52, "ds_min_f64", VReg_64>; 869defm DS_MAX_F64 : DS_1A1D_NORET <0x53, "ds_max_f64", VReg_64>; 870 871defm DS_ADD_RTN_U64 : DS_1A1D_RET <0x60, "ds_add_rtn_u64", VReg_64, "ds_add_u64">; 872defm DS_SUB_RTN_U64 : DS_1A1D_RET <0x61, "ds_sub_rtn_u64", VReg_64, "ds_sub_u64">; 873defm DS_RSUB_RTN_U64 : DS_1A1D_RET <0x62, "ds_rsub_rtn_u64", VReg_64, "ds_rsub_u64">; 874defm DS_INC_RTN_U64 : DS_1A1D_RET <0x63, "ds_inc_rtn_u64", VReg_64, "ds_inc_u64">; 875defm DS_DEC_RTN_U64 : DS_1A1D_RET <0x64, "ds_dec_rtn_u64", VReg_64, "ds_dec_u64">; 876defm DS_MIN_RTN_I64 : DS_1A1D_RET <0x65, "ds_min_rtn_i64", VReg_64, "ds_min_i64">; 877defm DS_MAX_RTN_I64 : DS_1A1D_RET <0x66, "ds_max_rtn_i64", VReg_64, "ds_max_i64">; 878defm DS_MIN_RTN_U64 : DS_1A1D_RET <0x67, "ds_min_rtn_u64", VReg_64, "ds_min_u64">; 879defm DS_MAX_RTN_U64 : DS_1A1D_RET <0x68, "ds_max_rtn_u64", VReg_64, "ds_max_u64">; 880defm DS_AND_RTN_B64 : DS_1A1D_RET <0x69, "ds_and_rtn_b64", VReg_64, "ds_and_b64">; 881defm DS_OR_RTN_B64 : DS_1A1D_RET <0x6a, "ds_or_rtn_b64", VReg_64, "ds_or_b64">; 882defm DS_XOR_RTN_B64 : DS_1A1D_RET <0x6b, "ds_xor_rtn_b64", VReg_64, "ds_xor_b64">; 883defm DS_MSKOR_RTN_B64 : DS_1A2D_RET <0x6c, "ds_mskor_rtn_b64", VReg_64, "ds_mskor_b64">; 884defm DS_WRXCHG_RTN_B64 : DS_1A1D_RET <0x6d, "ds_wrxchg_rtn_b64", VReg_64, "ds_wrxchg_b64">; 885defm DS_WRXCHG2_RTN_B64 : DS_1A2D_RET <0x6e, "ds_wrxchg2_rtn_b64", VReg_128, "ds_wrxchg2_b64", VReg_64>; 886defm DS_WRXCHG2ST64_RTN_B64 : DS_1A2D_RET <0x6f, "ds_wrxchg2st64_rtn_b64", VReg_128, "ds_wrxchg2st64_b64", VReg_64>; 887defm DS_CMPST_RTN_B64 : DS_1A2D_RET <0x70, "ds_cmpst_rtn_b64", VReg_64, "ds_cmpst_b64">; 888defm DS_CMPST_RTN_F64 : DS_1A2D_RET <0x71, "ds_cmpst_rtn_f64", VReg_64, "ds_cmpst_f64">; 889defm DS_MIN_RTN_F64 : DS_1A1D_RET <0x72, "ds_min_rtn_f64", VReg_64, "ds_min_f64">; 890defm DS_MAX_RTN_F64 : DS_1A1D_RET <0x73, "ds_max_rtn_f64", VReg_64, "ds_max_f64">; 891 892let mayStore = 0 in { 893defm DS_READ_B64 : DS_1A_RET <0x76, "ds_read_b64", VReg_64>; 894defm DS_READ2_B64 : DS_1A_Off8_RET <0x77, "ds_read2_b64", VReg_128>; 895defm DS_READ2ST64_B64 : DS_1A_Off8_RET <0x78, "ds_read2st64_b64", VReg_128>; 896} 897 898defm DS_ADD_SRC2_U32 : DS_1A <0x80, "ds_add_src2_u32">; 899defm DS_SUB_SRC2_U32 : DS_1A <0x81, "ds_sub_src2_u32">; 900defm DS_RSUB_SRC2_U32 : DS_1A <0x82, "ds_rsub_src2_u32">; 901defm DS_INC_SRC2_U32 : DS_1A <0x83, "ds_inc_src2_u32">; 902defm DS_DEC_SRC2_U32 : DS_1A <0x84, "ds_dec_src2_u32">; 903defm DS_MIN_SRC2_I32 : DS_1A <0x85, "ds_min_src2_i32">; 904defm DS_MAX_SRC2_I32 : DS_1A <0x86, "ds_max_src2_i32">; 905defm DS_MIN_SRC2_U32 : DS_1A <0x87, "ds_min_src2_u32">; 906defm DS_MAX_SRC2_U32 : DS_1A <0x88, "ds_max_src2_u32">; 907defm DS_AND_SRC2_B32 : DS_1A <0x89, "ds_and_src_b32">; 908defm DS_OR_SRC2_B32 : DS_1A <0x8a, "ds_or_src2_b32">; 909defm DS_XOR_SRC2_B32 : DS_1A <0x8b, "ds_xor_src2_b32">; 910defm DS_WRITE_SRC2_B32 : DS_1A <0x8c, "ds_write_src2_b32">; 911 912defm DS_MIN_SRC2_F32 : DS_1A <0x92, "ds_min_src2_f32">; 913defm DS_MAX_SRC2_F32 : DS_1A <0x93, "ds_max_src2_f32">; 914 915defm DS_ADD_SRC2_U64 : DS_1A <0xc0, "ds_add_src2_u64">; 916defm DS_SUB_SRC2_U64 : DS_1A <0xc1, "ds_sub_src2_u64">; 917defm DS_RSUB_SRC2_U64 : DS_1A <0xc2, "ds_rsub_src2_u64">; 918defm DS_INC_SRC2_U64 : DS_1A <0xc3, "ds_inc_src2_u64">; 919defm DS_DEC_SRC2_U64 : DS_1A <0xc4, "ds_dec_src2_u64">; 920defm DS_MIN_SRC2_I64 : DS_1A <0xc5, "ds_min_src2_i64">; 921defm DS_MAX_SRC2_I64 : DS_1A <0xc6, "ds_max_src2_i64">; 922defm DS_MIN_SRC2_U64 : DS_1A <0xc7, "ds_min_src2_u64">; 923defm DS_MAX_SRC2_U64 : DS_1A <0xc8, "ds_max_src2_u64">; 924defm DS_AND_SRC2_B64 : DS_1A <0xc9, "ds_and_src2_b64">; 925defm DS_OR_SRC2_B64 : DS_1A <0xca, "ds_or_src2_b64">; 926defm DS_XOR_SRC2_B64 : DS_1A <0xcb, "ds_xor_src2_b64">; 927defm DS_WRITE_SRC2_B64 : DS_1A <0xcc, "ds_write_src2_b64">; 928 929defm DS_MIN_SRC2_F64 : DS_1A <0xd2, "ds_min_src2_f64">; 930defm DS_MAX_SRC2_F64 : DS_1A <0xd3, "ds_max_src2_f64">; 931 932//===----------------------------------------------------------------------===// 933// MUBUF Instructions 934//===----------------------------------------------------------------------===// 935 936defm BUFFER_LOAD_FORMAT_X : MUBUF_Load_Helper < 937 mubuf<0x00>, "buffer_load_format_x", VGPR_32 938>; 939defm BUFFER_LOAD_FORMAT_XY : MUBUF_Load_Helper < 940 mubuf<0x01>, "buffer_load_format_xy", VReg_64 941>; 942defm BUFFER_LOAD_FORMAT_XYZ : MUBUF_Load_Helper < 943 mubuf<0x02>, "buffer_load_format_xyz", VReg_96 944>; 945defm BUFFER_LOAD_FORMAT_XYZW : MUBUF_Load_Helper < 946 mubuf<0x03>, "buffer_load_format_xyzw", VReg_128 947>; 948defm BUFFER_STORE_FORMAT_X : MUBUF_Store_Helper < 949 mubuf<0x04>, "buffer_store_format_x", VGPR_32 950>; 951defm BUFFER_STORE_FORMAT_XY : MUBUF_Store_Helper < 952 mubuf<0x05>, "buffer_store_format_xy", VReg_64 953>; 954defm BUFFER_STORE_FORMAT_XYZ : MUBUF_Store_Helper < 955 mubuf<0x06>, "buffer_store_format_xyz", VReg_96 956>; 957defm BUFFER_STORE_FORMAT_XYZW : MUBUF_Store_Helper < 958 mubuf<0x07>, "buffer_store_format_xyzw", VReg_128 959>; 960defm BUFFER_LOAD_UBYTE : MUBUF_Load_Helper < 961 mubuf<0x08, 0x10>, "buffer_load_ubyte", VGPR_32, i32, az_extloadi8_global 962>; 963defm BUFFER_LOAD_SBYTE : MUBUF_Load_Helper < 964 mubuf<0x09, 0x11>, "buffer_load_sbyte", VGPR_32, i32, sextloadi8_global 965>; 966defm BUFFER_LOAD_USHORT : MUBUF_Load_Helper < 967 mubuf<0x0a, 0x12>, "buffer_load_ushort", VGPR_32, i32, az_extloadi16_global 968>; 969defm BUFFER_LOAD_SSHORT : MUBUF_Load_Helper < 970 mubuf<0x0b, 0x13>, "buffer_load_sshort", VGPR_32, i32, sextloadi16_global 971>; 972defm BUFFER_LOAD_DWORD : MUBUF_Load_Helper < 973 mubuf<0x0c, 0x14>, "buffer_load_dword", VGPR_32, i32, mubuf_load 974>; 975defm BUFFER_LOAD_DWORDX2 : MUBUF_Load_Helper < 976 mubuf<0x0d, 0x15>, "buffer_load_dwordx2", VReg_64, v2i32, mubuf_load 977>; 978defm BUFFER_LOAD_DWORDX4 : MUBUF_Load_Helper < 979 mubuf<0x0e, 0x17>, "buffer_load_dwordx4", VReg_128, v4i32, mubuf_load 980>; 981 982defm BUFFER_STORE_BYTE : MUBUF_Store_Helper < 983 mubuf<0x18>, "buffer_store_byte", VGPR_32, i32, truncstorei8_global 984>; 985 986defm BUFFER_STORE_SHORT : MUBUF_Store_Helper < 987 mubuf<0x1a>, "buffer_store_short", VGPR_32, i32, truncstorei16_global 988>; 989 990defm BUFFER_STORE_DWORD : MUBUF_Store_Helper < 991 mubuf<0x1c>, "buffer_store_dword", VGPR_32, i32, global_store 992>; 993 994defm BUFFER_STORE_DWORDX2 : MUBUF_Store_Helper < 995 mubuf<0x1d>, "buffer_store_dwordx2", VReg_64, v2i32, global_store 996>; 997 998defm BUFFER_STORE_DWORDX4 : MUBUF_Store_Helper < 999 mubuf<0x1e, 0x1f>, "buffer_store_dwordx4", VReg_128, v4i32, global_store 1000>; 1001 1002defm BUFFER_ATOMIC_SWAP : MUBUF_Atomic < 1003 mubuf<0x30, 0x40>, "buffer_atomic_swap", VGPR_32, i32, atomic_swap_global 1004>; 1005//def BUFFER_ATOMIC_CMPSWAP : MUBUF_ <mubuf<0x31, 0x41>, "buffer_atomic_cmpswap", []>; 1006defm BUFFER_ATOMIC_ADD : MUBUF_Atomic < 1007 mubuf<0x32, 0x42>, "buffer_atomic_add", VGPR_32, i32, atomic_add_global 1008>; 1009defm BUFFER_ATOMIC_SUB : MUBUF_Atomic < 1010 mubuf<0x33, 0x43>, "buffer_atomic_sub", VGPR_32, i32, atomic_sub_global 1011>; 1012//def BUFFER_ATOMIC_RSUB : MUBUF_ <mubuf<0x34>, "buffer_atomic_rsub", []>; // isn't on CI & VI 1013defm BUFFER_ATOMIC_SMIN : MUBUF_Atomic < 1014 mubuf<0x35, 0x44>, "buffer_atomic_smin", VGPR_32, i32, atomic_min_global 1015>; 1016defm BUFFER_ATOMIC_UMIN : MUBUF_Atomic < 1017 mubuf<0x36, 0x45>, "buffer_atomic_umin", VGPR_32, i32, atomic_umin_global 1018>; 1019defm BUFFER_ATOMIC_SMAX : MUBUF_Atomic < 1020 mubuf<0x37, 0x46>, "buffer_atomic_smax", VGPR_32, i32, atomic_max_global 1021>; 1022defm BUFFER_ATOMIC_UMAX : MUBUF_Atomic < 1023 mubuf<0x38, 0x47>, "buffer_atomic_umax", VGPR_32, i32, atomic_umax_global 1024>; 1025defm BUFFER_ATOMIC_AND : MUBUF_Atomic < 1026 mubuf<0x39, 0x48>, "buffer_atomic_and", VGPR_32, i32, atomic_and_global 1027>; 1028defm BUFFER_ATOMIC_OR : MUBUF_Atomic < 1029 mubuf<0x3a, 0x49>, "buffer_atomic_or", VGPR_32, i32, atomic_or_global 1030>; 1031defm BUFFER_ATOMIC_XOR : MUBUF_Atomic < 1032 mubuf<0x3b, 0x4a>, "buffer_atomic_xor", VGPR_32, i32, atomic_xor_global 1033>; 1034//def BUFFER_ATOMIC_INC : MUBUF_ <mubuf<0x3c, 0x4b>, "buffer_atomic_inc", []>; 1035//def BUFFER_ATOMIC_DEC : MUBUF_ <mubuf<0x3d, 0x4c>, "buffer_atomic_dec", []>; 1036//def BUFFER_ATOMIC_FCMPSWAP : MUBUF_ <mubuf<0x3e>, "buffer_atomic_fcmpswap", []>; // isn't on VI 1037//def BUFFER_ATOMIC_FMIN : MUBUF_ <mubuf<0x3f>, "buffer_atomic_fmin", []>; // isn't on VI 1038//def BUFFER_ATOMIC_FMAX : MUBUF_ <mubuf<0x40>, "buffer_atomic_fmax", []>; // isn't on VI 1039//def BUFFER_ATOMIC_SWAP_X2 : MUBUF_X2 <mubuf<0x50, 0x60>, "buffer_atomic_swap_x2", []>; 1040//def BUFFER_ATOMIC_CMPSWAP_X2 : MUBUF_X2 <mubuf<0x51, 0x61>, "buffer_atomic_cmpswap_x2", []>; 1041//def BUFFER_ATOMIC_ADD_X2 : MUBUF_X2 <mubuf<0x52, 0x62>, "buffer_atomic_add_x2", []>; 1042//def BUFFER_ATOMIC_SUB_X2 : MUBUF_X2 <mubuf<0x53, 0x63>, "buffer_atomic_sub_x2", []>; 1043//def BUFFER_ATOMIC_RSUB_X2 : MUBUF_X2 <mubuf<0x54>, "buffer_atomic_rsub_x2", []>; // isn't on CI & VI 1044//def BUFFER_ATOMIC_SMIN_X2 : MUBUF_X2 <mubuf<0x55, 0x64>, "buffer_atomic_smin_x2", []>; 1045//def BUFFER_ATOMIC_UMIN_X2 : MUBUF_X2 <mubuf<0x56, 0x65>, "buffer_atomic_umin_x2", []>; 1046//def BUFFER_ATOMIC_SMAX_X2 : MUBUF_X2 <mubuf<0x57, 0x66>, "buffer_atomic_smax_x2", []>; 1047//def BUFFER_ATOMIC_UMAX_X2 : MUBUF_X2 <mubuf<0x58, 0x67>, "buffer_atomic_umax_x2", []>; 1048//def BUFFER_ATOMIC_AND_X2 : MUBUF_X2 <mubuf<0x59, 0x68>, "buffer_atomic_and_x2", []>; 1049//def BUFFER_ATOMIC_OR_X2 : MUBUF_X2 <mubuf<0x5a, 0x69>, "buffer_atomic_or_x2", []>; 1050//def BUFFER_ATOMIC_XOR_X2 : MUBUF_X2 <mubuf<0x5b, 0x6a>, "buffer_atomic_xor_x2", []>; 1051//def BUFFER_ATOMIC_INC_X2 : MUBUF_X2 <mubuf<0x5c, 0x6b>, "buffer_atomic_inc_x2", []>; 1052//def BUFFER_ATOMIC_DEC_X2 : MUBUF_X2 <mubuf<0x5d, 0x6c>, "buffer_atomic_dec_x2", []>; 1053//def BUFFER_ATOMIC_FCMPSWAP_X2 : MUBUF_X2 <mubuf<0x5e>, "buffer_atomic_fcmpswap_x2", []>; // isn't on VI 1054//def BUFFER_ATOMIC_FMIN_X2 : MUBUF_X2 <mubuf<0x5f>, "buffer_atomic_fmin_x2", []>; // isn't on VI 1055//def BUFFER_ATOMIC_FMAX_X2 : MUBUF_X2 <mubuf<0x60>, "buffer_atomic_fmax_x2", []>; // isn't on VI 1056 1057let SubtargetPredicate = isSI, DisableVIDecoder = 1 in { 1058defm BUFFER_WBINVL1_SC : MUBUF_Invalidate <mubuf<0x70>, "buffer_wbinvl1_sc", int_amdgcn_buffer_wbinvl1_sc>; // isn't on CI & VI 1059} 1060 1061defm BUFFER_WBINVL1 : MUBUF_Invalidate <mubuf<0x71, 0x3e>, "buffer_wbinvl1", int_amdgcn_buffer_wbinvl1>; 1062 1063//===----------------------------------------------------------------------===// 1064// MTBUF Instructions 1065//===----------------------------------------------------------------------===// 1066 1067//def TBUFFER_LOAD_FORMAT_X : MTBUF_ <0x00000000, "tbuffer_load_format_x", []>; 1068//def TBUFFER_LOAD_FORMAT_XY : MTBUF_ <0x00000001, "tbuffer_load_format_xy", []>; 1069//def TBUFFER_LOAD_FORMAT_XYZ : MTBUF_ <0x00000002, "tbuffer_load_format_xyz", []>; 1070defm TBUFFER_LOAD_FORMAT_XYZW : MTBUF_Load_Helper <0x00000003, "tbuffer_load_format_xyzw", VReg_128>; 1071defm TBUFFER_STORE_FORMAT_X : MTBUF_Store_Helper <0x00000004, "tbuffer_store_format_x", VGPR_32>; 1072defm TBUFFER_STORE_FORMAT_XY : MTBUF_Store_Helper <0x00000005, "tbuffer_store_format_xy", VReg_64>; 1073defm TBUFFER_STORE_FORMAT_XYZ : MTBUF_Store_Helper <0x00000006, "tbuffer_store_format_xyz", VReg_128>; 1074defm TBUFFER_STORE_FORMAT_XYZW : MTBUF_Store_Helper <0x00000007, "tbuffer_store_format_xyzw", VReg_128>; 1075 1076//===----------------------------------------------------------------------===// 1077// MIMG Instructions 1078//===----------------------------------------------------------------------===// 1079 1080defm IMAGE_LOAD : MIMG_NoSampler <0x00000000, "image_load">; 1081defm IMAGE_LOAD_MIP : MIMG_NoSampler <0x00000001, "image_load_mip">; 1082//def IMAGE_LOAD_PCK : MIMG_NoPattern_ <"image_load_pck", 0x00000002>; 1083//def IMAGE_LOAD_PCK_SGN : MIMG_NoPattern_ <"image_load_pck_sgn", 0x00000003>; 1084//def IMAGE_LOAD_MIP_PCK : MIMG_NoPattern_ <"image_load_mip_pck", 0x00000004>; 1085//def IMAGE_LOAD_MIP_PCK_SGN : MIMG_NoPattern_ <"image_load_mip_pck_sgn", 0x00000005>; 1086defm IMAGE_STORE : MIMG_Store <0x00000008, "image_store">; 1087defm IMAGE_STORE_MIP : MIMG_Store <0x00000009, "image_store_mip">; 1088//def IMAGE_STORE_PCK : MIMG_NoPattern_ <"image_store_pck", 0x0000000a>; 1089//def IMAGE_STORE_MIP_PCK : MIMG_NoPattern_ <"image_store_mip_pck", 0x0000000b>; 1090defm IMAGE_GET_RESINFO : MIMG_NoSampler <0x0000000e, "image_get_resinfo">; 1091//def IMAGE_ATOMIC_SWAP : MIMG_NoPattern_ <"image_atomic_swap", 0x0000000f>; 1092//def IMAGE_ATOMIC_CMPSWAP : MIMG_NoPattern_ <"image_atomic_cmpswap", 0x00000010>; 1093//def IMAGE_ATOMIC_ADD : MIMG_NoPattern_ <"image_atomic_add", 0x00000011>; 1094//def IMAGE_ATOMIC_SUB : MIMG_NoPattern_ <"image_atomic_sub", 0x00000012>; 1095//def IMAGE_ATOMIC_RSUB : MIMG_NoPattern_ <"image_atomic_rsub", 0x00000013>; 1096//def IMAGE_ATOMIC_SMIN : MIMG_NoPattern_ <"image_atomic_smin", 0x00000014>; 1097//def IMAGE_ATOMIC_UMIN : MIMG_NoPattern_ <"image_atomic_umin", 0x00000015>; 1098//def IMAGE_ATOMIC_SMAX : MIMG_NoPattern_ <"image_atomic_smax", 0x00000016>; 1099//def IMAGE_ATOMIC_UMAX : MIMG_NoPattern_ <"image_atomic_umax", 0x00000017>; 1100//def IMAGE_ATOMIC_AND : MIMG_NoPattern_ <"image_atomic_and", 0x00000018>; 1101//def IMAGE_ATOMIC_OR : MIMG_NoPattern_ <"image_atomic_or", 0x00000019>; 1102//def IMAGE_ATOMIC_XOR : MIMG_NoPattern_ <"image_atomic_xor", 0x0000001a>; 1103//def IMAGE_ATOMIC_INC : MIMG_NoPattern_ <"image_atomic_inc", 0x0000001b>; 1104//def IMAGE_ATOMIC_DEC : MIMG_NoPattern_ <"image_atomic_dec", 0x0000001c>; 1105//def IMAGE_ATOMIC_FCMPSWAP : MIMG_NoPattern_ <"image_atomic_fcmpswap", 0x0000001d>; 1106//def IMAGE_ATOMIC_FMIN : MIMG_NoPattern_ <"image_atomic_fmin", 0x0000001e>; 1107//def IMAGE_ATOMIC_FMAX : MIMG_NoPattern_ <"image_atomic_fmax", 0x0000001f>; 1108defm IMAGE_SAMPLE : MIMG_Sampler_WQM <0x00000020, "image_sample">; 1109defm IMAGE_SAMPLE_CL : MIMG_Sampler_WQM <0x00000021, "image_sample_cl">; 1110defm IMAGE_SAMPLE_D : MIMG_Sampler <0x00000022, "image_sample_d">; 1111defm IMAGE_SAMPLE_D_CL : MIMG_Sampler <0x00000023, "image_sample_d_cl">; 1112defm IMAGE_SAMPLE_L : MIMG_Sampler <0x00000024, "image_sample_l">; 1113defm IMAGE_SAMPLE_B : MIMG_Sampler_WQM <0x00000025, "image_sample_b">; 1114defm IMAGE_SAMPLE_B_CL : MIMG_Sampler_WQM <0x00000026, "image_sample_b_cl">; 1115defm IMAGE_SAMPLE_LZ : MIMG_Sampler <0x00000027, "image_sample_lz">; 1116defm IMAGE_SAMPLE_C : MIMG_Sampler_WQM <0x00000028, "image_sample_c">; 1117defm IMAGE_SAMPLE_C_CL : MIMG_Sampler_WQM <0x00000029, "image_sample_c_cl">; 1118defm IMAGE_SAMPLE_C_D : MIMG_Sampler <0x0000002a, "image_sample_c_d">; 1119defm IMAGE_SAMPLE_C_D_CL : MIMG_Sampler <0x0000002b, "image_sample_c_d_cl">; 1120defm IMAGE_SAMPLE_C_L : MIMG_Sampler <0x0000002c, "image_sample_c_l">; 1121defm IMAGE_SAMPLE_C_B : MIMG_Sampler_WQM <0x0000002d, "image_sample_c_b">; 1122defm IMAGE_SAMPLE_C_B_CL : MIMG_Sampler_WQM <0x0000002e, "image_sample_c_b_cl">; 1123defm IMAGE_SAMPLE_C_LZ : MIMG_Sampler <0x0000002f, "image_sample_c_lz">; 1124defm IMAGE_SAMPLE_O : MIMG_Sampler_WQM <0x00000030, "image_sample_o">; 1125defm IMAGE_SAMPLE_CL_O : MIMG_Sampler_WQM <0x00000031, "image_sample_cl_o">; 1126defm IMAGE_SAMPLE_D_O : MIMG_Sampler <0x00000032, "image_sample_d_o">; 1127defm IMAGE_SAMPLE_D_CL_O : MIMG_Sampler <0x00000033, "image_sample_d_cl_o">; 1128defm IMAGE_SAMPLE_L_O : MIMG_Sampler <0x00000034, "image_sample_l_o">; 1129defm IMAGE_SAMPLE_B_O : MIMG_Sampler_WQM <0x00000035, "image_sample_b_o">; 1130defm IMAGE_SAMPLE_B_CL_O : MIMG_Sampler_WQM <0x00000036, "image_sample_b_cl_o">; 1131defm IMAGE_SAMPLE_LZ_O : MIMG_Sampler <0x00000037, "image_sample_lz_o">; 1132defm IMAGE_SAMPLE_C_O : MIMG_Sampler_WQM <0x00000038, "image_sample_c_o">; 1133defm IMAGE_SAMPLE_C_CL_O : MIMG_Sampler_WQM <0x00000039, "image_sample_c_cl_o">; 1134defm IMAGE_SAMPLE_C_D_O : MIMG_Sampler <0x0000003a, "image_sample_c_d_o">; 1135defm IMAGE_SAMPLE_C_D_CL_O : MIMG_Sampler <0x0000003b, "image_sample_c_d_cl_o">; 1136defm IMAGE_SAMPLE_C_L_O : MIMG_Sampler <0x0000003c, "image_sample_c_l_o">; 1137defm IMAGE_SAMPLE_C_B_O : MIMG_Sampler_WQM <0x0000003d, "image_sample_c_b_o">; 1138defm IMAGE_SAMPLE_C_B_CL_O : MIMG_Sampler_WQM <0x0000003e, "image_sample_c_b_cl_o">; 1139defm IMAGE_SAMPLE_C_LZ_O : MIMG_Sampler <0x0000003f, "image_sample_c_lz_o">; 1140defm IMAGE_GATHER4 : MIMG_Gather_WQM <0x00000040, "image_gather4">; 1141defm IMAGE_GATHER4_CL : MIMG_Gather_WQM <0x00000041, "image_gather4_cl">; 1142defm IMAGE_GATHER4_L : MIMG_Gather <0x00000044, "image_gather4_l">; 1143defm IMAGE_GATHER4_B : MIMG_Gather_WQM <0x00000045, "image_gather4_b">; 1144defm IMAGE_GATHER4_B_CL : MIMG_Gather_WQM <0x00000046, "image_gather4_b_cl">; 1145defm IMAGE_GATHER4_LZ : MIMG_Gather <0x00000047, "image_gather4_lz">; 1146defm IMAGE_GATHER4_C : MIMG_Gather_WQM <0x00000048, "image_gather4_c">; 1147defm IMAGE_GATHER4_C_CL : MIMG_Gather_WQM <0x00000049, "image_gather4_c_cl">; 1148defm IMAGE_GATHER4_C_L : MIMG_Gather <0x0000004c, "image_gather4_c_l">; 1149defm IMAGE_GATHER4_C_B : MIMG_Gather_WQM <0x0000004d, "image_gather4_c_b">; 1150defm IMAGE_GATHER4_C_B_CL : MIMG_Gather_WQM <0x0000004e, "image_gather4_c_b_cl">; 1151defm IMAGE_GATHER4_C_LZ : MIMG_Gather <0x0000004f, "image_gather4_c_lz">; 1152defm IMAGE_GATHER4_O : MIMG_Gather_WQM <0x00000050, "image_gather4_o">; 1153defm IMAGE_GATHER4_CL_O : MIMG_Gather_WQM <0x00000051, "image_gather4_cl_o">; 1154defm IMAGE_GATHER4_L_O : MIMG_Gather <0x00000054, "image_gather4_l_o">; 1155defm IMAGE_GATHER4_B_O : MIMG_Gather_WQM <0x00000055, "image_gather4_b_o">; 1156defm IMAGE_GATHER4_B_CL_O : MIMG_Gather <0x00000056, "image_gather4_b_cl_o">; 1157defm IMAGE_GATHER4_LZ_O : MIMG_Gather <0x00000057, "image_gather4_lz_o">; 1158defm IMAGE_GATHER4_C_O : MIMG_Gather_WQM <0x00000058, "image_gather4_c_o">; 1159defm IMAGE_GATHER4_C_CL_O : MIMG_Gather_WQM <0x00000059, "image_gather4_c_cl_o">; 1160defm IMAGE_GATHER4_C_L_O : MIMG_Gather <0x0000005c, "image_gather4_c_l_o">; 1161defm IMAGE_GATHER4_C_B_O : MIMG_Gather_WQM <0x0000005d, "image_gather4_c_b_o">; 1162defm IMAGE_GATHER4_C_B_CL_O : MIMG_Gather_WQM <0x0000005e, "image_gather4_c_b_cl_o">; 1163defm IMAGE_GATHER4_C_LZ_O : MIMG_Gather <0x0000005f, "image_gather4_c_lz_o">; 1164defm IMAGE_GET_LOD : MIMG_Sampler_WQM <0x00000060, "image_get_lod">; 1165defm IMAGE_SAMPLE_CD : MIMG_Sampler <0x00000068, "image_sample_cd">; 1166defm IMAGE_SAMPLE_CD_CL : MIMG_Sampler <0x00000069, "image_sample_cd_cl">; 1167defm IMAGE_SAMPLE_C_CD : MIMG_Sampler <0x0000006a, "image_sample_c_cd">; 1168defm IMAGE_SAMPLE_C_CD_CL : MIMG_Sampler <0x0000006b, "image_sample_c_cd_cl">; 1169defm IMAGE_SAMPLE_CD_O : MIMG_Sampler <0x0000006c, "image_sample_cd_o">; 1170defm IMAGE_SAMPLE_CD_CL_O : MIMG_Sampler <0x0000006d, "image_sample_cd_cl_o">; 1171defm IMAGE_SAMPLE_C_CD_O : MIMG_Sampler <0x0000006e, "image_sample_c_cd_o">; 1172defm IMAGE_SAMPLE_C_CD_CL_O : MIMG_Sampler <0x0000006f, "image_sample_c_cd_cl_o">; 1173//def IMAGE_RSRC256 : MIMG_NoPattern_RSRC256 <"image_rsrc256", 0x0000007e>; 1174//def IMAGE_SAMPLER : MIMG_NoPattern_ <"image_sampler", 0x0000007f>; 1175 1176//===----------------------------------------------------------------------===// 1177// VOP1 Instructions 1178//===----------------------------------------------------------------------===// 1179 1180let vdst = 0, src0 = 0, VOPAsmPrefer32Bit = 1 in { 1181defm V_NOP : VOP1Inst <vop1<0x0>, "v_nop", VOP_NONE>; 1182} 1183 1184let isMoveImm = 1, isReMaterializable = 1, isAsCheapAsAMove = 1 in { 1185defm V_MOV_B32 : VOP1Inst <vop1<0x1>, "v_mov_b32", VOP_I32_I32>; 1186} // End isMoveImm = 1 1187 1188let Uses = [EXEC] in { 1189 1190// FIXME: Specify SchedRW for READFIRSTLANE_B32 1191 1192def V_READFIRSTLANE_B32 : VOP1 < 1193 0x00000002, 1194 (outs SReg_32:$vdst), 1195 (ins VGPR_32:$src0), 1196 "v_readfirstlane_b32 $vdst, $src0", 1197 [] 1198>; 1199 1200} 1201 1202let SchedRW = [WriteQuarterRate32] in { 1203 1204defm V_CVT_I32_F64 : VOP1Inst <vop1<0x3>, "v_cvt_i32_f64", 1205 VOP_I32_F64, fp_to_sint 1206>; 1207defm V_CVT_F64_I32 : VOP1Inst <vop1<0x4>, "v_cvt_f64_i32", 1208 VOP_F64_I32, sint_to_fp 1209>; 1210defm V_CVT_F32_I32 : VOP1Inst <vop1<0x5>, "v_cvt_f32_i32", 1211 VOP_F32_I32, sint_to_fp 1212>; 1213defm V_CVT_F32_U32 : VOP1Inst <vop1<0x6>, "v_cvt_f32_u32", 1214 VOP_F32_I32, uint_to_fp 1215>; 1216defm V_CVT_U32_F32 : VOP1Inst <vop1<0x7>, "v_cvt_u32_f32", 1217 VOP_I32_F32, fp_to_uint 1218>; 1219defm V_CVT_I32_F32 : VOP1Inst <vop1<0x8>, "v_cvt_i32_f32", 1220 VOP_I32_F32, fp_to_sint 1221>; 1222defm V_CVT_F16_F32 : VOP1Inst <vop1<0xa>, "v_cvt_f16_f32", 1223 VOP_I32_F32, fp_to_f16 1224>; 1225defm V_CVT_F32_F16 : VOP1Inst <vop1<0xb>, "v_cvt_f32_f16", 1226 VOP_F32_I32, f16_to_fp 1227>; 1228defm V_CVT_RPI_I32_F32 : VOP1Inst <vop1<0xc>, "v_cvt_rpi_i32_f32", 1229 VOP_I32_F32, cvt_rpi_i32_f32>; 1230defm V_CVT_FLR_I32_F32 : VOP1Inst <vop1<0xd>, "v_cvt_flr_i32_f32", 1231 VOP_I32_F32, cvt_flr_i32_f32>; 1232defm V_CVT_OFF_F32_I4 : VOP1Inst <vop1<0x0e>, "v_cvt_off_f32_i4", VOP_F32_I32>; 1233defm V_CVT_F32_F64 : VOP1Inst <vop1<0xf>, "v_cvt_f32_f64", 1234 VOP_F32_F64, fround 1235>; 1236defm V_CVT_F64_F32 : VOP1Inst <vop1<0x10>, "v_cvt_f64_f32", 1237 VOP_F64_F32, fextend 1238>; 1239defm V_CVT_F32_UBYTE0 : VOP1Inst <vop1<0x11>, "v_cvt_f32_ubyte0", 1240 VOP_F32_I32, AMDGPUcvt_f32_ubyte0 1241>; 1242defm V_CVT_F32_UBYTE1 : VOP1Inst <vop1<0x12>, "v_cvt_f32_ubyte1", 1243 VOP_F32_I32, AMDGPUcvt_f32_ubyte1 1244>; 1245defm V_CVT_F32_UBYTE2 : VOP1Inst <vop1<0x13>, "v_cvt_f32_ubyte2", 1246 VOP_F32_I32, AMDGPUcvt_f32_ubyte2 1247>; 1248defm V_CVT_F32_UBYTE3 : VOP1Inst <vop1<0x14>, "v_cvt_f32_ubyte3", 1249 VOP_F32_I32, AMDGPUcvt_f32_ubyte3 1250>; 1251defm V_CVT_U32_F64 : VOP1Inst <vop1<0x15>, "v_cvt_u32_f64", 1252 VOP_I32_F64, fp_to_uint 1253>; 1254defm V_CVT_F64_U32 : VOP1Inst <vop1<0x16>, "v_cvt_f64_u32", 1255 VOP_F64_I32, uint_to_fp 1256>; 1257 1258} // End SchedRW = [WriteQuarterRate32] 1259 1260defm V_FRACT_F32 : VOP1Inst <vop1<0x20, 0x1b>, "v_fract_f32", 1261 VOP_F32_F32, AMDGPUfract 1262>; 1263defm V_TRUNC_F32 : VOP1Inst <vop1<0x21, 0x1c>, "v_trunc_f32", 1264 VOP_F32_F32, ftrunc 1265>; 1266defm V_CEIL_F32 : VOP1Inst <vop1<0x22, 0x1d>, "v_ceil_f32", 1267 VOP_F32_F32, fceil 1268>; 1269defm V_RNDNE_F32 : VOP1Inst <vop1<0x23, 0x1e>, "v_rndne_f32", 1270 VOP_F32_F32, frint 1271>; 1272defm V_FLOOR_F32 : VOP1Inst <vop1<0x24, 0x1f>, "v_floor_f32", 1273 VOP_F32_F32, ffloor 1274>; 1275defm V_EXP_F32 : VOP1Inst <vop1<0x25, 0x20>, "v_exp_f32", 1276 VOP_F32_F32, fexp2 1277>; 1278 1279let SchedRW = [WriteQuarterRate32] in { 1280 1281defm V_LOG_F32 : VOP1Inst <vop1<0x27, 0x21>, "v_log_f32", 1282 VOP_F32_F32, flog2 1283>; 1284defm V_RCP_F32 : VOP1Inst <vop1<0x2a, 0x22>, "v_rcp_f32", 1285 VOP_F32_F32, AMDGPUrcp 1286>; 1287defm V_RCP_IFLAG_F32 : VOP1Inst <vop1<0x2b, 0x23>, "v_rcp_iflag_f32", 1288 VOP_F32_F32 1289>; 1290defm V_RSQ_F32 : VOP1Inst <vop1<0x2e, 0x24>, "v_rsq_f32", 1291 VOP_F32_F32, AMDGPUrsq 1292>; 1293 1294} // End SchedRW = [WriteQuarterRate32] 1295 1296let SchedRW = [WriteDouble] in { 1297 1298defm V_RCP_F64 : VOP1Inst <vop1<0x2f, 0x25>, "v_rcp_f64", 1299 VOP_F64_F64, AMDGPUrcp 1300>; 1301defm V_RSQ_F64 : VOP1Inst <vop1<0x31, 0x26>, "v_rsq_f64", 1302 VOP_F64_F64, AMDGPUrsq 1303>; 1304 1305} // End SchedRW = [WriteDouble]; 1306 1307defm V_SQRT_F32 : VOP1Inst <vop1<0x33, 0x27>, "v_sqrt_f32", 1308 VOP_F32_F32, fsqrt 1309>; 1310 1311let SchedRW = [WriteDouble] in { 1312 1313defm V_SQRT_F64 : VOP1Inst <vop1<0x34, 0x28>, "v_sqrt_f64", 1314 VOP_F64_F64, fsqrt 1315>; 1316 1317} // End SchedRW = [WriteDouble] 1318 1319let SchedRW = [WriteQuarterRate32] in { 1320 1321defm V_SIN_F32 : VOP1Inst <vop1<0x35, 0x29>, "v_sin_f32", 1322 VOP_F32_F32, AMDGPUsin 1323>; 1324defm V_COS_F32 : VOP1Inst <vop1<0x36, 0x2a>, "v_cos_f32", 1325 VOP_F32_F32, AMDGPUcos 1326>; 1327 1328} // End SchedRW = [WriteQuarterRate32] 1329 1330defm V_NOT_B32 : VOP1Inst <vop1<0x37, 0x2b>, "v_not_b32", VOP_I32_I32>; 1331defm V_BFREV_B32 : VOP1Inst <vop1<0x38, 0x2c>, "v_bfrev_b32", VOP_I32_I32>; 1332defm V_FFBH_U32 : VOP1Inst <vop1<0x39, 0x2d>, "v_ffbh_u32", VOP_I32_I32>; 1333defm V_FFBL_B32 : VOP1Inst <vop1<0x3a, 0x2e>, "v_ffbl_b32", VOP_I32_I32>; 1334defm V_FFBH_I32 : VOP1Inst <vop1<0x3b, 0x2f>, "v_ffbh_i32", VOP_I32_I32>; 1335defm V_FREXP_EXP_I32_F64 : VOP1Inst <vop1<0x3c,0x30>, "v_frexp_exp_i32_f64", 1336 VOP_I32_F64 1337>; 1338 1339let SchedRW = [WriteDoubleAdd] in { 1340defm V_FREXP_MANT_F64 : VOP1Inst <vop1<0x3d, 0x31>, "v_frexp_mant_f64", 1341 VOP_F64_F64 1342>; 1343 1344defm V_FRACT_F64 : VOP1Inst <vop1<0x3e, 0x32>, "v_fract_f64", 1345 VOP_F64_F64 1346>; 1347} // End SchedRW = [WriteDoubleAdd] 1348 1349 1350defm V_FREXP_EXP_I32_F32 : VOP1Inst <vop1<0x3f, 0x33>, "v_frexp_exp_i32_f32", 1351 VOP_I32_F32 1352>; 1353defm V_FREXP_MANT_F32 : VOP1Inst <vop1<0x40, 0x34>, "v_frexp_mant_f32", 1354 VOP_F32_F32 1355>; 1356let vdst = 0, src0 = 0, VOPAsmPrefer32Bit = 1 in { 1357defm V_CLREXCP : VOP1Inst <vop1<0x41,0x35>, "v_clrexcp", VOP_NONE>; 1358} 1359 1360let Uses = [M0, EXEC] in { 1361defm V_MOVRELD_B32 : VOP1Inst <vop1<0x42, 0x36>, "v_movreld_b32", VOP_I32_I32>; 1362defm V_MOVRELS_B32 : VOP1Inst <vop1<0x43, 0x37>, "v_movrels_b32", VOP_I32_I32>; 1363defm V_MOVRELSD_B32 : VOP1Inst <vop1<0x44, 0x38>, "v_movrelsd_b32", VOP_I32_I32>; 1364} // End Uses = [M0, EXEC] 1365 1366// These instruction only exist on SI and CI 1367let SubtargetPredicate = isSICI in { 1368 1369let SchedRW = [WriteQuarterRate32] in { 1370 1371defm V_MOV_FED_B32 : VOP1InstSI <vop1<0x9>, "v_mov_fed_b32", VOP_I32_I32>; 1372defm V_LOG_CLAMP_F32 : VOP1InstSI <vop1<0x26>, "v_log_clamp_f32", 1373 VOP_F32_F32, int_amdgcn_log_clamp>; 1374defm V_RCP_CLAMP_F32 : VOP1InstSI <vop1<0x28>, "v_rcp_clamp_f32", VOP_F32_F32>; 1375defm V_RCP_LEGACY_F32 : VOP1InstSI <vop1<0x29>, "v_rcp_legacy_f32", VOP_F32_F32>; 1376defm V_RSQ_CLAMP_F32 : VOP1InstSI <vop1<0x2c>, "v_rsq_clamp_f32", 1377 VOP_F32_F32, AMDGPUrsq_clamp 1378>; 1379defm V_RSQ_LEGACY_F32 : VOP1InstSI <vop1<0x2d>, "v_rsq_legacy_f32", 1380 VOP_F32_F32, AMDGPUrsq_legacy 1381>; 1382 1383} // End SchedRW = [WriteQuarterRate32] 1384 1385let SchedRW = [WriteDouble] in { 1386 1387defm V_RCP_CLAMP_F64 : VOP1InstSI <vop1<0x30>, "v_rcp_clamp_f64", VOP_F64_F64>; 1388defm V_RSQ_CLAMP_F64 : VOP1InstSI <vop1<0x32>, "v_rsq_clamp_f64", 1389 VOP_F64_F64, AMDGPUrsq_clamp 1390>; 1391 1392} // End SchedRW = [WriteDouble] 1393 1394} // End SubtargetPredicate = isSICI 1395 1396//===----------------------------------------------------------------------===// 1397// VINTRP Instructions 1398//===----------------------------------------------------------------------===// 1399 1400let Uses = [M0, EXEC] in { 1401 1402// FIXME: Specify SchedRW for VINTRP insturctions. 1403 1404multiclass V_INTERP_P1_F32_m : VINTRP_m < 1405 0x00000000, 1406 (outs VGPR_32:$dst), 1407 (ins VGPR_32:$i, i32imm:$attr_chan, i32imm:$attr), 1408 "v_interp_p1_f32 $dst, $i, $attr_chan, $attr, [m0]", 1409 [(set f32:$dst, (AMDGPUinterp_p1 i32:$i, (i32 imm:$attr_chan), 1410 (i32 imm:$attr)))] 1411>; 1412 1413let OtherPredicates = [has32BankLDS] in { 1414 1415defm V_INTERP_P1_F32 : V_INTERP_P1_F32_m; 1416 1417} // End OtherPredicates = [has32BankLDS] 1418 1419let OtherPredicates = [has16BankLDS], Constraints = "@earlyclobber $dst", isAsmParserOnly=1 in { 1420 1421defm V_INTERP_P1_F32_16bank : V_INTERP_P1_F32_m; 1422 1423} // End OtherPredicates = [has32BankLDS], Constraints = "@earlyclobber $dst", isAsmParserOnly=1 1424 1425let DisableEncoding = "$src0", Constraints = "$src0 = $dst" in { 1426 1427defm V_INTERP_P2_F32 : VINTRP_m < 1428 0x00000001, 1429 (outs VGPR_32:$dst), 1430 (ins VGPR_32:$src0, VGPR_32:$j, i32imm:$attr_chan, i32imm:$attr), 1431 "v_interp_p2_f32 $dst, [$src0], $j, $attr_chan, $attr, [m0]", 1432 [(set f32:$dst, (AMDGPUinterp_p2 f32:$src0, i32:$j, (i32 imm:$attr_chan), 1433 (i32 imm:$attr)))]>; 1434 1435} // End DisableEncoding = "$src0", Constraints = "$src0 = $dst" 1436 1437defm V_INTERP_MOV_F32 : VINTRP_m < 1438 0x00000002, 1439 (outs VGPR_32:$dst), 1440 (ins InterpSlot:$src0, i32imm:$attr_chan, i32imm:$attr), 1441 "v_interp_mov_f32 $dst, $src0, $attr_chan, $attr, [m0]", 1442 [(set f32:$dst, (AMDGPUinterp_mov (i32 imm:$src0), (i32 imm:$attr_chan), 1443 (i32 imm:$attr)))]>; 1444 1445} // End Uses = [M0, EXEC] 1446 1447//===----------------------------------------------------------------------===// 1448// VOP2 Instructions 1449//===----------------------------------------------------------------------===// 1450 1451multiclass V_CNDMASK <vop2 op, string name> { 1452 defm _e32 : VOP2_m <op, name, VOP_CNDMASK, [], name>; 1453 1454 defm _e64 : VOP3_m < 1455 op, VOP_CNDMASK.Outs, VOP_CNDMASK.Ins64, 1456 name#!cast<string>(VOP_CNDMASK.Asm64), [], name, 3, 0>; 1457} 1458 1459defm V_CNDMASK_B32 : V_CNDMASK<vop2<0x0>, "v_cndmask_b32">; 1460 1461let isCommutable = 1 in { 1462defm V_ADD_F32 : VOP2Inst <vop2<0x3, 0x1>, "v_add_f32", 1463 VOP_F32_F32_F32, fadd 1464>; 1465 1466defm V_SUB_F32 : VOP2Inst <vop2<0x4, 0x2>, "v_sub_f32", VOP_F32_F32_F32, fsub>; 1467defm V_SUBREV_F32 : VOP2Inst <vop2<0x5, 0x3>, "v_subrev_f32", 1468 VOP_F32_F32_F32, null_frag, "v_sub_f32" 1469>; 1470} // End isCommutable = 1 1471 1472let isCommutable = 1 in { 1473 1474defm V_MUL_LEGACY_F32 : VOP2Inst <vop2<0x7, 0x4>, "v_mul_legacy_f32", 1475 VOP_F32_F32_F32 1476>; 1477 1478defm V_MUL_F32 : VOP2Inst <vop2<0x8, 0x5>, "v_mul_f32", 1479 VOP_F32_F32_F32, fmul 1480>; 1481 1482defm V_MUL_I32_I24 : VOP2Inst <vop2<0x9, 0x6>, "v_mul_i32_i24", 1483 VOP_I32_I32_I32, AMDGPUmul_i24 1484>; 1485 1486defm V_MUL_HI_I32_I24 : VOP2Inst <vop2<0xa,0x7>, "v_mul_hi_i32_i24", 1487 VOP_I32_I32_I32 1488>; 1489 1490defm V_MUL_U32_U24 : VOP2Inst <vop2<0xb, 0x8>, "v_mul_u32_u24", 1491 VOP_I32_I32_I32, AMDGPUmul_u24 1492>; 1493 1494defm V_MUL_HI_U32_U24 : VOP2Inst <vop2<0xc,0x9>, "v_mul_hi_u32_u24", 1495 VOP_I32_I32_I32 1496>; 1497 1498defm V_MIN_F32 : VOP2Inst <vop2<0xf, 0xa>, "v_min_f32", VOP_F32_F32_F32, 1499 fminnum>; 1500defm V_MAX_F32 : VOP2Inst <vop2<0x10, 0xb>, "v_max_f32", VOP_F32_F32_F32, 1501 fmaxnum>; 1502defm V_MIN_I32 : VOP2Inst <vop2<0x11, 0xc>, "v_min_i32", VOP_I32_I32_I32>; 1503defm V_MAX_I32 : VOP2Inst <vop2<0x12, 0xd>, "v_max_i32", VOP_I32_I32_I32>; 1504defm V_MIN_U32 : VOP2Inst <vop2<0x13, 0xe>, "v_min_u32", VOP_I32_I32_I32>; 1505defm V_MAX_U32 : VOP2Inst <vop2<0x14, 0xf>, "v_max_u32", VOP_I32_I32_I32>; 1506 1507defm V_LSHRREV_B32 : VOP2Inst < 1508 vop2<0x16, 0x10>, "v_lshrrev_b32", VOP_I32_I32_I32, null_frag, 1509 "v_lshr_b32" 1510>; 1511 1512defm V_ASHRREV_I32 : VOP2Inst < 1513 vop2<0x18, 0x11>, "v_ashrrev_i32", VOP_I32_I32_I32, null_frag, 1514 "v_ashr_i32" 1515>; 1516 1517defm V_LSHLREV_B32 : VOP2Inst < 1518 vop2<0x1a, 0x12>, "v_lshlrev_b32", VOP_I32_I32_I32, null_frag, 1519 "v_lshl_b32" 1520>; 1521 1522defm V_AND_B32 : VOP2Inst <vop2<0x1b, 0x13>, "v_and_b32", VOP_I32_I32_I32>; 1523defm V_OR_B32 : VOP2Inst <vop2<0x1c, 0x14>, "v_or_b32", VOP_I32_I32_I32>; 1524defm V_XOR_B32 : VOP2Inst <vop2<0x1d, 0x15>, "v_xor_b32", VOP_I32_I32_I32>; 1525 1526let Constraints = "$vdst = $src2", DisableEncoding="$src2", 1527 isConvertibleToThreeAddress = 1 in { 1528defm V_MAC_F32 : VOP2Inst <vop2<0x1f, 0x16>, "v_mac_f32", VOP_MAC>; 1529} 1530} // End isCommutable = 1 1531 1532defm V_MADMK_F32 : VOP2MADK <vop2<0x20, 0x17>, "v_madmk_f32">; 1533 1534let isCommutable = 1 in { 1535defm V_MADAK_F32 : VOP2MADK <vop2<0x21, 0x18>, "v_madak_f32">; 1536} // End isCommutable = 1 1537 1538let isCommutable = 1 in { 1539// No patterns so that the scalar instructions are always selected. 1540// The scalar versions will be replaced with vector when needed later. 1541 1542// V_ADD_I32, V_SUB_I32, and V_SUBREV_I32 where renamed to *_U32 in VI, 1543// but the VI instructions behave the same as the SI versions. 1544defm V_ADD_I32 : VOP2bInst <vop2<0x25, 0x19>, "v_add_i32", 1545 VOP2b_I32_I1_I32_I32 1546>; 1547defm V_SUB_I32 : VOP2bInst <vop2<0x26, 0x1a>, "v_sub_i32", VOP2b_I32_I1_I32_I32>; 1548 1549defm V_SUBREV_I32 : VOP2bInst <vop2<0x27, 0x1b>, "v_subrev_i32", 1550 VOP2b_I32_I1_I32_I32, null_frag, "v_sub_i32" 1551>; 1552 1553defm V_ADDC_U32 : VOP2bInst <vop2<0x28, 0x1c>, "v_addc_u32", 1554 VOP2b_I32_I1_I32_I32_I1 1555>; 1556defm V_SUBB_U32 : VOP2bInst <vop2<0x29, 0x1d>, "v_subb_u32", 1557 VOP2b_I32_I1_I32_I32_I1 1558>; 1559defm V_SUBBREV_U32 : VOP2bInst <vop2<0x2a, 0x1e>, "v_subbrev_u32", 1560 VOP2b_I32_I1_I32_I32_I1, null_frag, "v_subb_u32" 1561>; 1562 1563} // End isCommutable = 1 1564 1565defm V_READLANE_B32 : VOP2SI_3VI_m < 1566 vop3 <0x001, 0x289>, 1567 "v_readlane_b32", 1568 (outs SReg_32:$vdst), 1569 (ins VGPR_32:$src0, SCSrc_32:$src1), 1570 "v_readlane_b32 $vdst, $src0, $src1" 1571>; 1572 1573defm V_WRITELANE_B32 : VOP2SI_3VI_m < 1574 vop3 <0x002, 0x28a>, 1575 "v_writelane_b32", 1576 (outs VGPR_32:$vdst), 1577 (ins SReg_32:$src0, SCSrc_32:$src1), 1578 "v_writelane_b32 $vdst, $src0, $src1" 1579>; 1580 1581// These instructions only exist on SI and CI 1582let SubtargetPredicate = isSICI in { 1583 1584let isCommutable = 1 in { 1585defm V_MAC_LEGACY_F32 : VOP2InstSI <vop2<0x6>, "v_mac_legacy_f32", 1586 VOP_F32_F32_F32 1587>; 1588} // End isCommutable = 1 1589 1590defm V_MIN_LEGACY_F32 : VOP2InstSI <vop2<0xd>, "v_min_legacy_f32", 1591 VOP_F32_F32_F32, AMDGPUfmin_legacy 1592>; 1593defm V_MAX_LEGACY_F32 : VOP2InstSI <vop2<0xe>, "v_max_legacy_f32", 1594 VOP_F32_F32_F32, AMDGPUfmax_legacy 1595>; 1596 1597let isCommutable = 1 in { 1598defm V_LSHR_B32 : VOP2InstSI <vop2<0x15>, "v_lshr_b32", VOP_I32_I32_I32>; 1599defm V_ASHR_I32 : VOP2InstSI <vop2<0x17>, "v_ashr_i32", VOP_I32_I32_I32>; 1600defm V_LSHL_B32 : VOP2InstSI <vop2<0x19>, "v_lshl_b32", VOP_I32_I32_I32>; 1601} // End isCommutable = 1 1602} // End let SubtargetPredicate = SICI 1603 1604defm V_BFM_B32 : VOP2_VI3_Inst <vop23<0x1e, 0x293>, "v_bfm_b32", 1605 VOP_I32_I32_I32 1606>; 1607defm V_BCNT_U32_B32 : VOP2_VI3_Inst <vop23<0x22, 0x28b>, "v_bcnt_u32_b32", 1608 VOP_I32_I32_I32 1609>; 1610defm V_MBCNT_LO_U32_B32 : VOP2_VI3_Inst <vop23<0x23, 0x28c>, "v_mbcnt_lo_u32_b32", 1611 VOP_I32_I32_I32, int_amdgcn_mbcnt_lo 1612>; 1613defm V_MBCNT_HI_U32_B32 : VOP2_VI3_Inst <vop23<0x24, 0x28d>, "v_mbcnt_hi_u32_b32", 1614 VOP_I32_I32_I32, int_amdgcn_mbcnt_hi 1615>; 1616defm V_LDEXP_F32 : VOP2_VI3_Inst <vop23<0x2b, 0x288>, "v_ldexp_f32", 1617 VOP_F32_F32_I32, AMDGPUldexp 1618>; 1619 1620defm V_CVT_PKACCUM_U8_F32 : VOP2_VI3_Inst <vop23<0x2c, 0x1f0>, "v_cvt_pkaccum_u8_f32", 1621 VOP_I32_F32_I32>; // TODO: set "Uses = dst" 1622 1623defm V_CVT_PKNORM_I16_F32 : VOP2_VI3_Inst <vop23<0x2d, 0x294>, "v_cvt_pknorm_i16_f32", 1624 VOP_I32_F32_F32 1625>; 1626defm V_CVT_PKNORM_U16_F32 : VOP2_VI3_Inst <vop23<0x2e, 0x295>, "v_cvt_pknorm_u16_f32", 1627 VOP_I32_F32_F32 1628>; 1629defm V_CVT_PKRTZ_F16_F32 : VOP2_VI3_Inst <vop23<0x2f, 0x296>, "v_cvt_pkrtz_f16_f32", 1630 VOP_I32_F32_F32, int_SI_packf16 1631>; 1632defm V_CVT_PK_U16_U32 : VOP2_VI3_Inst <vop23<0x30, 0x297>, "v_cvt_pk_u16_u32", 1633 VOP_I32_I32_I32 1634>; 1635defm V_CVT_PK_I16_I32 : VOP2_VI3_Inst <vop23<0x31, 0x298>, "v_cvt_pk_i16_i32", 1636 VOP_I32_I32_I32 1637>; 1638 1639//===----------------------------------------------------------------------===// 1640// VOP3 Instructions 1641//===----------------------------------------------------------------------===// 1642 1643let isCommutable = 1 in { 1644defm V_MAD_LEGACY_F32 : VOP3Inst <vop3<0x140, 0x1c0>, "v_mad_legacy_f32", 1645 VOP_F32_F32_F32_F32 1646>; 1647 1648defm V_MAD_F32 : VOP3Inst <vop3<0x141, 0x1c1>, "v_mad_f32", 1649 VOP_F32_F32_F32_F32, fmad 1650>; 1651 1652defm V_MAD_I32_I24 : VOP3Inst <vop3<0x142, 0x1c2>, "v_mad_i32_i24", 1653 VOP_I32_I32_I32_I32, AMDGPUmad_i24 1654>; 1655defm V_MAD_U32_U24 : VOP3Inst <vop3<0x143, 0x1c3>, "v_mad_u32_u24", 1656 VOP_I32_I32_I32_I32, AMDGPUmad_u24 1657>; 1658} // End isCommutable = 1 1659 1660defm V_CUBEID_F32 : VOP3Inst <vop3<0x144, 0x1c4>, "v_cubeid_f32", 1661 VOP_F32_F32_F32_F32, int_amdgcn_cubeid 1662>; 1663defm V_CUBESC_F32 : VOP3Inst <vop3<0x145, 0x1c5>, "v_cubesc_f32", 1664 VOP_F32_F32_F32_F32, int_amdgcn_cubesc 1665>; 1666defm V_CUBETC_F32 : VOP3Inst <vop3<0x146, 0x1c6>, "v_cubetc_f32", 1667 VOP_F32_F32_F32_F32, int_amdgcn_cubetc 1668>; 1669defm V_CUBEMA_F32 : VOP3Inst <vop3<0x147, 0x1c7>, "v_cubema_f32", 1670 VOP_F32_F32_F32_F32, int_amdgcn_cubema 1671>; 1672 1673defm V_BFE_U32 : VOP3Inst <vop3<0x148, 0x1c8>, "v_bfe_u32", 1674 VOP_I32_I32_I32_I32, AMDGPUbfe_u32 1675>; 1676defm V_BFE_I32 : VOP3Inst <vop3<0x149, 0x1c9>, "v_bfe_i32", 1677 VOP_I32_I32_I32_I32, AMDGPUbfe_i32 1678>; 1679 1680defm V_BFI_B32 : VOP3Inst <vop3<0x14a, 0x1ca>, "v_bfi_b32", 1681 VOP_I32_I32_I32_I32, AMDGPUbfi 1682>; 1683 1684let isCommutable = 1 in { 1685defm V_FMA_F32 : VOP3Inst <vop3<0x14b, 0x1cb>, "v_fma_f32", 1686 VOP_F32_F32_F32_F32, fma 1687>; 1688defm V_FMA_F64 : VOP3Inst <vop3<0x14c, 0x1cc>, "v_fma_f64", 1689 VOP_F64_F64_F64_F64, fma 1690>; 1691} // End isCommutable = 1 1692 1693//def V_LERP_U8 : VOP3_U8 <0x0000014d, "v_lerp_u8", []>; 1694defm V_ALIGNBIT_B32 : VOP3Inst <vop3<0x14e, 0x1ce>, "v_alignbit_b32", 1695 VOP_I32_I32_I32_I32 1696>; 1697defm V_ALIGNBYTE_B32 : VOP3Inst <vop3<0x14f, 0x1cf>, "v_alignbyte_b32", 1698 VOP_I32_I32_I32_I32 1699>; 1700 1701defm V_MIN3_F32 : VOP3Inst <vop3<0x151, 0x1d0>, "v_min3_f32", 1702 VOP_F32_F32_F32_F32, AMDGPUfmin3>; 1703 1704defm V_MIN3_I32 : VOP3Inst <vop3<0x152, 0x1d1>, "v_min3_i32", 1705 VOP_I32_I32_I32_I32, AMDGPUsmin3 1706>; 1707defm V_MIN3_U32 : VOP3Inst <vop3<0x153, 0x1d2>, "v_min3_u32", 1708 VOP_I32_I32_I32_I32, AMDGPUumin3 1709>; 1710defm V_MAX3_F32 : VOP3Inst <vop3<0x154, 0x1d3>, "v_max3_f32", 1711 VOP_F32_F32_F32_F32, AMDGPUfmax3 1712>; 1713defm V_MAX3_I32 : VOP3Inst <vop3<0x155, 0x1d4>, "v_max3_i32", 1714 VOP_I32_I32_I32_I32, AMDGPUsmax3 1715>; 1716defm V_MAX3_U32 : VOP3Inst <vop3<0x156, 0x1d5>, "v_max3_u32", 1717 VOP_I32_I32_I32_I32, AMDGPUumax3 1718>; 1719defm V_MED3_F32 : VOP3Inst <vop3<0x157, 0x1d6>, "v_med3_f32", 1720 VOP_F32_F32_F32_F32, AMDGPUfmed3 1721>; 1722defm V_MED3_I32 : VOP3Inst <vop3<0x158, 0x1d7>, "v_med3_i32", 1723 VOP_I32_I32_I32_I32, AMDGPUsmed3 1724>; 1725defm V_MED3_U32 : VOP3Inst <vop3<0x159, 0x1d8>, "v_med3_u32", 1726 VOP_I32_I32_I32_I32, AMDGPUumed3 1727>; 1728 1729//def V_SAD_U8 : VOP3_U8 <0x0000015a, "v_sad_u8", []>; 1730//def V_SAD_HI_U8 : VOP3_U8 <0x0000015b, "v_sad_hi_u8", []>; 1731//def V_SAD_U16 : VOP3_U16 <0x0000015c, "v_sad_u16", []>; 1732defm V_SAD_U32 : VOP3Inst <vop3<0x15d, 0x1dc>, "v_sad_u32", 1733 VOP_I32_I32_I32_I32 1734>; 1735//def V_CVT_PK_U8_F32 : VOP3_U8 <0x0000015e, "v_cvt_pk_u8_f32", []>; 1736defm V_DIV_FIXUP_F32 : VOP3Inst < 1737 vop3<0x15f, 0x1de>, "v_div_fixup_f32", VOP_F32_F32_F32_F32, AMDGPUdiv_fixup 1738>; 1739 1740let SchedRW = [WriteDoubleAdd] in { 1741 1742defm V_DIV_FIXUP_F64 : VOP3Inst < 1743 vop3<0x160, 0x1df>, "v_div_fixup_f64", VOP_F64_F64_F64_F64, AMDGPUdiv_fixup 1744>; 1745 1746} // End SchedRW = [WriteDouble] 1747 1748let SchedRW = [WriteDoubleAdd] in { 1749let isCommutable = 1 in { 1750 1751defm V_ADD_F64 : VOP3Inst <vop3<0x164, 0x280>, "v_add_f64", 1752 VOP_F64_F64_F64, fadd, 1 1753>; 1754defm V_MUL_F64 : VOP3Inst <vop3<0x165, 0x281>, "v_mul_f64", 1755 VOP_F64_F64_F64, fmul, 1 1756>; 1757 1758defm V_MIN_F64 : VOP3Inst <vop3<0x166, 0x282>, "v_min_f64", 1759 VOP_F64_F64_F64, fminnum, 1 1760>; 1761defm V_MAX_F64 : VOP3Inst <vop3<0x167, 0x283>, "v_max_f64", 1762 VOP_F64_F64_F64, fmaxnum, 1 1763>; 1764 1765} // End isCommutable = 1 1766 1767defm V_LDEXP_F64 : VOP3Inst <vop3<0x168, 0x284>, "v_ldexp_f64", 1768 VOP_F64_F64_I32, AMDGPUldexp, 1 1769>; 1770 1771} // End let SchedRW = [WriteDoubleAdd] 1772 1773let isCommutable = 1, SchedRW = [WriteQuarterRate32] in { 1774 1775defm V_MUL_LO_U32 : VOP3Inst <vop3<0x169, 0x285>, "v_mul_lo_u32", 1776 VOP_I32_I32_I32 1777>; 1778defm V_MUL_HI_U32 : VOP3Inst <vop3<0x16a, 0x286>, "v_mul_hi_u32", 1779 VOP_I32_I32_I32, mulhu 1780>; 1781 1782let DisableVIDecoder=1 in { // removed from VI as identical to V_MUL_LO_U32 1783defm V_MUL_LO_I32 : VOP3Inst <vop3<0x16b, 0x285>, "v_mul_lo_i32", 1784 VOP_I32_I32_I32 1785>; 1786} 1787 1788defm V_MUL_HI_I32 : VOP3Inst <vop3<0x16c, 0x287>, "v_mul_hi_i32", 1789 VOP_I32_I32_I32, mulhs 1790>; 1791 1792} // End isCommutable = 1, SchedRW = [WriteQuarterRate32] 1793 1794let SchedRW = [WriteFloatFMA, WriteSALU] in { 1795defm V_DIV_SCALE_F32 : VOP3bInst <vop3<0x16d, 0x1e0>, "v_div_scale_f32", 1796 VOP3b_F32_I1_F32_F32_F32, [], 1 1797>; 1798} 1799 1800let SchedRW = [WriteDouble, WriteSALU] in { 1801// Double precision division pre-scale. 1802defm V_DIV_SCALE_F64 : VOP3bInst <vop3<0x16e, 0x1e1>, "v_div_scale_f64", 1803 VOP3b_F64_I1_F64_F64_F64, [], 1 1804>; 1805} // End SchedRW = [WriteDouble] 1806 1807let isCommutable = 1, Uses = [VCC, EXEC] in { 1808 1809let SchedRW = [WriteFloatFMA] in { 1810// v_div_fmas_f32: 1811// result = src0 * src1 + src2 1812// if (vcc) 1813// result *= 2^32 1814// 1815defm V_DIV_FMAS_F32 : VOP3_VCC_Inst <vop3<0x16f, 0x1e2>, "v_div_fmas_f32", 1816 VOP_F32_F32_F32_F32, AMDGPUdiv_fmas 1817>; 1818} 1819 1820let SchedRW = [WriteDouble] in { 1821// v_div_fmas_f64: 1822// result = src0 * src1 + src2 1823// if (vcc) 1824// result *= 2^64 1825// 1826defm V_DIV_FMAS_F64 : VOP3_VCC_Inst <vop3<0x170, 0x1e3>, "v_div_fmas_f64", 1827 VOP_F64_F64_F64_F64, AMDGPUdiv_fmas 1828>; 1829 1830} // End SchedRW = [WriteDouble] 1831} // End isCommutable = 1, Uses = [VCC, EXEC] 1832 1833//def V_MSAD_U8 : VOP3_U8 <0x00000171, "v_msad_u8", []>; 1834//def V_QSAD_U8 : VOP3_U8 <0x00000172, "v_qsad_u8", []>; 1835//def V_MQSAD_U8 : VOP3_U8 <0x00000173, "v_mqsad_u8", []>; 1836 1837let SchedRW = [WriteDouble] in { 1838defm V_TRIG_PREOP_F64 : VOP3Inst < 1839 vop3<0x174, 0x292>, "v_trig_preop_f64", VOP_F64_F64_I32, AMDGPUtrig_preop 1840>; 1841 1842} // End SchedRW = [WriteDouble] 1843 1844// These instructions only exist on SI and CI 1845let SubtargetPredicate = isSICI in { 1846 1847defm V_LSHL_B64 : VOP3Inst <vop3<0x161>, "v_lshl_b64", VOP_I64_I64_I32>; 1848defm V_LSHR_B64 : VOP3Inst <vop3<0x162>, "v_lshr_b64", VOP_I64_I64_I32>; 1849defm V_ASHR_I64 : VOP3Inst <vop3<0x163>, "v_ashr_i64", VOP_I64_I64_I32>; 1850 1851defm V_MULLIT_F32 : VOP3Inst <vop3<0x150>, "v_mullit_f32", 1852 VOP_F32_F32_F32_F32>; 1853 1854} // End SubtargetPredicate = isSICI 1855 1856let SubtargetPredicate = isVI, DisableSIDecoder = 1 in { 1857 1858defm V_LSHLREV_B64 : VOP3Inst <vop3<0, 0x28f>, "v_lshlrev_b64", 1859 VOP_I64_I32_I64 1860>; 1861defm V_LSHRREV_B64 : VOP3Inst <vop3<0, 0x290>, "v_lshrrev_b64", 1862 VOP_I64_I32_I64 1863>; 1864defm V_ASHRREV_I64 : VOP3Inst <vop3<0, 0x291>, "v_ashrrev_i64", 1865 VOP_I64_I32_I64 1866>; 1867 1868} // End SubtargetPredicate = isVI 1869 1870//===----------------------------------------------------------------------===// 1871// Pseudo Instructions 1872//===----------------------------------------------------------------------===// 1873let isCodeGenOnly = 1, isPseudo = 1 in { 1874 1875// For use in patterns 1876def V_CNDMASK_B64_PSEUDO : VOP3Common <(outs VReg_64:$vdst), 1877 (ins VSrc_64:$src0, VSrc_64:$src1, SSrc_64:$src2), "", [] 1878>; 1879 1880let hasSideEffects = 0, mayLoad = 0, mayStore = 0, Uses = [EXEC] in { 1881// 64-bit vector move instruction. This is mainly used by the SIFoldOperands 1882// pass to enable folding of inline immediates. 1883def V_MOV_B64_PSEUDO : InstSI <(outs VReg_64:$vdst), (ins VSrc_64:$src0), "", []>; 1884} // End let hasSideEffects = 0, mayLoad = 0, mayStore = 0 1885 1886let hasSideEffects = 1, SALU = 1 in { 1887def SGPR_USE : InstSI <(outs),(ins), "", []>; 1888} 1889 1890// SI pseudo instructions. These are used by the CFG structurizer pass 1891// and should be lowered to ISA instructions prior to codegen. 1892 1893let mayLoad = 1, mayStore = 1, hasSideEffects = 1 in { 1894let Uses = [EXEC], Defs = [EXEC] in { 1895 1896let isBranch = 1, isTerminator = 1 in { 1897 1898def SI_IF: InstSI < 1899 (outs SReg_64:$dst), 1900 (ins SReg_64:$vcc, brtarget:$target), 1901 "", 1902 [(set i64:$dst, (int_amdgcn_if i1:$vcc, bb:$target))] 1903>; 1904 1905def SI_ELSE : InstSI < 1906 (outs SReg_64:$dst), 1907 (ins SReg_64:$src, brtarget:$target), 1908 "", 1909 [(set i64:$dst, (int_amdgcn_else i64:$src, bb:$target))] 1910> { 1911 let Constraints = "$src = $dst"; 1912} 1913 1914def SI_LOOP : InstSI < 1915 (outs), 1916 (ins SReg_64:$saved, brtarget:$target), 1917 "si_loop $saved, $target", 1918 [(int_amdgcn_loop i64:$saved, bb:$target)] 1919>; 1920 1921} // End isBranch = 1, isTerminator = 1 1922 1923def SI_BREAK : InstSI < 1924 (outs SReg_64:$dst), 1925 (ins SReg_64:$src), 1926 "si_else $dst, $src", 1927 [(set i64:$dst, (int_amdgcn_break i64:$src))] 1928>; 1929 1930def SI_IF_BREAK : InstSI < 1931 (outs SReg_64:$dst), 1932 (ins SReg_64:$vcc, SReg_64:$src), 1933 "si_if_break $dst, $vcc, $src", 1934 [(set i64:$dst, (int_amdgcn_if_break i1:$vcc, i64:$src))] 1935>; 1936 1937def SI_ELSE_BREAK : InstSI < 1938 (outs SReg_64:$dst), 1939 (ins SReg_64:$src0, SReg_64:$src1), 1940 "si_else_break $dst, $src0, $src1", 1941 [(set i64:$dst, (int_amdgcn_else_break i64:$src0, i64:$src1))] 1942>; 1943 1944def SI_END_CF : InstSI < 1945 (outs), 1946 (ins SReg_64:$saved), 1947 "si_end_cf $saved", 1948 [(int_amdgcn_end_cf i64:$saved)] 1949>; 1950 1951} // End Uses = [EXEC], Defs = [EXEC] 1952 1953let Uses = [EXEC], Defs = [EXEC,VCC] in { 1954def SI_KILL : InstSI < 1955 (outs), 1956 (ins VSrc_32:$src), 1957 "si_kill $src", 1958 [(int_AMDGPU_kill f32:$src)] 1959>; 1960} // End Uses = [EXEC], Defs = [EXEC,VCC] 1961 1962} // End mayLoad = 1, mayStore = 1, hasSideEffects = 1 1963 1964let Uses = [EXEC], Defs = [EXEC,VCC,M0] in { 1965 1966class SI_INDIRECT_SRC<RegisterClass rc> : InstSI < 1967 (outs VGPR_32:$dst, SReg_64:$temp), 1968 (ins rc:$src, VSrc_32:$idx, i32imm:$off), 1969 "si_indirect_src $dst, $temp, $src, $idx, $off", 1970 [] 1971>; 1972 1973class SI_INDIRECT_DST<RegisterClass rc> : InstSI < 1974 (outs rc:$dst, SReg_64:$temp), 1975 (ins unknown:$src, VSrc_32:$idx, i32imm:$off, VGPR_32:$val), 1976 "si_indirect_dst $dst, $temp, $src, $idx, $off, $val", 1977 [] 1978> { 1979 let Constraints = "$src = $dst"; 1980} 1981 1982// TODO: We can support indirect SGPR access. 1983def SI_INDIRECT_SRC_V1 : SI_INDIRECT_SRC<VGPR_32>; 1984def SI_INDIRECT_SRC_V2 : SI_INDIRECT_SRC<VReg_64>; 1985def SI_INDIRECT_SRC_V4 : SI_INDIRECT_SRC<VReg_128>; 1986def SI_INDIRECT_SRC_V8 : SI_INDIRECT_SRC<VReg_256>; 1987def SI_INDIRECT_SRC_V16 : SI_INDIRECT_SRC<VReg_512>; 1988 1989def SI_INDIRECT_DST_V1 : SI_INDIRECT_DST<VGPR_32>; 1990def SI_INDIRECT_DST_V2 : SI_INDIRECT_DST<VReg_64>; 1991def SI_INDIRECT_DST_V4 : SI_INDIRECT_DST<VReg_128>; 1992def SI_INDIRECT_DST_V8 : SI_INDIRECT_DST<VReg_256>; 1993def SI_INDIRECT_DST_V16 : SI_INDIRECT_DST<VReg_512>; 1994 1995} // End Uses = [EXEC], Defs = [EXEC,VCC,M0] 1996 1997multiclass SI_SPILL_SGPR <RegisterClass sgpr_class> { 1998 1999 let UseNamedOperandTable = 1, Uses = [EXEC] in { 2000 def _SAVE : InstSI < 2001 (outs), 2002 (ins sgpr_class:$src, i32imm:$frame_idx), 2003 "", []> { 2004 let mayStore = 1; 2005 let mayLoad = 0; 2006 } 2007 2008 def _RESTORE : InstSI < 2009 (outs sgpr_class:$dst), 2010 (ins i32imm:$frame_idx), 2011 "", []> { 2012 let mayStore = 0; 2013 let mayLoad = 1; 2014 } 2015 } // End UseNamedOperandTable = 1 2016} 2017 2018// It's unclear whether you can use M0 as the output of v_readlane_b32 2019// instructions, so use SGPR_32 register class for spills to prevent 2020// this from happening. 2021defm SI_SPILL_S32 : SI_SPILL_SGPR <SGPR_32>; 2022defm SI_SPILL_S64 : SI_SPILL_SGPR <SReg_64>; 2023defm SI_SPILL_S128 : SI_SPILL_SGPR <SReg_128>; 2024defm SI_SPILL_S256 : SI_SPILL_SGPR <SReg_256>; 2025defm SI_SPILL_S512 : SI_SPILL_SGPR <SReg_512>; 2026 2027multiclass SI_SPILL_VGPR <RegisterClass vgpr_class> { 2028 let UseNamedOperandTable = 1, VGPRSpill = 1, Uses = [EXEC] in { 2029 def _SAVE : InstSI < 2030 (outs), 2031 (ins vgpr_class:$src, i32imm:$frame_idx, SReg_128:$scratch_rsrc, 2032 SReg_32:$scratch_offset), 2033 "", []> { 2034 let mayStore = 1; 2035 let mayLoad = 0; 2036 } 2037 2038 def _RESTORE : InstSI < 2039 (outs vgpr_class:$dst), 2040 (ins i32imm:$frame_idx, SReg_128:$scratch_rsrc, SReg_32:$scratch_offset), 2041 "", []> { 2042 let mayStore = 0; 2043 let mayLoad = 1; 2044 } 2045 } // End UseNamedOperandTable = 1, VGPRSpill = 1 2046} 2047 2048defm SI_SPILL_V32 : SI_SPILL_VGPR <VGPR_32>; 2049defm SI_SPILL_V64 : SI_SPILL_VGPR <VReg_64>; 2050defm SI_SPILL_V96 : SI_SPILL_VGPR <VReg_96>; 2051defm SI_SPILL_V128 : SI_SPILL_VGPR <VReg_128>; 2052defm SI_SPILL_V256 : SI_SPILL_VGPR <VReg_256>; 2053defm SI_SPILL_V512 : SI_SPILL_VGPR <VReg_512>; 2054 2055let Defs = [SCC] in { 2056 2057def SI_CONSTDATA_PTR : InstSI < 2058 (outs SReg_64:$dst), 2059 (ins const_ga:$ptr), 2060 "", [(set SReg_64:$dst, (i64 (SIconstdata_ptr (tglobaladdr:$ptr))))] 2061> { 2062 let SALU = 1; 2063} 2064 2065} // End Defs = [SCC] 2066 2067} // End isCodeGenOnly, isPseudo 2068 2069} // End SubtargetPredicate = isGCN 2070 2071let Predicates = [isGCN] in { 2072 2073def : Pat < 2074 (int_AMDGPU_kilp), 2075 (SI_KILL 0xbf800000) 2076>; 2077 2078/* int_SI_vs_load_input */ 2079def : Pat< 2080 (SIload_input v4i32:$tlst, imm:$attr_offset, i32:$buf_idx_vgpr), 2081 (BUFFER_LOAD_FORMAT_XYZW_IDXEN $buf_idx_vgpr, $tlst, 0, imm:$attr_offset, 0, 0, 0) 2082>; 2083 2084def : Pat < 2085 (int_SI_export imm:$en, imm:$vm, imm:$done, imm:$tgt, imm:$compr, 2086 f32:$src0, f32:$src1, f32:$src2, f32:$src3), 2087 (EXP imm:$en, imm:$tgt, imm:$compr, imm:$done, imm:$vm, 2088 $src0, $src1, $src2, $src3) 2089>; 2090 2091//===----------------------------------------------------------------------===// 2092// SMRD Patterns 2093//===----------------------------------------------------------------------===// 2094 2095multiclass SMRD_Pattern <string Instr, ValueType vt> { 2096 2097 // 1. IMM offset 2098 def : Pat < 2099 (smrd_load (SMRDImm i64:$sbase, i32:$offset)), 2100 (vt (!cast<SMRD>(Instr#"_IMM") $sbase, $offset)) 2101 >; 2102 2103 // 2. SGPR offset 2104 def : Pat < 2105 (smrd_load (SMRDSgpr i64:$sbase, i32:$offset)), 2106 (vt (!cast<SMRD>(Instr#"_SGPR") $sbase, $offset)) 2107 >; 2108 2109 def : Pat < 2110 (smrd_load (SMRDImm32 i64:$sbase, i32:$offset)), 2111 (vt (!cast<SMRD>(Instr#"_IMM_ci") $sbase, $offset)) 2112 > { 2113 let Predicates = [isCIOnly]; 2114 } 2115} 2116 2117// Global and constant loads can be selected to either MUBUF or SMRD 2118// instructions, but SMRD instructions are faster so we want the instruction 2119// selector to prefer those. 2120let AddedComplexity = 100 in { 2121 2122defm : SMRD_Pattern <"S_LOAD_DWORD", i32>; 2123defm : SMRD_Pattern <"S_LOAD_DWORDX2", v2i32>; 2124defm : SMRD_Pattern <"S_LOAD_DWORDX4", v4i32>; 2125defm : SMRD_Pattern <"S_LOAD_DWORDX8", v8i32>; 2126defm : SMRD_Pattern <"S_LOAD_DWORDX16", v16i32>; 2127 2128// 1. Offset as an immediate 2129def : Pat < 2130 (SIload_constant v4i32:$sbase, (SMRDBufferImm i32:$offset)), 2131 (S_BUFFER_LOAD_DWORD_IMM $sbase, $offset) 2132>; 2133 2134// 2. Offset loaded in an 32bit SGPR 2135def : Pat < 2136 (SIload_constant v4i32:$sbase, (SMRDBufferSgpr i32:$offset)), 2137 (S_BUFFER_LOAD_DWORD_SGPR $sbase, $offset) 2138>; 2139 2140let Predicates = [isCI] in { 2141 2142def : Pat < 2143 (SIload_constant v4i32:$sbase, (SMRDBufferImm32 i32:$offset)), 2144 (S_BUFFER_LOAD_DWORD_IMM_ci $sbase, $offset) 2145>; 2146 2147} // End Predicates = [isCI] 2148 2149} // End let AddedComplexity = 10000 2150 2151//===----------------------------------------------------------------------===// 2152// SOP1 Patterns 2153//===----------------------------------------------------------------------===// 2154 2155def : Pat < 2156 (i64 (ctpop i64:$src)), 2157 (i64 (REG_SEQUENCE SReg_64, 2158 (i32 (COPY_TO_REGCLASS (S_BCNT1_I32_B64 $src), SReg_32)), sub0, 2159 (S_MOV_B32 0), sub1)) 2160>; 2161 2162def : Pat < 2163 (i32 (smax i32:$x, (i32 (ineg i32:$x)))), 2164 (S_ABS_I32 $x) 2165>; 2166 2167//===----------------------------------------------------------------------===// 2168// SOP2 Patterns 2169//===----------------------------------------------------------------------===// 2170 2171// V_ADD_I32_e32/S_ADD_U32 produces carry in VCC/SCC. For the vector 2172// case, the sgpr-copies pass will fix this to use the vector version. 2173def : Pat < 2174 (i32 (addc i32:$src0, i32:$src1)), 2175 (S_ADD_U32 $src0, $src1) 2176>; 2177 2178//===----------------------------------------------------------------------===// 2179// SOPP Patterns 2180//===----------------------------------------------------------------------===// 2181 2182// FIXME: These should be removed eventually 2183def : Pat < 2184 (int_AMDGPU_barrier_global), 2185 (S_BARRIER) 2186>; 2187 2188def : Pat < 2189 (int_AMDGPU_barrier_local), 2190 (S_BARRIER) 2191>; 2192 2193//===----------------------------------------------------------------------===// 2194// VOP1 Patterns 2195//===----------------------------------------------------------------------===// 2196 2197let Predicates = [UnsafeFPMath] in { 2198 2199//def : RcpPat<V_RCP_F64_e32, f64>; 2200//defm : RsqPat<V_RSQ_F64_e32, f64>; 2201//defm : RsqPat<V_RSQ_F32_e32, f32>; 2202 2203def : RsqPat<V_RSQ_F32_e32, f32>; 2204def : RsqPat<V_RSQ_F64_e32, f64>; 2205} 2206 2207//===----------------------------------------------------------------------===// 2208// VOP2 Patterns 2209//===----------------------------------------------------------------------===// 2210 2211def : Pat < 2212 (i32 (add (i32 (ctpop i32:$popcnt)), i32:$val)), 2213 (V_BCNT_U32_B32_e64 $popcnt, $val) 2214>; 2215 2216def : Pat < 2217 (i32 (select i1:$src0, i32:$src1, i32:$src2)), 2218 (V_CNDMASK_B32_e64 $src2, $src1, $src0) 2219>; 2220 2221// Pattern for V_MAC_F32 2222def : Pat < 2223 (fmad (VOP3NoMods0 f32:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod), 2224 (VOP3NoMods f32:$src1, i32:$src1_modifiers), 2225 (VOP3NoMods f32:$src2, i32:$src2_modifiers)), 2226 (V_MAC_F32_e64 $src0_modifiers, $src0, $src1_modifiers, $src1, 2227 $src2_modifiers, $src2, $clamp, $omod) 2228>; 2229 2230/********** ======================= **********/ 2231/********** Image sampling patterns **********/ 2232/********** ======================= **********/ 2233 2234// Image + sampler 2235class SampleRawPattern<SDPatternOperator name, MIMG opcode, ValueType vt> : Pat < 2236 (name vt:$addr, v8i32:$rsrc, v4i32:$sampler, i32:$dmask, i32:$unorm, 2237 i32:$r128, i32:$da, i32:$glc, i32:$slc, i32:$tfe, i32:$lwe), 2238 (opcode $addr, $rsrc, $sampler, 2239 (as_i32imm $dmask), (as_i1imm $unorm), (as_i1imm $glc), (as_i1imm $slc), 2240 (as_i1imm $r128), (as_i1imm $tfe), (as_i1imm $lwe), (as_i1imm $da)) 2241>; 2242 2243multiclass SampleRawPatterns<SDPatternOperator name, string opcode> { 2244 def : SampleRawPattern<name, !cast<MIMG>(opcode # _V4_V1), i32>; 2245 def : SampleRawPattern<name, !cast<MIMG>(opcode # _V4_V2), v2i32>; 2246 def : SampleRawPattern<name, !cast<MIMG>(opcode # _V4_V4), v4i32>; 2247 def : SampleRawPattern<name, !cast<MIMG>(opcode # _V4_V8), v8i32>; 2248 def : SampleRawPattern<name, !cast<MIMG>(opcode # _V4_V16), v16i32>; 2249} 2250 2251// Image only 2252class ImagePattern<SDPatternOperator name, MIMG opcode, ValueType vt> : Pat < 2253 (name vt:$addr, v8i32:$rsrc, imm:$dmask, imm:$unorm, 2254 imm:$r128, imm:$da, imm:$glc, imm:$slc, imm:$tfe, imm:$lwe), 2255 (opcode $addr, $rsrc, 2256 (as_i32imm $dmask), (as_i1imm $unorm), (as_i1imm $glc), (as_i1imm $slc), 2257 (as_i1imm $r128), (as_i1imm $tfe), (as_i1imm $lwe), (as_i1imm $da)) 2258>; 2259 2260multiclass ImagePatterns<SDPatternOperator name, string opcode> { 2261 def : ImagePattern<name, !cast<MIMG>(opcode # _V4_V1), i32>; 2262 def : ImagePattern<name, !cast<MIMG>(opcode # _V4_V2), v2i32>; 2263 def : ImagePattern<name, !cast<MIMG>(opcode # _V4_V4), v4i32>; 2264} 2265 2266class ImageLoadPattern<SDPatternOperator name, MIMG opcode, ValueType vt> : Pat < 2267 (name vt:$addr, v8i32:$rsrc, imm:$dmask, imm:$r128, imm:$da, imm:$glc, 2268 imm:$slc), 2269 (opcode $addr, $rsrc, 2270 (as_i32imm $dmask), 1, (as_i1imm $glc), (as_i1imm $slc), 2271 (as_i1imm $r128), 0, 0, (as_i1imm $da)) 2272>; 2273 2274multiclass ImageLoadPatterns<SDPatternOperator name, string opcode> { 2275 def : ImageLoadPattern<name, !cast<MIMG>(opcode # _V4_V1), i32>; 2276 def : ImageLoadPattern<name, !cast<MIMG>(opcode # _V4_V2), v2i32>; 2277 def : ImageLoadPattern<name, !cast<MIMG>(opcode # _V4_V4), v4i32>; 2278} 2279 2280class ImageStorePattern<SDPatternOperator name, MIMG opcode, ValueType vt> : Pat < 2281 (name v4f32:$data, vt:$addr, v8i32:$rsrc, i32:$dmask, imm:$r128, imm:$da, 2282 imm:$glc, imm:$slc), 2283 (opcode $data, $addr, $rsrc, 2284 (as_i32imm $dmask), 1, (as_i1imm $glc), (as_i1imm $slc), 2285 (as_i1imm $r128), 0, 0, (as_i1imm $da)) 2286>; 2287 2288multiclass ImageStorePatterns<SDPatternOperator name, string opcode> { 2289 def : ImageStorePattern<name, !cast<MIMG>(opcode # _V4_V1), i32>; 2290 def : ImageStorePattern<name, !cast<MIMG>(opcode # _V4_V2), v2i32>; 2291 def : ImageStorePattern<name, !cast<MIMG>(opcode # _V4_V4), v4i32>; 2292} 2293 2294// Basic sample 2295defm : SampleRawPatterns<int_SI_image_sample, "IMAGE_SAMPLE">; 2296defm : SampleRawPatterns<int_SI_image_sample_cl, "IMAGE_SAMPLE_CL">; 2297defm : SampleRawPatterns<int_SI_image_sample_d, "IMAGE_SAMPLE_D">; 2298defm : SampleRawPatterns<int_SI_image_sample_d_cl, "IMAGE_SAMPLE_D_CL">; 2299defm : SampleRawPatterns<int_SI_image_sample_l, "IMAGE_SAMPLE_L">; 2300defm : SampleRawPatterns<int_SI_image_sample_b, "IMAGE_SAMPLE_B">; 2301defm : SampleRawPatterns<int_SI_image_sample_b_cl, "IMAGE_SAMPLE_B_CL">; 2302defm : SampleRawPatterns<int_SI_image_sample_lz, "IMAGE_SAMPLE_LZ">; 2303defm : SampleRawPatterns<int_SI_image_sample_cd, "IMAGE_SAMPLE_CD">; 2304defm : SampleRawPatterns<int_SI_image_sample_cd_cl, "IMAGE_SAMPLE_CD_CL">; 2305 2306// Sample with comparison 2307defm : SampleRawPatterns<int_SI_image_sample_c, "IMAGE_SAMPLE_C">; 2308defm : SampleRawPatterns<int_SI_image_sample_c_cl, "IMAGE_SAMPLE_C_CL">; 2309defm : SampleRawPatterns<int_SI_image_sample_c_d, "IMAGE_SAMPLE_C_D">; 2310defm : SampleRawPatterns<int_SI_image_sample_c_d_cl, "IMAGE_SAMPLE_C_D_CL">; 2311defm : SampleRawPatterns<int_SI_image_sample_c_l, "IMAGE_SAMPLE_C_L">; 2312defm : SampleRawPatterns<int_SI_image_sample_c_b, "IMAGE_SAMPLE_C_B">; 2313defm : SampleRawPatterns<int_SI_image_sample_c_b_cl, "IMAGE_SAMPLE_C_B_CL">; 2314defm : SampleRawPatterns<int_SI_image_sample_c_lz, "IMAGE_SAMPLE_C_LZ">; 2315defm : SampleRawPatterns<int_SI_image_sample_c_cd, "IMAGE_SAMPLE_C_CD">; 2316defm : SampleRawPatterns<int_SI_image_sample_c_cd_cl, "IMAGE_SAMPLE_C_CD_CL">; 2317 2318// Sample with offsets 2319defm : SampleRawPatterns<int_SI_image_sample_o, "IMAGE_SAMPLE_O">; 2320defm : SampleRawPatterns<int_SI_image_sample_cl_o, "IMAGE_SAMPLE_CL_O">; 2321defm : SampleRawPatterns<int_SI_image_sample_d_o, "IMAGE_SAMPLE_D_O">; 2322defm : SampleRawPatterns<int_SI_image_sample_d_cl_o, "IMAGE_SAMPLE_D_CL_O">; 2323defm : SampleRawPatterns<int_SI_image_sample_l_o, "IMAGE_SAMPLE_L_O">; 2324defm : SampleRawPatterns<int_SI_image_sample_b_o, "IMAGE_SAMPLE_B_O">; 2325defm : SampleRawPatterns<int_SI_image_sample_b_cl_o, "IMAGE_SAMPLE_B_CL_O">; 2326defm : SampleRawPatterns<int_SI_image_sample_lz_o, "IMAGE_SAMPLE_LZ_O">; 2327defm : SampleRawPatterns<int_SI_image_sample_cd_o, "IMAGE_SAMPLE_CD_O">; 2328defm : SampleRawPatterns<int_SI_image_sample_cd_cl_o, "IMAGE_SAMPLE_CD_CL_O">; 2329 2330// Sample with comparison and offsets 2331defm : SampleRawPatterns<int_SI_image_sample_c_o, "IMAGE_SAMPLE_C_O">; 2332defm : SampleRawPatterns<int_SI_image_sample_c_cl_o, "IMAGE_SAMPLE_C_CL_O">; 2333defm : SampleRawPatterns<int_SI_image_sample_c_d_o, "IMAGE_SAMPLE_C_D_O">; 2334defm : SampleRawPatterns<int_SI_image_sample_c_d_cl_o, "IMAGE_SAMPLE_C_D_CL_O">; 2335defm : SampleRawPatterns<int_SI_image_sample_c_l_o, "IMAGE_SAMPLE_C_L_O">; 2336defm : SampleRawPatterns<int_SI_image_sample_c_b_o, "IMAGE_SAMPLE_C_B_O">; 2337defm : SampleRawPatterns<int_SI_image_sample_c_b_cl_o, "IMAGE_SAMPLE_C_B_CL_O">; 2338defm : SampleRawPatterns<int_SI_image_sample_c_lz_o, "IMAGE_SAMPLE_C_LZ_O">; 2339defm : SampleRawPatterns<int_SI_image_sample_c_cd_o, "IMAGE_SAMPLE_C_CD_O">; 2340defm : SampleRawPatterns<int_SI_image_sample_c_cd_cl_o, "IMAGE_SAMPLE_C_CD_CL_O">; 2341 2342// Gather opcodes 2343// Only the variants which make sense are defined. 2344def : SampleRawPattern<int_SI_gather4, IMAGE_GATHER4_V4_V2, v2i32>; 2345def : SampleRawPattern<int_SI_gather4, IMAGE_GATHER4_V4_V4, v4i32>; 2346def : SampleRawPattern<int_SI_gather4_cl, IMAGE_GATHER4_CL_V4_V4, v4i32>; 2347def : SampleRawPattern<int_SI_gather4_l, IMAGE_GATHER4_L_V4_V4, v4i32>; 2348def : SampleRawPattern<int_SI_gather4_b, IMAGE_GATHER4_B_V4_V4, v4i32>; 2349def : SampleRawPattern<int_SI_gather4_b_cl, IMAGE_GATHER4_B_CL_V4_V4, v4i32>; 2350def : SampleRawPattern<int_SI_gather4_b_cl, IMAGE_GATHER4_B_CL_V4_V8, v8i32>; 2351def : SampleRawPattern<int_SI_gather4_lz, IMAGE_GATHER4_LZ_V4_V2, v2i32>; 2352def : SampleRawPattern<int_SI_gather4_lz, IMAGE_GATHER4_LZ_V4_V4, v4i32>; 2353 2354def : SampleRawPattern<int_SI_gather4_c, IMAGE_GATHER4_C_V4_V4, v4i32>; 2355def : SampleRawPattern<int_SI_gather4_c_cl, IMAGE_GATHER4_C_CL_V4_V4, v4i32>; 2356def : SampleRawPattern<int_SI_gather4_c_cl, IMAGE_GATHER4_C_CL_V4_V8, v8i32>; 2357def : SampleRawPattern<int_SI_gather4_c_l, IMAGE_GATHER4_C_L_V4_V4, v4i32>; 2358def : SampleRawPattern<int_SI_gather4_c_l, IMAGE_GATHER4_C_L_V4_V8, v8i32>; 2359def : SampleRawPattern<int_SI_gather4_c_b, IMAGE_GATHER4_C_B_V4_V4, v4i32>; 2360def : SampleRawPattern<int_SI_gather4_c_b, IMAGE_GATHER4_C_B_V4_V8, v8i32>; 2361def : SampleRawPattern<int_SI_gather4_c_b_cl, IMAGE_GATHER4_C_B_CL_V4_V8, v8i32>; 2362def : SampleRawPattern<int_SI_gather4_c_lz, IMAGE_GATHER4_C_LZ_V4_V4, v4i32>; 2363 2364def : SampleRawPattern<int_SI_gather4_o, IMAGE_GATHER4_O_V4_V4, v4i32>; 2365def : SampleRawPattern<int_SI_gather4_cl_o, IMAGE_GATHER4_CL_O_V4_V4, v4i32>; 2366def : SampleRawPattern<int_SI_gather4_cl_o, IMAGE_GATHER4_CL_O_V4_V8, v8i32>; 2367def : SampleRawPattern<int_SI_gather4_l_o, IMAGE_GATHER4_L_O_V4_V4, v4i32>; 2368def : SampleRawPattern<int_SI_gather4_l_o, IMAGE_GATHER4_L_O_V4_V8, v8i32>; 2369def : SampleRawPattern<int_SI_gather4_b_o, IMAGE_GATHER4_B_O_V4_V4, v4i32>; 2370def : SampleRawPattern<int_SI_gather4_b_o, IMAGE_GATHER4_B_O_V4_V8, v8i32>; 2371def : SampleRawPattern<int_SI_gather4_b_cl_o, IMAGE_GATHER4_B_CL_O_V4_V8, v8i32>; 2372def : SampleRawPattern<int_SI_gather4_lz_o, IMAGE_GATHER4_LZ_O_V4_V4, v4i32>; 2373 2374def : SampleRawPattern<int_SI_gather4_c_o, IMAGE_GATHER4_C_O_V4_V4, v4i32>; 2375def : SampleRawPattern<int_SI_gather4_c_o, IMAGE_GATHER4_C_O_V4_V8, v8i32>; 2376def : SampleRawPattern<int_SI_gather4_c_cl_o, IMAGE_GATHER4_C_CL_O_V4_V8, v8i32>; 2377def : SampleRawPattern<int_SI_gather4_c_l_o, IMAGE_GATHER4_C_L_O_V4_V8, v8i32>; 2378def : SampleRawPattern<int_SI_gather4_c_b_o, IMAGE_GATHER4_C_B_O_V4_V8, v8i32>; 2379def : SampleRawPattern<int_SI_gather4_c_b_cl_o, IMAGE_GATHER4_C_B_CL_O_V4_V8, v8i32>; 2380def : SampleRawPattern<int_SI_gather4_c_lz_o, IMAGE_GATHER4_C_LZ_O_V4_V4, v4i32>; 2381def : SampleRawPattern<int_SI_gather4_c_lz_o, IMAGE_GATHER4_C_LZ_O_V4_V8, v8i32>; 2382 2383def : SampleRawPattern<int_SI_getlod, IMAGE_GET_LOD_V4_V1, i32>; 2384def : SampleRawPattern<int_SI_getlod, IMAGE_GET_LOD_V4_V2, v2i32>; 2385def : SampleRawPattern<int_SI_getlod, IMAGE_GET_LOD_V4_V4, v4i32>; 2386 2387def : ImagePattern<int_SI_getresinfo, IMAGE_GET_RESINFO_V4_V1, i32>; 2388defm : ImagePatterns<int_SI_image_load, "IMAGE_LOAD">; 2389defm : ImagePatterns<int_SI_image_load_mip, "IMAGE_LOAD_MIP">; 2390defm : ImageLoadPatterns<int_amdgcn_image_load, "IMAGE_LOAD">; 2391defm : ImageLoadPatterns<int_amdgcn_image_load_mip, "IMAGE_LOAD_MIP">; 2392defm : ImageStorePatterns<int_amdgcn_image_store, "IMAGE_STORE">; 2393defm : ImageStorePatterns<int_amdgcn_image_store_mip, "IMAGE_STORE_MIP">; 2394 2395/* SIsample for simple 1D texture lookup */ 2396def : Pat < 2397 (SIsample i32:$addr, v8i32:$rsrc, v4i32:$sampler, imm), 2398 (IMAGE_SAMPLE_V4_V1 $addr, $rsrc, $sampler, 0xf, 0, 0, 0, 0, 0, 0, 0) 2399>; 2400 2401class SamplePattern<SDNode name, MIMG opcode, ValueType vt> : Pat < 2402 (name vt:$addr, v8i32:$rsrc, v4i32:$sampler, imm), 2403 (opcode $addr, $rsrc, $sampler, 0xf, 0, 0, 0, 0, 0, 0, 0) 2404>; 2405 2406class SampleRectPattern<SDNode name, MIMG opcode, ValueType vt> : Pat < 2407 (name vt:$addr, v8i32:$rsrc, v4i32:$sampler, TEX_RECT), 2408 (opcode $addr, $rsrc, $sampler, 0xf, 1, 0, 0, 0, 0, 0, 0) 2409>; 2410 2411class SampleArrayPattern<SDNode name, MIMG opcode, ValueType vt> : Pat < 2412 (name vt:$addr, v8i32:$rsrc, v4i32:$sampler, TEX_ARRAY), 2413 (opcode $addr, $rsrc, $sampler, 0xf, 0, 0, 0, 0, 0, 0, 1) 2414>; 2415 2416class SampleShadowPattern<SDNode name, MIMG opcode, 2417 ValueType vt> : Pat < 2418 (name vt:$addr, v8i32:$rsrc, v4i32:$sampler, TEX_SHADOW), 2419 (opcode $addr, $rsrc, $sampler, 0xf, 0, 0, 0, 0, 0, 0, 0) 2420>; 2421 2422class SampleShadowArrayPattern<SDNode name, MIMG opcode, 2423 ValueType vt> : Pat < 2424 (name vt:$addr, v8i32:$rsrc, v4i32:$sampler, TEX_SHADOW_ARRAY), 2425 (opcode $addr, $rsrc, $sampler, 0xf, 0, 0, 0, 0, 0, 0, 1) 2426>; 2427 2428/* SIsample* for texture lookups consuming more address parameters */ 2429multiclass SamplePatterns<MIMG sample, MIMG sample_c, MIMG sample_l, 2430 MIMG sample_c_l, MIMG sample_b, MIMG sample_c_b, 2431MIMG sample_d, MIMG sample_c_d, ValueType addr_type> { 2432 def : SamplePattern <SIsample, sample, addr_type>; 2433 def : SampleRectPattern <SIsample, sample, addr_type>; 2434 def : SampleArrayPattern <SIsample, sample, addr_type>; 2435 def : SampleShadowPattern <SIsample, sample_c, addr_type>; 2436 def : SampleShadowArrayPattern <SIsample, sample_c, addr_type>; 2437 2438 def : SamplePattern <SIsamplel, sample_l, addr_type>; 2439 def : SampleArrayPattern <SIsamplel, sample_l, addr_type>; 2440 def : SampleShadowPattern <SIsamplel, sample_c_l, addr_type>; 2441 def : SampleShadowArrayPattern <SIsamplel, sample_c_l, addr_type>; 2442 2443 def : SamplePattern <SIsampleb, sample_b, addr_type>; 2444 def : SampleArrayPattern <SIsampleb, sample_b, addr_type>; 2445 def : SampleShadowPattern <SIsampleb, sample_c_b, addr_type>; 2446 def : SampleShadowArrayPattern <SIsampleb, sample_c_b, addr_type>; 2447 2448 def : SamplePattern <SIsampled, sample_d, addr_type>; 2449 def : SampleArrayPattern <SIsampled, sample_d, addr_type>; 2450 def : SampleShadowPattern <SIsampled, sample_c_d, addr_type>; 2451 def : SampleShadowArrayPattern <SIsampled, sample_c_d, addr_type>; 2452} 2453 2454defm : SamplePatterns<IMAGE_SAMPLE_V4_V2, IMAGE_SAMPLE_C_V4_V2, 2455 IMAGE_SAMPLE_L_V4_V2, IMAGE_SAMPLE_C_L_V4_V2, 2456 IMAGE_SAMPLE_B_V4_V2, IMAGE_SAMPLE_C_B_V4_V2, 2457 IMAGE_SAMPLE_D_V4_V2, IMAGE_SAMPLE_C_D_V4_V2, 2458 v2i32>; 2459defm : SamplePatterns<IMAGE_SAMPLE_V4_V4, IMAGE_SAMPLE_C_V4_V4, 2460 IMAGE_SAMPLE_L_V4_V4, IMAGE_SAMPLE_C_L_V4_V4, 2461 IMAGE_SAMPLE_B_V4_V4, IMAGE_SAMPLE_C_B_V4_V4, 2462 IMAGE_SAMPLE_D_V4_V4, IMAGE_SAMPLE_C_D_V4_V4, 2463 v4i32>; 2464defm : SamplePatterns<IMAGE_SAMPLE_V4_V8, IMAGE_SAMPLE_C_V4_V8, 2465 IMAGE_SAMPLE_L_V4_V8, IMAGE_SAMPLE_C_L_V4_V8, 2466 IMAGE_SAMPLE_B_V4_V8, IMAGE_SAMPLE_C_B_V4_V8, 2467 IMAGE_SAMPLE_D_V4_V8, IMAGE_SAMPLE_C_D_V4_V8, 2468 v8i32>; 2469defm : SamplePatterns<IMAGE_SAMPLE_V4_V16, IMAGE_SAMPLE_C_V4_V16, 2470 IMAGE_SAMPLE_L_V4_V16, IMAGE_SAMPLE_C_L_V4_V16, 2471 IMAGE_SAMPLE_B_V4_V16, IMAGE_SAMPLE_C_B_V4_V16, 2472 IMAGE_SAMPLE_D_V4_V16, IMAGE_SAMPLE_C_D_V4_V16, 2473 v16i32>; 2474 2475/********** ============================================ **********/ 2476/********** Extraction, Insertion, Building and Casting **********/ 2477/********** ============================================ **********/ 2478 2479foreach Index = 0-2 in { 2480 def Extract_Element_v2i32_#Index : Extract_Element < 2481 i32, v2i32, Index, !cast<SubRegIndex>(sub#Index) 2482 >; 2483 def Insert_Element_v2i32_#Index : Insert_Element < 2484 i32, v2i32, Index, !cast<SubRegIndex>(sub#Index) 2485 >; 2486 2487 def Extract_Element_v2f32_#Index : Extract_Element < 2488 f32, v2f32, Index, !cast<SubRegIndex>(sub#Index) 2489 >; 2490 def Insert_Element_v2f32_#Index : Insert_Element < 2491 f32, v2f32, Index, !cast<SubRegIndex>(sub#Index) 2492 >; 2493} 2494 2495foreach Index = 0-3 in { 2496 def Extract_Element_v4i32_#Index : Extract_Element < 2497 i32, v4i32, Index, !cast<SubRegIndex>(sub#Index) 2498 >; 2499 def Insert_Element_v4i32_#Index : Insert_Element < 2500 i32, v4i32, Index, !cast<SubRegIndex>(sub#Index) 2501 >; 2502 2503 def Extract_Element_v4f32_#Index : Extract_Element < 2504 f32, v4f32, Index, !cast<SubRegIndex>(sub#Index) 2505 >; 2506 def Insert_Element_v4f32_#Index : Insert_Element < 2507 f32, v4f32, Index, !cast<SubRegIndex>(sub#Index) 2508 >; 2509} 2510 2511foreach Index = 0-7 in { 2512 def Extract_Element_v8i32_#Index : Extract_Element < 2513 i32, v8i32, Index, !cast<SubRegIndex>(sub#Index) 2514 >; 2515 def Insert_Element_v8i32_#Index : Insert_Element < 2516 i32, v8i32, Index, !cast<SubRegIndex>(sub#Index) 2517 >; 2518 2519 def Extract_Element_v8f32_#Index : Extract_Element < 2520 f32, v8f32, Index, !cast<SubRegIndex>(sub#Index) 2521 >; 2522 def Insert_Element_v8f32_#Index : Insert_Element < 2523 f32, v8f32, Index, !cast<SubRegIndex>(sub#Index) 2524 >; 2525} 2526 2527foreach Index = 0-15 in { 2528 def Extract_Element_v16i32_#Index : Extract_Element < 2529 i32, v16i32, Index, !cast<SubRegIndex>(sub#Index) 2530 >; 2531 def Insert_Element_v16i32_#Index : Insert_Element < 2532 i32, v16i32, Index, !cast<SubRegIndex>(sub#Index) 2533 >; 2534 2535 def Extract_Element_v16f32_#Index : Extract_Element < 2536 f32, v16f32, Index, !cast<SubRegIndex>(sub#Index) 2537 >; 2538 def Insert_Element_v16f32_#Index : Insert_Element < 2539 f32, v16f32, Index, !cast<SubRegIndex>(sub#Index) 2540 >; 2541} 2542 2543// FIXME: Why do only some of these type combinations for SReg and 2544// VReg? 2545// 32-bit bitcast 2546def : BitConvert <i32, f32, VGPR_32>; 2547def : BitConvert <f32, i32, VGPR_32>; 2548def : BitConvert <i32, f32, SReg_32>; 2549def : BitConvert <f32, i32, SReg_32>; 2550 2551// 64-bit bitcast 2552def : BitConvert <i64, f64, VReg_64>; 2553def : BitConvert <f64, i64, VReg_64>; 2554def : BitConvert <v2i32, v2f32, VReg_64>; 2555def : BitConvert <v2f32, v2i32, VReg_64>; 2556def : BitConvert <i64, v2i32, VReg_64>; 2557def : BitConvert <v2i32, i64, VReg_64>; 2558def : BitConvert <i64, v2f32, VReg_64>; 2559def : BitConvert <v2f32, i64, VReg_64>; 2560def : BitConvert <f64, v2f32, VReg_64>; 2561def : BitConvert <v2f32, f64, VReg_64>; 2562def : BitConvert <f64, v2i32, VReg_64>; 2563def : BitConvert <v2i32, f64, VReg_64>; 2564def : BitConvert <v4i32, v4f32, VReg_128>; 2565def : BitConvert <v4f32, v4i32, VReg_128>; 2566 2567// 128-bit bitcast 2568def : BitConvert <v2i64, v4i32, SReg_128>; 2569def : BitConvert <v4i32, v2i64, SReg_128>; 2570def : BitConvert <v2f64, v4f32, VReg_128>; 2571def : BitConvert <v2f64, v4i32, VReg_128>; 2572def : BitConvert <v4f32, v2f64, VReg_128>; 2573def : BitConvert <v4i32, v2f64, VReg_128>; 2574 2575// 256-bit bitcast 2576def : BitConvert <v8i32, v8f32, SReg_256>; 2577def : BitConvert <v8f32, v8i32, SReg_256>; 2578def : BitConvert <v8i32, v8f32, VReg_256>; 2579def : BitConvert <v8f32, v8i32, VReg_256>; 2580 2581// 512-bit bitcast 2582def : BitConvert <v16i32, v16f32, VReg_512>; 2583def : BitConvert <v16f32, v16i32, VReg_512>; 2584 2585/********** =================== **********/ 2586/********** Src & Dst modifiers **********/ 2587/********** =================== **********/ 2588 2589def : Pat < 2590 (AMDGPUclamp (VOP3Mods0Clamp f32:$src0, i32:$src0_modifiers, i32:$omod), 2591 (f32 FP_ZERO), (f32 FP_ONE)), 2592 (V_ADD_F32_e64 $src0_modifiers, $src0, 0, 0, 1, $omod) 2593>; 2594 2595/********** ================================ **********/ 2596/********** Floating point absolute/negative **********/ 2597/********** ================================ **********/ 2598 2599// Prevent expanding both fneg and fabs. 2600 2601def : Pat < 2602 (fneg (fabs f32:$src)), 2603 (S_OR_B32 $src, 0x80000000) // Set sign bit 2604>; 2605 2606// FIXME: Should use S_OR_B32 2607def : Pat < 2608 (fneg (fabs f64:$src)), 2609 (REG_SEQUENCE VReg_64, 2610 (i32 (EXTRACT_SUBREG f64:$src, sub0)), 2611 sub0, 2612 (V_OR_B32_e32 (EXTRACT_SUBREG f64:$src, sub1), 2613 (V_MOV_B32_e32 0x80000000)), // Set sign bit. 2614 sub1) 2615>; 2616 2617def : Pat < 2618 (fabs f32:$src), 2619 (V_AND_B32_e32 $src, (V_MOV_B32_e32 0x7fffffff)) 2620>; 2621 2622def : Pat < 2623 (fneg f32:$src), 2624 (V_XOR_B32_e32 $src, (V_MOV_B32_e32 0x80000000)) 2625>; 2626 2627def : Pat < 2628 (fabs f64:$src), 2629 (REG_SEQUENCE VReg_64, 2630 (i32 (EXTRACT_SUBREG f64:$src, sub0)), 2631 sub0, 2632 (V_AND_B32_e32 (EXTRACT_SUBREG f64:$src, sub1), 2633 (V_MOV_B32_e32 0x7fffffff)), // Set sign bit. 2634 sub1) 2635>; 2636 2637def : Pat < 2638 (fneg f64:$src), 2639 (REG_SEQUENCE VReg_64, 2640 (i32 (EXTRACT_SUBREG f64:$src, sub0)), 2641 sub0, 2642 (V_XOR_B32_e32 (EXTRACT_SUBREG f64:$src, sub1), 2643 (V_MOV_B32_e32 0x80000000)), 2644 sub1) 2645>; 2646 2647/********** ================== **********/ 2648/********** Immediate Patterns **********/ 2649/********** ================== **********/ 2650 2651def : Pat < 2652 (SGPRImm<(i32 imm)>:$imm), 2653 (S_MOV_B32 imm:$imm) 2654>; 2655 2656def : Pat < 2657 (SGPRImm<(f32 fpimm)>:$imm), 2658 (S_MOV_B32 (f32 (bitcast_fpimm_to_i32 $imm))) 2659>; 2660 2661def : Pat < 2662 (i32 imm:$imm), 2663 (V_MOV_B32_e32 imm:$imm) 2664>; 2665 2666def : Pat < 2667 (f32 fpimm:$imm), 2668 (V_MOV_B32_e32 (f32 (bitcast_fpimm_to_i32 $imm))) 2669>; 2670 2671def : Pat < 2672 (i64 InlineImm<i64>:$imm), 2673 (S_MOV_B64 InlineImm<i64>:$imm) 2674>; 2675 2676// XXX - Should this use a s_cmp to set SCC? 2677 2678// Set to sign-extended 64-bit value (true = -1, false = 0) 2679def : Pat < 2680 (i1 imm:$imm), 2681 (S_MOV_B64 (i64 (as_i64imm $imm))) 2682>; 2683 2684def : Pat < 2685 (f64 InlineFPImm<f64>:$imm), 2686 (S_MOV_B64 (f64 (bitcast_fpimm_to_i64 InlineFPImm<f64>:$imm))) 2687>; 2688 2689/********** ================== **********/ 2690/********** Intrinsic Patterns **********/ 2691/********** ================== **********/ 2692 2693def : POW_Common <V_LOG_F32_e32, V_EXP_F32_e32, V_MUL_LEGACY_F32_e32>; 2694 2695def : Pat < 2696 (int_AMDGPU_cube v4f32:$src), 2697 (REG_SEQUENCE VReg_128, 2698 (V_CUBETC_F32 0 /* src0_modifiers */, (EXTRACT_SUBREG $src, sub0), 2699 0 /* src1_modifiers */, (EXTRACT_SUBREG $src, sub1), 2700 0 /* src2_modifiers */, (EXTRACT_SUBREG $src, sub2), 2701 0 /* clamp */, 0 /* omod */), sub0, 2702 (V_CUBESC_F32 0 /* src0_modifiers */, (EXTRACT_SUBREG $src, sub0), 2703 0 /* src1_modifiers */,(EXTRACT_SUBREG $src, sub1), 2704 0 /* src2_modifiers */,(EXTRACT_SUBREG $src, sub2), 2705 0 /* clamp */, 0 /* omod */), sub1, 2706 (V_CUBEMA_F32 0 /* src1_modifiers */,(EXTRACT_SUBREG $src, sub0), 2707 0 /* src1_modifiers */,(EXTRACT_SUBREG $src, sub1), 2708 0 /* src1_modifiers */,(EXTRACT_SUBREG $src, sub2), 2709 0 /* clamp */, 0 /* omod */), sub2, 2710 (V_CUBEID_F32 0 /* src1_modifiers */,(EXTRACT_SUBREG $src, sub0), 2711 0 /* src1_modifiers */,(EXTRACT_SUBREG $src, sub1), 2712 0 /* src1_modifiers */,(EXTRACT_SUBREG $src, sub2), 2713 0 /* clamp */, 0 /* omod */), sub3) 2714>; 2715 2716def : Pat < 2717 (i32 (sext i1:$src0)), 2718 (V_CNDMASK_B32_e64 (i32 0), (i32 -1), $src0) 2719>; 2720 2721class Ext32Pat <SDNode ext> : Pat < 2722 (i32 (ext i1:$src0)), 2723 (V_CNDMASK_B32_e64 (i32 0), (i32 1), $src0) 2724>; 2725 2726def : Ext32Pat <zext>; 2727def : Ext32Pat <anyext>; 2728 2729// Offset in an 32-bit VGPR 2730def : Pat < 2731 (SIload_constant v4i32:$sbase, i32:$voff), 2732 (BUFFER_LOAD_DWORD_OFFEN $voff, $sbase, 0, 0, 0, 0, 0) 2733>; 2734 2735// The multiplication scales from [0,1] to the unsigned integer range 2736def : Pat < 2737 (AMDGPUurecip i32:$src0), 2738 (V_CVT_U32_F32_e32 2739 (V_MUL_F32_e32 CONST.FP_UINT_MAX_PLUS_1, 2740 (V_RCP_IFLAG_F32_e32 (V_CVT_F32_U32_e32 $src0)))) 2741>; 2742 2743def : Pat < 2744 (int_SI_tid), 2745 (V_MBCNT_HI_U32_B32_e64 0xffffffff, 2746 (V_MBCNT_LO_U32_B32_e64 0xffffffff, 0)) 2747>; 2748 2749//===----------------------------------------------------------------------===// 2750// VOP3 Patterns 2751//===----------------------------------------------------------------------===// 2752 2753def : IMad24Pat<V_MAD_I32_I24>; 2754def : UMad24Pat<V_MAD_U32_U24>; 2755 2756defm : BFIPatterns <V_BFI_B32, S_MOV_B32, SReg_64>; 2757def : ROTRPattern <V_ALIGNBIT_B32>; 2758 2759/********** ======================= **********/ 2760/********** Load/Store Patterns **********/ 2761/********** ======================= **********/ 2762 2763class DSReadPat <DS inst, ValueType vt, PatFrag frag> : Pat < 2764 (vt (frag (DS1Addr1Offset i32:$ptr, i32:$offset))), 2765 (inst $ptr, (as_i16imm $offset), (i1 0)) 2766>; 2767 2768def : DSReadPat <DS_READ_I8, i32, si_sextload_local_i8>; 2769def : DSReadPat <DS_READ_U8, i32, si_az_extload_local_i8>; 2770def : DSReadPat <DS_READ_I16, i32, si_sextload_local_i16>; 2771def : DSReadPat <DS_READ_U16, i32, si_az_extload_local_i16>; 2772def : DSReadPat <DS_READ_B32, i32, si_load_local>; 2773 2774let AddedComplexity = 100 in { 2775 2776def : DSReadPat <DS_READ_B64, v2i32, si_load_local_align8>; 2777 2778} // End AddedComplexity = 100 2779 2780def : Pat < 2781 (v2i32 (si_load_local (DS64Bit4ByteAligned i32:$ptr, i8:$offset0, 2782 i8:$offset1))), 2783 (DS_READ2_B32 $ptr, $offset0, $offset1, (i1 0)) 2784>; 2785 2786class DSWritePat <DS inst, ValueType vt, PatFrag frag> : Pat < 2787 (frag vt:$value, (DS1Addr1Offset i32:$ptr, i32:$offset)), 2788 (inst $ptr, $value, (as_i16imm $offset), (i1 0)) 2789>; 2790 2791def : DSWritePat <DS_WRITE_B8, i32, si_truncstore_local_i8>; 2792def : DSWritePat <DS_WRITE_B16, i32, si_truncstore_local_i16>; 2793def : DSWritePat <DS_WRITE_B32, i32, si_store_local>; 2794 2795let AddedComplexity = 100 in { 2796 2797def : DSWritePat <DS_WRITE_B64, v2i32, si_store_local_align8>; 2798} // End AddedComplexity = 100 2799 2800def : Pat < 2801 (si_store_local v2i32:$value, (DS64Bit4ByteAligned i32:$ptr, i8:$offset0, 2802 i8:$offset1)), 2803 (DS_WRITE2_B32 $ptr, (EXTRACT_SUBREG $value, sub0), 2804 (EXTRACT_SUBREG $value, sub1), $offset0, $offset1, 2805 (i1 0)) 2806>; 2807 2808class DSAtomicRetPat<DS inst, ValueType vt, PatFrag frag> : Pat < 2809 (frag (DS1Addr1Offset i32:$ptr, i32:$offset), vt:$value), 2810 (inst $ptr, $value, (as_i16imm $offset), (i1 0)) 2811>; 2812 2813// Special case of DSAtomicRetPat for add / sub 1 -> inc / dec 2814// 2815// We need to use something for the data0, so we set a register to 2816// -1. For the non-rtn variants, the manual says it does 2817// DS[A] = (DS[A] >= D0) ? 0 : DS[A] + 1, and setting D0 to uint_max 2818// will always do the increment so I'm assuming it's the same. 2819class DSAtomicIncRetPat<DS inst, ValueType vt, 2820 Instruction LoadImm, PatFrag frag> : Pat < 2821 (frag (DS1Addr1Offset i32:$ptr, i32:$offset), (vt 1)), 2822 (inst $ptr, (LoadImm (vt -1)), (as_i16imm $offset), (i1 0)) 2823>; 2824 2825 2826class DSAtomicCmpXChg <DS inst, ValueType vt, PatFrag frag> : Pat < 2827 (frag (DS1Addr1Offset i32:$ptr, i32:$offset), vt:$cmp, vt:$swap), 2828 (inst $ptr, $cmp, $swap, (as_i16imm $offset), (i1 0)) 2829>; 2830 2831 2832// 32-bit atomics. 2833def : DSAtomicIncRetPat<DS_INC_RTN_U32, i32, 2834 V_MOV_B32_e32, si_atomic_load_add_local>; 2835def : DSAtomicIncRetPat<DS_DEC_RTN_U32, i32, 2836 V_MOV_B32_e32, si_atomic_load_sub_local>; 2837 2838def : DSAtomicRetPat<DS_WRXCHG_RTN_B32, i32, si_atomic_swap_local>; 2839def : DSAtomicRetPat<DS_ADD_RTN_U32, i32, si_atomic_load_add_local>; 2840def : DSAtomicRetPat<DS_SUB_RTN_U32, i32, si_atomic_load_sub_local>; 2841def : DSAtomicRetPat<DS_AND_RTN_B32, i32, si_atomic_load_and_local>; 2842def : DSAtomicRetPat<DS_OR_RTN_B32, i32, si_atomic_load_or_local>; 2843def : DSAtomicRetPat<DS_XOR_RTN_B32, i32, si_atomic_load_xor_local>; 2844def : DSAtomicRetPat<DS_MIN_RTN_I32, i32, si_atomic_load_min_local>; 2845def : DSAtomicRetPat<DS_MAX_RTN_I32, i32, si_atomic_load_max_local>; 2846def : DSAtomicRetPat<DS_MIN_RTN_U32, i32, si_atomic_load_umin_local>; 2847def : DSAtomicRetPat<DS_MAX_RTN_U32, i32, si_atomic_load_umax_local>; 2848 2849def : DSAtomicCmpXChg<DS_CMPST_RTN_B32, i32, si_atomic_cmp_swap_32_local>; 2850 2851// 64-bit atomics. 2852def : DSAtomicIncRetPat<DS_INC_RTN_U64, i64, 2853 V_MOV_B64_PSEUDO, si_atomic_load_add_local>; 2854def : DSAtomicIncRetPat<DS_DEC_RTN_U64, i64, 2855 V_MOV_B64_PSEUDO, si_atomic_load_sub_local>; 2856 2857def : DSAtomicRetPat<DS_WRXCHG_RTN_B64, i64, si_atomic_swap_local>; 2858def : DSAtomicRetPat<DS_ADD_RTN_U64, i64, si_atomic_load_add_local>; 2859def : DSAtomicRetPat<DS_SUB_RTN_U64, i64, si_atomic_load_sub_local>; 2860def : DSAtomicRetPat<DS_AND_RTN_B64, i64, si_atomic_load_and_local>; 2861def : DSAtomicRetPat<DS_OR_RTN_B64, i64, si_atomic_load_or_local>; 2862def : DSAtomicRetPat<DS_XOR_RTN_B64, i64, si_atomic_load_xor_local>; 2863def : DSAtomicRetPat<DS_MIN_RTN_I64, i64, si_atomic_load_min_local>; 2864def : DSAtomicRetPat<DS_MAX_RTN_I64, i64, si_atomic_load_max_local>; 2865def : DSAtomicRetPat<DS_MIN_RTN_U64, i64, si_atomic_load_umin_local>; 2866def : DSAtomicRetPat<DS_MAX_RTN_U64, i64, si_atomic_load_umax_local>; 2867 2868def : DSAtomicCmpXChg<DS_CMPST_RTN_B64, i64, si_atomic_cmp_swap_64_local>; 2869 2870 2871//===----------------------------------------------------------------------===// 2872// MUBUF Patterns 2873//===----------------------------------------------------------------------===// 2874 2875multiclass MUBUFLoad_Pattern <MUBUF Instr_ADDR64, ValueType vt, 2876 PatFrag constant_ld> { 2877 def : Pat < 2878 (vt (constant_ld (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr, i32:$soffset, 2879 i16:$offset, i1:$glc, i1:$slc, i1:$tfe))), 2880 (Instr_ADDR64 $vaddr, $srsrc, $soffset, $offset, $glc, $slc, $tfe) 2881 >; 2882} 2883 2884let Predicates = [isSICI] in { 2885defm : MUBUFLoad_Pattern <BUFFER_LOAD_SBYTE_ADDR64, i32, sextloadi8_constant>; 2886defm : MUBUFLoad_Pattern <BUFFER_LOAD_UBYTE_ADDR64, i32, az_extloadi8_constant>; 2887defm : MUBUFLoad_Pattern <BUFFER_LOAD_SSHORT_ADDR64, i32, sextloadi16_constant>; 2888defm : MUBUFLoad_Pattern <BUFFER_LOAD_USHORT_ADDR64, i32, az_extloadi16_constant>; 2889} // End Predicates = [isSICI] 2890 2891class MUBUFScratchLoadPat <MUBUF Instr, ValueType vt, PatFrag ld> : Pat < 2892 (vt (ld (MUBUFScratch v4i32:$srsrc, i32:$vaddr, 2893 i32:$soffset, u16imm:$offset))), 2894 (Instr $vaddr, $srsrc, $soffset, $offset, 0, 0, 0) 2895>; 2896 2897def : MUBUFScratchLoadPat <BUFFER_LOAD_SBYTE_OFFEN, i32, sextloadi8_private>; 2898def : MUBUFScratchLoadPat <BUFFER_LOAD_UBYTE_OFFEN, i32, extloadi8_private>; 2899def : MUBUFScratchLoadPat <BUFFER_LOAD_SSHORT_OFFEN, i32, sextloadi16_private>; 2900def : MUBUFScratchLoadPat <BUFFER_LOAD_USHORT_OFFEN, i32, extloadi16_private>; 2901def : MUBUFScratchLoadPat <BUFFER_LOAD_DWORD_OFFEN, i32, load_private>; 2902def : MUBUFScratchLoadPat <BUFFER_LOAD_DWORDX2_OFFEN, v2i32, load_private>; 2903def : MUBUFScratchLoadPat <BUFFER_LOAD_DWORDX4_OFFEN, v4i32, load_private>; 2904 2905// BUFFER_LOAD_DWORD*, addr64=0 2906multiclass MUBUF_Load_Dword <ValueType vt, MUBUF offset, MUBUF offen, MUBUF idxen, 2907 MUBUF bothen> { 2908 2909 def : Pat < 2910 (vt (int_SI_buffer_load_dword v4i32:$rsrc, (i32 imm), i32:$soffset, 2911 imm:$offset, 0, 0, imm:$glc, imm:$slc, 2912 imm:$tfe)), 2913 (offset $rsrc, $soffset, (as_i16imm $offset), (as_i1imm $glc), 2914 (as_i1imm $slc), (as_i1imm $tfe)) 2915 >; 2916 2917 def : Pat < 2918 (vt (int_SI_buffer_load_dword v4i32:$rsrc, i32:$vaddr, i32:$soffset, 2919 imm:$offset, 1, 0, imm:$glc, imm:$slc, 2920 imm:$tfe)), 2921 (offen $vaddr, $rsrc, $soffset, (as_i16imm $offset), (as_i1imm $glc), (as_i1imm $slc), 2922 (as_i1imm $tfe)) 2923 >; 2924 2925 def : Pat < 2926 (vt (int_SI_buffer_load_dword v4i32:$rsrc, i32:$vaddr, i32:$soffset, 2927 imm:$offset, 0, 1, imm:$glc, imm:$slc, 2928 imm:$tfe)), 2929 (idxen $vaddr, $rsrc, $soffset, (as_i16imm $offset), (as_i1imm $glc), 2930 (as_i1imm $slc), (as_i1imm $tfe)) 2931 >; 2932 2933 def : Pat < 2934 (vt (int_SI_buffer_load_dword v4i32:$rsrc, v2i32:$vaddr, i32:$soffset, 2935 imm:$offset, 1, 1, imm:$glc, imm:$slc, 2936 imm:$tfe)), 2937 (bothen $vaddr, $rsrc, $soffset, (as_i16imm $offset), (as_i1imm $glc), (as_i1imm $slc), 2938 (as_i1imm $tfe)) 2939 >; 2940} 2941 2942defm : MUBUF_Load_Dword <i32, BUFFER_LOAD_DWORD_OFFSET, BUFFER_LOAD_DWORD_OFFEN, 2943 BUFFER_LOAD_DWORD_IDXEN, BUFFER_LOAD_DWORD_BOTHEN>; 2944defm : MUBUF_Load_Dword <v2i32, BUFFER_LOAD_DWORDX2_OFFSET, BUFFER_LOAD_DWORDX2_OFFEN, 2945 BUFFER_LOAD_DWORDX2_IDXEN, BUFFER_LOAD_DWORDX2_BOTHEN>; 2946defm : MUBUF_Load_Dword <v4i32, BUFFER_LOAD_DWORDX4_OFFSET, BUFFER_LOAD_DWORDX4_OFFEN, 2947 BUFFER_LOAD_DWORDX4_IDXEN, BUFFER_LOAD_DWORDX4_BOTHEN>; 2948 2949class MUBUFScratchStorePat <MUBUF Instr, ValueType vt, PatFrag st> : Pat < 2950 (st vt:$value, (MUBUFScratch v4i32:$srsrc, i32:$vaddr, i32:$soffset, 2951 u16imm:$offset)), 2952 (Instr $value, $vaddr, $srsrc, $soffset, $offset, 0, 0, 0) 2953>; 2954 2955def : MUBUFScratchStorePat <BUFFER_STORE_BYTE_OFFEN, i32, truncstorei8_private>; 2956def : MUBUFScratchStorePat <BUFFER_STORE_SHORT_OFFEN, i32, truncstorei16_private>; 2957def : MUBUFScratchStorePat <BUFFER_STORE_DWORD_OFFEN, i32, store_private>; 2958def : MUBUFScratchStorePat <BUFFER_STORE_DWORDX2_OFFEN, v2i32, store_private>; 2959def : MUBUFScratchStorePat <BUFFER_STORE_DWORDX4_OFFEN, v4i32, store_private>; 2960 2961//===----------------------------------------------------------------------===// 2962// MTBUF Patterns 2963//===----------------------------------------------------------------------===// 2964 2965// TBUFFER_STORE_FORMAT_*, addr64=0 2966class MTBUF_StoreResource <ValueType vt, int num_channels, MTBUF opcode> : Pat< 2967 (SItbuffer_store v4i32:$rsrc, vt:$vdata, num_channels, i32:$vaddr, 2968 i32:$soffset, imm:$inst_offset, imm:$dfmt, 2969 imm:$nfmt, imm:$offen, imm:$idxen, 2970 imm:$glc, imm:$slc, imm:$tfe), 2971 (opcode 2972 $vdata, (as_i16imm $inst_offset), (as_i1imm $offen), (as_i1imm $idxen), 2973 (as_i1imm $glc), 0, (as_i8imm $dfmt), (as_i8imm $nfmt), $vaddr, $rsrc, 2974 (as_i1imm $slc), (as_i1imm $tfe), $soffset) 2975>; 2976 2977def : MTBUF_StoreResource <i32, 1, TBUFFER_STORE_FORMAT_X>; 2978def : MTBUF_StoreResource <v2i32, 2, TBUFFER_STORE_FORMAT_XY>; 2979def : MTBUF_StoreResource <v4i32, 3, TBUFFER_STORE_FORMAT_XYZ>; 2980def : MTBUF_StoreResource <v4i32, 4, TBUFFER_STORE_FORMAT_XYZW>; 2981 2982/********** ====================== **********/ 2983/********** Indirect adressing **********/ 2984/********** ====================== **********/ 2985 2986multiclass SI_INDIRECT_Pattern <ValueType vt, ValueType eltvt, string VecSize> { 2987 2988 // 1. Extract with offset 2989 def : Pat< 2990 (eltvt (extractelt vt:$vec, (add i32:$idx, imm:$off))), 2991 (!cast<Instruction>("SI_INDIRECT_SRC_"#VecSize) $vec, $idx, imm:$off) 2992 >; 2993 2994 // 2. Extract without offset 2995 def : Pat< 2996 (eltvt (extractelt vt:$vec, i32:$idx)), 2997 (!cast<Instruction>("SI_INDIRECT_SRC_"#VecSize) $vec, $idx, 0) 2998 >; 2999 3000 // 3. Insert with offset 3001 def : Pat< 3002 (insertelt vt:$vec, eltvt:$val, (add i32:$idx, imm:$off)), 3003 (!cast<Instruction>("SI_INDIRECT_DST_"#VecSize) $vec, $idx, imm:$off, $val) 3004 >; 3005 3006 // 4. Insert without offset 3007 def : Pat< 3008 (insertelt vt:$vec, eltvt:$val, i32:$idx), 3009 (!cast<Instruction>("SI_INDIRECT_DST_"#VecSize) $vec, $idx, 0, $val) 3010 >; 3011} 3012 3013defm : SI_INDIRECT_Pattern <v2f32, f32, "V2">; 3014defm : SI_INDIRECT_Pattern <v4f32, f32, "V4">; 3015defm : SI_INDIRECT_Pattern <v8f32, f32, "V8">; 3016defm : SI_INDIRECT_Pattern <v16f32, f32, "V16">; 3017 3018defm : SI_INDIRECT_Pattern <v2i32, i32, "V2">; 3019defm : SI_INDIRECT_Pattern <v4i32, i32, "V4">; 3020defm : SI_INDIRECT_Pattern <v8i32, i32, "V8">; 3021defm : SI_INDIRECT_Pattern <v16i32, i32, "V16">; 3022 3023//===----------------------------------------------------------------------===// 3024// Conversion Patterns 3025//===----------------------------------------------------------------------===// 3026 3027def : Pat<(i32 (sext_inreg i32:$src, i1)), 3028 (S_BFE_I32 i32:$src, 65536)>; // 0 | 1 << 16 3029 3030// Handle sext_inreg in i64 3031def : Pat < 3032 (i64 (sext_inreg i64:$src, i1)), 3033 (S_BFE_I64 i64:$src, 0x10000) // 0 | 1 << 16 3034>; 3035 3036def : Pat < 3037 (i64 (sext_inreg i64:$src, i8)), 3038 (S_BFE_I64 i64:$src, 0x80000) // 0 | 8 << 16 3039>; 3040 3041def : Pat < 3042 (i64 (sext_inreg i64:$src, i16)), 3043 (S_BFE_I64 i64:$src, 0x100000) // 0 | 16 << 16 3044>; 3045 3046def : Pat < 3047 (i64 (sext_inreg i64:$src, i32)), 3048 (S_BFE_I64 i64:$src, 0x200000) // 0 | 32 << 16 3049>; 3050 3051class ZExt_i64_i32_Pat <SDNode ext> : Pat < 3052 (i64 (ext i32:$src)), 3053 (REG_SEQUENCE SReg_64, $src, sub0, (S_MOV_B32 0), sub1) 3054>; 3055 3056class ZExt_i64_i1_Pat <SDNode ext> : Pat < 3057 (i64 (ext i1:$src)), 3058 (REG_SEQUENCE VReg_64, 3059 (V_CNDMASK_B32_e64 (i32 0), (i32 1), $src), sub0, 3060 (S_MOV_B32 0), sub1) 3061>; 3062 3063 3064def : ZExt_i64_i32_Pat<zext>; 3065def : ZExt_i64_i32_Pat<anyext>; 3066def : ZExt_i64_i1_Pat<zext>; 3067def : ZExt_i64_i1_Pat<anyext>; 3068 3069// FIXME: We need to use COPY_TO_REGCLASS to work-around the fact that 3070// REG_SEQUENCE patterns don't support instructions with multiple outputs. 3071def : Pat < 3072 (i64 (sext i32:$src)), 3073 (REG_SEQUENCE SReg_64, $src, sub0, 3074 (i32 (COPY_TO_REGCLASS (S_ASHR_I32 $src, 31), SGPR_32)), sub1) 3075>; 3076 3077def : Pat < 3078 (i64 (sext i1:$src)), 3079 (REG_SEQUENCE VReg_64, 3080 (V_CNDMASK_B32_e64 0, -1, $src), sub0, 3081 (V_CNDMASK_B32_e64 0, -1, $src), sub1) 3082>; 3083 3084// If we need to perform a logical operation on i1 values, we need to 3085// use vector comparisons since there is only one SCC register. Vector 3086// comparisions still write to a pair of SGPRs, so treat these as 3087// 64-bit comparisons. When legalizing SGPR copies, instructions 3088// resulting in the copies from SCC to these instructions will be 3089// moved to the VALU. 3090def : Pat < 3091 (i1 (and i1:$src0, i1:$src1)), 3092 (S_AND_B64 $src0, $src1) 3093>; 3094 3095def : Pat < 3096 (i1 (or i1:$src0, i1:$src1)), 3097 (S_OR_B64 $src0, $src1) 3098>; 3099 3100def : Pat < 3101 (i1 (xor i1:$src0, i1:$src1)), 3102 (S_XOR_B64 $src0, $src1) 3103>; 3104 3105def : Pat < 3106 (f32 (sint_to_fp i1:$src)), 3107 (V_CNDMASK_B32_e64 (i32 0), CONST.FP32_NEG_ONE, $src) 3108>; 3109 3110def : Pat < 3111 (f32 (uint_to_fp i1:$src)), 3112 (V_CNDMASK_B32_e64 (i32 0), CONST.FP32_ONE, $src) 3113>; 3114 3115def : Pat < 3116 (f64 (sint_to_fp i1:$src)), 3117 (V_CVT_F64_I32_e32 (V_CNDMASK_B32_e64 (i32 0), (i32 -1), $src)) 3118>; 3119 3120def : Pat < 3121 (f64 (uint_to_fp i1:$src)), 3122 (V_CVT_F64_U32_e32 (V_CNDMASK_B32_e64 (i32 0), (i32 1), $src)) 3123>; 3124 3125//===----------------------------------------------------------------------===// 3126// Miscellaneous Patterns 3127//===----------------------------------------------------------------------===// 3128 3129def : Pat < 3130 (i32 (trunc i64:$a)), 3131 (EXTRACT_SUBREG $a, sub0) 3132>; 3133 3134def : Pat < 3135 (i1 (trunc i32:$a)), 3136 (V_CMP_EQ_I32_e64 (S_AND_B32 (i32 1), $a), 1) 3137>; 3138 3139def : Pat < 3140 (i1 (trunc i64:$a)), 3141 (V_CMP_EQ_I32_e64 (S_AND_B32 (i32 1), 3142 (EXTRACT_SUBREG $a, sub0)), 1) 3143>; 3144 3145def : Pat < 3146 (i32 (bswap i32:$a)), 3147 (V_BFI_B32 (S_MOV_B32 0x00ff00ff), 3148 (V_ALIGNBIT_B32 $a, $a, 24), 3149 (V_ALIGNBIT_B32 $a, $a, 8)) 3150>; 3151 3152def : Pat < 3153 (f32 (select i1:$src2, f32:$src1, f32:$src0)), 3154 (V_CNDMASK_B32_e64 $src0, $src1, $src2) 3155>; 3156 3157multiclass BFMPatterns <ValueType vt, InstSI BFM, InstSI MOV> { 3158 def : Pat < 3159 (vt (shl (vt (add (vt (shl 1, vt:$a)), -1)), vt:$b)), 3160 (BFM $a, $b) 3161 >; 3162 3163 def : Pat < 3164 (vt (add (vt (shl 1, vt:$a)), -1)), 3165 (BFM $a, (MOV 0)) 3166 >; 3167} 3168 3169defm : BFMPatterns <i32, S_BFM_B32, S_MOV_B32>; 3170// FIXME: defm : BFMPatterns <i64, S_BFM_B64, S_MOV_B64>; 3171 3172def : BFEPattern <V_BFE_U32, S_MOV_B32>; 3173 3174let Predicates = [isSICI] in { 3175def : Pat < 3176 (i64 (readcyclecounter)), 3177 (S_MEMTIME) 3178>; 3179} 3180 3181//===----------------------------------------------------------------------===// 3182// Fract Patterns 3183//===----------------------------------------------------------------------===// 3184 3185let Predicates = [isSI] in { 3186 3187// V_FRACT is buggy on SI, so the F32 version is never used and (x-floor(x)) is 3188// used instead. However, SI doesn't have V_FLOOR_F64, so the most efficient 3189// way to implement it is using V_FRACT_F64. 3190// The workaround for the V_FRACT bug is: 3191// fract(x) = isnan(x) ? x : min(V_FRACT(x), 0.99999999999999999) 3192 3193// Convert (x + (-floor(x)) to fract(x) 3194def : Pat < 3195 (f64 (fadd (f64 (VOP3Mods f64:$x, i32:$mods)), 3196 (f64 (fneg (f64 (ffloor (f64 (VOP3Mods f64:$x, i32:$mods)))))))), 3197 (V_CNDMASK_B64_PSEUDO 3198 (V_MIN_F64 3199 SRCMODS.NONE, 3200 (V_FRACT_F64_e64 $mods, $x, DSTCLAMP.NONE, DSTOMOD.NONE), 3201 SRCMODS.NONE, 3202 (V_MOV_B64_PSEUDO 0x3fefffffffffffff), 3203 DSTCLAMP.NONE, DSTOMOD.NONE), 3204 $x, 3205 (V_CMP_CLASS_F64_e64 SRCMODS.NONE, $x, 3/*NaN*/)) 3206>; 3207 3208// Convert floor(x) to (x - fract(x)) 3209def : Pat < 3210 (f64 (ffloor (f64 (VOP3Mods f64:$x, i32:$mods)))), 3211 (V_ADD_F64 3212 $mods, 3213 $x, 3214 SRCMODS.NEG, 3215 (V_CNDMASK_B64_PSEUDO 3216 (V_MIN_F64 3217 SRCMODS.NONE, 3218 (V_FRACT_F64_e64 $mods, $x, DSTCLAMP.NONE, DSTOMOD.NONE), 3219 SRCMODS.NONE, 3220 (V_MOV_B64_PSEUDO 0x3fefffffffffffff), 3221 DSTCLAMP.NONE, DSTOMOD.NONE), 3222 $x, 3223 (V_CMP_CLASS_F64_e64 SRCMODS.NONE, $x, 3/*NaN*/)), 3224 DSTCLAMP.NONE, DSTOMOD.NONE) 3225>; 3226 3227} // End Predicates = [isSI] 3228 3229//============================================================================// 3230// Miscellaneous Optimization Patterns 3231//============================================================================// 3232 3233def : SHA256MaPattern <V_BFI_B32, V_XOR_B32_e64>; 3234 3235//============================================================================// 3236// Assembler aliases 3237//============================================================================// 3238 3239def : MnemonicAlias<"v_add_u32", "v_add_i32">; 3240def : MnemonicAlias<"v_sub_u32", "v_sub_i32">; 3241def : MnemonicAlias<"v_subrev_u32", "v_subrev_i32">; 3242 3243} // End isGCN predicate 3244