1//===-- SIInstrInfo.td - SI Instruction Infos -------------*- tablegen -*--===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9def isWave32 : Predicate<"Subtarget->getWavefrontSize() == 32">,
10  AssemblerPredicate <"FeatureWavefrontSize32">;
11def isWave64 : Predicate<"Subtarget->getWavefrontSize() == 64">,
12  AssemblerPredicate <"FeatureWavefrontSize64">;
13
14def DisableInst : Predicate <"false">, AssemblerPredicate<"FeatureDisable">;
15
16class GCNPredicateControl : PredicateControl {
17  Predicate SIAssemblerPredicate = isGFX6GFX7;
18  Predicate VIAssemblerPredicate = isGFX8GFX9;
19}
20
21// Execpt for the NONE field, this must be kept in sync with the
22// SIEncodingFamily enum in AMDGPUInstrInfo.cpp
23def SIEncodingFamily {
24  int NONE = -1;
25  int SI = 0;
26  int VI = 1;
27  int SDWA = 2;
28  int SDWA9 = 3;
29  int GFX80 = 4;
30  int GFX9 = 5;
31  int GFX10 = 6;
32  int SDWA10 = 7;
33}
34
35//===----------------------------------------------------------------------===//
36// SI DAG Nodes
37//===----------------------------------------------------------------------===//
38
39def AMDGPUclamp : SDNode<"AMDGPUISD::CLAMP", SDTFPUnaryOp>;
40
41def SIsbuffer_load : SDNode<"AMDGPUISD::SBUFFER_LOAD",
42  SDTypeProfile<1, 3, [SDTCisVT<1, v4i32>, SDTCisVT<2, i32>, SDTCisVT<3, i32>]>,
43  [SDNPMayLoad, SDNPMemOperand]
44>;
45
46def SIds_ordered_count : SDNode<"AMDGPUISD::DS_ORDERED_COUNT",
47  SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisVT<1, i32>, SDTCisVT<2, i16>]>,
48  [SDNPMayLoad, SDNPMayStore, SDNPMemOperand, SDNPHasChain, SDNPInGlue]
49>;
50
51def SIatomic_inc : SDNode<"AMDGPUISD::ATOMIC_INC", SDTAtomic2,
52  [SDNPMayLoad, SDNPMayStore, SDNPMemOperand, SDNPHasChain]
53>;
54
55def SIatomic_dec : SDNode<"AMDGPUISD::ATOMIC_DEC", SDTAtomic2,
56  [SDNPMayLoad, SDNPMayStore, SDNPMemOperand, SDNPHasChain]
57>;
58
59def SDTAtomic2_f32 : SDTypeProfile<1, 2, [
60  SDTCisSameAs<0,2>, SDTCisFP<0>, SDTCisPtrTy<1>
61]>;
62
63def SIatomic_fmin : SDNode<"AMDGPUISD::ATOMIC_LOAD_FMIN", SDTAtomic2_f32,
64  [SDNPMayLoad, SDNPMayStore, SDNPMemOperand, SDNPHasChain]
65>;
66
67def SIatomic_fmax : SDNode<"AMDGPUISD::ATOMIC_LOAD_FMAX", SDTAtomic2_f32,
68  [SDNPMayLoad, SDNPMayStore, SDNPMemOperand, SDNPHasChain]
69>;
70
71// load_d16_{lo|hi} ptr, tied_input
72def SIload_d16 : SDTypeProfile<1, 2, [
73  SDTCisPtrTy<1>,
74  SDTCisSameAs<0, 2>
75]>;
76
77
78def SDTtbuffer_load : SDTypeProfile<1, 8,
79  [                     // vdata
80   SDTCisVT<1, v4i32>,  // rsrc
81   SDTCisVT<2, i32>,    // vindex(VGPR)
82   SDTCisVT<3, i32>,    // voffset(VGPR)
83   SDTCisVT<4, i32>,    // soffset(SGPR)
84   SDTCisVT<5, i32>,    // offset(imm)
85   SDTCisVT<6, i32>,    // format(imm)
86   SDTCisVT<7, i32>,    // cachepolicy, swizzled buffer(imm)
87   SDTCisVT<8, i1>      // idxen(imm)
88  ]>;
89
90def SItbuffer_load :   SDNode<"AMDGPUISD::TBUFFER_LOAD_FORMAT", SDTtbuffer_load,
91                              [SDNPMayLoad, SDNPMemOperand, SDNPHasChain]>;
92def SItbuffer_load_d16 : SDNode<"AMDGPUISD::TBUFFER_LOAD_FORMAT_D16",
93                                SDTtbuffer_load,
94                                [SDNPMayLoad, SDNPMemOperand, SDNPHasChain]>;
95
96def SDTtbuffer_store : SDTypeProfile<0, 9,
97    [                     // vdata
98     SDTCisVT<1, v4i32>,  // rsrc
99     SDTCisVT<2, i32>,    // vindex(VGPR)
100     SDTCisVT<3, i32>,    // voffset(VGPR)
101     SDTCisVT<4, i32>,    // soffset(SGPR)
102     SDTCisVT<5, i32>,    // offset(imm)
103     SDTCisVT<6, i32>,    // format(imm)
104     SDTCisVT<7, i32>,    // cachepolicy, swizzled buffer(imm)
105     SDTCisVT<8, i1>      // idxen(imm)
106    ]>;
107
108def SItbuffer_store : SDNode<"AMDGPUISD::TBUFFER_STORE_FORMAT", SDTtbuffer_store,
109                             [SDNPMayStore, SDNPMemOperand, SDNPHasChain]>;
110def SItbuffer_store_d16 : SDNode<"AMDGPUISD::TBUFFER_STORE_FORMAT_D16",
111                                SDTtbuffer_store,
112                                [SDNPMayStore, SDNPMemOperand, SDNPHasChain]>;
113
114def SDTBufferLoad : SDTypeProfile<1, 7,
115    [                    // vdata
116     SDTCisVT<1, v4i32>, // rsrc
117     SDTCisVT<2, i32>,   // vindex(VGPR)
118     SDTCisVT<3, i32>,   // voffset(VGPR)
119     SDTCisVT<4, i32>,   // soffset(SGPR)
120     SDTCisVT<5, i32>,   // offset(imm)
121     SDTCisVT<6, i32>,   // cachepolicy, swizzled buffer(imm)
122     SDTCisVT<7, i1>]>;  // idxen(imm)
123
124def SIbuffer_load : SDNode <"AMDGPUISD::BUFFER_LOAD", SDTBufferLoad,
125                            [SDNPMemOperand, SDNPHasChain, SDNPMayLoad]>;
126def SIbuffer_load_ubyte : SDNode <"AMDGPUISD::BUFFER_LOAD_UBYTE", SDTBufferLoad,
127                            [SDNPMemOperand, SDNPHasChain, SDNPMayLoad]>;
128def SIbuffer_load_ushort : SDNode <"AMDGPUISD::BUFFER_LOAD_USHORT", SDTBufferLoad,
129                            [SDNPMemOperand, SDNPHasChain, SDNPMayLoad]>;
130def SIbuffer_load_byte : SDNode <"AMDGPUISD::BUFFER_LOAD_BYTE", SDTBufferLoad,
131                            [SDNPMemOperand, SDNPHasChain, SDNPMayLoad]>;
132def SIbuffer_load_short: SDNode <"AMDGPUISD::BUFFER_LOAD_SHORT", SDTBufferLoad,
133                            [SDNPMemOperand, SDNPHasChain, SDNPMayLoad]>;
134def SIbuffer_load_format : SDNode <"AMDGPUISD::BUFFER_LOAD_FORMAT", SDTBufferLoad,
135                            [SDNPMemOperand, SDNPHasChain, SDNPMayLoad]>;
136def SIbuffer_load_format_d16 : SDNode <"AMDGPUISD::BUFFER_LOAD_FORMAT_D16",
137                                SDTBufferLoad,
138                                [SDNPMemOperand, SDNPHasChain, SDNPMayLoad]>;
139
140def SDTBufferStore : SDTypeProfile<0, 8,
141    [                    // vdata
142     SDTCisVT<1, v4i32>, // rsrc
143     SDTCisVT<2, i32>,   // vindex(VGPR)
144     SDTCisVT<3, i32>,   // voffset(VGPR)
145     SDTCisVT<4, i32>,   // soffset(SGPR)
146     SDTCisVT<5, i32>,   // offset(imm)
147     SDTCisVT<6, i32>,   // cachepolicy, swizzled buffer(imm)
148     SDTCisVT<7, i1>]>;  // idxen(imm)
149
150def SIbuffer_store : SDNode <"AMDGPUISD::BUFFER_STORE", SDTBufferStore,
151                             [SDNPMayStore, SDNPMemOperand, SDNPHasChain]>;
152def SIbuffer_store_byte: SDNode <"AMDGPUISD::BUFFER_STORE_BYTE",
153                         SDTBufferStore,
154                         [SDNPMayStore, SDNPMemOperand, SDNPHasChain]>;
155def SIbuffer_store_short : SDNode <"AMDGPUISD::BUFFER_STORE_SHORT",
156                           SDTBufferStore,
157                           [SDNPMayStore, SDNPMemOperand, SDNPHasChain]>;
158def SIbuffer_store_format : SDNode <"AMDGPUISD::BUFFER_STORE_FORMAT",
159                            SDTBufferStore,
160                            [SDNPMayStore, SDNPMemOperand, SDNPHasChain]>;
161def SIbuffer_store_format_d16 : SDNode <"AMDGPUISD::BUFFER_STORE_FORMAT_D16",
162                            SDTBufferStore,
163                            [SDNPMayStore, SDNPMemOperand, SDNPHasChain]>;
164
165class SDBufferAtomic<string opcode> : SDNode <opcode,
166  SDTypeProfile<1, 8,
167       [SDTCisVT<2, v4i32>, // rsrc
168       SDTCisVT<3, i32>,   // vindex(VGPR)
169       SDTCisVT<4, i32>,   // voffset(VGPR)
170       SDTCisVT<5, i32>,   // soffset(SGPR)
171       SDTCisVT<6, i32>,   // offset(imm)
172       SDTCisVT<7, i32>,   // cachepolicy(imm)
173       SDTCisVT<8, i1>]>,  // idxen(imm)
174  [SDNPMemOperand, SDNPHasChain, SDNPMayLoad, SDNPMayStore]
175>;
176
177class SDBufferAtomicNoRtn<string opcode, ValueType ty> : SDNode <opcode,
178  SDTypeProfile<0, 8,
179      [SDTCisVT<0, ty>,    // vdata
180       SDTCisVT<1, v4i32>, // rsrc
181       SDTCisVT<2, i32>,   // vindex(VGPR)
182       SDTCisVT<3, i32>,   // voffset(VGPR)
183       SDTCisVT<4, i32>,   // soffset(SGPR)
184       SDTCisVT<5, i32>,   // offset(imm)
185       SDTCisVT<6, i32>,   // cachepolicy(imm)
186       SDTCisVT<7, i1>]>,  // idxen(imm)
187  [SDNPMemOperand, SDNPHasChain, SDNPMayLoad, SDNPMayStore]
188>;
189
190def SIbuffer_atomic_swap : SDBufferAtomic <"AMDGPUISD::BUFFER_ATOMIC_SWAP">;
191def SIbuffer_atomic_add : SDBufferAtomic <"AMDGPUISD::BUFFER_ATOMIC_ADD">;
192def SIbuffer_atomic_sub : SDBufferAtomic <"AMDGPUISD::BUFFER_ATOMIC_SUB">;
193def SIbuffer_atomic_smin : SDBufferAtomic <"AMDGPUISD::BUFFER_ATOMIC_SMIN">;
194def SIbuffer_atomic_umin : SDBufferAtomic <"AMDGPUISD::BUFFER_ATOMIC_UMIN">;
195def SIbuffer_atomic_smax : SDBufferAtomic <"AMDGPUISD::BUFFER_ATOMIC_SMAX">;
196def SIbuffer_atomic_umax : SDBufferAtomic <"AMDGPUISD::BUFFER_ATOMIC_UMAX">;
197def SIbuffer_atomic_and : SDBufferAtomic <"AMDGPUISD::BUFFER_ATOMIC_AND">;
198def SIbuffer_atomic_or : SDBufferAtomic <"AMDGPUISD::BUFFER_ATOMIC_OR">;
199def SIbuffer_atomic_xor : SDBufferAtomic <"AMDGPUISD::BUFFER_ATOMIC_XOR">;
200def SIbuffer_atomic_inc : SDBufferAtomic <"AMDGPUISD::BUFFER_ATOMIC_INC">;
201def SIbuffer_atomic_dec : SDBufferAtomic <"AMDGPUISD::BUFFER_ATOMIC_DEC">;
202def SIbuffer_atomic_fadd : SDBufferAtomicNoRtn <"AMDGPUISD::BUFFER_ATOMIC_FADD", f32>;
203def SIbuffer_atomic_pk_fadd : SDBufferAtomicNoRtn <"AMDGPUISD::BUFFER_ATOMIC_PK_FADD", v2f16>;
204
205def SIbuffer_atomic_cmpswap : SDNode <"AMDGPUISD::BUFFER_ATOMIC_CMPSWAP",
206  SDTypeProfile<1, 9,
207    [SDTCisVT<0, i32>,   // dst
208     SDTCisVT<1, i32>,   // src
209     SDTCisVT<2, i32>,   // cmp
210     SDTCisVT<3, v4i32>, // rsrc
211     SDTCisVT<4, i32>,   // vindex(VGPR)
212     SDTCisVT<5, i32>,   // voffset(VGPR)
213     SDTCisVT<6, i32>,   // soffset(SGPR)
214     SDTCisVT<7, i32>,   // offset(imm)
215     SDTCisVT<8, i32>,   // cachepolicy(imm)
216     SDTCisVT<9, i1>]>,  // idxen(imm)
217  [SDNPMemOperand, SDNPHasChain, SDNPMayLoad, SDNPMayStore]
218>;
219
220class SDGlobalAtomicNoRtn<string opcode, ValueType ty> : SDNode <opcode,
221  SDTypeProfile<0, 2,
222      [SDTCisPtrTy<0>,     // vaddr
223       SDTCisVT<1, ty>]>,  // vdata
224  [SDNPMemOperand, SDNPHasChain, SDNPMayLoad, SDNPMayStore]
225>;
226
227def SIglobal_atomic_pk_fadd : SDGlobalAtomicNoRtn <"AMDGPUISD::ATOMIC_PK_FADD", v2f16>;
228
229def SIpc_add_rel_offset : SDNode<"AMDGPUISD::PC_ADD_REL_OFFSET",
230  SDTypeProfile<1, 2, [SDTCisVT<0, iPTR>, SDTCisSameAs<0,1>, SDTCisSameAs<0,2>]>
231>;
232
233def SIlds : SDNode<"AMDGPUISD::LDS",
234  SDTypeProfile<1, 1, [SDTCisVT<0, iPTR>, SDTCisSameAs<0,1>]>
235>;
236
237def SIload_d16_lo : SDNode<"AMDGPUISD::LOAD_D16_LO",
238  SIload_d16,
239  [SDNPMayLoad, SDNPMemOperand, SDNPHasChain]
240>;
241
242def SIload_d16_lo_u8 : SDNode<"AMDGPUISD::LOAD_D16_LO_U8",
243  SIload_d16,
244  [SDNPMayLoad, SDNPMemOperand, SDNPHasChain]
245>;
246
247def SIload_d16_lo_i8 : SDNode<"AMDGPUISD::LOAD_D16_LO_I8",
248  SIload_d16,
249  [SDNPMayLoad, SDNPMemOperand, SDNPHasChain]
250>;
251
252def SIload_d16_hi : SDNode<"AMDGPUISD::LOAD_D16_HI",
253  SIload_d16,
254  [SDNPMayLoad, SDNPMemOperand, SDNPHasChain]
255>;
256
257def SIload_d16_hi_u8 : SDNode<"AMDGPUISD::LOAD_D16_HI_U8",
258  SIload_d16,
259  [SDNPMayLoad, SDNPMemOperand, SDNPHasChain]
260>;
261
262def SIload_d16_hi_i8 : SDNode<"AMDGPUISD::LOAD_D16_HI_I8",
263  SIload_d16,
264  [SDNPMayLoad, SDNPMemOperand, SDNPHasChain]
265>;
266
267def SIdenorm_mode : SDNode<"AMDGPUISD::DENORM_MODE",
268  SDTypeProfile<0 ,1, [SDTCisInt<0>]>,
269  [SDNPHasChain, SDNPSideEffect, SDNPOptInGlue, SDNPOutGlue]
270>;
271
272//===----------------------------------------------------------------------===//
273// ValueType helpers
274//===----------------------------------------------------------------------===//
275
276// Returns 1 if the source arguments have modifiers, 0 if they do not.
277// XXX - do f16 instructions?
278class isFloatType<ValueType SrcVT> {
279  bit ret =
280    !if(!eq(SrcVT.Value, f16.Value), 1,
281    !if(!eq(SrcVT.Value, f32.Value), 1,
282    !if(!eq(SrcVT.Value, f64.Value), 1,
283    !if(!eq(SrcVT.Value, v2f16.Value), 1,
284    !if(!eq(SrcVT.Value, v4f16.Value), 1,
285    !if(!eq(SrcVT.Value, v2f32.Value), 1,
286    !if(!eq(SrcVT.Value, v2f64.Value), 1,
287    0)))))));
288}
289
290class isIntType<ValueType SrcVT> {
291  bit ret =
292    !if(!eq(SrcVT.Value, i16.Value), 1,
293    !if(!eq(SrcVT.Value, i32.Value), 1,
294    !if(!eq(SrcVT.Value, i64.Value), 1,
295    0)));
296}
297
298class isPackedType<ValueType SrcVT> {
299  bit ret =
300    !if(!eq(SrcVT.Value, v2i16.Value), 1,
301      !if(!eq(SrcVT.Value, v2f16.Value), 1,
302        !if(!eq(SrcVT.Value, v4f16.Value), 1, 0)
303    ));
304}
305
306//===----------------------------------------------------------------------===//
307// PatFrags for global memory operations
308//===----------------------------------------------------------------------===//
309
310foreach as = [ "global", "flat", "constant", "local", "private", "region" ] in {
311let AddressSpaces = !cast<AddressSpaceList>("LoadAddress_"#as).AddrSpaces in {
312
313
314defm atomic_inc_#as : binary_atomic_op<SIatomic_inc>;
315defm atomic_dec_#as : binary_atomic_op<SIatomic_dec>;
316defm atomic_load_fmin_#as : binary_atomic_op<SIatomic_fmin, 0>;
317defm atomic_load_fmax_#as : binary_atomic_op<SIatomic_fmax, 0>;
318
319
320} // End let AddressSpaces = ...
321} // End foreach AddrSpace
322
323def atomic_fadd_global_noret : PatFrag<
324  (ops node:$ptr, node:$value),
325  (atomic_load_fadd node:$ptr, node:$value)> {
326  // FIXME: Move this
327  let MemoryVT = f32;
328  let IsAtomic = 1;
329  let AddressSpaces = StoreAddress_global.AddrSpaces;
330}
331
332def atomic_pk_fadd_global_noret : PatFrag<
333    (ops node:$ptr, node:$value),
334    (SIglobal_atomic_pk_fadd node:$ptr, node:$value)> {
335  // FIXME: Move this
336  let MemoryVT = v2f16;
337  let IsAtomic = 1;
338  let AddressSpaces = StoreAddress_global.AddrSpaces;
339}
340
341//===----------------------------------------------------------------------===//
342// SDNodes PatFrags for loads/stores with a glue input.
343// This is for SDNodes and PatFrag for local loads and stores to
344// enable s_mov_b32 m0, -1 to be glued to the memory instructions.
345//
346// These mirror the regular load/store PatFrags and rely on special
347// processing during Select() to add the glued copy.
348//
349//===----------------------------------------------------------------------===//
350
351def AMDGPUld_glue : SDNode <"ISD::LOAD", SDTLoad,
352  [SDNPHasChain, SDNPMayLoad, SDNPMemOperand, SDNPInGlue]
353>;
354
355def AMDGPUatomic_ld_glue : SDNode <"ISD::ATOMIC_LOAD", SDTAtomicLoad,
356  [SDNPHasChain, SDNPMayLoad, SDNPMemOperand, SDNPInGlue]
357>;
358
359def unindexedload_glue : PatFrag <(ops node:$ptr), (AMDGPUld_glue node:$ptr)> {
360  let IsLoad = 1;
361  let IsUnindexed = 1;
362}
363
364def load_glue : PatFrag <(ops node:$ptr), (unindexedload_glue node:$ptr)> {
365  let IsLoad = 1;
366  let IsNonExtLoad = 1;
367}
368
369def atomic_load_32_glue : PatFrag<(ops node:$ptr),
370  (AMDGPUatomic_ld_glue node:$ptr)> {
371  let IsAtomic = 1;
372  let MemoryVT = i32;
373}
374
375def atomic_load_64_glue : PatFrag<(ops node:$ptr),
376  (AMDGPUatomic_ld_glue node:$ptr)> {
377  let IsAtomic = 1;
378  let MemoryVT = i64;
379}
380
381def extload_glue : PatFrag<(ops node:$ptr), (unindexedload_glue node:$ptr)> {
382  let IsLoad = 1;
383  let IsAnyExtLoad = 1;
384}
385
386def sextload_glue : PatFrag<(ops node:$ptr), (unindexedload_glue node:$ptr)> {
387  let IsLoad = 1;
388  let IsSignExtLoad = 1;
389}
390
391def zextload_glue : PatFrag<(ops node:$ptr), (unindexedload_glue node:$ptr)> {
392  let IsLoad = 1;
393  let IsZeroExtLoad = 1;
394}
395
396def extloadi8_glue : PatFrag<(ops node:$ptr), (extload_glue node:$ptr)> {
397  let IsLoad = 1;
398  let MemoryVT = i8;
399}
400
401def zextloadi8_glue : PatFrag<(ops node:$ptr), (zextload_glue node:$ptr)> {
402  let IsLoad = 1;
403  let MemoryVT = i8;
404}
405
406def extloadi16_glue : PatFrag<(ops node:$ptr), (extload_glue node:$ptr)> {
407  let IsLoad = 1;
408  let MemoryVT = i16;
409}
410
411def zextloadi16_glue : PatFrag<(ops node:$ptr), (zextload_glue node:$ptr)> {
412  let IsLoad = 1;
413  let MemoryVT = i16;
414}
415
416def sextloadi8_glue : PatFrag<(ops node:$ptr), (sextload_glue node:$ptr)> {
417  let IsLoad = 1;
418  let MemoryVT = i8;
419}
420
421def sextloadi16_glue : PatFrag<(ops node:$ptr), (sextload_glue node:$ptr)> {
422  let IsLoad = 1;
423  let MemoryVT = i16;
424}
425
426
427let IsLoad = 1, AddressSpaces = LoadAddress_local.AddrSpaces in {
428def load_local_m0 : PatFrag<(ops node:$ptr), (load_glue node:$ptr)> {
429  let IsNonExtLoad = 1;
430}
431
432let MemoryVT = i8 in {
433def extloadi8_local_m0 : PatFrag<(ops node:$ptr), (extloadi8_glue node:$ptr)>;
434def sextloadi8_local_m0 : PatFrag<(ops node:$ptr), (sextloadi8_glue node:$ptr)>;
435def zextloadi8_local_m0 : PatFrag<(ops node:$ptr), (zextloadi8_glue node:$ptr)>;
436}
437
438let MemoryVT = i16 in {
439def extloadi16_local_m0 : PatFrag<(ops node:$ptr), (extloadi16_glue node:$ptr)>;
440def sextloadi16_local_m0 : PatFrag<(ops node:$ptr), (sextloadi16_glue node:$ptr)>;
441def zextloadi16_local_m0 : PatFrag<(ops node:$ptr), (zextloadi16_glue node:$ptr)>;
442}
443
444def load_align8_local_m0 : PatFrag<(ops node:$ptr),
445                                   (load_local_m0 node:$ptr)> {
446  let IsLoad = 1;
447  let IsNonExtLoad = 1;
448  let MinAlignment = 8;
449}
450def load_align16_local_m0 : PatFrag<(ops node:$ptr),
451                                    (load_local_m0 node:$ptr)> {
452  let IsLoad = 1;
453  let IsNonExtLoad = 1;
454  let MinAlignment = 16;
455}
456
457} // End IsLoad = 1
458
459let IsAtomic = 1, AddressSpaces = LoadAddress_local.AddrSpaces in {
460def atomic_load_32_local_m0 : PatFrag<(ops node:$ptr),
461                                      (atomic_load_32_glue node:$ptr)> {
462  let MemoryVT = i32;
463}
464def atomic_load_64_local_m0 : PatFrag<(ops node:$ptr),
465                                       (atomic_load_64_glue node:$ptr)> {
466  let MemoryVT = i64;
467}
468
469} // End let AddressSpaces = LoadAddress_local.AddrSpaces
470
471
472def AMDGPUst_glue : SDNode <"ISD::STORE", SDTStore,
473  [SDNPHasChain, SDNPMayStore, SDNPMemOperand, SDNPInGlue]
474>;
475
476def AMDGPUatomic_st_glue : SDNode <"ISD::ATOMIC_STORE", SDTAtomicStore,
477  [SDNPHasChain, SDNPMayStore, SDNPMemOperand, SDNPInGlue]
478>;
479
480def unindexedstore_glue : PatFrag<(ops node:$val, node:$ptr),
481                                   (AMDGPUst_glue node:$val, node:$ptr)> {
482  let IsStore = 1;
483  let IsUnindexed = 1;
484}
485
486def store_glue : PatFrag<(ops node:$val, node:$ptr),
487                         (unindexedstore_glue node:$val, node:$ptr)> {
488  let IsStore = 1;
489  let IsTruncStore = 0;
490}
491
492def truncstore_glue : PatFrag<(ops node:$val, node:$ptr),
493  (unindexedstore_glue node:$val, node:$ptr)> {
494  let IsStore = 1;
495  let IsTruncStore = 1;
496}
497
498def truncstorei8_glue : PatFrag<(ops node:$val, node:$ptr),
499                           (truncstore_glue node:$val, node:$ptr)> {
500  let IsStore = 1;
501  let MemoryVT = i8;
502}
503
504def truncstorei16_glue : PatFrag<(ops node:$val, node:$ptr),
505                           (truncstore_glue node:$val, node:$ptr)> {
506  let IsStore = 1;
507  let MemoryVT = i16;
508}
509
510let IsStore = 1, AddressSpaces = StoreAddress_local.AddrSpaces in {
511def store_local_m0 : PatFrag<(ops node:$val, node:$ptr),
512                             (store_glue node:$val, node:$ptr)> {
513  let IsStore = 1;
514  let IsTruncStore = 0;
515}
516
517def truncstorei8_local_m0 : PatFrag<(ops node:$val, node:$ptr),
518                                    (unindexedstore_glue node:$val, node:$ptr)> {
519  let IsStore = 1;
520  let MemoryVT = i8;
521}
522
523def truncstorei16_local_m0 : PatFrag<(ops node:$val, node:$ptr),
524                                    (unindexedstore_glue node:$val, node:$ptr)> {
525  let IsStore = 1;
526  let MemoryVT = i16;
527}
528}
529
530def store_align16_local_m0 : PatFrag <
531  (ops node:$value, node:$ptr),
532  (store_local_m0 node:$value, node:$ptr)> {
533  let IsStore = 1;
534  let IsTruncStore = 0;
535  let MinAlignment = 16;
536}
537
538def store_align8_local_m0 : PatFrag <
539  (ops node:$value, node:$ptr),
540  (store_local_m0 node:$value, node:$ptr)> {
541  let IsStore = 1;
542  let IsTruncStore = 0;
543  let MinAlignment = 8;
544}
545
546let AddressSpaces = StoreAddress_local.AddrSpaces in {
547
548def atomic_store_local_32_m0 : PatFrag <
549  (ops node:$value, node:$ptr),
550  (AMDGPUatomic_st_glue node:$value, node:$ptr)> {
551  let IsAtomic = 1;
552  let MemoryVT = i32;
553}
554def atomic_store_local_64_m0 : PatFrag <
555  (ops node:$value, node:$ptr),
556  (AMDGPUatomic_st_glue node:$value, node:$ptr)> {
557  let IsAtomic = 1;
558  let MemoryVT = i64;
559}
560} // End let AddressSpaces = StoreAddress_local.AddrSpaces
561
562
563def si_setcc_uniform : PatFrag <
564  (ops node:$lhs, node:$rhs, node:$cond),
565  (setcc node:$lhs, node:$rhs, node:$cond), [{
566  for (SDNode *Use : N->uses()) {
567    if (Use->isMachineOpcode() || Use->getOpcode() != ISD::CopyToReg)
568      return false;
569
570    unsigned Reg = cast<RegisterSDNode>(Use->getOperand(1))->getReg();
571    if (Reg != AMDGPU::SCC)
572      return false;
573  }
574  return true;
575}]>;
576
577//===----------------------------------------------------------------------===//
578// SDNodes PatFrags for d16 loads
579//===----------------------------------------------------------------------===//
580
581class LoadD16Frag <SDPatternOperator op> : PatFrag<
582  (ops node:$ptr, node:$tied_in),
583  (op node:$ptr, node:$tied_in)> {
584  let IsLoad = 1;
585}
586
587foreach as = [ "global", "flat", "constant", "local", "private", "region" ] in {
588let AddressSpaces = !cast<AddressSpaceList>("LoadAddress_"#as).AddrSpaces in {
589
590def load_d16_hi_#as : LoadD16Frag <SIload_d16_hi>;
591
592def az_extloadi8_d16_hi_#as : LoadD16Frag <SIload_d16_hi_u8> {
593  let MemoryVT = i8;
594}
595
596def sextloadi8_d16_hi_#as : LoadD16Frag <SIload_d16_hi_i8> {
597  let MemoryVT = i8;
598}
599
600def load_d16_lo_#as : LoadD16Frag <SIload_d16_lo>;
601
602def az_extloadi8_d16_lo_#as : LoadD16Frag <SIload_d16_lo_u8> {
603  let MemoryVT = i8;
604}
605
606def sextloadi8_d16_lo_#as : LoadD16Frag <SIload_d16_lo_i8> {
607  let MemoryVT = i8;
608}
609
610} // End let AddressSpaces = ...
611} // End foreach AddrSpace
612
613def lshr_rev : PatFrag <
614  (ops node:$src1, node:$src0),
615  (srl $src0, $src1)
616>;
617
618def ashr_rev : PatFrag <
619  (ops node:$src1, node:$src0),
620  (sra $src0, $src1)
621>;
622
623def lshl_rev : PatFrag <
624  (ops node:$src1, node:$src0),
625  (shl $src0, $src1)
626>;
627
628def add_ctpop : PatFrag <
629  (ops node:$src0, node:$src1),
630  (add (ctpop $src0), $src1)
631>;
632
633multiclass SIAtomicM0Glue2 <string op_name, bit is_amdgpu = 0,
634                            SDTypeProfile tc = SDTAtomic2,
635                            bit IsInt = 1> {
636
637  def _glue : SDNode <
638    !if(is_amdgpu, "AMDGPUISD", "ISD")#"::ATOMIC_"#op_name, tc,
639    [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand, SDNPInGlue]
640  >;
641
642  let AddressSpaces = StoreAddress_local.AddrSpaces in {
643    defm _local_m0 : binary_atomic_op <!cast<SDNode>(NAME#"_glue"), IsInt>;
644  }
645
646  let AddressSpaces = StoreAddress_region.AddrSpaces in {
647    defm _region_m0 : binary_atomic_op <!cast<SDNode>(NAME#"_glue"), IsInt>;
648  }
649}
650
651defm atomic_load_add : SIAtomicM0Glue2 <"LOAD_ADD">;
652defm atomic_load_sub : SIAtomicM0Glue2 <"LOAD_SUB">;
653defm atomic_inc : SIAtomicM0Glue2 <"INC", 1>;
654defm atomic_dec : SIAtomicM0Glue2 <"DEC", 1>;
655defm atomic_load_and : SIAtomicM0Glue2 <"LOAD_AND">;
656defm atomic_load_min : SIAtomicM0Glue2 <"LOAD_MIN">;
657defm atomic_load_max : SIAtomicM0Glue2 <"LOAD_MAX">;
658defm atomic_load_or : SIAtomicM0Glue2 <"LOAD_OR">;
659defm atomic_load_xor : SIAtomicM0Glue2 <"LOAD_XOR">;
660defm atomic_load_umin : SIAtomicM0Glue2 <"LOAD_UMIN">;
661defm atomic_load_umax : SIAtomicM0Glue2 <"LOAD_UMAX">;
662defm atomic_swap : SIAtomicM0Glue2 <"SWAP">;
663defm atomic_load_fadd : SIAtomicM0Glue2 <"LOAD_FADD", 0, SDTAtomic2_f32, 0>;
664defm atomic_load_fmin : SIAtomicM0Glue2 <"LOAD_FMIN", 1, SDTAtomic2_f32, 0>;
665defm atomic_load_fmax : SIAtomicM0Glue2 <"LOAD_FMAX", 1, SDTAtomic2_f32, 0>;
666
667def as_i1timm : SDNodeXForm<timm, [{
668  return CurDAG->getTargetConstant(N->getZExtValue(), SDLoc(N), MVT::i1);
669}]>;
670
671def as_i8imm : SDNodeXForm<imm, [{
672  return CurDAG->getTargetConstant(N->getZExtValue(), SDLoc(N), MVT::i8);
673}]>;
674
675def as_i8timm : SDNodeXForm<timm, [{
676  return CurDAG->getTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i16);
677}]>;
678
679def as_i16imm : SDNodeXForm<imm, [{
680  return CurDAG->getTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i16);
681}]>;
682
683def as_i16timm : SDNodeXForm<timm, [{
684  return CurDAG->getTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i16);
685}]>;
686
687def as_i32imm: SDNodeXForm<imm, [{
688  return CurDAG->getTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i32);
689}]>;
690
691def as_i32timm: SDNodeXForm<timm, [{
692  return CurDAG->getTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i32);
693}]>;
694
695def as_i64imm: SDNodeXForm<imm, [{
696  return CurDAG->getTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i64);
697}]>;
698
699def cond_as_i32imm: SDNodeXForm<cond, [{
700  return CurDAG->getTargetConstant(N->get(), SDLoc(N), MVT::i32);
701}]>;
702
703// Copied from the AArch64 backend:
704def bitcast_fpimm_to_i32 : SDNodeXForm<fpimm, [{
705return CurDAG->getTargetConstant(
706  N->getValueAPF().bitcastToAPInt().getZExtValue(), SDLoc(N), MVT::i32);
707}]>;
708
709def frameindex_to_targetframeindex : SDNodeXForm<frameindex, [{
710  auto FI = cast<FrameIndexSDNode>(N);
711  return CurDAG->getTargetFrameIndex(FI->getIndex(), MVT::i32);
712}]>;
713
714// Copied from the AArch64 backend:
715def bitcast_fpimm_to_i64 : SDNodeXForm<fpimm, [{
716return CurDAG->getTargetConstant(
717  N->getValueAPF().bitcastToAPInt().getZExtValue(), SDLoc(N), MVT::i64);
718}]>;
719
720class bitextract_imm<int bitnum> : SDNodeXForm<imm, [{
721  uint64_t Imm = N->getZExtValue();
722  unsigned Bit = (Imm >> }] # bitnum # [{ ) & 1;
723  return CurDAG->getTargetConstant(Bit, SDLoc(N), MVT::i1);
724}]>;
725
726def SIMM16bit : ImmLeaf <i32,
727  [{return isInt<16>(Imm);}]
728>;
729
730def UIMM16bit : ImmLeaf <i32,
731  [{return isUInt<16>(Imm);}]
732>;
733
734def i64imm_32bit : ImmLeaf<i64, [{
735  return (Imm & 0xffffffffULL) == static_cast<uint64_t>(Imm);
736}]>;
737
738def InlineImm16 : ImmLeaf<i16, [{
739  return isInlineImmediate16(Imm);
740}]>;
741
742def InlineImm32 : ImmLeaf<i32, [{
743  return isInlineImmediate32(Imm);
744}]>;
745
746def InlineImm64 : ImmLeaf<i64, [{
747  return isInlineImmediate64(Imm);
748}]>;
749
750def InlineImmFP32 : FPImmLeaf<f32, [{
751  return isInlineImmediate(Imm);
752}]>;
753
754def InlineImmFP64 : FPImmLeaf<f64, [{
755  return isInlineImmediate(Imm);
756}]>;
757
758
759class VGPRImm <dag frag> : PatLeaf<frag, [{
760  return isVGPRImm(N);
761}]>;
762
763def NegateImm : SDNodeXForm<imm, [{
764  return CurDAG->getConstant(-N->getSExtValue(), SDLoc(N), MVT::i32);
765}]>;
766
767// TODO: When FP inline imm values work?
768def NegSubInlineConst32 : ImmLeaf<i32, [{
769  return Imm < -16 && Imm >= -64;
770}], NegateImm>;
771
772def NegSubInlineConst16 : ImmLeaf<i16, [{
773  return Imm < -16 && Imm >= -64;
774}], NegateImm>;
775
776def ShiftAmt32Imm : ImmLeaf <i32, [{
777  return Imm < 32;
778}]>;
779
780def getNegV2I16Imm : SDNodeXForm<build_vector, [{
781  return SDValue(packNegConstantV2I16(N, *CurDAG), 0);
782}]>;
783
784def NegSubInlineConstV216 : PatLeaf<(build_vector), [{
785  assert(N->getNumOperands() == 2);
786  assert(N->getOperand(0).getValueType().getSizeInBits() == 16);
787  SDValue Src0 = N->getOperand(0);
788  SDValue Src1 = N->getOperand(1);
789  if (Src0 == Src1)
790    return isNegInlineImmediate(Src0.getNode());
791
792  return (isNullConstantOrUndef(Src0) && isNegInlineImmediate(Src1.getNode())) ||
793         (isNullConstantOrUndef(Src1) && isNegInlineImmediate(Src0.getNode()));
794}], getNegV2I16Imm>;
795
796//===----------------------------------------------------------------------===//
797// MUBUF/SMEM Patterns
798//===----------------------------------------------------------------------===//
799
800def extract_glc : SDNodeXForm<timm, [{
801  return CurDAG->getTargetConstant(N->getZExtValue() & 1, SDLoc(N), MVT::i8);
802}]>;
803
804def extract_slc : SDNodeXForm<timm, [{
805  return CurDAG->getTargetConstant((N->getZExtValue() >> 1) & 1, SDLoc(N), MVT::i8);
806}]>;
807
808def extract_dlc : SDNodeXForm<timm, [{
809  return CurDAG->getTargetConstant((N->getZExtValue() >> 2) & 1, SDLoc(N), MVT::i8);
810}]>;
811
812def extract_swz : SDNodeXForm<timm, [{
813  return CurDAG->getTargetConstant((N->getZExtValue() >> 3) & 1, SDLoc(N), MVT::i8);
814}]>;
815
816//===----------------------------------------------------------------------===//
817// Custom Operands
818//===----------------------------------------------------------------------===//
819
820def SoppBrTarget : AsmOperandClass {
821  let Name = "SoppBrTarget";
822  let ParserMethod = "parseSOppBrTarget";
823}
824
825def sopp_brtarget : Operand<OtherVT> {
826  let EncoderMethod = "getSOPPBrEncoding";
827  let DecoderMethod = "decodeSoppBrTarget";
828  let OperandType = "OPERAND_PCREL";
829  let ParserMatchClass = SoppBrTarget;
830}
831
832def si_ga : Operand<iPTR>;
833
834def InterpSlotMatchClass : AsmOperandClass {
835  let Name = "InterpSlot";
836  let PredicateMethod = "isInterpSlot";
837  let ParserMethod = "parseInterpSlot";
838  let RenderMethod = "addImmOperands";
839}
840
841def InterpSlot : Operand<i32> {
842  let PrintMethod = "printInterpSlot";
843  let ParserMatchClass = InterpSlotMatchClass;
844  let OperandType = "OPERAND_IMMEDIATE";
845}
846
847def AttrMatchClass : AsmOperandClass {
848  let Name = "Attr";
849  let PredicateMethod = "isInterpAttr";
850  let ParserMethod = "parseInterpAttr";
851  let RenderMethod = "addImmOperands";
852}
853
854// It appears to be necessary to create a separate operand for this to
855// be able to parse attr<num> with no space.
856def Attr : Operand<i32> {
857  let PrintMethod = "printInterpAttr";
858  let ParserMatchClass = AttrMatchClass;
859  let OperandType = "OPERAND_IMMEDIATE";
860}
861
862def AttrChanMatchClass : AsmOperandClass {
863  let Name = "AttrChan";
864  let PredicateMethod = "isAttrChan";
865  let RenderMethod = "addImmOperands";
866}
867
868def AttrChan : Operand<i32> {
869  let PrintMethod = "printInterpAttrChan";
870  let ParserMatchClass = AttrChanMatchClass;
871  let OperandType = "OPERAND_IMMEDIATE";
872}
873
874def SendMsgMatchClass : AsmOperandClass {
875  let Name = "SendMsg";
876  let PredicateMethod = "isSendMsg";
877  let ParserMethod = "parseSendMsgOp";
878  let RenderMethod = "addImmOperands";
879}
880
881def SwizzleMatchClass : AsmOperandClass {
882  let Name = "Swizzle";
883  let PredicateMethod = "isSwizzle";
884  let ParserMethod = "parseSwizzleOp";
885  let RenderMethod = "addImmOperands";
886  let IsOptional = 1;
887}
888
889def EndpgmMatchClass : AsmOperandClass {
890  let Name = "EndpgmImm";
891  let PredicateMethod = "isEndpgm";
892  let ParserMethod = "parseEndpgmOp";
893  let RenderMethod = "addImmOperands";
894  let IsOptional = 1;
895}
896
897def ExpTgtMatchClass : AsmOperandClass {
898  let Name = "ExpTgt";
899  let PredicateMethod = "isExpTgt";
900  let ParserMethod = "parseExpTgt";
901  let RenderMethod = "printExpTgt";
902}
903
904def SWaitMatchClass : AsmOperandClass {
905  let Name = "SWaitCnt";
906  let RenderMethod = "addImmOperands";
907  let ParserMethod = "parseSWaitCntOps";
908}
909
910def VReg32OrOffClass : AsmOperandClass {
911  let Name = "VReg32OrOff";
912  let ParserMethod = "parseVReg32OrOff";
913}
914
915let OperandType = "OPERAND_IMMEDIATE" in {
916def SendMsgImm : Operand<i32> {
917  let PrintMethod = "printSendMsg";
918  let ParserMatchClass = SendMsgMatchClass;
919}
920
921def SwizzleImm : Operand<i16> {
922  let PrintMethod = "printSwizzle";
923  let ParserMatchClass = SwizzleMatchClass;
924}
925
926def EndpgmImm : Operand<i16> {
927  let PrintMethod = "printEndpgm";
928  let ParserMatchClass = EndpgmMatchClass;
929}
930
931def WAIT_FLAG : Operand <i32> {
932  let ParserMatchClass = SWaitMatchClass;
933  let PrintMethod = "printWaitFlag";
934}
935} // End OperandType = "OPERAND_IMMEDIATE"
936
937include "SIInstrFormats.td"
938include "VIInstrFormats.td"
939
940def BoolReg : AsmOperandClass {
941  let Name = "BoolReg";
942  let ParserMethod = "parseBoolReg";
943  let RenderMethod = "addRegOperands";
944}
945
946class BoolRC : RegisterOperand<SReg_1> {
947  let ParserMatchClass = BoolReg;
948  let DecoderMethod = "decodeBoolReg";
949}
950
951def SSrc_i1 : RegisterOperand<SReg_1_XEXEC> {
952  let ParserMatchClass = BoolReg;
953  let DecoderMethod = "decodeBoolReg";
954}
955
956def VOPDstS64orS32 : BoolRC {
957  let PrintMethod = "printVOPDst";
958}
959
960// SCSrc_i1 is the operand for pseudo instructions only.
961// Boolean immeadiates shall not be exposed to codegen instructions.
962def SCSrc_i1 : RegisterOperand<SReg_1_XEXEC> {
963  let OperandNamespace = "AMDGPU";
964  let OperandType = "OPERAND_REG_IMM_INT32";
965  let ParserMatchClass = BoolReg;
966  let DecoderMethod = "decodeBoolReg";
967}
968
969// ===----------------------------------------------------------------------===//
970// ExpSrc* Special cases for exp src operands which are printed as
971// "off" depending on en operand.
972// ===----------------------------------------------------------------------===//
973
974def ExpSrc0 : RegisterOperand<VGPR_32> {
975  let PrintMethod = "printExpSrc0";
976  let ParserMatchClass = VReg32OrOffClass;
977}
978
979def ExpSrc1 : RegisterOperand<VGPR_32> {
980  let PrintMethod = "printExpSrc1";
981  let ParserMatchClass = VReg32OrOffClass;
982}
983
984def ExpSrc2 : RegisterOperand<VGPR_32> {
985  let PrintMethod = "printExpSrc2";
986  let ParserMatchClass = VReg32OrOffClass;
987}
988
989def ExpSrc3 : RegisterOperand<VGPR_32> {
990  let PrintMethod = "printExpSrc3";
991  let ParserMatchClass = VReg32OrOffClass;
992}
993
994class SDWASrc<ValueType vt> : RegisterOperand<VS_32> {
995  let OperandNamespace = "AMDGPU";
996  string Type = !if(isFloatType<vt>.ret, "FP", "INT");
997  let OperandType = "OPERAND_REG_INLINE_C_"#Type#vt.Size;
998  let DecoderMethod = "decodeSDWASrc"#vt.Size;
999  let EncoderMethod = "getSDWASrcEncoding";
1000}
1001
1002def SDWASrc_i32 : SDWASrc<i32>;
1003def SDWASrc_i16 : SDWASrc<i16>;
1004def SDWASrc_f32 : SDWASrc<f32>;
1005def SDWASrc_f16 : SDWASrc<f16>;
1006
1007def SDWAVopcDst : BoolRC {
1008  let OperandNamespace = "AMDGPU";
1009  let OperandType = "OPERAND_SDWA_VOPC_DST";
1010  let EncoderMethod = "getSDWAVopcDstEncoding";
1011  let DecoderMethod = "decodeSDWAVopcDst";
1012  let PrintMethod = "printVOPDst";
1013}
1014
1015class NamedMatchClass<string CName, bit Optional = 1> : AsmOperandClass {
1016  let Name = "Imm"#CName;
1017  let PredicateMethod = "is"#CName;
1018  let ParserMethod = !if(Optional, "parseOptionalOperand", "parse"#CName);
1019  let RenderMethod = "addImmOperands";
1020  let IsOptional = Optional;
1021  let DefaultMethod = !if(Optional, "default"#CName, ?);
1022}
1023
1024class NamedOperandBit<string Name, AsmOperandClass MatchClass> : Operand<i1> {
1025  let PrintMethod = "print"#Name;
1026  let ParserMatchClass = MatchClass;
1027}
1028
1029class NamedOperandBit_0<string Name, AsmOperandClass MatchClass> :
1030  OperandWithDefaultOps<i1, (ops (i1 0))> {
1031  let PrintMethod = "print"#Name;
1032  let ParserMatchClass = MatchClass;
1033}
1034
1035class NamedOperandU8<string Name, AsmOperandClass MatchClass> : Operand<i8> {
1036  let PrintMethod = "print"#Name;
1037  let ParserMatchClass = MatchClass;
1038}
1039
1040class NamedOperandU16<string Name, AsmOperandClass MatchClass> : Operand<i16> {
1041  let PrintMethod = "print"#Name;
1042  let ParserMatchClass = MatchClass;
1043}
1044
1045class NamedOperandU32<string Name, AsmOperandClass MatchClass> : Operand<i32> {
1046  let PrintMethod = "print"#Name;
1047  let ParserMatchClass = MatchClass;
1048}
1049
1050class NamedOperandU32_0<string Name, AsmOperandClass MatchClass> :
1051  OperandWithDefaultOps<i32, (ops (i32 0))> {
1052  let PrintMethod = "print"#Name;
1053  let ParserMatchClass = MatchClass;
1054}
1055
1056class NamedOperandU32Default0<string Name, AsmOperandClass MatchClass> :
1057  OperandWithDefaultOps<i32, (ops (i32 0))> {
1058  let PrintMethod = "print"#Name;
1059  let ParserMatchClass = MatchClass;
1060}
1061
1062let OperandType = "OPERAND_IMMEDIATE" in {
1063
1064def offen : NamedOperandBit<"Offen", NamedMatchClass<"Offen">>;
1065def idxen : NamedOperandBit<"Idxen", NamedMatchClass<"Idxen">>;
1066def addr64 : NamedOperandBit<"Addr64", NamedMatchClass<"Addr64">>;
1067
1068def flat_offset : NamedOperandU16<"FlatOffset", NamedMatchClass<"FlatOffset">>;
1069def offset : NamedOperandU16<"Offset", NamedMatchClass<"Offset">>;
1070def offset0 : NamedOperandU8<"Offset0", NamedMatchClass<"Offset0">>;
1071def offset1 : NamedOperandU8<"Offset1", NamedMatchClass<"Offset1">>;
1072
1073def gds : NamedOperandBit<"GDS", NamedMatchClass<"GDS">>;
1074
1075def omod : NamedOperandU32<"OModSI", NamedMatchClass<"OModSI">>;
1076def omod0 : NamedOperandU32_0<"OModSI", NamedMatchClass<"OModSI">>;
1077
1078// We need to make the cases with a default of 0 distinct from no
1079// default to help deal with some cases where the operand appears
1080// before a mandatory operand.
1081def clampmod : NamedOperandBit<"ClampSI", NamedMatchClass<"ClampSI">>;
1082def clampmod0 : NamedOperandBit_0<"ClampSI", NamedMatchClass<"ClampSI">>;
1083def highmod : NamedOperandBit<"High", NamedMatchClass<"High">>;
1084
1085def DLC : NamedOperandBit<"DLC", NamedMatchClass<"DLC">>;
1086def GLC : NamedOperandBit<"GLC", NamedMatchClass<"GLC">>;
1087def SLC : NamedOperandBit<"SLC", NamedMatchClass<"SLC">>;
1088def TFE : NamedOperandBit<"TFE", NamedMatchClass<"TFE">>;
1089def SWZ : NamedOperandBit<"SWZ", NamedMatchClass<"SWZ">>;
1090def UNorm : NamedOperandBit<"UNorm", NamedMatchClass<"UNorm">>;
1091def DA : NamedOperandBit<"DA", NamedMatchClass<"DA">>;
1092def R128A16 : NamedOperandBit<"R128A16", NamedMatchClass<"R128A16">>;
1093def D16 : NamedOperandBit<"D16", NamedMatchClass<"D16">>;
1094def LWE : NamedOperandBit<"LWE", NamedMatchClass<"LWE">>;
1095def exp_compr : NamedOperandBit<"ExpCompr", NamedMatchClass<"ExpCompr">>;
1096def exp_vm : NamedOperandBit<"ExpVM", NamedMatchClass<"ExpVM">>;
1097
1098def FORMAT : NamedOperandU8<"FORMAT", NamedMatchClass<"FORMAT">>;
1099
1100def DMask : NamedOperandU16<"DMask", NamedMatchClass<"DMask">>;
1101def Dim : NamedOperandU8<"Dim", NamedMatchClass<"Dim", 0>>;
1102
1103def dpp8 : NamedOperandU32<"DPP8", NamedMatchClass<"DPP8", 0>>;
1104
1105def dpp_ctrl : NamedOperandU32<"DPPCtrl", NamedMatchClass<"DPPCtrl", 0>>;
1106def row_mask : NamedOperandU32<"RowMask", NamedMatchClass<"RowMask">>;
1107def bank_mask : NamedOperandU32<"BankMask", NamedMatchClass<"BankMask">>;
1108def bound_ctrl : NamedOperandBit<"BoundCtrl", NamedMatchClass<"BoundCtrl">>;
1109def FI : NamedOperandU32<"FI", NamedMatchClass<"FI">>;
1110
1111def dst_sel : NamedOperandU32<"SDWADstSel", NamedMatchClass<"SDWADstSel">>;
1112def src0_sel : NamedOperandU32<"SDWASrc0Sel", NamedMatchClass<"SDWASrc0Sel">>;
1113def src1_sel : NamedOperandU32<"SDWASrc1Sel", NamedMatchClass<"SDWASrc1Sel">>;
1114def dst_unused : NamedOperandU32<"SDWADstUnused", NamedMatchClass<"SDWADstUnused">>;
1115
1116def op_sel : NamedOperandU32Default0<"OpSel", NamedMatchClass<"OpSel">>;
1117def op_sel_hi : NamedOperandU32Default0<"OpSelHi", NamedMatchClass<"OpSelHi">>;
1118def neg_lo : NamedOperandU32Default0<"NegLo", NamedMatchClass<"NegLo">>;
1119def neg_hi : NamedOperandU32Default0<"NegHi", NamedMatchClass<"NegHi">>;
1120
1121def blgp : NamedOperandU32<"BLGP", NamedMatchClass<"BLGP">>;
1122def cbsz : NamedOperandU32<"CBSZ", NamedMatchClass<"CBSZ">>;
1123def abid : NamedOperandU32<"ABID", NamedMatchClass<"ABID">>;
1124
1125def hwreg : NamedOperandU16<"Hwreg", NamedMatchClass<"Hwreg", 0>>;
1126
1127def exp_tgt : NamedOperandU32<"ExpTgt", NamedMatchClass<"ExpTgt", 0>> {
1128
1129}
1130
1131} // End OperandType = "OPERAND_IMMEDIATE"
1132
1133class KImmMatchClass<int size> : AsmOperandClass {
1134  let Name = "KImmFP"#size;
1135  let PredicateMethod = "isKImmFP"#size;
1136  let ParserMethod = "parseImm";
1137  let RenderMethod = "addKImmFP"#size#"Operands";
1138}
1139
1140class kimmOperand<ValueType vt> : Operand<vt> {
1141  let OperandNamespace = "AMDGPU";
1142  let OperandType = "OPERAND_KIMM"#vt.Size;
1143  let PrintMethod = "printU"#vt.Size#"ImmOperand";
1144  let ParserMatchClass = !cast<AsmOperandClass>("KImmFP"#vt.Size#"MatchClass");
1145}
1146
1147// 32-bit VALU immediate operand that uses the constant bus.
1148def KImmFP32MatchClass : KImmMatchClass<32>;
1149def f32kimm : kimmOperand<i32>;
1150
1151// 32-bit VALU immediate operand with a 16-bit value that uses the
1152// constant bus.
1153def KImmFP16MatchClass : KImmMatchClass<16>;
1154def f16kimm : kimmOperand<i16>;
1155
1156class FPInputModsMatchClass <int opSize> : AsmOperandClass {
1157  let Name = "RegOrImmWithFP"#opSize#"InputMods";
1158  let ParserMethod = "parseRegOrImmWithFPInputMods";
1159  let PredicateMethod = "isRegOrImmWithFP"#opSize#"InputMods";
1160}
1161
1162def FP16InputModsMatchClass : FPInputModsMatchClass<16>;
1163def FP32InputModsMatchClass : FPInputModsMatchClass<32>;
1164def FP64InputModsMatchClass : FPInputModsMatchClass<64>;
1165
1166class InputMods <AsmOperandClass matchClass> : Operand <i32> {
1167  let OperandNamespace = "AMDGPU";
1168  let OperandType = "OPERAND_INPUT_MODS";
1169  let ParserMatchClass = matchClass;
1170}
1171
1172class FPInputMods <FPInputModsMatchClass matchClass> : InputMods <matchClass> {
1173  let PrintMethod = "printOperandAndFPInputMods";
1174}
1175
1176def FP16InputMods : FPInputMods<FP16InputModsMatchClass>;
1177def FP32InputMods : FPInputMods<FP32InputModsMatchClass>;
1178def FP64InputMods : FPInputMods<FP64InputModsMatchClass>;
1179
1180class IntInputModsMatchClass <int opSize> : AsmOperandClass {
1181  let Name = "RegOrImmWithInt"#opSize#"InputMods";
1182  let ParserMethod = "parseRegOrImmWithIntInputMods";
1183  let PredicateMethod = "isRegOrImmWithInt"#opSize#"InputMods";
1184}
1185def Int32InputModsMatchClass : IntInputModsMatchClass<32>;
1186def Int64InputModsMatchClass : IntInputModsMatchClass<64>;
1187
1188class IntInputMods <IntInputModsMatchClass matchClass> : InputMods <matchClass> {
1189  let PrintMethod = "printOperandAndIntInputMods";
1190}
1191def Int32InputMods : IntInputMods<Int32InputModsMatchClass>;
1192def Int64InputMods : IntInputMods<Int64InputModsMatchClass>;
1193
1194class OpSelModsMatchClass : AsmOperandClass {
1195  let Name = "OpSelMods";
1196  let ParserMethod = "parseRegOrImm";
1197  let PredicateMethod = "isRegOrImm";
1198}
1199
1200def IntOpSelModsMatchClass : OpSelModsMatchClass;
1201def IntOpSelMods : InputMods<IntOpSelModsMatchClass>;
1202
1203class FPSDWAInputModsMatchClass <int opSize> : AsmOperandClass {
1204  let Name = "SDWAWithFP"#opSize#"InputMods";
1205  let ParserMethod = "parseRegOrImmWithFPInputMods";
1206  let PredicateMethod = "isSDWAFP"#opSize#"Operand";
1207}
1208
1209def FP16SDWAInputModsMatchClass : FPSDWAInputModsMatchClass<16>;
1210def FP32SDWAInputModsMatchClass : FPSDWAInputModsMatchClass<32>;
1211
1212class FPSDWAInputMods <FPSDWAInputModsMatchClass matchClass> :
1213  InputMods <matchClass> {
1214  let PrintMethod = "printOperandAndFPInputMods";
1215}
1216
1217def FP16SDWAInputMods : FPSDWAInputMods<FP16SDWAInputModsMatchClass>;
1218def FP32SDWAInputMods : FPSDWAInputMods<FP32SDWAInputModsMatchClass>;
1219
1220def FPVRegInputModsMatchClass : AsmOperandClass {
1221  let Name = "VRegWithFPInputMods";
1222  let ParserMethod = "parseRegWithFPInputMods";
1223  let PredicateMethod = "isVReg32";
1224}
1225
1226def FPVRegInputMods : InputMods <FPVRegInputModsMatchClass> {
1227  let PrintMethod = "printOperandAndFPInputMods";
1228}
1229
1230class IntSDWAInputModsMatchClass <int opSize> : AsmOperandClass {
1231  let Name = "SDWAWithInt"#opSize#"InputMods";
1232  let ParserMethod = "parseRegOrImmWithIntInputMods";
1233  let PredicateMethod = "isSDWAInt"#opSize#"Operand";
1234}
1235
1236def Int16SDWAInputModsMatchClass : IntSDWAInputModsMatchClass<16>;
1237def Int32SDWAInputModsMatchClass : IntSDWAInputModsMatchClass<32>;
1238
1239class IntSDWAInputMods <IntSDWAInputModsMatchClass matchClass> :
1240  InputMods <matchClass> {
1241  let PrintMethod = "printOperandAndIntInputMods";
1242}
1243
1244def Int16SDWAInputMods : IntSDWAInputMods<Int16SDWAInputModsMatchClass>;
1245def Int32SDWAInputMods : IntSDWAInputMods<Int32SDWAInputModsMatchClass>;
1246
1247def IntVRegInputModsMatchClass : AsmOperandClass {
1248  let Name = "VRegWithIntInputMods";
1249  let ParserMethod = "parseRegWithIntInputMods";
1250  let PredicateMethod = "isVReg32";
1251}
1252
1253def IntVRegInputMods : InputMods <IntVRegInputModsMatchClass> {
1254  let PrintMethod = "printOperandAndIntInputMods";
1255}
1256
1257class PackedFPInputModsMatchClass <int opSize> : AsmOperandClass {
1258  let Name = "PackedFP"#opSize#"InputMods";
1259  let ParserMethod = "parseRegOrImm";
1260  let PredicateMethod = "isRegOrImm";
1261//  let PredicateMethod = "isPackedFP"#opSize#"InputMods";
1262}
1263
1264class PackedIntInputModsMatchClass <int opSize> : AsmOperandClass {
1265  let Name = "PackedInt"#opSize#"InputMods";
1266  let ParserMethod = "parseRegOrImm";
1267  let PredicateMethod = "isRegOrImm";
1268//  let PredicateMethod = "isPackedInt"#opSize#"InputMods";
1269}
1270
1271def PackedF16InputModsMatchClass : PackedFPInputModsMatchClass<16>;
1272def PackedI16InputModsMatchClass : PackedIntInputModsMatchClass<16>;
1273
1274class PackedFPInputMods <PackedFPInputModsMatchClass matchClass> : InputMods <matchClass> {
1275//  let PrintMethod = "printPackedFPInputMods";
1276}
1277
1278class PackedIntInputMods <PackedIntInputModsMatchClass matchClass> : InputMods <matchClass> {
1279  //let PrintMethod = "printPackedIntInputMods";
1280}
1281
1282def PackedF16InputMods : PackedFPInputMods<PackedF16InputModsMatchClass>;
1283def PackedI16InputMods : PackedIntInputMods<PackedI16InputModsMatchClass>;
1284
1285//===----------------------------------------------------------------------===//
1286// Complex patterns
1287//===----------------------------------------------------------------------===//
1288
1289def DS1Addr1Offset : ComplexPattern<i32, 2, "SelectDS1Addr1Offset">;
1290def DS64Bit4ByteAligned : ComplexPattern<i32, 3, "SelectDS64Bit4ByteAligned">;
1291
1292def MOVRELOffset : ComplexPattern<i32, 2, "SelectMOVRELOffset">;
1293
1294def VOP3Mods0 : ComplexPattern<untyped, 4, "SelectVOP3Mods0">;
1295def VOP3Mods0Clamp : ComplexPattern<untyped, 3, "SelectVOP3Mods0Clamp">;
1296def VOP3Mods  : ComplexPattern<untyped, 2, "SelectVOP3Mods">;
1297def VOP3NoMods : ComplexPattern<untyped, 1, "SelectVOP3NoMods">;
1298// VOP3Mods, but the input source is known to never be NaN.
1299def VOP3Mods_nnan : ComplexPattern<fAny, 2, "SelectVOP3Mods_NNaN">;
1300
1301def VOP3OMods : ComplexPattern<untyped, 3, "SelectVOP3OMods">;
1302
1303def VOP3PMods  : ComplexPattern<untyped, 2, "SelectVOP3PMods">;
1304def VOP3PMods0 : ComplexPattern<untyped, 3, "SelectVOP3PMods0">;
1305
1306def VOP3OpSel  : ComplexPattern<untyped, 2, "SelectVOP3OpSel">;
1307def VOP3OpSel0 : ComplexPattern<untyped, 3, "SelectVOP3OpSel0">;
1308
1309def VOP3OpSelMods  : ComplexPattern<untyped, 2, "SelectVOP3OpSelMods">;
1310def VOP3OpSelMods0 : ComplexPattern<untyped, 3, "SelectVOP3OpSelMods0">;
1311
1312def VOP3PMadMixMods  : ComplexPattern<untyped, 2, "SelectVOP3PMadMixMods">;
1313
1314
1315def Hi16Elt  : ComplexPattern<untyped, 1, "SelectHi16Elt">;
1316
1317//===----------------------------------------------------------------------===//
1318// SI assembler operands
1319//===----------------------------------------------------------------------===//
1320
1321def SIOperand {
1322  int ZERO = 0x80;
1323  int VCC = 0x6A;
1324  int FLAT_SCR = 0x68;
1325}
1326
1327// This should be kept in sync with SISrcMods enum
1328def SRCMODS {
1329  int NONE = 0;
1330  int NEG = 1;
1331  int ABS = 2;
1332  int NEG_ABS = 3;
1333
1334  int NEG_HI = ABS;
1335  int OP_SEL_0 = 4;
1336  int OP_SEL_1 = 8;
1337  int DST_OP_SEL = 8;
1338}
1339
1340def DSTCLAMP {
1341  int NONE = 0;
1342  int ENABLE = 1;
1343}
1344
1345def DSTOMOD {
1346  int NONE = 0;
1347}
1348
1349def TRAPID{
1350  int LLVM_TRAP = 2;
1351  int LLVM_DEBUG_TRAP = 3;
1352}
1353
1354def HWREG {
1355  int MODE = 1;
1356  int STATUS = 2;
1357  int TRAPSTS = 3;
1358  int HW_ID = 4;
1359  int GPR_ALLOC = 5;
1360  int LDS_ALLOC = 6;
1361  int IB_STS = 7;
1362  int MEM_BASES = 15;
1363  int TBA_LO = 16;
1364  int TBA_HI = 17;
1365  int TMA_LO = 18;
1366  int TMA_HI = 19;
1367  int FLAT_SCR_LO = 20;
1368  int FLAT_SCR_HI = 21;
1369  int XNACK_MASK = 22;
1370  int POPS_PACKER = 25;
1371}
1372
1373class getHwRegImm<int Reg, int Offset = 0, int Size = 32> {
1374  int ret = !or(Reg,
1375                !or(!shl(Offset, 6),
1376                    !shl(!add(Size, -1), 11)));
1377}
1378
1379//===----------------------------------------------------------------------===//
1380//
1381// SI Instruction multiclass helpers.
1382//
1383// Instructions with _32 take 32-bit operands.
1384// Instructions with _64 take 64-bit operands.
1385//
1386// VOP_* instructions can use either a 32-bit or 64-bit encoding.  The 32-bit
1387// encoding is the standard encoding, but instruction that make use of
1388// any of the instruction modifiers must use the 64-bit encoding.
1389//
1390// Instructions with _e32 use the 32-bit encoding.
1391// Instructions with _e64 use the 64-bit encoding.
1392//
1393//===----------------------------------------------------------------------===//
1394
1395class SIMCInstr <string pseudo, int subtarget> {
1396  string PseudoInstr = pseudo;
1397  int Subtarget = subtarget;
1398}
1399
1400//===----------------------------------------------------------------------===//
1401// EXP classes
1402//===----------------------------------------------------------------------===//
1403
1404class EXP_Helper<bit done> : EXPCommon<
1405  (outs),
1406  (ins exp_tgt:$tgt,
1407       ExpSrc0:$src0, ExpSrc1:$src1, ExpSrc2:$src2, ExpSrc3:$src3,
1408       exp_vm:$vm, exp_compr:$compr, i32imm:$en),
1409  "exp$tgt $src0, $src1, $src2, $src3"#!if(done, " done", "")#"$compr$vm", []> {
1410  let AsmMatchConverter = "cvtExp";
1411}
1412
1413// Split EXP instruction into EXP and EXP_DONE so we can set
1414// mayLoad for done=1.
1415multiclass EXP_m<bit done> {
1416  let mayLoad = done, DisableWQM = 1 in {
1417    let isPseudo = 1, isCodeGenOnly = 1 in {
1418      def "" : EXP_Helper<done>,
1419               SIMCInstr <"exp"#!if(done, "_done", ""), SIEncodingFamily.NONE>;
1420    }
1421
1422    let done = done in {
1423      def _si : EXP_Helper<done>,
1424                SIMCInstr <"exp"#!if(done, "_done", ""), SIEncodingFamily.SI>,
1425                EXPe {
1426        let AssemblerPredicate = isGFX6GFX7;
1427        let DecoderNamespace = "GFX6GFX7";
1428        let DisableDecoder = DisableSIDecoder;
1429      }
1430
1431      def _vi : EXP_Helper<done>,
1432                SIMCInstr <"exp"#!if(done, "_done", ""), SIEncodingFamily.VI>,
1433                EXPe_vi {
1434        let AssemblerPredicate = isGFX8GFX9;
1435        let DecoderNamespace = "GFX8";
1436        let DisableDecoder = DisableVIDecoder;
1437      }
1438
1439      def _gfx10 : EXP_Helper<done>,
1440                SIMCInstr <"exp"#!if(done, "_done", ""), SIEncodingFamily.GFX10>,
1441                EXPe {
1442        let AssemblerPredicate = isGFX10Plus;
1443        let DecoderNamespace = "GFX10";
1444        let DisableDecoder = DisableSIDecoder;
1445      }
1446    }
1447  }
1448}
1449
1450//===----------------------------------------------------------------------===//
1451// Vector ALU classes
1452//===----------------------------------------------------------------------===//
1453
1454class getNumSrcArgs<ValueType Src0, ValueType Src1, ValueType Src2> {
1455  int ret =
1456    !if (!eq(Src0.Value, untyped.Value),      0,
1457      !if (!eq(Src1.Value, untyped.Value),    1,   // VOP1
1458         !if (!eq(Src2.Value, untyped.Value), 2,   // VOP2
1459                                              3))); // VOP3
1460}
1461
1462// Returns the register class to use for the destination of VOP[123C]
1463// instructions for the given VT.
1464class getVALUDstForVT<ValueType VT> {
1465  RegisterOperand ret = !if(!eq(VT.Size, 32), VOPDstOperand<VGPR_32>,
1466                          !if(!eq(VT.Size, 128), VOPDstOperand<VReg_128>,
1467                            !if(!eq(VT.Size, 64), VOPDstOperand<VReg_64>,
1468                              !if(!eq(VT.Size, 16), VOPDstOperand<VGPR_32>,
1469                              VOPDstS64orS32)))); // else VT == i1
1470}
1471
1472// Returns the register class to use for the destination of VOP[12C]
1473// instructions with SDWA extension
1474class getSDWADstForVT<ValueType VT> {
1475  RegisterOperand ret = !if(!eq(VT.Size, 1),
1476                            SDWAVopcDst, // VOPC
1477                            VOPDstOperand<VGPR_32>); // VOP1/2 32-bit dst
1478}
1479
1480// Returns the register class to use for source 0 of VOP[12C]
1481// instructions for the given VT.
1482class getVOPSrc0ForVT<ValueType VT> {
1483  bit isFP = isFloatType<VT>.ret;
1484
1485  RegisterOperand ret =
1486    !if(isFP,
1487      !if(!eq(VT.Size, 64),
1488         VSrc_f64,
1489         !if(!eq(VT.Value, f16.Value),
1490            VSrc_f16,
1491            !if(!eq(VT.Value, v2f16.Value),
1492               VSrc_v2f16,
1493               !if(!eq(VT.Value, v4f16.Value),
1494                 AVSrc_64,
1495                 VSrc_f32
1496               )
1497            )
1498         )
1499       ),
1500       !if(!eq(VT.Size, 64),
1501          VSrc_b64,
1502          !if(!eq(VT.Value, i16.Value),
1503             VSrc_b16,
1504             !if(!eq(VT.Value, v2i16.Value),
1505                VSrc_v2b16,
1506                VSrc_b32
1507             )
1508          )
1509       )
1510    );
1511}
1512
1513// Returns the vreg register class to use for source operand given VT
1514class getVregSrcForVT<ValueType VT> {
1515  RegisterClass ret = !if(!eq(VT.Size, 128), VReg_128,
1516                        !if(!eq(VT.Size, 96), VReg_96,
1517                          !if(!eq(VT.Size, 64), VReg_64,
1518                            !if(!eq(VT.Size, 48), VReg_64,
1519                              VGPR_32))));
1520}
1521
1522class getSDWASrcForVT <ValueType VT> {
1523  bit isFP = isFloatType<VT>.ret;
1524  RegisterOperand retFlt = !if(!eq(VT.Size, 16), SDWASrc_f16, SDWASrc_f32);
1525  RegisterOperand retInt = !if(!eq(VT.Size, 16), SDWASrc_i16, SDWASrc_i32);
1526  RegisterOperand ret = !if(isFP, retFlt, retInt);
1527}
1528
1529// Returns the register class to use for sources of VOP3 instructions for the
1530// given VT.
1531class getVOP3SrcForVT<ValueType VT> {
1532  bit isFP = isFloatType<VT>.ret;
1533  RegisterOperand ret =
1534  !if(!eq(VT.Size, 128),
1535     VSrc_128,
1536     !if(!eq(VT.Size, 64),
1537        !if(isFP,
1538           VSrc_f64,
1539           VSrc_b64),
1540        !if(!eq(VT.Value, i1.Value),
1541           SSrc_i1,
1542           !if(isFP,
1543              !if(!eq(VT.Value, f16.Value),
1544                 VSrc_f16,
1545                 !if(!eq(VT.Value, v2f16.Value),
1546                    VSrc_v2f16,
1547                    !if(!eq(VT.Value, v4f16.Value),
1548                      AVSrc_64,
1549                      VSrc_f32
1550                    )
1551                 )
1552              ),
1553              !if(!eq(VT.Value, i16.Value),
1554                 VSrc_b16,
1555                 !if(!eq(VT.Value, v2i16.Value),
1556                    VSrc_v2b16,
1557                    VSrc_b32
1558                 )
1559              )
1560           )
1561        )
1562     )
1563  );
1564}
1565
1566// Float or packed int
1567class isModifierType<ValueType SrcVT> {
1568  bit ret =
1569    !if(!eq(SrcVT.Value, f16.Value), 1,
1570    !if(!eq(SrcVT.Value, f32.Value), 1,
1571    !if(!eq(SrcVT.Value, f64.Value), 1,
1572    !if(!eq(SrcVT.Value, v2f16.Value), 1,
1573    !if(!eq(SrcVT.Value, v2i16.Value), 1,
1574    0)))));
1575}
1576
1577// Return type of input modifiers operand for specified input operand
1578class getSrcMod <ValueType VT, bit EnableF32SrcMods> {
1579  bit isFP = isFloatType<VT>.ret;
1580  bit isPacked = isPackedType<VT>.ret;
1581  Operand ret =  !if(!eq(VT.Size, 64),
1582                     !if(isFP, FP64InputMods, Int64InputMods),
1583                       !if(isFP,
1584                         !if(!eq(VT.Value, f16.Value),
1585                            FP16InputMods,
1586                            FP32InputMods
1587                          ),
1588                         !if(EnableF32SrcMods, FP32InputMods, Int32InputMods))
1589                     );
1590}
1591
1592class getOpSelMod <ValueType VT> {
1593  Operand ret = !if(!eq(VT.Value, f16.Value), FP16InputMods, IntOpSelMods);
1594}
1595
1596// Return type of input modifiers operand specified input operand for DPP
1597class getSrcModExt <ValueType VT> {
1598  bit isFP = isFloatType<VT>.ret;
1599  Operand ret = !if(isFP, FPVRegInputMods, IntVRegInputMods);
1600}
1601
1602// Return type of input modifiers operand specified input operand for SDWA
1603class getSrcModSDWA <ValueType VT> {
1604  Operand ret = !if(!eq(VT.Value, f16.Value), FP16SDWAInputMods,
1605                !if(!eq(VT.Value, f32.Value), FP32SDWAInputMods,
1606                !if(!eq(VT.Value, i16.Value), Int16SDWAInputMods,
1607                Int32SDWAInputMods)));
1608}
1609
1610// Returns the input arguments for VOP[12C] instructions for the given SrcVT.
1611class getIns32 <RegisterOperand Src0RC, RegisterClass Src1RC, int NumSrcArgs> {
1612  dag ret = !if(!eq(NumSrcArgs, 1), (ins Src0RC:$src0),               // VOP1
1613            !if(!eq(NumSrcArgs, 2), (ins Src0RC:$src0, Src1RC:$src1), // VOP2
1614                                    (ins)));
1615}
1616
1617// Returns the input arguments for VOP3 instructions for the given SrcVT.
1618class getIns64 <RegisterOperand Src0RC, RegisterOperand Src1RC,
1619                RegisterOperand Src2RC, int NumSrcArgs,
1620                bit HasIntClamp, bit HasModifiers, bit HasSrc2Mods, bit HasOMod,
1621                Operand Src0Mod, Operand Src1Mod, Operand Src2Mod> {
1622
1623  dag ret =
1624    !if (!eq(NumSrcArgs, 0),
1625      // VOP1 without input operands (V_NOP, V_CLREXCP)
1626      (ins),
1627      /* else */
1628    !if (!eq(NumSrcArgs, 1),
1629      !if (!eq(HasModifiers, 1),
1630        // VOP1 with modifiers
1631        (ins Src0Mod:$src0_modifiers, Src0RC:$src0,
1632             clampmod0:$clamp, omod0:$omod)
1633      /* else */,
1634        // VOP1 without modifiers
1635        !if (!eq(HasIntClamp, 1),
1636          (ins Src0RC:$src0, clampmod0:$clamp),
1637          (ins Src0RC:$src0))
1638      /* endif */ ),
1639    !if (!eq(NumSrcArgs, 2),
1640      !if (!eq(HasModifiers, 1),
1641        // VOP 2 with modifiers
1642        !if( !eq(HasOMod, 1),
1643          (ins Src0Mod:$src0_modifiers, Src0RC:$src0,
1644               Src1Mod:$src1_modifiers, Src1RC:$src1,
1645               clampmod0:$clamp, omod0:$omod),
1646           (ins Src0Mod:$src0_modifiers, Src0RC:$src0,
1647               Src1Mod:$src1_modifiers, Src1RC:$src1,
1648               clampmod0:$clamp))
1649      /* else */,
1650        // VOP2 without modifiers
1651        !if (!eq(HasIntClamp, 1),
1652          (ins Src0RC:$src0, Src1RC:$src1, clampmod0:$clamp),
1653          (ins Src0RC:$src0, Src1RC:$src1))
1654
1655      /* endif */ )
1656    /* NumSrcArgs == 3 */,
1657      !if (!eq(HasModifiers, 1),
1658        !if (!eq(HasSrc2Mods, 1),
1659          // VOP3 with modifiers
1660          !if (!eq(HasOMod, 1),
1661            (ins Src0Mod:$src0_modifiers, Src0RC:$src0,
1662                 Src1Mod:$src1_modifiers, Src1RC:$src1,
1663                 Src2Mod:$src2_modifiers, Src2RC:$src2,
1664                 clampmod0:$clamp, omod0:$omod),
1665            !if (!eq(HasIntClamp, 1),
1666              (ins Src0Mod:$src0_modifiers, Src0RC:$src0,
1667                   Src1Mod:$src1_modifiers, Src1RC:$src1,
1668                   Src2Mod:$src2_modifiers, Src2RC:$src2,
1669                   clampmod0:$clamp),
1670              (ins Src0Mod:$src0_modifiers, Src0RC:$src0,
1671                   Src1Mod:$src1_modifiers, Src1RC:$src1,
1672                   Src2Mod:$src2_modifiers, Src2RC:$src2))),
1673          // VOP3 with modifiers except src2
1674          !if (!eq(HasOMod, 1),
1675            (ins Src0Mod:$src0_modifiers, Src0RC:$src0,
1676                 Src1Mod:$src1_modifiers, Src1RC:$src1,
1677                 Src2RC:$src2, clampmod0:$clamp, omod0:$omod),
1678            !if (!eq(HasIntClamp, 1),
1679              (ins Src0Mod:$src0_modifiers, Src0RC:$src0,
1680                   Src1Mod:$src1_modifiers, Src1RC:$src1,
1681                   Src2RC:$src2, clampmod0:$clamp),
1682              (ins Src0Mod:$src0_modifiers, Src0RC:$src0,
1683                   Src1Mod:$src1_modifiers, Src1RC:$src1,
1684                   Src2RC:$src2))))
1685      /* else */,
1686        // VOP3 without modifiers
1687        !if (!eq(HasIntClamp, 1),
1688          (ins Src0RC:$src0, Src1RC:$src1, Src2RC:$src2, clampmod0:$clamp),
1689          (ins Src0RC:$src0, Src1RC:$src1, Src2RC:$src2))
1690      /* endif */ ))));
1691}
1692
1693/// XXX - src1 may only allow VGPRs?
1694
1695// The modifiers (except clamp) are dummy operands for the benefit of
1696// printing and parsing. They defer their values to looking at the
1697// srcN_modifiers for what to print.
1698class getInsVOP3P <RegisterOperand Src0RC, RegisterOperand Src1RC,
1699                   RegisterOperand Src2RC, int NumSrcArgs,
1700                   bit HasClamp,
1701                   Operand Src0Mod, Operand Src1Mod, Operand Src2Mod> {
1702  dag ret = !if (!eq(NumSrcArgs, 2),
1703    !if (HasClamp,
1704      (ins Src0Mod:$src0_modifiers, Src0RC:$src0,
1705           Src1Mod:$src1_modifiers, Src1RC:$src1,
1706           clampmod:$clamp,
1707           op_sel:$op_sel, op_sel_hi:$op_sel_hi,
1708           neg_lo:$neg_lo, neg_hi:$neg_hi),
1709      (ins Src0Mod:$src0_modifiers, Src0RC:$src0,
1710           Src1Mod:$src1_modifiers, Src1RC:$src1,
1711           op_sel:$op_sel, op_sel_hi:$op_sel_hi,
1712           neg_lo:$neg_lo, neg_hi:$neg_hi)),
1713    // else NumSrcArgs == 3
1714    !if (HasClamp,
1715      (ins Src0Mod:$src0_modifiers, Src0RC:$src0,
1716           Src1Mod:$src1_modifiers, Src1RC:$src1,
1717           Src2Mod:$src2_modifiers, Src2RC:$src2,
1718           clampmod:$clamp,
1719           op_sel:$op_sel, op_sel_hi:$op_sel_hi,
1720           neg_lo:$neg_lo, neg_hi:$neg_hi),
1721      (ins Src0Mod:$src0_modifiers, Src0RC:$src0,
1722           Src1Mod:$src1_modifiers, Src1RC:$src1,
1723           Src2Mod:$src2_modifiers, Src2RC:$src2,
1724           op_sel:$op_sel, op_sel_hi:$op_sel_hi,
1725           neg_lo:$neg_lo, neg_hi:$neg_hi))
1726  );
1727}
1728
1729class getInsVOP3OpSel <RegisterOperand Src0RC,
1730                       RegisterOperand Src1RC,
1731                       RegisterOperand Src2RC,
1732                       int NumSrcArgs,
1733                       bit HasClamp,
1734                       Operand Src0Mod,
1735                       Operand Src1Mod,
1736                       Operand Src2Mod> {
1737  dag ret = !if (!eq(NumSrcArgs, 2),
1738    !if (HasClamp,
1739      (ins Src0Mod:$src0_modifiers, Src0RC:$src0,
1740           Src1Mod:$src1_modifiers, Src1RC:$src1,
1741           clampmod:$clamp,
1742           op_sel:$op_sel),
1743      (ins Src0Mod:$src0_modifiers, Src0RC:$src0,
1744           Src1Mod:$src1_modifiers, Src1RC:$src1,
1745           op_sel:$op_sel)),
1746    // else NumSrcArgs == 3
1747    !if (HasClamp,
1748      (ins Src0Mod:$src0_modifiers, Src0RC:$src0,
1749           Src1Mod:$src1_modifiers, Src1RC:$src1,
1750           Src2Mod:$src2_modifiers, Src2RC:$src2,
1751           clampmod:$clamp,
1752           op_sel:$op_sel),
1753      (ins Src0Mod:$src0_modifiers, Src0RC:$src0,
1754           Src1Mod:$src1_modifiers, Src1RC:$src1,
1755           Src2Mod:$src2_modifiers, Src2RC:$src2,
1756           op_sel:$op_sel))
1757  );
1758}
1759
1760class getInsDPP <RegisterOperand DstRC, RegisterClass Src0RC, RegisterClass Src1RC,
1761                 int NumSrcArgs, bit HasModifiers,
1762                 Operand Src0Mod, Operand Src1Mod> {
1763
1764  dag ret = !if (!eq(NumSrcArgs, 0),
1765                // VOP1 without input operands (V_NOP)
1766                (ins dpp_ctrl:$dpp_ctrl, row_mask:$row_mask,
1767                     bank_mask:$bank_mask, bound_ctrl:$bound_ctrl),
1768            !if (!eq(NumSrcArgs, 1),
1769              !if (!eq(HasModifiers, 1),
1770                // VOP1_DPP with modifiers
1771                (ins DstRC:$old, Src0Mod:$src0_modifiers,
1772                     Src0RC:$src0, dpp_ctrl:$dpp_ctrl, row_mask:$row_mask,
1773                     bank_mask:$bank_mask, bound_ctrl:$bound_ctrl)
1774              /* else */,
1775                // VOP1_DPP without modifiers
1776                (ins DstRC:$old, Src0RC:$src0,
1777                     dpp_ctrl:$dpp_ctrl, row_mask:$row_mask,
1778                     bank_mask:$bank_mask, bound_ctrl:$bound_ctrl)
1779              /* endif */)
1780              /* NumSrcArgs == 2 */,
1781              !if (!eq(HasModifiers, 1),
1782                // VOP2_DPP with modifiers
1783                (ins DstRC:$old,
1784                     Src0Mod:$src0_modifiers, Src0RC:$src0,
1785                     Src1Mod:$src1_modifiers, Src1RC:$src1,
1786                     dpp_ctrl:$dpp_ctrl, row_mask:$row_mask,
1787                     bank_mask:$bank_mask, bound_ctrl:$bound_ctrl)
1788              /* else */,
1789                // VOP2_DPP without modifiers
1790                (ins DstRC:$old,
1791                     Src0RC:$src0, Src1RC:$src1, dpp_ctrl:$dpp_ctrl,
1792                     row_mask:$row_mask, bank_mask:$bank_mask,
1793                     bound_ctrl:$bound_ctrl)
1794             /* endif */)));
1795}
1796
1797class getInsDPP16 <RegisterOperand DstRC, RegisterClass Src0RC, RegisterClass Src1RC,
1798                   int NumSrcArgs, bit HasModifiers,
1799                   Operand Src0Mod, Operand Src1Mod> {
1800  dag ret = !con(getInsDPP<DstRC, Src0RC, Src1RC, NumSrcArgs,
1801                           HasModifiers, Src0Mod, Src1Mod>.ret,
1802                 (ins FI:$fi));
1803}
1804
1805class getInsDPP8 <RegisterOperand DstRC, RegisterClass Src0RC, RegisterClass Src1RC,
1806                 int NumSrcArgs, bit HasModifiers,
1807                 Operand Src0Mod, Operand Src1Mod> {
1808  dag ret = !if (!eq(NumSrcArgs, 0),
1809                // VOP1 without input operands (V_NOP)
1810                (ins dpp8:$dpp8, FI:$fi),
1811            !if (!eq(NumSrcArgs, 1),
1812              !if (!eq(HasModifiers, 1),
1813                // VOP1_DPP with modifiers
1814                (ins DstRC:$old, Src0Mod:$src0_modifiers,
1815                     Src0RC:$src0, dpp8:$dpp8, FI:$fi)
1816              /* else */,
1817                // VOP1_DPP without modifiers
1818                (ins DstRC:$old, Src0RC:$src0, dpp8:$dpp8, FI:$fi)
1819              /* endif */)
1820              /* NumSrcArgs == 2 */,
1821              !if (!eq(HasModifiers, 1),
1822                // VOP2_DPP with modifiers
1823                (ins DstRC:$old,
1824                     Src0Mod:$src0_modifiers, Src0RC:$src0,
1825                     Src1Mod:$src1_modifiers, Src1RC:$src1,
1826                     dpp8:$dpp8, FI:$fi)
1827              /* else */,
1828                // VOP2_DPP without modifiers
1829                (ins DstRC:$old,
1830                     Src0RC:$src0, Src1RC:$src1, dpp8:$dpp8, FI:$fi)
1831             /* endif */)));
1832}
1833
1834
1835// Ins for SDWA
1836class getInsSDWA <RegisterOperand Src0RC, RegisterOperand Src1RC, int NumSrcArgs,
1837                  bit HasSDWAOMod, Operand Src0Mod, Operand Src1Mod,
1838                  ValueType DstVT> {
1839
1840  dag ret = !if(!eq(NumSrcArgs, 0),
1841               // VOP1 without input operands (V_NOP)
1842               (ins),
1843            !if(!eq(NumSrcArgs, 1),
1844               // VOP1
1845               !if(!eq(HasSDWAOMod, 0),
1846                  // VOP1_SDWA without omod
1847                  (ins Src0Mod:$src0_modifiers, Src0RC:$src0,
1848                       clampmod:$clamp,
1849                       dst_sel:$dst_sel, dst_unused:$dst_unused,
1850                       src0_sel:$src0_sel),
1851                  // VOP1_SDWA with omod
1852                  (ins Src0Mod:$src0_modifiers, Src0RC:$src0,
1853                       clampmod:$clamp, omod:$omod,
1854                       dst_sel:$dst_sel, dst_unused:$dst_unused,
1855                       src0_sel:$src0_sel)),
1856            !if(!eq(NumSrcArgs, 2),
1857               !if(!eq(DstVT.Size, 1),
1858                  // VOPC_SDWA
1859                  (ins Src0Mod:$src0_modifiers, Src0RC:$src0,
1860                       Src1Mod:$src1_modifiers, Src1RC:$src1,
1861                       clampmod:$clamp, src0_sel:$src0_sel, src1_sel:$src1_sel),
1862                  // VOP2_SDWA
1863                  !if(!eq(HasSDWAOMod, 0),
1864                     // VOP2_SDWA without omod
1865                     (ins Src0Mod:$src0_modifiers, Src0RC:$src0,
1866                          Src1Mod:$src1_modifiers, Src1RC:$src1,
1867                          clampmod:$clamp,
1868                          dst_sel:$dst_sel, dst_unused:$dst_unused,
1869                          src0_sel:$src0_sel, src1_sel:$src1_sel),
1870                     // VOP2_SDWA with omod
1871                     (ins Src0Mod:$src0_modifiers, Src0RC:$src0,
1872                          Src1Mod:$src1_modifiers, Src1RC:$src1,
1873                          clampmod:$clamp, omod:$omod,
1874                          dst_sel:$dst_sel, dst_unused:$dst_unused,
1875                          src0_sel:$src0_sel, src1_sel:$src1_sel))),
1876            (ins)/* endif */)));
1877}
1878
1879// Outs for DPP and SDWA
1880class getOutsExt <bit HasDst, ValueType DstVT, RegisterOperand DstRCExt> {
1881  dag ret = !if(HasDst,
1882                !if(!eq(DstVT.Size, 1),
1883                    (outs), // no dst for VOPC, we use "vcc"-token as dst in SDWA VOPC instructions
1884                    (outs DstRCExt:$vdst)),
1885                (outs)); // V_NOP
1886}
1887
1888// Outs for SDWA
1889class getOutsSDWA <bit HasDst, ValueType DstVT, RegisterOperand DstRCSDWA> {
1890  dag ret = !if(HasDst,
1891                !if(!eq(DstVT.Size, 1),
1892                    (outs DstRCSDWA:$sdst),
1893                    (outs DstRCSDWA:$vdst)),
1894                (outs)); // V_NOP
1895}
1896
1897// Returns the assembly string for the inputs and outputs of a VOP[12C]
1898// instruction.  This does not add the _e32 suffix, so it can be reused
1899// by getAsm64.
1900class getAsm32 <bit HasDst, int NumSrcArgs, ValueType DstVT = i32> {
1901  string dst = !if(!eq(DstVT.Size, 1), "$sdst", "$vdst"); // use $sdst for VOPC
1902  string src0 = ", $src0";
1903  string src1 = ", $src1";
1904  string src2 = ", $src2";
1905  string ret = !if(HasDst, dst, "") #
1906               !if(!eq(NumSrcArgs, 1), src0, "") #
1907               !if(!eq(NumSrcArgs, 2), src0#src1, "") #
1908               !if(!eq(NumSrcArgs, 3), src0#src1#src2, "");
1909}
1910
1911// Returns the assembly string for the inputs and outputs of a VOP3
1912// instruction.
1913class getAsm64 <bit HasDst, int NumSrcArgs, bit HasIntClamp, bit HasModifiers,
1914                bit HasOMod, ValueType DstVT = i32> {
1915  string dst = !if(!eq(DstVT.Size, 1), "$sdst", "$vdst"); // use $sdst for VOPC
1916  string src0 = !if(!eq(NumSrcArgs, 1), "$src0_modifiers", "$src0_modifiers,");
1917  string src1 = !if(!eq(NumSrcArgs, 1), "",
1918                   !if(!eq(NumSrcArgs, 2), " $src1_modifiers",
1919                                           " $src1_modifiers,"));
1920  string src2 = !if(!eq(NumSrcArgs, 3), " $src2_modifiers", "");
1921  string iclamp = !if(HasIntClamp, "$clamp", "");
1922  string ret =
1923  !if(!eq(HasModifiers, 0),
1924      getAsm32<HasDst, NumSrcArgs, DstVT>.ret # iclamp,
1925      dst#", "#src0#src1#src2#"$clamp"#!if(HasOMod, "$omod", ""));
1926}
1927
1928// Returns the assembly string for the inputs and outputs of a VOP3P
1929// instruction.
1930class getAsmVOP3P <bit HasDst, int NumSrcArgs, bit HasModifiers,
1931                   bit HasClamp, ValueType DstVT = i32> {
1932  string dst = " $vdst";
1933  string src0 = !if(!eq(NumSrcArgs, 1), "$src0", "$src0,");
1934  string src1 = !if(!eq(NumSrcArgs, 1), "",
1935                   !if(!eq(NumSrcArgs, 2), " $src1",
1936                                           " $src1,"));
1937  string src2 = !if(!eq(NumSrcArgs, 3), " $src2", "");
1938
1939  string mods = !if(HasModifiers, "$neg_lo$neg_hi", "");
1940  string clamp = !if(HasClamp, "$clamp", "");
1941
1942  // Each modifier is printed as an array of bits for each operand, so
1943  // all operands are printed as part of src0_modifiers.
1944  string ret = dst#", "#src0#src1#src2#"$op_sel$op_sel_hi"#mods#clamp;
1945}
1946
1947class getAsmVOP3OpSel <int NumSrcArgs,
1948                       bit HasClamp,
1949                       bit Src0HasMods,
1950                       bit Src1HasMods,
1951                       bit Src2HasMods> {
1952  string dst = " $vdst";
1953
1954  string isrc0 = !if(!eq(NumSrcArgs, 1), "$src0", "$src0,");
1955  string isrc1 = !if(!eq(NumSrcArgs, 1), "",
1956                     !if(!eq(NumSrcArgs, 2), " $src1",
1957                                             " $src1,"));
1958  string isrc2 = !if(!eq(NumSrcArgs, 3), " $src2", "");
1959
1960  string fsrc0 = !if(!eq(NumSrcArgs, 1), "$src0_modifiers", "$src0_modifiers,");
1961  string fsrc1 = !if(!eq(NumSrcArgs, 1), "",
1962                     !if(!eq(NumSrcArgs, 2), " $src1_modifiers",
1963                                             " $src1_modifiers,"));
1964  string fsrc2 = !if(!eq(NumSrcArgs, 3), " $src2_modifiers", "");
1965
1966  string src0 = !if(Src0HasMods, fsrc0, isrc0);
1967  string src1 = !if(Src1HasMods, fsrc1, isrc1);
1968  string src2 = !if(Src2HasMods, fsrc2, isrc2);
1969
1970  string clamp = !if(HasClamp, "$clamp", "");
1971
1972  string ret = dst#", "#src0#src1#src2#"$op_sel"#clamp;
1973}
1974
1975class getAsmDPP <bit HasDst, int NumSrcArgs, bit HasModifiers, ValueType DstVT = i32> {
1976  string dst = !if(HasDst,
1977                   !if(!eq(DstVT.Size, 1),
1978                       "$sdst",
1979                       "$vdst"),
1980                    ""); // use $sdst for VOPC
1981  string src0 = !if(!eq(NumSrcArgs, 1), "$src0_modifiers", "$src0_modifiers,");
1982  string src1 = !if(!eq(NumSrcArgs, 1), "",
1983                   !if(!eq(NumSrcArgs, 2), " $src1_modifiers",
1984                                           " $src1_modifiers,"));
1985  string args = !if(!eq(HasModifiers, 0),
1986                     getAsm32<0, NumSrcArgs, DstVT>.ret,
1987                     ", "#src0#src1);
1988  string ret = dst#args#" $dpp_ctrl$row_mask$bank_mask$bound_ctrl";
1989}
1990
1991class getAsmDPP16 <bit HasDst, int NumSrcArgs, bit HasModifiers, ValueType DstVT = i32> {
1992  string ret = getAsmDPP<HasDst, NumSrcArgs, HasModifiers, DstVT>.ret#"$fi";
1993}
1994
1995class getAsmDPP8 <bit HasDst, int NumSrcArgs, bit HasModifiers, ValueType DstVT = i32> {
1996  string dst = !if(HasDst,
1997                   !if(!eq(DstVT.Size, 1),
1998                       "$sdst",
1999                       "$vdst"),
2000                    ""); // use $sdst for VOPC
2001  string src0 = !if(!eq(NumSrcArgs, 1), "$src0_modifiers", "$src0_modifiers,");
2002  string src1 = !if(!eq(NumSrcArgs, 1), "",
2003                   !if(!eq(NumSrcArgs, 2), " $src1_modifiers",
2004                                           " $src1_modifiers,"));
2005  string args = !if(!eq(HasModifiers, 0),
2006                     getAsm32<0, NumSrcArgs, DstVT>.ret,
2007                     ", "#src0#src1);
2008  string ret = dst#args#"$dpp8$fi";
2009}
2010
2011class getAsmSDWA <bit HasDst, int NumSrcArgs, ValueType DstVT = i32> {
2012  string dst = !if(HasDst,
2013                   !if(!eq(DstVT.Size, 1),
2014                       " vcc", // use vcc token as dst for VOPC instructioins
2015                       "$vdst"),
2016                    "");
2017  string src0 = "$src0_modifiers";
2018  string src1 = "$src1_modifiers";
2019  string args = !if(!eq(NumSrcArgs, 0),
2020                    "",
2021                    !if(!eq(NumSrcArgs, 1),
2022                        ", "#src0#"$clamp",
2023                        ", "#src0#", "#src1#"$clamp"
2024                     )
2025                );
2026  string sdwa = !if(!eq(NumSrcArgs, 0),
2027                    "",
2028                    !if(!eq(NumSrcArgs, 1),
2029                        " $dst_sel $dst_unused $src0_sel",
2030                        !if(!eq(DstVT.Size, 1),
2031                            " $src0_sel $src1_sel", // No dst_sel and dst_unused for VOPC
2032                            " $dst_sel $dst_unused $src0_sel $src1_sel"
2033                        )
2034                    )
2035                );
2036  string ret = dst#args#sdwa;
2037}
2038
2039class getAsmSDWA9 <bit HasDst, bit HasOMod, int NumSrcArgs,
2040                   ValueType DstVT = i32> {
2041  string dst = !if(HasDst,
2042                   !if(!eq(DstVT.Size, 1),
2043                       "$sdst", // VOPC
2044                       "$vdst"), // VOP1/2
2045                    "");
2046  string src0 = "$src0_modifiers";
2047  string src1 = "$src1_modifiers";
2048  string out_mods = !if(!eq(HasOMod, 0), "$clamp", "$clamp$omod");
2049  string args = !if(!eq(NumSrcArgs, 0), "",
2050                    !if(!eq(NumSrcArgs, 1),
2051                        ", "#src0,
2052                        ", "#src0#", "#src1
2053                     )
2054                );
2055  string sdwa = !if(!eq(NumSrcArgs, 0), "",
2056                    !if(!eq(NumSrcArgs, 1),
2057                        out_mods#" $dst_sel $dst_unused $src0_sel",
2058                        !if(!eq(DstVT.Size, 1),
2059                            " $src0_sel $src1_sel", // No dst_sel, dst_unused and output modifiers for VOPC
2060                            out_mods#" $dst_sel $dst_unused $src0_sel $src1_sel"
2061                        )
2062                    )
2063                );
2064  string ret = dst#args#sdwa;
2065}
2066
2067
2068// Function that checks if instruction supports DPP and SDWA
2069class getHasExt <int NumSrcArgs, ValueType DstVT = i32, ValueType Src0VT = i32,
2070                 ValueType Src1VT = i32> {
2071  bit ret = !if(!eq(NumSrcArgs, 3),
2072                0, // NumSrcArgs == 3 - No DPP or SDWA for VOP3
2073                !if(!eq(DstVT.Size, 64),
2074                    0, // 64-bit dst - No DPP or SDWA for 64-bit operands
2075                    !if(!eq(Src0VT.Size, 64),
2076                        0, // 64-bit src0
2077                        !if(!eq(Src1VT.Size, 64),
2078                            0, // 64-bit src2
2079                            1
2080                        )
2081                    )
2082                )
2083            );
2084}
2085
2086class getHasDPP <int NumSrcArgs, ValueType DstVT = i32, ValueType Src0VT = i32,
2087                 ValueType Src1VT = i32> {
2088  bit ret = !if(!eq(NumSrcArgs, 0), 0,
2089                getHasExt<NumSrcArgs, DstVT, Src0VT, Src1VT>.ret);
2090}
2091
2092class BitOr<bit a, bit b> {
2093  bit ret = !if(a, 1, !if(b, 1, 0));
2094}
2095
2096class BitAnd<bit a, bit b> {
2097  bit ret = !if(a, !if(b, 1, 0), 0);
2098}
2099
2100def PatGenMode {
2101  int NoPattern = 0;
2102  int Pattern   = 1;
2103}
2104
2105class VOPProfile <list<ValueType> _ArgVT, bit _EnableF32SrcMods = 0,
2106                  bit _EnableClamp = 0> {
2107
2108  field list<ValueType> ArgVT = _ArgVT;
2109  field bit EnableF32SrcMods = _EnableF32SrcMods;
2110  field bit EnableClamp = _EnableClamp;
2111
2112  field ValueType DstVT = ArgVT[0];
2113  field ValueType Src0VT = ArgVT[1];
2114  field ValueType Src1VT = ArgVT[2];
2115  field ValueType Src2VT = ArgVT[3];
2116  field RegisterOperand DstRC = getVALUDstForVT<DstVT>.ret;
2117  field RegisterOperand DstRCDPP = getVALUDstForVT<DstVT>.ret;
2118  field RegisterOperand DstRCSDWA = getSDWADstForVT<DstVT>.ret;
2119  field RegisterOperand Src0RC32 = getVOPSrc0ForVT<Src0VT>.ret;
2120  field RegisterClass Src1RC32 = getVregSrcForVT<Src1VT>.ret;
2121  field RegisterOperand Src0RC64 = getVOP3SrcForVT<Src0VT>.ret;
2122  field RegisterOperand Src1RC64 = getVOP3SrcForVT<Src1VT>.ret;
2123  field RegisterOperand Src2RC64 = getVOP3SrcForVT<Src2VT>.ret;
2124  field RegisterClass Src0DPP = getVregSrcForVT<Src0VT>.ret;
2125  field RegisterClass Src1DPP = getVregSrcForVT<Src1VT>.ret;
2126  field RegisterOperand Src0SDWA = getSDWASrcForVT<Src0VT>.ret;
2127  field RegisterOperand Src1SDWA = getSDWASrcForVT<Src0VT>.ret;
2128  field Operand Src0Mod = getSrcMod<Src0VT, EnableF32SrcMods>.ret;
2129  field Operand Src1Mod = getSrcMod<Src1VT, EnableF32SrcMods>.ret;
2130  field Operand Src2Mod = getSrcMod<Src2VT, EnableF32SrcMods>.ret;
2131  field Operand Src0ModDPP = getSrcModExt<Src0VT>.ret;
2132  field Operand Src1ModDPP = getSrcModExt<Src1VT>.ret;
2133  field Operand Src0ModSDWA = getSrcModSDWA<Src0VT>.ret;
2134  field Operand Src1ModSDWA = getSrcModSDWA<Src1VT>.ret;
2135
2136
2137  field bit HasDst = !if(!eq(DstVT.Value, untyped.Value), 0, 1);
2138  field bit HasDst32 = HasDst;
2139  field bit EmitDst = HasDst; // force dst encoding, see v_movreld_b32 special case
2140  field int NumSrcArgs = getNumSrcArgs<Src0VT, Src1VT, Src2VT>.ret;
2141  field bit HasSrc0 = !if(!eq(Src0VT.Value, untyped.Value), 0, 1);
2142  field bit HasSrc1 = !if(!eq(Src1VT.Value, untyped.Value), 0, 1);
2143  field bit HasSrc2 = !if(!eq(Src2VT.Value, untyped.Value), 0, 1);
2144
2145  // TODO: Modifiers logic is somewhat adhoc here, to be refined later
2146  // HasModifiers affects the normal and DPP encodings. We take note of EnableF32SrcMods, which
2147  // enables modifiers for i32 type.
2148  field bit HasModifiers = BitOr<isModifierType<Src0VT>.ret, EnableF32SrcMods>.ret;
2149
2150  // HasSrc*FloatMods affects the SDWA encoding. We ignore EnableF32SrcMods.
2151  field bit HasSrc0FloatMods = isFloatType<Src0VT>.ret;
2152  field bit HasSrc1FloatMods = isFloatType<Src1VT>.ret;
2153  field bit HasSrc2FloatMods = isFloatType<Src2VT>.ret;
2154
2155  // HasSrc*IntMods affects the SDWA encoding. We ignore EnableF32SrcMods.
2156  field bit HasSrc0IntMods = isIntType<Src0VT>.ret;
2157  field bit HasSrc1IntMods = isIntType<Src1VT>.ret;
2158  field bit HasSrc2IntMods = isIntType<Src2VT>.ret;
2159
2160  field bit HasSrc0Mods = HasModifiers;
2161  field bit HasSrc1Mods = !if(HasModifiers, BitOr<HasSrc1FloatMods, HasSrc1IntMods>.ret, 0);
2162  field bit HasSrc2Mods = !if(HasModifiers, BitOr<HasSrc2FloatMods, HasSrc2IntMods>.ret, 0);
2163
2164  field bit HasClamp = BitOr<isModifierType<Src0VT>.ret, EnableClamp>.ret;
2165  field bit HasSDWAClamp = EmitDst;
2166  field bit HasFPClamp = BitAnd<isFloatType<DstVT>.ret, HasClamp>.ret;
2167  field bit HasIntClamp = !if(isFloatType<DstVT>.ret, 0, HasClamp);
2168  field bit HasClampLo = HasClamp;
2169  field bit HasClampHi = BitAnd<isPackedType<DstVT>.ret, HasClamp>.ret;
2170  field bit HasHigh = 0;
2171
2172  field bit IsPacked = isPackedType<Src0VT>.ret;
2173  field bit HasOpSel = IsPacked;
2174  field bit HasOMod = !if(HasOpSel, 0, isFloatType<DstVT>.ret);
2175  field bit HasSDWAOMod = isFloatType<DstVT>.ret;
2176
2177  field bit HasExt = getHasExt<NumSrcArgs, DstVT, Src0VT, Src1VT>.ret;
2178  field bit HasExtDPP = getHasDPP<NumSrcArgs, DstVT, Src0VT, Src1VT>.ret;
2179  field bit HasExtSDWA = HasExt;
2180  field bit HasExtSDWA9 = HasExt;
2181  field int NeedPatGen = PatGenMode.NoPattern;
2182
2183  field bit IsMAI = 0;
2184  field bit IsDOT = 0;
2185
2186  field Operand Src0PackedMod = !if(HasSrc0FloatMods, PackedF16InputMods, PackedI16InputMods);
2187  field Operand Src1PackedMod = !if(HasSrc1FloatMods, PackedF16InputMods, PackedI16InputMods);
2188  field Operand Src2PackedMod = !if(HasSrc2FloatMods, PackedF16InputMods, PackedI16InputMods);
2189
2190  field dag Outs = !if(HasDst,(outs DstRC:$vdst),(outs));
2191
2192  // VOP3b instructions are a special case with a second explicit
2193  // output. This is manually overridden for them.
2194  field dag Outs32 = Outs;
2195  field dag Outs64 = Outs;
2196  field dag OutsDPP = getOutsExt<HasDst, DstVT, DstRCDPP>.ret;
2197  field dag OutsDPP8 = getOutsExt<HasDst, DstVT, DstRCDPP>.ret;
2198  field dag OutsSDWA = getOutsSDWA<HasDst, DstVT, DstRCSDWA>.ret;
2199
2200  field dag Ins32 = getIns32<Src0RC32, Src1RC32, NumSrcArgs>.ret;
2201  field dag Ins64 = getIns64<Src0RC64, Src1RC64, Src2RC64, NumSrcArgs,
2202                             HasIntClamp, HasModifiers, HasSrc2Mods,
2203                             HasOMod, Src0Mod, Src1Mod, Src2Mod>.ret;
2204  field dag InsVOP3P = getInsVOP3P<Src0RC64, Src1RC64, Src2RC64,
2205                                   NumSrcArgs, HasClamp,
2206                                   Src0PackedMod, Src1PackedMod, Src2PackedMod>.ret;
2207  field dag InsVOP3OpSel = getInsVOP3OpSel<Src0RC64, Src1RC64, Src2RC64,
2208                                           NumSrcArgs,
2209                                           HasClamp,
2210                                           getOpSelMod<Src0VT>.ret,
2211                                           getOpSelMod<Src1VT>.ret,
2212                                           getOpSelMod<Src2VT>.ret>.ret;
2213  field dag InsDPP = !if(HasExtDPP,
2214                         getInsDPP<DstRCDPP, Src0DPP, Src1DPP, NumSrcArgs,
2215                                   HasModifiers, Src0ModDPP, Src1ModDPP>.ret,
2216                         (ins));
2217  field dag InsDPP16 = getInsDPP16<DstRCDPP, Src0DPP, Src1DPP, NumSrcArgs,
2218                                   HasModifiers, Src0ModDPP, Src1ModDPP>.ret;
2219  field dag InsDPP8 = getInsDPP8<DstRCDPP, Src0DPP, Src1DPP, NumSrcArgs, 0,
2220                                 Src0ModDPP, Src1ModDPP>.ret;
2221  field dag InsSDWA = getInsSDWA<Src0SDWA, Src1SDWA, NumSrcArgs,
2222                                 HasSDWAOMod, Src0ModSDWA, Src1ModSDWA,
2223                                 DstVT>.ret;
2224
2225
2226  field string Asm32 = getAsm32<HasDst, NumSrcArgs, DstVT>.ret;
2227  field string Asm64 = getAsm64<HasDst, NumSrcArgs, HasIntClamp, HasModifiers, HasOMod, DstVT>.ret;
2228  field string AsmVOP3P = getAsmVOP3P<HasDst, NumSrcArgs, HasModifiers, HasClamp, DstVT>.ret;
2229  field string AsmVOP3OpSel = getAsmVOP3OpSel<NumSrcArgs,
2230                                              HasClamp,
2231                                              HasSrc0FloatMods,
2232                                              HasSrc1FloatMods,
2233                                              HasSrc2FloatMods>.ret;
2234  field string AsmDPP = !if(HasExtDPP,
2235                            getAsmDPP<HasDst, NumSrcArgs, HasModifiers, DstVT>.ret, "");
2236  field string AsmDPP16 = getAsmDPP16<HasDst, NumSrcArgs, HasModifiers, DstVT>.ret;
2237  field string AsmDPP8 = getAsmDPP8<HasDst, NumSrcArgs, 0, DstVT>.ret;
2238  field string AsmSDWA = getAsmSDWA<HasDst, NumSrcArgs, DstVT>.ret;
2239  field string AsmSDWA9 = getAsmSDWA9<HasDst, HasSDWAOMod, NumSrcArgs, DstVT>.ret;
2240
2241  field string TieRegDPP = "$old";
2242}
2243
2244class VOP_NO_EXT <VOPProfile p> : VOPProfile <p.ArgVT> {
2245  let HasExt = 0;
2246  let HasExtDPP = 0;
2247  let HasExtSDWA = 0;
2248  let HasExtSDWA9 = 0;
2249}
2250
2251class VOP_PAT_GEN <VOPProfile p, int mode=PatGenMode.Pattern> : VOPProfile <p.ArgVT> {
2252  let NeedPatGen = mode;
2253}
2254
2255def VOP_F16_F16 : VOPProfile <[f16, f16, untyped, untyped]>;
2256def VOP_F16_I16 : VOPProfile <[f16, i16, untyped, untyped]>;
2257def VOP_I16_F16 : VOPProfile <[i16, f16, untyped, untyped]>;
2258
2259def VOP_F16_F16_F16 : VOPProfile <[f16, f16, f16, untyped]>;
2260def VOP_F16_F16_I16 : VOPProfile <[f16, f16, i16, untyped]>;
2261def VOP_F16_F16_I32 : VOPProfile <[f16, f16, i32, untyped]>;
2262def VOP_I16_I16_I16 : VOPProfile <[i16, i16, i16, untyped]>;
2263
2264def VOP_I16_I16_I16_I16 : VOPProfile <[i16, i16, i16, i16, untyped]>;
2265def VOP_F16_F16_F16_F16 : VOPProfile <[f16, f16, f16, f16, untyped]>;
2266
2267def VOP_I32_I16_I16_I32 : VOPProfile <[i32, i16, i16, i32, untyped]>;
2268
2269def VOP_V2F16_V2F16_V2F16 : VOPProfile <[v2f16, v2f16, v2f16, untyped]>;
2270def VOP_V2I16_V2I16_V2I16 : VOPProfile <[v2i16, v2i16, v2i16, untyped]>;
2271def VOP_B32_F16_F16 : VOPProfile <[i32, f16, f16, untyped]>;
2272
2273def VOP_V2F16_V2F16_V2F16_V2F16 : VOPProfile <[v2f16, v2f16, v2f16, v2f16]>;
2274def VOP_V2I16_V2I16_V2I16_V2I16 : VOPProfile <[v2i16, v2i16, v2i16, v2i16]>;
2275def VOP_V2I16_F32_F32 : VOPProfile <[v2i16, f32, f32, untyped]>;
2276def VOP_V2I16_I32_I32 : VOPProfile <[v2i16, i32, i32, untyped]>;
2277
2278def VOP_F32_V2F16_V2F16_V2F16 : VOPProfile <[f32, v2f16, v2f16, v2f16]>;
2279
2280def VOP_NONE : VOPProfile <[untyped, untyped, untyped, untyped]>;
2281
2282def VOP_F32_F32 : VOPProfile <[f32, f32, untyped, untyped]>;
2283def VOP_F32_F64 : VOPProfile <[f32, f64, untyped, untyped]>;
2284def VOP_F32_I32 : VOPProfile <[f32, i32, untyped, untyped]>;
2285def VOP_F64_F32 : VOPProfile <[f64, f32, untyped, untyped]>;
2286def VOP_F64_F64 : VOPProfile <[f64, f64, untyped, untyped]>;
2287def VOP_F64_I32 : VOPProfile <[f64, i32, untyped, untyped]>;
2288def VOP_I32_F32 : VOPProfile <[i32, f32, untyped, untyped]>;
2289def VOP_I32_F64 : VOPProfile <[i32, f64, untyped, untyped]>;
2290def VOP_I32_I32 : VOPProfile <[i32, i32, untyped, untyped]>;
2291def VOP_F16_F32 : VOPProfile <[f16, f32, untyped, untyped]>;
2292def VOP_F32_F16 : VOPProfile <[f32, f16, untyped, untyped]>;
2293
2294def VOP_F32_F32_F16 : VOPProfile <[f32, f32, f16, untyped]>;
2295def VOP_F32_F32_F32 : VOPProfile <[f32, f32, f32, untyped]>;
2296def VOP_F32_F32_I32 : VOPProfile <[f32, f32, i32, untyped]>;
2297def VOP_F64_F64_F64 : VOPProfile <[f64, f64, f64, untyped]>;
2298def VOP_F64_F64_I32 : VOPProfile <[f64, f64, i32, untyped]>;
2299def VOP_I32_F32_F32 : VOPProfile <[i32, f32, f32, untyped]>;
2300def VOP_I32_F32_I32 : VOPProfile <[i32, f32, i32, untyped]>;
2301def VOP_I32_I32_I32 : VOPProfile <[i32, i32, i32, untyped]>;
2302def VOP_I32_I32_I32_ARITH : VOPProfile <[i32, i32, i32, untyped], 0, /*EnableClamp=*/1>;
2303def VOP_V2F16_F32_F32 : VOPProfile <[v2f16, f32, f32, untyped]>;
2304def VOP_F32_F16_F16_F16 : VOPProfile <[f32, f16, f16, f16]>;
2305
2306def VOP_I64_I64_I32 : VOPProfile <[i64, i64, i32, untyped]>;
2307def VOP_I64_I32_I64 : VOPProfile <[i64, i32, i64, untyped]>;
2308def VOP_I64_I64_I64 : VOPProfile <[i64, i64, i64, untyped]>;
2309
2310def VOP_F16_F32_F16_F32 : VOPProfile <[f16, f32, f16, f32]>;
2311def VOP_F32_F32_F16_F16 : VOPProfile <[f32, f32, f16, f16]>;
2312def VOP_F32_F32_F32_F32 : VOPProfile <[f32, f32, f32, f32]>;
2313def VOP_F64_F64_F64_F64 : VOPProfile <[f64, f64, f64, f64]>;
2314def VOP_I32_I32_I32_I32 : VOPProfile <[i32, i32, i32, i32]>;
2315def VOP_I64_I32_I32_I64 : VOPProfile <[i64, i32, i32, i64]>;
2316def VOP_I32_F32_I32_I32 : VOPProfile <[i32, f32, i32, i32]>;
2317def VOP_I64_I64_I32_I64 : VOPProfile <[i64, i64, i32, i64]>;
2318def VOP_V4I32_I64_I32_V4I32 : VOPProfile <[v4i32, i64, i32, v4i32]>;
2319
2320def VOP_F32_V2F16_V2F16_F32 : VOPProfile <[f32, v2f16, v2f16, f32]>;
2321def VOP_I32_V2I16_V2I16_I32 : VOPProfile <[i32, v2i16, v2i16, i32]>;
2322
2323def VOP_V4F32_F32_F32_V4F32       : VOPProfile <[v4f32,  f32,   f32,   v4f32]>;
2324def VOP_V16F32_F32_F32_V16F32     : VOPProfile <[v16f32, f32,   f32,   v16f32]>;
2325def VOP_V32F32_F32_F32_V32F32     : VOPProfile <[v32f32, f32,   f32,   v32f32]>;
2326def VOP_V4F32_V4F16_V4F16_V4F32   : VOPProfile <[v4f32,  v4f16, v4f16, v4f32]>;
2327def VOP_V16F32_V4F16_V4F16_V16F32 : VOPProfile <[v16f32, v4f16, v4f16, v16f32]>;
2328def VOP_V32F32_V4F16_V4F16_V32F32 : VOPProfile <[v32f32, v4f16, v4f16, v32f32]>;
2329def VOP_V4F32_V2I16_V2I16_V4F32   : VOPProfile <[v4f32,  v2i16, v2i16, v4f32]>;
2330def VOP_V16F32_V2I16_V2I16_V16F32 : VOPProfile <[v16f32, v2i16, v2i16, v16f32]>;
2331def VOP_V32F32_V2I16_V2I16_V32F32 : VOPProfile <[v32f32, v2i16, v2i16, v32f32]>;
2332def VOP_V4I32_I32_I32_V4I32       : VOPProfile <[v4i32,  i32,   i32,   v4i32]>;
2333def VOP_V16I32_I32_I32_V16I32     : VOPProfile <[v16i32, i32,   i32,   v16i32]>;
2334def VOP_V32I32_I32_I32_V32I32     : VOPProfile <[v32i32, i32,   i32,   v32i32]>;
2335
2336class Commutable_REV <string revOp, bit isOrig> {
2337  string RevOp = revOp;
2338  bit IsOrig = isOrig;
2339}
2340
2341class AtomicNoRet <string noRetOp, bit isRet> {
2342  string NoRetOp = noRetOp;
2343  bit IsRet = isRet;
2344}
2345
2346//===----------------------------------------------------------------------===//
2347// Interpolation opcodes
2348//===----------------------------------------------------------------------===//
2349
2350class VINTRPDstOperand <RegisterClass rc> : RegisterOperand <rc, "printVINTRPDst">;
2351
2352class VINTRP_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
2353  VINTRPCommon <outs, ins, "", pattern>,
2354  SIMCInstr<opName, SIEncodingFamily.NONE> {
2355  let isPseudo = 1;
2356  let isCodeGenOnly = 1;
2357}
2358
2359// FIXME-GFX10: WIP.
2360class VINTRP_Real_si <bits <2> op, string opName, dag outs, dag ins,
2361                      string asm, int encodingFamily> :
2362  VINTRPCommon <outs, ins, asm, []>,
2363  VINTRPe <op>,
2364  SIMCInstr<opName, encodingFamily> {
2365  let DisableDecoder = DisableSIDecoder;
2366}
2367
2368class VINTRP_Real_vi <bits <2> op, string opName, dag outs, dag ins,
2369                      string asm> :
2370  VINTRPCommon <outs, ins, asm, []>,
2371  VINTRPe_vi <op>,
2372  SIMCInstr<opName, SIEncodingFamily.VI> {
2373  let AssemblerPredicate = VIAssemblerPredicate;
2374  let DecoderNamespace = "GFX8";
2375  let DisableDecoder = DisableVIDecoder;
2376}
2377
2378// FIXME-GFX10: WIP.
2379multiclass VINTRP_m <bits <2> op, dag outs, dag ins, string asm,
2380                     list<dag> pattern = []> {
2381  def "" : VINTRP_Pseudo <NAME, outs, ins, pattern>;
2382
2383  let AssemblerPredicate = isGFX6GFX7, DecoderNamespace = "GFX6GFX7" in {
2384    def _si : VINTRP_Real_si <op, NAME, outs, ins, asm, SIEncodingFamily.SI>;
2385  } // End AssemblerPredicate = isGFX6GFX7, DecoderNamespace = "GFX6GFX7"
2386
2387  def _vi : VINTRP_Real_vi <op, NAME, outs, ins, asm>;
2388
2389  let AssemblerPredicate = isGFX10Plus, DecoderNamespace = "GFX10" in {
2390    def _gfx10 : VINTRP_Real_si<op, NAME, outs, ins, asm, SIEncodingFamily.GFX10>;
2391  } // End AssemblerPredicate = isGFX10Plus, DecoderNamespace = "GFX10"
2392}
2393//===----------------------------------------------------------------------===//
2394// Vector instruction mappings
2395//===----------------------------------------------------------------------===//
2396
2397// Maps an opcode in e32 form to its e64 equivalent
2398def getVOPe64 : InstrMapping {
2399  let FilterClass = "VOP";
2400  let RowFields = ["OpName"];
2401  let ColFields = ["Size", "VOP3"];
2402  let KeyCol = ["4", "0"];
2403  let ValueCols = [["8", "1"]];
2404}
2405
2406// Maps an opcode in e64 form to its e32 equivalent
2407def getVOPe32 : InstrMapping {
2408  let FilterClass = "VOP";
2409  let RowFields = ["OpName"];
2410  let ColFields = ["Size", "VOP3"];
2411  let KeyCol = ["8", "1"];
2412  let ValueCols = [["4", "0"]];
2413}
2414
2415// Maps ordinary instructions to their SDWA counterparts
2416def getSDWAOp : InstrMapping {
2417  let FilterClass = "VOP";
2418  let RowFields = ["OpName"];
2419  let ColFields = ["AsmVariantName"];
2420  let KeyCol = ["Default"];
2421  let ValueCols = [["SDWA"]];
2422}
2423
2424// Maps SDWA instructions to their ordinary counterparts
2425def getBasicFromSDWAOp : InstrMapping {
2426  let FilterClass = "VOP";
2427  let RowFields = ["OpName"];
2428  let ColFields = ["AsmVariantName"];
2429  let KeyCol = ["SDWA"];
2430  let ValueCols = [["Default"]];
2431}
2432
2433// Maps ordinary instructions to their DPP counterparts
2434def getDPPOp32 : InstrMapping {
2435  let FilterClass = "VOP";
2436  let RowFields = ["OpName"];
2437  let ColFields = ["AsmVariantName"];
2438  let KeyCol = ["Default"];
2439  let ValueCols = [["DPP"]];
2440}
2441
2442// Maps an commuted opcode to its original version
2443def getCommuteOrig : InstrMapping {
2444  let FilterClass = "Commutable_REV";
2445  let RowFields = ["RevOp"];
2446  let ColFields = ["IsOrig"];
2447  let KeyCol = ["0"];
2448  let ValueCols = [["1"]];
2449}
2450
2451// Maps an original opcode to its commuted version
2452def getCommuteRev : InstrMapping {
2453  let FilterClass = "Commutable_REV";
2454  let RowFields = ["RevOp"];
2455  let ColFields = ["IsOrig"];
2456  let KeyCol = ["1"];
2457  let ValueCols = [["0"]];
2458}
2459
2460def getMCOpcodeGen : InstrMapping {
2461  let FilterClass = "SIMCInstr";
2462  let RowFields = ["PseudoInstr"];
2463  let ColFields = ["Subtarget"];
2464  let KeyCol = [!cast<string>(SIEncodingFamily.NONE)];
2465  let ValueCols = [[!cast<string>(SIEncodingFamily.SI)],
2466                   [!cast<string>(SIEncodingFamily.VI)],
2467                   [!cast<string>(SIEncodingFamily.SDWA)],
2468                   [!cast<string>(SIEncodingFamily.SDWA9)],
2469                   // GFX80 encoding is added to work around a multiple matching
2470                   // issue for buffer instructions with unpacked d16 data. This
2471                   // does not actually change the encoding, and thus may be
2472                   // removed later.
2473                   [!cast<string>(SIEncodingFamily.GFX80)],
2474                   [!cast<string>(SIEncodingFamily.GFX9)],
2475                   [!cast<string>(SIEncodingFamily.GFX10)],
2476                   [!cast<string>(SIEncodingFamily.SDWA10)]];
2477}
2478
2479// Get equivalent SOPK instruction.
2480def getSOPKOp : InstrMapping {
2481  let FilterClass = "SOPKInstTable";
2482  let RowFields = ["BaseCmpOp"];
2483  let ColFields = ["IsSOPK"];
2484  let KeyCol = ["0"];
2485  let ValueCols = [["1"]];
2486}
2487
2488def getAddr64Inst : InstrMapping {
2489  let FilterClass = "MUBUFAddr64Table";
2490  let RowFields = ["OpName"];
2491  let ColFields = ["IsAddr64"];
2492  let KeyCol = ["0"];
2493  let ValueCols = [["1"]];
2494}
2495
2496def getIfAddr64Inst : InstrMapping {
2497  let FilterClass = "MUBUFAddr64Table";
2498  let RowFields = ["OpName"];
2499  let ColFields = ["IsAddr64"];
2500  let KeyCol = ["1"];
2501  let ValueCols = [["1"]];
2502}
2503
2504def getMUBUFNoLdsInst : InstrMapping {
2505  let FilterClass = "MUBUFLdsTable";
2506  let RowFields = ["OpName"];
2507  let ColFields = ["IsLds"];
2508  let KeyCol = ["1"];
2509  let ValueCols = [["0"]];
2510}
2511
2512// Maps an atomic opcode to its version with a return value.
2513def getAtomicRetOp : InstrMapping {
2514  let FilterClass = "AtomicNoRet";
2515  let RowFields = ["NoRetOp"];
2516  let ColFields = ["IsRet"];
2517  let KeyCol = ["0"];
2518  let ValueCols = [["1"]];
2519}
2520
2521// Maps an atomic opcode to its returnless version.
2522def getAtomicNoRetOp : InstrMapping {
2523  let FilterClass = "AtomicNoRet";
2524  let RowFields = ["NoRetOp"];
2525  let ColFields = ["IsRet"];
2526  let KeyCol = ["1"];
2527  let ValueCols = [["0"]];
2528}
2529
2530// Maps a GLOBAL to its SADDR form.
2531def getGlobalSaddrOp : InstrMapping {
2532  let FilterClass = "GlobalSaddrTable";
2533  let RowFields = ["SaddrOp"];
2534  let ColFields = ["IsSaddr"];
2535  let KeyCol = ["0"];
2536  let ValueCols = [["1"]];
2537}
2538
2539// Maps a v_cmpx opcode with sdst to opcode without sdst.
2540def getVCMPXNoSDstOp : InstrMapping {
2541  let FilterClass = "VCMPXNoSDstTable";
2542  let RowFields = ["NoSDstOp"];
2543  let ColFields = ["HasSDst"];
2544  let KeyCol = ["1"];
2545  let ValueCols = [["0"]];
2546}
2547
2548// Maps a SOPP to a SOPP with S_NOP
2549def getSOPPWithRelaxation : InstrMapping {
2550  let FilterClass = "Base_SOPP";
2551  let RowFields = ["AsmString"];
2552  let ColFields = ["Size"];
2553  let KeyCol = ["4"];
2554  let ValueCols = [["8"]];
2555}
2556
2557include "SIInstructions.td"
2558
2559include "DSInstructions.td"
2560include "MIMGInstructions.td"
2561