1//===-- SIInstrInfo.td - SI Instruction Infos -------------*- tablegen -*--===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9def isWave32 : Predicate<"Subtarget->getWavefrontSize() == 32">,
10  AssemblerPredicate <(all_of FeatureWavefrontSize32)>;
11def isWave64 : Predicate<"Subtarget->getWavefrontSize() == 64">,
12  AssemblerPredicate <(all_of FeatureWavefrontSize64)>;
13
14class GCNPredicateControl : PredicateControl {
15  Predicate SIAssemblerPredicate = isGFX6GFX7;
16  Predicate VIAssemblerPredicate = isGFX8GFX9;
17}
18
19// Except for the NONE field, this must be kept in sync with the
20// SIEncodingFamily enum in AMDGPUInstrInfo.cpp
21def SIEncodingFamily {
22  int NONE = -1;
23  int SI = 0;
24  int VI = 1;
25  int SDWA = 2;
26  int SDWA9 = 3;
27  int GFX80 = 4;
28  int GFX9 = 5;
29  int GFX10 = 6;
30  int SDWA10 = 7;
31  int GFX90A = 8;
32  int GFX940 = 9;
33}
34
35//===----------------------------------------------------------------------===//
36// SI DAG Nodes
37//===----------------------------------------------------------------------===//
38
39def AMDGPUclamp : SDNode<"AMDGPUISD::CLAMP", SDTFPUnaryOp>;
40
41def SIsbuffer_load : SDNode<"AMDGPUISD::SBUFFER_LOAD",
42  SDTypeProfile<1, 3, [SDTCisVT<1, v4i32>, SDTCisVT<2, i32>, SDTCisVT<3, i32>]>,
43  [SDNPMayLoad, SDNPMemOperand]
44>;
45
46def SIds_ordered_count : SDNode<"AMDGPUISD::DS_ORDERED_COUNT",
47  SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisVT<1, i32>, SDTCisVT<2, i16>]>,
48  [SDNPMayLoad, SDNPMayStore, SDNPMemOperand, SDNPHasChain, SDNPInGlue]
49>;
50
51def SIatomic_inc : SDNode<"AMDGPUISD::ATOMIC_INC", SDTAtomic2,
52  [SDNPMayLoad, SDNPMayStore, SDNPMemOperand, SDNPHasChain]
53>;
54
55def SIatomic_dec : SDNode<"AMDGPUISD::ATOMIC_DEC", SDTAtomic2,
56  [SDNPMayLoad, SDNPMayStore, SDNPMemOperand, SDNPHasChain]
57>;
58
59def SDTAtomic2_f32 : SDTypeProfile<1, 2, [
60  SDTCisSameAs<0,2>, SDTCisFP<0>, SDTCisPtrTy<1>
61]>;
62
63def SIatomic_fmin : SDNode<"AMDGPUISD::ATOMIC_LOAD_FMIN", SDTAtomic2_f32,
64  [SDNPMayLoad, SDNPMayStore, SDNPMemOperand, SDNPHasChain]
65>;
66
67def SIatomic_fmax : SDNode<"AMDGPUISD::ATOMIC_LOAD_FMAX", SDTAtomic2_f32,
68  [SDNPMayLoad, SDNPMayStore, SDNPMemOperand, SDNPHasChain]
69>;
70
71// load_d16_{lo|hi} ptr, tied_input
72def SIload_d16 : SDTypeProfile<1, 2, [
73  SDTCisPtrTy<1>,
74  SDTCisSameAs<0, 2>
75]>;
76
77
78def SDTtbuffer_load : SDTypeProfile<1, 8,
79  [                     // vdata
80   SDTCisVT<1, v4i32>,  // rsrc
81   SDTCisVT<2, i32>,    // vindex(VGPR)
82   SDTCisVT<3, i32>,    // voffset(VGPR)
83   SDTCisVT<4, i32>,    // soffset(SGPR)
84   SDTCisVT<5, i32>,    // offset(imm)
85   SDTCisVT<6, i32>,    // format(imm)
86   SDTCisVT<7, i32>,    // cachepolicy, swizzled buffer(imm)
87   SDTCisVT<8, i1>      // idxen(imm)
88  ]>;
89
90def SItbuffer_load :   SDNode<"AMDGPUISD::TBUFFER_LOAD_FORMAT", SDTtbuffer_load,
91                              [SDNPMayLoad, SDNPMemOperand, SDNPHasChain]>;
92def SItbuffer_load_d16 : SDNode<"AMDGPUISD::TBUFFER_LOAD_FORMAT_D16",
93                                SDTtbuffer_load,
94                                [SDNPMayLoad, SDNPMemOperand, SDNPHasChain]>;
95
96def SDTtbuffer_store : SDTypeProfile<0, 9,
97    [                     // vdata
98     SDTCisVT<1, v4i32>,  // rsrc
99     SDTCisVT<2, i32>,    // vindex(VGPR)
100     SDTCisVT<3, i32>,    // voffset(VGPR)
101     SDTCisVT<4, i32>,    // soffset(SGPR)
102     SDTCisVT<5, i32>,    // offset(imm)
103     SDTCisVT<6, i32>,    // format(imm)
104     SDTCisVT<7, i32>,    // cachepolicy, swizzled buffer(imm)
105     SDTCisVT<8, i1>      // idxen(imm)
106    ]>;
107
108def SItbuffer_store : SDNode<"AMDGPUISD::TBUFFER_STORE_FORMAT", SDTtbuffer_store,
109                             [SDNPMayStore, SDNPMemOperand, SDNPHasChain]>;
110def SItbuffer_store_d16 : SDNode<"AMDGPUISD::TBUFFER_STORE_FORMAT_D16",
111                                SDTtbuffer_store,
112                                [SDNPMayStore, SDNPMemOperand, SDNPHasChain]>;
113
114def SDTBufferLoad : SDTypeProfile<1, 7,
115    [                    // vdata
116     SDTCisVT<1, v4i32>, // rsrc
117     SDTCisVT<2, i32>,   // vindex(VGPR)
118     SDTCisVT<3, i32>,   // voffset(VGPR)
119     SDTCisVT<4, i32>,   // soffset(SGPR)
120     SDTCisVT<5, i32>,   // offset(imm)
121     SDTCisVT<6, i32>,   // cachepolicy, swizzled buffer(imm)
122     SDTCisVT<7, i1>]>;  // idxen(imm)
123
124def SIbuffer_load : SDNode <"AMDGPUISD::BUFFER_LOAD", SDTBufferLoad,
125                            [SDNPMemOperand, SDNPHasChain, SDNPMayLoad]>;
126def SIbuffer_load_ubyte : SDNode <"AMDGPUISD::BUFFER_LOAD_UBYTE", SDTBufferLoad,
127                            [SDNPMemOperand, SDNPHasChain, SDNPMayLoad]>;
128def SIbuffer_load_ushort : SDNode <"AMDGPUISD::BUFFER_LOAD_USHORT", SDTBufferLoad,
129                            [SDNPMemOperand, SDNPHasChain, SDNPMayLoad]>;
130def SIbuffer_load_byte : SDNode <"AMDGPUISD::BUFFER_LOAD_BYTE", SDTBufferLoad,
131                            [SDNPMemOperand, SDNPHasChain, SDNPMayLoad]>;
132def SIbuffer_load_short: SDNode <"AMDGPUISD::BUFFER_LOAD_SHORT", SDTBufferLoad,
133                            [SDNPMemOperand, SDNPHasChain, SDNPMayLoad]>;
134def SIbuffer_load_format : SDNode <"AMDGPUISD::BUFFER_LOAD_FORMAT", SDTBufferLoad,
135                            [SDNPMemOperand, SDNPHasChain, SDNPMayLoad]>;
136def SIbuffer_load_format_d16 : SDNode <"AMDGPUISD::BUFFER_LOAD_FORMAT_D16",
137                                SDTBufferLoad,
138                                [SDNPMemOperand, SDNPHasChain, SDNPMayLoad]>;
139
140def SDTBufferStore : SDTypeProfile<0, 8,
141    [                    // vdata
142     SDTCisVT<1, v4i32>, // rsrc
143     SDTCisVT<2, i32>,   // vindex(VGPR)
144     SDTCisVT<3, i32>,   // voffset(VGPR)
145     SDTCisVT<4, i32>,   // soffset(SGPR)
146     SDTCisVT<5, i32>,   // offset(imm)
147     SDTCisVT<6, i32>,   // cachepolicy, swizzled buffer(imm)
148     SDTCisVT<7, i1>]>;  // idxen(imm)
149
150def SIbuffer_store : SDNode <"AMDGPUISD::BUFFER_STORE", SDTBufferStore,
151                             [SDNPMayStore, SDNPMemOperand, SDNPHasChain]>;
152def SIbuffer_store_byte: SDNode <"AMDGPUISD::BUFFER_STORE_BYTE",
153                         SDTBufferStore,
154                         [SDNPMayStore, SDNPMemOperand, SDNPHasChain]>;
155def SIbuffer_store_short : SDNode <"AMDGPUISD::BUFFER_STORE_SHORT",
156                           SDTBufferStore,
157                           [SDNPMayStore, SDNPMemOperand, SDNPHasChain]>;
158def SIbuffer_store_format : SDNode <"AMDGPUISD::BUFFER_STORE_FORMAT",
159                            SDTBufferStore,
160                            [SDNPMayStore, SDNPMemOperand, SDNPHasChain]>;
161def SIbuffer_store_format_d16 : SDNode <"AMDGPUISD::BUFFER_STORE_FORMAT_D16",
162                            SDTBufferStore,
163                            [SDNPMayStore, SDNPMemOperand, SDNPHasChain]>;
164
165class SDBufferAtomic<string opcode> : SDNode <opcode,
166  SDTypeProfile<1, 8,
167       [SDTCisVT<2, v4i32>, // rsrc
168       SDTCisVT<3, i32>,   // vindex(VGPR)
169       SDTCisVT<4, i32>,   // voffset(VGPR)
170       SDTCisVT<5, i32>,   // soffset(SGPR)
171       SDTCisVT<6, i32>,   // offset(imm)
172       SDTCisVT<7, i32>,   // cachepolicy(imm)
173       SDTCisVT<8, i1>]>,  // idxen(imm)
174  [SDNPMemOperand, SDNPHasChain, SDNPMayLoad, SDNPMayStore]
175>;
176
177def SIbuffer_atomic_swap : SDBufferAtomic <"AMDGPUISD::BUFFER_ATOMIC_SWAP">;
178def SIbuffer_atomic_add : SDBufferAtomic <"AMDGPUISD::BUFFER_ATOMIC_ADD">;
179def SIbuffer_atomic_sub : SDBufferAtomic <"AMDGPUISD::BUFFER_ATOMIC_SUB">;
180def SIbuffer_atomic_smin : SDBufferAtomic <"AMDGPUISD::BUFFER_ATOMIC_SMIN">;
181def SIbuffer_atomic_umin : SDBufferAtomic <"AMDGPUISD::BUFFER_ATOMIC_UMIN">;
182def SIbuffer_atomic_smax : SDBufferAtomic <"AMDGPUISD::BUFFER_ATOMIC_SMAX">;
183def SIbuffer_atomic_umax : SDBufferAtomic <"AMDGPUISD::BUFFER_ATOMIC_UMAX">;
184def SIbuffer_atomic_and : SDBufferAtomic <"AMDGPUISD::BUFFER_ATOMIC_AND">;
185def SIbuffer_atomic_or : SDBufferAtomic <"AMDGPUISD::BUFFER_ATOMIC_OR">;
186def SIbuffer_atomic_xor : SDBufferAtomic <"AMDGPUISD::BUFFER_ATOMIC_XOR">;
187def SIbuffer_atomic_inc : SDBufferAtomic <"AMDGPUISD::BUFFER_ATOMIC_INC">;
188def SIbuffer_atomic_dec : SDBufferAtomic <"AMDGPUISD::BUFFER_ATOMIC_DEC">;
189def SIbuffer_atomic_csub : SDBufferAtomic <"AMDGPUISD::BUFFER_ATOMIC_CSUB">;
190def SIbuffer_atomic_fadd : SDBufferAtomic <"AMDGPUISD::BUFFER_ATOMIC_FADD">;
191def SIbuffer_atomic_fmin : SDBufferAtomic <"AMDGPUISD::BUFFER_ATOMIC_FMIN">;
192def SIbuffer_atomic_fmax : SDBufferAtomic <"AMDGPUISD::BUFFER_ATOMIC_FMAX">;
193
194multiclass SDBufferAtomicRetNoRet {
195  def "_ret" : PatFrag<
196    (ops node:$vdata_in, node:$rsrc, node:$vindex, node:$voffset, node:$soffset,
197      node:$offset, node:$cachepolicy, node:$idxen),
198    (!cast<SDNode>(NAME) node:$vdata_in, node:$rsrc, node:$vindex,
199      node:$voffset, node:$soffset, node:$offset, node:$cachepolicy,
200      node:$idxen)> {
201    let PredicateCode = [{ return !(SDValue(N, 0).use_empty()); }];
202    let GISelPredicateCode = [{ return true; }];
203  }
204
205  def "_noret" : PatFrag<
206    (ops node:$vdata_in, node:$rsrc, node:$vindex, node:$voffset, node:$soffset,
207      node:$offset, node:$cachepolicy, node:$idxen),
208    (!cast<SDNode>(NAME) node:$vdata_in, node:$rsrc, node:$vindex,
209      node:$voffset, node:$soffset, node:$offset, node:$cachepolicy,
210      node:$idxen)> {
211    let PredicateCode = [{ return SDValue(N, 0).use_empty(); }];
212    let GISelPredicateCode = [{ return false; }];
213  }
214}
215
216defm SIbuffer_atomic_swap : SDBufferAtomicRetNoRet;
217defm SIbuffer_atomic_add : SDBufferAtomicRetNoRet;
218defm SIbuffer_atomic_sub : SDBufferAtomicRetNoRet;
219defm SIbuffer_atomic_smin : SDBufferAtomicRetNoRet;
220defm SIbuffer_atomic_umin : SDBufferAtomicRetNoRet;
221defm SIbuffer_atomic_smax : SDBufferAtomicRetNoRet;
222defm SIbuffer_atomic_umax : SDBufferAtomicRetNoRet;
223defm SIbuffer_atomic_and : SDBufferAtomicRetNoRet;
224defm SIbuffer_atomic_or : SDBufferAtomicRetNoRet;
225defm SIbuffer_atomic_xor : SDBufferAtomicRetNoRet;
226defm SIbuffer_atomic_inc : SDBufferAtomicRetNoRet;
227defm SIbuffer_atomic_dec : SDBufferAtomicRetNoRet;
228defm SIbuffer_atomic_fadd : SDBufferAtomicRetNoRet;
229defm SIbuffer_atomic_fmin : SDBufferAtomicRetNoRet;
230defm SIbuffer_atomic_fmax : SDBufferAtomicRetNoRet;
231
232def SIbuffer_atomic_cmpswap : SDNode <"AMDGPUISD::BUFFER_ATOMIC_CMPSWAP",
233  SDTypeProfile<1, 9,
234    [SDTCisVT<0, i32>,   // dst
235     SDTCisVT<1, i32>,   // src
236     SDTCisVT<2, i32>,   // cmp
237     SDTCisVT<3, v4i32>, // rsrc
238     SDTCisVT<4, i32>,   // vindex(VGPR)
239     SDTCisVT<5, i32>,   // voffset(VGPR)
240     SDTCisVT<6, i32>,   // soffset(SGPR)
241     SDTCisVT<7, i32>,   // offset(imm)
242     SDTCisVT<8, i32>,   // cachepolicy(imm)
243     SDTCisVT<9, i1>]>,  // idxen(imm)
244  [SDNPMemOperand, SDNPHasChain, SDNPMayLoad, SDNPMayStore]
245>;
246
247def SIbuffer_atomic_cmpswap_ret : PatFrag<
248  (ops node:$src, node:$cmp, node:$rsrc, node:$vindex, node:$voffset,
249    node:$soffset, node:$offset, node:$cachepolicy, node:$idxen),
250  (SIbuffer_atomic_cmpswap node:$src, node:$cmp, node:$rsrc, node:$vindex,
251    node:$voffset, node:$soffset, node:$offset, node:$cachepolicy,
252    node:$idxen)> {
253  let PredicateCode = [{ return !(SDValue(N, 0).use_empty()); }];
254  let GISelPredicateCode = [{ return true; }];
255}
256
257def SIbuffer_atomic_cmpswap_noret : PatFrag<
258  (ops node:$src, node:$cmp, node:$rsrc, node:$vindex, node:$voffset,
259    node:$soffset, node:$offset, node:$cachepolicy, node:$idxen),
260  (SIbuffer_atomic_cmpswap node:$src, node:$cmp, node:$rsrc, node:$vindex,
261    node:$voffset, node:$soffset, node:$offset, node:$cachepolicy,
262    node:$idxen)> {
263  let PredicateCode = [{ return SDValue(N, 0).use_empty(); }];
264  let GISelPredicateCode = [{ return false; }];
265}
266
267class SDGlobalAtomicNoRtn<string opcode, ValueType ty> : SDNode <opcode,
268  SDTypeProfile<0, 2,
269      [SDTCisPtrTy<0>,     // vaddr
270       SDTCisVT<1, ty>]>,  // vdata
271  [SDNPMemOperand, SDNPHasChain, SDNPMayLoad, SDNPMayStore]
272>;
273
274def SIpc_add_rel_offset : SDNode<"AMDGPUISD::PC_ADD_REL_OFFSET",
275  SDTypeProfile<1, 2, [SDTCisVT<0, iPTR>, SDTCisSameAs<0,1>, SDTCisSameAs<0,2>]>
276>;
277
278def SIlds : SDNode<"AMDGPUISD::LDS",
279  SDTypeProfile<1, 1, [SDTCisVT<0, iPTR>, SDTCisSameAs<0,1>]>
280>;
281
282def SIload_d16_lo : SDNode<"AMDGPUISD::LOAD_D16_LO",
283  SIload_d16,
284  [SDNPMayLoad, SDNPMemOperand, SDNPHasChain]
285>;
286
287def SIload_d16_lo_u8 : SDNode<"AMDGPUISD::LOAD_D16_LO_U8",
288  SIload_d16,
289  [SDNPMayLoad, SDNPMemOperand, SDNPHasChain]
290>;
291
292def SIload_d16_lo_i8 : SDNode<"AMDGPUISD::LOAD_D16_LO_I8",
293  SIload_d16,
294  [SDNPMayLoad, SDNPMemOperand, SDNPHasChain]
295>;
296
297def SIload_d16_hi : SDNode<"AMDGPUISD::LOAD_D16_HI",
298  SIload_d16,
299  [SDNPMayLoad, SDNPMemOperand, SDNPHasChain]
300>;
301
302def SIload_d16_hi_u8 : SDNode<"AMDGPUISD::LOAD_D16_HI_U8",
303  SIload_d16,
304  [SDNPMayLoad, SDNPMemOperand, SDNPHasChain]
305>;
306
307def SIload_d16_hi_i8 : SDNode<"AMDGPUISD::LOAD_D16_HI_I8",
308  SIload_d16,
309  [SDNPMayLoad, SDNPMemOperand, SDNPHasChain]
310>;
311
312def SIdenorm_mode : SDNode<"AMDGPUISD::DENORM_MODE",
313  SDTypeProfile<0 ,1, [SDTCisInt<0>]>,
314  [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]
315>;
316
317def SIfptrunc_round_upward : SDNode<"AMDGPUISD::FPTRUNC_ROUND_UPWARD",
318  SDTFPRoundOp
319>;
320
321def SIfptrunc_round_downward : SDNode<"AMDGPUISD::FPTRUNC_ROUND_DOWNWARD",
322  SDTFPRoundOp
323>;
324
325//===----------------------------------------------------------------------===//
326// ValueType helpers
327//===----------------------------------------------------------------------===//
328
329// Returns 1 if the source arguments have modifiers, 0 if they do not.
330// XXX - do f16 instructions?
331class isFloatType<ValueType SrcVT> {
332  bit ret = !or(!eq(SrcVT.Value, f16.Value),
333                !eq(SrcVT.Value, f32.Value),
334                !eq(SrcVT.Value, f64.Value),
335                !eq(SrcVT.Value, v2f16.Value),
336                !eq(SrcVT.Value, v4f16.Value),
337                !eq(SrcVT.Value, v2f32.Value),
338                !eq(SrcVT.Value, v2f64.Value),
339                !eq(SrcVT.Value, v4f64.Value));
340}
341
342class isIntType<ValueType SrcVT> {
343  bit ret = !or(!eq(SrcVT.Value, i16.Value),
344                !eq(SrcVT.Value, i32.Value),
345                !eq(SrcVT.Value, i64.Value),
346                !eq(SrcVT.Value, v2i32.Value));
347}
348
349class isPackedType<ValueType SrcVT> {
350  bit ret = !or(!eq(SrcVT.Value, v2i16.Value),
351                !eq(SrcVT.Value, v2f16.Value),
352                !eq(SrcVT.Value, v4f16.Value),
353                !eq(SrcVT.Value, v2f32.Value));
354}
355
356
357//===----------------------------------------------------------------------===//
358// PatFrags for global memory operations
359//===----------------------------------------------------------------------===//
360
361defm atomic_inc : binary_atomic_op_all_as<SIatomic_inc>;
362defm atomic_dec : binary_atomic_op_all_as<SIatomic_dec>;
363defm atomic_load_fmin : binary_atomic_op_all_as<SIatomic_fmin, 0>;
364defm atomic_load_fmax : binary_atomic_op_all_as<SIatomic_fmax, 0>;
365
366//===----------------------------------------------------------------------===//
367// SDNodes PatFrags for loads/stores with a glue input.
368// This is for SDNodes and PatFrag for local loads and stores to
369// enable s_mov_b32 m0, -1 to be glued to the memory instructions.
370//
371// These mirror the regular load/store PatFrags and rely on special
372// processing during Select() to add the glued copy.
373//
374//===----------------------------------------------------------------------===//
375
376def AMDGPUld_glue : SDNode <"ISD::LOAD", SDTLoad,
377  [SDNPHasChain, SDNPMayLoad, SDNPMemOperand, SDNPInGlue]
378>;
379
380def AMDGPUatomic_ld_glue : SDNode <"ISD::ATOMIC_LOAD", SDTAtomicLoad,
381  [SDNPHasChain, SDNPMayLoad, SDNPMemOperand, SDNPInGlue]
382>;
383
384def unindexedload_glue : PatFrag <(ops node:$ptr), (AMDGPUld_glue node:$ptr)> {
385  let IsLoad = 1;
386  let IsUnindexed = 1;
387}
388
389def load_glue : PatFrag <(ops node:$ptr), (unindexedload_glue node:$ptr)> {
390  let IsLoad = 1;
391  let IsNonExtLoad = 1;
392}
393
394def atomic_load_8_glue : PatFrag<(ops node:$ptr),
395  (AMDGPUatomic_ld_glue node:$ptr)> {
396  let IsAtomic = 1;
397  let MemoryVT = i8;
398}
399
400def atomic_load_16_glue : PatFrag<(ops node:$ptr),
401  (AMDGPUatomic_ld_glue node:$ptr)> {
402  let IsAtomic = 1;
403  let MemoryVT = i16;
404}
405
406def atomic_load_32_glue : PatFrag<(ops node:$ptr),
407  (AMDGPUatomic_ld_glue node:$ptr)> {
408  let IsAtomic = 1;
409  let MemoryVT = i32;
410}
411
412def atomic_load_64_glue : PatFrag<(ops node:$ptr),
413  (AMDGPUatomic_ld_glue node:$ptr)> {
414  let IsAtomic = 1;
415  let MemoryVT = i64;
416}
417
418def extload_glue : PatFrag<(ops node:$ptr), (unindexedload_glue node:$ptr)> {
419  let IsLoad = 1;
420  let IsAnyExtLoad = 1;
421}
422
423def sextload_glue : PatFrag<(ops node:$ptr), (unindexedload_glue node:$ptr)> {
424  let IsLoad = 1;
425  let IsSignExtLoad = 1;
426}
427
428def zextload_glue : PatFrag<(ops node:$ptr), (unindexedload_glue node:$ptr)> {
429  let IsLoad = 1;
430  let IsZeroExtLoad = 1;
431}
432
433def extloadi8_glue : PatFrag<(ops node:$ptr), (extload_glue node:$ptr)> {
434  let IsLoad = 1;
435  let MemoryVT = i8;
436}
437
438def zextloadi8_glue : PatFrag<(ops node:$ptr), (zextload_glue node:$ptr)> {
439  let IsLoad = 1;
440  let MemoryVT = i8;
441}
442
443def extloadi16_glue : PatFrag<(ops node:$ptr), (extload_glue node:$ptr)> {
444  let IsLoad = 1;
445  let MemoryVT = i16;
446}
447
448def zextloadi16_glue : PatFrag<(ops node:$ptr), (zextload_glue node:$ptr)> {
449  let IsLoad = 1;
450  let MemoryVT = i16;
451}
452
453def sextloadi8_glue : PatFrag<(ops node:$ptr), (sextload_glue node:$ptr)> {
454  let IsLoad = 1;
455  let MemoryVT = i8;
456}
457
458def sextloadi16_glue : PatFrag<(ops node:$ptr), (sextload_glue node:$ptr)> {
459  let IsLoad = 1;
460  let MemoryVT = i16;
461}
462
463
464let IsLoad = 1, AddressSpaces = LoadAddress_local.AddrSpaces in {
465def load_local_m0 : PatFrag<(ops node:$ptr), (load_glue node:$ptr)> {
466  let IsNonExtLoad = 1;
467}
468
469let MemoryVT = i8 in {
470def extloadi8_local_m0 : PatFrag<(ops node:$ptr), (extloadi8_glue node:$ptr)>;
471def sextloadi8_local_m0 : PatFrag<(ops node:$ptr), (sextloadi8_glue node:$ptr)>;
472def zextloadi8_local_m0 : PatFrag<(ops node:$ptr), (zextloadi8_glue node:$ptr)>;
473}
474
475let MemoryVT = i16 in {
476def extloadi16_local_m0 : PatFrag<(ops node:$ptr), (extloadi16_glue node:$ptr)>;
477def sextloadi16_local_m0 : PatFrag<(ops node:$ptr), (sextloadi16_glue node:$ptr)>;
478def zextloadi16_local_m0 : PatFrag<(ops node:$ptr), (zextloadi16_glue node:$ptr)>;
479}
480
481def load_align8_local_m0 : PatFrag<(ops node:$ptr),
482                                   (load_local_m0 node:$ptr)>, Aligned<8> {
483  let IsLoad = 1;
484  let IsNonExtLoad = 1;
485}
486
487def load_align16_local_m0 : PatFrag<(ops node:$ptr),
488                                   (load_local_m0 node:$ptr)>, Aligned<16> {
489  let IsLoad = 1;
490  let IsNonExtLoad = 1;
491}
492
493} // End IsLoad = 1
494
495let IsAtomic = 1, AddressSpaces = LoadAddress_local.AddrSpaces in {
496def atomic_load_8_local_m0 : PatFrag<(ops node:$ptr),
497                                      (atomic_load_8_glue node:$ptr)> {
498  let MemoryVT = i8;
499}
500def atomic_load_16_local_m0 : PatFrag<(ops node:$ptr),
501                                      (atomic_load_16_glue node:$ptr)> {
502  let MemoryVT = i16;
503}
504def atomic_load_32_local_m0 : PatFrag<(ops node:$ptr),
505                                      (atomic_load_32_glue node:$ptr)> {
506  let MemoryVT = i32;
507}
508def atomic_load_64_local_m0 : PatFrag<(ops node:$ptr),
509                                       (atomic_load_64_glue node:$ptr)> {
510  let MemoryVT = i64;
511}
512
513} // End let AddressSpaces = LoadAddress_local.AddrSpaces
514
515
516def AMDGPUst_glue : SDNode <"ISD::STORE", SDTStore,
517  [SDNPHasChain, SDNPMayStore, SDNPMemOperand, SDNPInGlue]
518>;
519
520def AMDGPUatomic_st_glue : SDNode <"ISD::ATOMIC_STORE", SDTAtomicStore,
521  [SDNPHasChain, SDNPMayStore, SDNPMemOperand, SDNPInGlue]
522>;
523
524def unindexedstore_glue : PatFrag<(ops node:$val, node:$ptr),
525                                   (AMDGPUst_glue node:$val, node:$ptr)> {
526  let IsStore = 1;
527  let IsUnindexed = 1;
528}
529
530def store_glue : PatFrag<(ops node:$val, node:$ptr),
531                         (unindexedstore_glue node:$val, node:$ptr)> {
532  let IsStore = 1;
533  let IsTruncStore = 0;
534}
535
536def truncstore_glue : PatFrag<(ops node:$val, node:$ptr),
537  (unindexedstore_glue node:$val, node:$ptr)> {
538  let IsStore = 1;
539  let IsTruncStore = 1;
540}
541
542def truncstorei8_glue : PatFrag<(ops node:$val, node:$ptr),
543                           (truncstore_glue node:$val, node:$ptr)> {
544  let IsStore = 1;
545  let MemoryVT = i8;
546}
547
548def truncstorei16_glue : PatFrag<(ops node:$val, node:$ptr),
549                           (truncstore_glue node:$val, node:$ptr)> {
550  let IsStore = 1;
551  let MemoryVT = i16;
552}
553
554let IsStore = 1, AddressSpaces = StoreAddress_local.AddrSpaces in {
555def store_local_m0 : PatFrag<(ops node:$val, node:$ptr),
556                             (store_glue node:$val, node:$ptr)> {
557  let IsStore = 1;
558  let IsTruncStore = 0;
559}
560
561def truncstorei8_local_m0 : PatFrag<(ops node:$val, node:$ptr),
562                                    (unindexedstore_glue node:$val, node:$ptr)> {
563  let IsStore = 1;
564  let MemoryVT = i8;
565}
566
567def truncstorei16_local_m0 : PatFrag<(ops node:$val, node:$ptr),
568                                    (unindexedstore_glue node:$val, node:$ptr)> {
569  let IsStore = 1;
570  let MemoryVT = i16;
571}
572}
573
574def store_align8_local_m0 : PatFrag <(ops node:$value, node:$ptr),
575                                     (store_local_m0 node:$value, node:$ptr)>,
576                            Aligned<8> {
577  let IsStore = 1;
578  let IsTruncStore = 0;
579}
580
581def store_align16_local_m0 : PatFrag <(ops node:$value, node:$ptr),
582                                     (store_local_m0 node:$value, node:$ptr)>,
583                            Aligned<16> {
584  let IsStore = 1;
585  let IsTruncStore = 0;
586}
587
588let AddressSpaces = StoreAddress_local.AddrSpaces in {
589
590def atomic_store_local_8_m0 : PatFrag <
591  (ops node:$value, node:$ptr),
592  (AMDGPUatomic_st_glue node:$value, node:$ptr)> {
593  let IsAtomic = 1;
594  let MemoryVT = i8;
595}
596def atomic_store_local_16_m0 : PatFrag <
597  (ops node:$value, node:$ptr),
598  (AMDGPUatomic_st_glue node:$value, node:$ptr)> {
599  let IsAtomic = 1;
600  let MemoryVT = i16;
601}
602def atomic_store_local_32_m0 : PatFrag <
603  (ops node:$value, node:$ptr),
604  (AMDGPUatomic_st_glue node:$value, node:$ptr)> {
605  let IsAtomic = 1;
606  let MemoryVT = i32;
607}
608def atomic_store_local_64_m0 : PatFrag <
609  (ops node:$value, node:$ptr),
610  (AMDGPUatomic_st_glue node:$value, node:$ptr)> {
611  let IsAtomic = 1;
612  let MemoryVT = i64;
613}
614} // End let AddressSpaces = StoreAddress_local.AddrSpaces
615
616
617def si_setcc_uniform : PatFrag <
618  (ops node:$lhs, node:$rhs, node:$cond),
619  (setcc node:$lhs, node:$rhs, node:$cond), [{
620  return !N->isDivergent();
621}]>;
622
623//===----------------------------------------------------------------------===//
624// SDNodes PatFrags for a16 loads and stores with 3 components.
625// v3f16/v3i16 is widened to v4f16/v4i16, so we need to match on the memory
626// load/store size.
627//===----------------------------------------------------------------------===//
628
629class mubuf_intrinsic_load<SDPatternOperator name, ValueType vt> : PatFrag <
630  (ops node:$rsrc, node:$vindex, node:$voffset, node:$soffset, node:$offset,
631            node:$auxiliary, node:$idxen),
632  (name node:$rsrc, node:$vindex, node:$voffset, node:$soffset, node:$offset,
633            node:$auxiliary, node:$idxen)> {
634  let IsLoad = 1;
635  let MemoryVT = vt;
636}
637
638class mubuf_intrinsic_store<SDPatternOperator name, ValueType vt> : PatFrag <
639  (ops node:$vdata, node:$rsrc, node:$vindex, node:$voffset, node:$soffset, node:$offset,
640            node:$auxiliary, node:$idxen),
641  (name node:$vdata, node:$rsrc, node:$vindex, node:$voffset, node:$soffset, node:$offset,
642            node:$auxiliary, node:$idxen)> {
643  let IsStore = 1;
644  let MemoryVT = vt;
645}
646
647class mtbuf_intrinsic_load<SDPatternOperator name, ValueType vt> : PatFrag <
648  (ops node:$rsrc, node:$vindex, node:$voffset, node:$soffset, node:$offset,
649            node:$format, node:$auxiliary, node:$idxen),
650  (name node:$rsrc, node:$vindex, node:$voffset, node:$soffset, node:$offset,
651            node:$format, node:$auxiliary, node:$idxen)> {
652  let IsLoad = 1;
653  let MemoryVT = vt;
654}
655
656class mtbuf_intrinsic_store<SDPatternOperator name, ValueType vt> : PatFrag <
657  (ops node:$vdata, node:$rsrc, node:$vindex, node:$voffset, node:$soffset, node:$offset,
658            node:$format, node:$auxiliary, node:$idxen),
659  (name node:$vdata, node:$rsrc, node:$vindex, node:$voffset, node:$soffset, node:$offset,
660            node:$format, node:$auxiliary, node:$idxen)> {
661  let IsStore = 1;
662  let MemoryVT = vt;
663}
664
665//===----------------------------------------------------------------------===//
666// SDNodes PatFrags for d16 loads
667//===----------------------------------------------------------------------===//
668
669class LoadD16Frag <SDPatternOperator op> : PatFrag<
670  (ops node:$ptr, node:$tied_in),
671  (op node:$ptr, node:$tied_in)> {
672  let IsLoad = 1;
673}
674
675foreach as = [ "global", "flat", "constant", "local", "private", "region" ] in {
676let AddressSpaces = !cast<AddressSpaceList>("LoadAddress_"#as).AddrSpaces in {
677
678def load_d16_hi_#as : LoadD16Frag <SIload_d16_hi>;
679
680def az_extloadi8_d16_hi_#as : LoadD16Frag <SIload_d16_hi_u8> {
681  let MemoryVT = i8;
682}
683
684def sextloadi8_d16_hi_#as : LoadD16Frag <SIload_d16_hi_i8> {
685  let MemoryVT = i8;
686}
687
688def load_d16_lo_#as : LoadD16Frag <SIload_d16_lo>;
689
690def az_extloadi8_d16_lo_#as : LoadD16Frag <SIload_d16_lo_u8> {
691  let MemoryVT = i8;
692}
693
694def sextloadi8_d16_lo_#as : LoadD16Frag <SIload_d16_lo_i8> {
695  let MemoryVT = i8;
696}
697
698} // End let AddressSpaces = ...
699} // End foreach AddrSpace
700
701def lshr_rev : PatFrag <
702  (ops node:$src1, node:$src0),
703  (srl $src0, $src1)
704>;
705
706def ashr_rev : PatFrag <
707  (ops node:$src1, node:$src0),
708  (sra $src0, $src1)
709>;
710
711def lshl_rev : PatFrag <
712  (ops node:$src1, node:$src0),
713  (shl $src0, $src1)
714>;
715
716def add_ctpop : PatFrag <
717  (ops node:$src0, node:$src1),
718  (add (ctpop $src0), $src1)
719>;
720
721def xnor : PatFrag <
722  (ops node:$src0, node:$src1),
723  (not (xor $src0, $src1))
724>;
725
726foreach I = 1-4 in {
727def shl#I#_add : PatFrag <
728  (ops node:$src0, node:$src1),
729  (add (shl_oneuse $src0, (i32 I)), $src1)> {
730  // FIXME: Poor substitute for disabling pattern in SelectionDAG
731  let PredicateCode = [{return false;}];
732  let GISelPredicateCode = [{return true;}];
733}
734}
735
736multiclass SIAtomicM0Glue2 <string op_name, bit is_amdgpu = 0,
737                            SDTypeProfile tc = SDTAtomic2,
738                            bit IsInt = 1> {
739
740  def _glue : SDNode <
741    !if(is_amdgpu, "AMDGPUISD", "ISD")#"::ATOMIC_"#op_name, tc,
742    [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand, SDNPInGlue]
743  >;
744
745  let AddressSpaces = StoreAddress_local.AddrSpaces in {
746    defm _local_m0 : binary_atomic_op <!cast<SDNode>(NAME#"_glue"), IsInt>;
747    defm _local_m0 : ret_noret_binary_atomic_op <!cast<SDNode>(NAME#"_glue"),
748                                                 IsInt>;
749  }
750
751  let AddressSpaces = StoreAddress_region.AddrSpaces in {
752    defm _region_m0 : binary_atomic_op <!cast<SDNode>(NAME#"_glue"), IsInt>;
753    defm _region_m0 : ret_noret_binary_atomic_op <!cast<SDNode>(NAME#"_glue"),
754                                                  IsInt>;
755  }
756}
757
758defm atomic_load_add : SIAtomicM0Glue2 <"LOAD_ADD">;
759defm atomic_load_sub : SIAtomicM0Glue2 <"LOAD_SUB">;
760defm atomic_inc : SIAtomicM0Glue2 <"INC", 1>;
761defm atomic_dec : SIAtomicM0Glue2 <"DEC", 1>;
762defm atomic_load_and : SIAtomicM0Glue2 <"LOAD_AND">;
763defm atomic_load_min : SIAtomicM0Glue2 <"LOAD_MIN">;
764defm atomic_load_max : SIAtomicM0Glue2 <"LOAD_MAX">;
765defm atomic_load_or : SIAtomicM0Glue2 <"LOAD_OR">;
766defm atomic_load_xor : SIAtomicM0Glue2 <"LOAD_XOR">;
767defm atomic_load_umin : SIAtomicM0Glue2 <"LOAD_UMIN">;
768defm atomic_load_umax : SIAtomicM0Glue2 <"LOAD_UMAX">;
769defm atomic_swap : SIAtomicM0Glue2 <"SWAP">;
770defm atomic_load_fadd : SIAtomicM0Glue2 <"LOAD_FADD", 0, SDTAtomic2_f32, 0>;
771defm atomic_load_fmin : SIAtomicM0Glue2 <"LOAD_FMIN", 1, SDTAtomic2_f32, 0>;
772defm atomic_load_fmax : SIAtomicM0Glue2 <"LOAD_FMAX", 1, SDTAtomic2_f32, 0>;
773
774def as_i1timm : SDNodeXForm<timm, [{
775  return CurDAG->getTargetConstant(N->getZExtValue(), SDLoc(N), MVT::i1);
776}]>;
777
778def as_i8imm : SDNodeXForm<imm, [{
779  return CurDAG->getTargetConstant(N->getZExtValue(), SDLoc(N), MVT::i8);
780}]>;
781
782def as_i8timm : SDNodeXForm<timm, [{
783  return CurDAG->getTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i16);
784}]>;
785
786def as_i16imm : SDNodeXForm<imm, [{
787  return CurDAG->getTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i16);
788}]>;
789
790def as_i16timm : SDNodeXForm<timm, [{
791  return CurDAG->getTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i16);
792}]>;
793
794def as_i32imm: SDNodeXForm<imm, [{
795  return CurDAG->getTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i32);
796}]>;
797
798def as_i32timm: SDNodeXForm<timm, [{
799  return CurDAG->getTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i32);
800}]>;
801
802def as_i64imm: SDNodeXForm<imm, [{
803  return CurDAG->getTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i64);
804}]>;
805
806def cond_as_i32imm: SDNodeXForm<cond, [{
807  return CurDAG->getTargetConstant(N->get(), SDLoc(N), MVT::i32);
808}]>;
809
810// Copied from the AArch64 backend:
811def bitcast_fpimm_to_i32 : SDNodeXForm<fpimm, [{
812return CurDAG->getTargetConstant(
813  N->getValueAPF().bitcastToAPInt().getZExtValue(), SDLoc(N), MVT::i32);
814}]>;
815
816def frameindex_to_targetframeindex : SDNodeXForm<frameindex, [{
817  auto FI = cast<FrameIndexSDNode>(N);
818  return CurDAG->getTargetFrameIndex(FI->getIndex(), MVT::i32);
819}]>;
820
821// Copied from the AArch64 backend:
822def bitcast_fpimm_to_i64 : SDNodeXForm<fpimm, [{
823return CurDAG->getTargetConstant(
824  N->getValueAPF().bitcastToAPInt().getZExtValue(), SDLoc(N), MVT::i64);
825}]>;
826
827class bitextract_imm<int bitnum> : SDNodeXForm<imm, [{
828  uint64_t Imm = N->getZExtValue();
829  unsigned Bit = (Imm >> }] # bitnum # [{ ) & 1;
830  return CurDAG->getTargetConstant(Bit, SDLoc(N), MVT::i1);
831}]>;
832
833def SIMM16bit : ImmLeaf <i32,
834  [{return isInt<16>(Imm);}]
835>;
836
837def UIMM16bit : ImmLeaf <i32,
838  [{return isUInt<16>(Imm);}]
839>;
840
841def i64imm_32bit : ImmLeaf<i64, [{
842  return (Imm & 0xffffffffULL) == static_cast<uint64_t>(Imm);
843}]>;
844
845def InlineImm16 : ImmLeaf<i16, [{
846  return isInlineImmediate16(Imm);
847}]>;
848
849def InlineImm32 : ImmLeaf<i32, [{
850  return isInlineImmediate32(Imm);
851}]>;
852
853def InlineImm64 : ImmLeaf<i64, [{
854  return isInlineImmediate64(Imm);
855}]>;
856
857def InlineImmFP32 : FPImmLeaf<f32, [{
858  return isInlineImmediate(Imm);
859}]>;
860
861def InlineImmFP64 : FPImmLeaf<f64, [{
862  return isInlineImmediate(Imm);
863}]>;
864
865
866class VGPRImm <dag frag> : PatLeaf<frag, [{
867  return isVGPRImm(N);
868}]>;
869
870def NegateImm : SDNodeXForm<imm, [{
871  return CurDAG->getConstant(-N->getSExtValue(), SDLoc(N), MVT::i32);
872}]>;
873
874// TODO: When FP inline imm values work?
875def NegSubInlineConst32 : ImmLeaf<i32, [{
876  return Imm < -16 && Imm >= -64;
877}], NegateImm>;
878
879def NegSubInlineIntConst16 : ImmLeaf<i16, [{
880  return Imm < -16 && Imm >= -64;
881}], NegateImm>;
882
883def ShiftAmt32Imm : ImmLeaf <i32, [{
884  return Imm < 32;
885}]>;
886
887def getNegV2I16Imm : SDNodeXForm<build_vector, [{
888  return SDValue(packNegConstantV2I16(N, *CurDAG), 0);
889}]>;
890
891def NegSubInlineConstV216 : PatLeaf<(build_vector), [{
892  assert(N->getNumOperands() == 2);
893  assert(N->getOperand(0).getValueType().getSizeInBits() == 16);
894  SDValue Src0 = N->getOperand(0);
895  SDValue Src1 = N->getOperand(1);
896  if (Src0 == Src1)
897    return isNegInlineImmediate(Src0.getNode());
898
899  return (isNullConstantOrUndef(Src0) && isNegInlineImmediate(Src1.getNode())) ||
900         (isNullConstantOrUndef(Src1) && isNegInlineImmediate(Src0.getNode()));
901}], getNegV2I16Imm>;
902
903
904def fp16_zeros_high_16bits : PatLeaf<(f16 VGPR_32:$src), [{
905  return fp16SrcZerosHighBits(N->getOpcode());
906}]>;
907
908
909//===----------------------------------------------------------------------===//
910// MUBUF/SMEM Patterns
911//===----------------------------------------------------------------------===//
912
913def extract_cpol : SDNodeXForm<timm, [{
914  return CurDAG->getTargetConstant(N->getZExtValue() & AMDGPU::CPol::ALL, SDLoc(N), MVT::i8);
915}]>;
916
917def extract_swz : SDNodeXForm<timm, [{
918  return CurDAG->getTargetConstant((N->getZExtValue() >> 3) & 1, SDLoc(N), MVT::i8);
919}]>;
920
921def set_glc : SDNodeXForm<timm, [{
922  return CurDAG->getTargetConstant(N->getZExtValue() | AMDGPU::CPol::GLC, SDLoc(N), MVT::i8);
923}]>;
924
925//===----------------------------------------------------------------------===//
926// Custom Operands
927//===----------------------------------------------------------------------===//
928
929def SoppBrTarget : AsmOperandClass {
930  let Name = "SoppBrTarget";
931  let ParserMethod = "parseSOppBrTarget";
932}
933
934def sopp_brtarget : Operand<OtherVT> {
935  let EncoderMethod = "getSOPPBrEncoding";
936  let DecoderMethod = "decodeSoppBrTarget";
937  let OperandType = "OPERAND_PCREL";
938  let ParserMatchClass = SoppBrTarget;
939}
940
941def si_ga : Operand<iPTR>;
942
943def InterpSlotMatchClass : AsmOperandClass {
944  let Name = "InterpSlot";
945  let PredicateMethod = "isInterpSlot";
946  let ParserMethod = "parseInterpSlot";
947  let RenderMethod = "addImmOperands";
948}
949
950def InterpSlot : Operand<i32> {
951  let PrintMethod = "printInterpSlot";
952  let ParserMatchClass = InterpSlotMatchClass;
953  let OperandType = "OPERAND_IMMEDIATE";
954}
955
956def AttrMatchClass : AsmOperandClass {
957  let Name = "Attr";
958  let PredicateMethod = "isInterpAttr";
959  let ParserMethod = "parseInterpAttr";
960  let RenderMethod = "addImmOperands";
961}
962
963// It appears to be necessary to create a separate operand for this to
964// be able to parse attr<num> with no space.
965def Attr : Operand<i32> {
966  let PrintMethod = "printInterpAttr";
967  let ParserMatchClass = AttrMatchClass;
968  let OperandType = "OPERAND_IMMEDIATE";
969}
970
971def AttrChanMatchClass : AsmOperandClass {
972  let Name = "AttrChan";
973  let PredicateMethod = "isAttrChan";
974  let RenderMethod = "addImmOperands";
975}
976
977def AttrChan : Operand<i32> {
978  let PrintMethod = "printInterpAttrChan";
979  let ParserMatchClass = AttrChanMatchClass;
980  let OperandType = "OPERAND_IMMEDIATE";
981}
982
983def SendMsgMatchClass : AsmOperandClass {
984  let Name = "SendMsg";
985  let PredicateMethod = "isSendMsg";
986  let ParserMethod = "parseSendMsgOp";
987  let RenderMethod = "addImmOperands";
988}
989
990def SwizzleMatchClass : AsmOperandClass {
991  let Name = "Swizzle";
992  let PredicateMethod = "isSwizzle";
993  let ParserMethod = "parseSwizzleOp";
994  let RenderMethod = "addImmOperands";
995  let IsOptional = 1;
996}
997
998def EndpgmMatchClass : AsmOperandClass {
999  let Name = "EndpgmImm";
1000  let PredicateMethod = "isEndpgm";
1001  let ParserMethod = "parseEndpgmOp";
1002  let RenderMethod = "addImmOperands";
1003  let IsOptional = 1;
1004}
1005
1006def ExpTgtMatchClass : AsmOperandClass {
1007  let Name = "ExpTgt";
1008  let PredicateMethod = "isExpTgt";
1009  let ParserMethod = "parseExpTgt";
1010  let RenderMethod = "printExpTgt";
1011}
1012
1013def SWaitMatchClass : AsmOperandClass {
1014  let Name = "SWaitCnt";
1015  let RenderMethod = "addImmOperands";
1016  let ParserMethod = "parseSWaitCntOps";
1017}
1018
1019def VReg32OrOffClass : AsmOperandClass {
1020  let Name = "VReg32OrOff";
1021  let ParserMethod = "parseVReg32OrOff";
1022}
1023
1024let OperandType = "OPERAND_IMMEDIATE" in {
1025def SendMsgImm : Operand<i32> {
1026  let PrintMethod = "printSendMsg";
1027  let ParserMatchClass = SendMsgMatchClass;
1028}
1029
1030def SwizzleImm : Operand<i16> {
1031  let PrintMethod = "printSwizzle";
1032  let ParserMatchClass = SwizzleMatchClass;
1033}
1034
1035def EndpgmImm : Operand<i16> {
1036  let PrintMethod = "printEndpgm";
1037  let ParserMatchClass = EndpgmMatchClass;
1038}
1039
1040def WAIT_FLAG : Operand <i32> {
1041  let ParserMatchClass = SWaitMatchClass;
1042  let PrintMethod = "printWaitFlag";
1043}
1044} // End OperandType = "OPERAND_IMMEDIATE"
1045
1046include "SIInstrFormats.td"
1047include "VIInstrFormats.td"
1048
1049def BoolReg : AsmOperandClass {
1050  let Name = "BoolReg";
1051  let ParserMethod = "parseBoolReg";
1052  let RenderMethod = "addRegOperands";
1053}
1054
1055class BoolRC : RegisterOperand<SReg_1> {
1056  let ParserMatchClass = BoolReg;
1057  let DecoderMethod = "decodeBoolReg";
1058}
1059
1060def SSrc_i1 : RegisterOperand<SReg_1_XEXEC> {
1061  let ParserMatchClass = BoolReg;
1062  let DecoderMethod = "decodeBoolReg";
1063}
1064
1065def VOPDstS64orS32 : BoolRC {
1066  let PrintMethod = "printVOPDst";
1067}
1068
1069// SCSrc_i1 is the operand for pseudo instructions only.
1070// Boolean immediates shall not be exposed to codegen instructions.
1071def SCSrc_i1 : RegisterOperand<SReg_1_XEXEC> {
1072  let OperandNamespace = "AMDGPU";
1073  let OperandType = "OPERAND_REG_IMM_INT32";
1074  let ParserMatchClass = BoolReg;
1075  let DecoderMethod = "decodeBoolReg";
1076}
1077
1078// ===----------------------------------------------------------------------===//
1079// ExpSrc* Special cases for exp src operands which are printed as
1080// "off" depending on en operand.
1081// ===----------------------------------------------------------------------===//
1082
1083def ExpSrc0 : RegisterOperand<VGPR_32> {
1084  let PrintMethod = "printExpSrc0";
1085  let ParserMatchClass = VReg32OrOffClass;
1086}
1087
1088def ExpSrc1 : RegisterOperand<VGPR_32> {
1089  let PrintMethod = "printExpSrc1";
1090  let ParserMatchClass = VReg32OrOffClass;
1091}
1092
1093def ExpSrc2 : RegisterOperand<VGPR_32> {
1094  let PrintMethod = "printExpSrc2";
1095  let ParserMatchClass = VReg32OrOffClass;
1096}
1097
1098def ExpSrc3 : RegisterOperand<VGPR_32> {
1099  let PrintMethod = "printExpSrc3";
1100  let ParserMatchClass = VReg32OrOffClass;
1101}
1102
1103class SDWASrc<ValueType vt> : RegisterOperand<VS_32> {
1104  let OperandNamespace = "AMDGPU";
1105  string Type = !if(isFloatType<vt>.ret, "FP", "INT");
1106  let OperandType = "OPERAND_REG_INLINE_C_"#Type#vt.Size;
1107  let DecoderMethod = "decodeSDWASrc"#vt.Size;
1108  let EncoderMethod = "getSDWASrcEncoding";
1109}
1110
1111def SDWASrc_i32 : SDWASrc<i32>;
1112def SDWASrc_i16 : SDWASrc<i16>;
1113def SDWASrc_f32 : SDWASrc<f32>;
1114def SDWASrc_f16 : SDWASrc<f16>;
1115
1116def SDWAVopcDst : BoolRC {
1117  let OperandNamespace = "AMDGPU";
1118  let OperandType = "OPERAND_SDWA_VOPC_DST";
1119  let EncoderMethod = "getSDWAVopcDstEncoding";
1120  let DecoderMethod = "decodeSDWAVopcDst";
1121  let PrintMethod = "printVOPDst";
1122}
1123
1124class NamedMatchClass<string CName, bit Optional = 1> : AsmOperandClass {
1125  let Name = "Imm"#CName;
1126  let PredicateMethod = "is"#CName;
1127  let ParserMethod = !if(Optional, "parseOptionalOperand", "parse"#CName);
1128  let RenderMethod = "addImmOperands";
1129  let IsOptional = Optional;
1130  let DefaultMethod = !if(Optional, "default"#CName, ?);
1131}
1132
1133class NamedOperandBit<string Name, AsmOperandClass MatchClass> : Operand<i1> {
1134  let PrintMethod = "print"#Name;
1135  let ParserMatchClass = MatchClass;
1136}
1137
1138class NamedOperandBit_0<string Name, AsmOperandClass MatchClass> :
1139  OperandWithDefaultOps<i1, (ops (i1 0))> {
1140  let PrintMethod = "print"#Name;
1141  let ParserMatchClass = MatchClass;
1142}
1143
1144class NamedOperandBit_1<string Name, AsmOperandClass MatchClass> :
1145  OperandWithDefaultOps<i1, (ops (i1 1))> {
1146  let PrintMethod = "print"#Name;
1147  let ParserMatchClass = MatchClass;
1148}
1149
1150class NamedOperandU8<string Name, AsmOperandClass MatchClass> : Operand<i8> {
1151  let PrintMethod = "print"#Name;
1152  let ParserMatchClass = MatchClass;
1153}
1154
1155class NamedOperandU16<string Name, AsmOperandClass MatchClass> : Operand<i16> {
1156  let PrintMethod = "print"#Name;
1157  let ParserMatchClass = MatchClass;
1158}
1159
1160class NamedOperandU32<string Name, AsmOperandClass MatchClass> : Operand<i32> {
1161  let PrintMethod = "print"#Name;
1162  let ParserMatchClass = MatchClass;
1163}
1164
1165class NamedOperandU32_0<string Name, AsmOperandClass MatchClass> :
1166  OperandWithDefaultOps<i32, (ops (i32 0))> {
1167  let PrintMethod = "print"#Name;
1168  let ParserMatchClass = MatchClass;
1169}
1170
1171class NamedOperandU32Default0<string Name, AsmOperandClass MatchClass> :
1172  OperandWithDefaultOps<i32, (ops (i32 0))> {
1173  let PrintMethod = "print"#Name;
1174  let ParserMatchClass = MatchClass;
1175}
1176
1177class NamedOperandU32Default1<string Name, AsmOperandClass MatchClass> :
1178  OperandWithDefaultOps<i32, (ops (i32 1))> {
1179  let PrintMethod = "print"#Name;
1180  let ParserMatchClass = MatchClass;
1181}
1182
1183let OperandType = "OPERAND_IMMEDIATE" in {
1184
1185def offen : NamedOperandBit<"Offen", NamedMatchClass<"Offen">>;
1186def idxen : NamedOperandBit<"Idxen", NamedMatchClass<"Idxen">>;
1187def addr64 : NamedOperandBit<"Addr64", NamedMatchClass<"Addr64">>;
1188
1189def flat_offset : NamedOperandU16<"FlatOffset", NamedMatchClass<"FlatOffset">>;
1190def offset : NamedOperandU16<"Offset", NamedMatchClass<"Offset">>;
1191def offset0 : NamedOperandU8<"Offset0", NamedMatchClass<"Offset0">>;
1192def offset1 : NamedOperandU8<"Offset1", NamedMatchClass<"Offset1">>;
1193
1194def gds : NamedOperandBit<"GDS", NamedMatchClass<"GDS">>;
1195
1196def omod : NamedOperandU32<"OModSI", NamedMatchClass<"OModSI">>;
1197def omod0 : NamedOperandU32_0<"OModSI", NamedMatchClass<"OModSI">>;
1198
1199// We need to make the cases with a default of 0 distinct from no
1200// default to help deal with some cases where the operand appears
1201// before a mandatory operand.
1202def clampmod : NamedOperandBit<"ClampSI", NamedMatchClass<"ClampSI">>;
1203def clampmod0 : NamedOperandBit_0<"ClampSI", NamedMatchClass<"ClampSI">>;
1204def highmod : NamedOperandBit<"High", NamedMatchClass<"High">>;
1205
1206def CPol : NamedOperandU32<"CPol", NamedMatchClass<"CPol">>;
1207def CPol_0 : NamedOperandU32Default0<"CPol", NamedMatchClass<"CPol">>;
1208def CPol_GLC1 : NamedOperandU32Default1<"CPol", NamedMatchClass<"CPol">>;
1209
1210def TFE : NamedOperandBit<"TFE", NamedMatchClass<"TFE">>;
1211def TFE_0 : NamedOperandBit_0<"TFE", NamedMatchClass<"TFE">>;
1212def SWZ : NamedOperandBit<"SWZ", NamedMatchClass<"SWZ">>;
1213def SWZ_0 : NamedOperandBit_0<"SWZ", NamedMatchClass<"SWZ">>;
1214def UNorm : NamedOperandBit<"UNorm", NamedMatchClass<"UNorm">>;
1215def DA : NamedOperandBit<"DA", NamedMatchClass<"DA">>;
1216def R128A16 : NamedOperandBit<"R128A16", NamedMatchClass<"R128A16">>;
1217def GFX10A16 : NamedOperandBit<"GFX10A16", NamedMatchClass<"GFX10A16">>;
1218def D16 : NamedOperandBit<"D16", NamedMatchClass<"D16">>;
1219def LWE : NamedOperandBit<"LWE", NamedMatchClass<"LWE">>;
1220def exp_compr : NamedOperandBit<"ExpCompr", NamedMatchClass<"ExpCompr">>;
1221def exp_vm : NamedOperandBit<"ExpVM", NamedMatchClass<"ExpVM">>;
1222
1223def FORMAT : NamedOperandU8<"FORMAT", NamedMatchClass<"FORMAT", 0>>;
1224
1225def DMask : NamedOperandU16<"DMask", NamedMatchClass<"DMask">>;
1226def Dim : NamedOperandU8<"Dim", NamedMatchClass<"Dim", 0>>;
1227
1228def dpp8 : NamedOperandU32<"DPP8", NamedMatchClass<"DPP8", 0>>;
1229
1230def dpp_ctrl : NamedOperandU32<"DPPCtrl", NamedMatchClass<"DPPCtrl", 0>>;
1231def row_mask : NamedOperandU32<"RowMask", NamedMatchClass<"RowMask">>;
1232def bank_mask : NamedOperandU32<"BankMask", NamedMatchClass<"BankMask">>;
1233def bound_ctrl : NamedOperandBit<"BoundCtrl", NamedMatchClass<"BoundCtrl">>;
1234def FI : NamedOperandU32<"FI", NamedMatchClass<"FI">>;
1235
1236def dst_sel : NamedOperandU32<"SDWADstSel", NamedMatchClass<"SDWADstSel">>;
1237def src0_sel : NamedOperandU32<"SDWASrc0Sel", NamedMatchClass<"SDWASrc0Sel">>;
1238def src1_sel : NamedOperandU32<"SDWASrc1Sel", NamedMatchClass<"SDWASrc1Sel">>;
1239def dst_unused : NamedOperandU32<"SDWADstUnused", NamedMatchClass<"SDWADstUnused">>;
1240
1241def op_sel0 : NamedOperandU32Default0<"OpSel", NamedMatchClass<"OpSel">>;
1242def op_sel_hi0 : NamedOperandU32Default0<"OpSelHi", NamedMatchClass<"OpSelHi">>;
1243def neg_lo0 : NamedOperandU32Default0<"NegLo", NamedMatchClass<"NegLo">>;
1244def neg_hi0 : NamedOperandU32Default0<"NegHi", NamedMatchClass<"NegHi">>;
1245
1246def blgp : NamedOperandU32<"BLGP", NamedMatchClass<"BLGP">>;
1247def cbsz : NamedOperandU32<"CBSZ", NamedMatchClass<"CBSZ">>;
1248def abid : NamedOperandU32<"ABID", NamedMatchClass<"ABID">>;
1249
1250def hwreg : NamedOperandU32<"Hwreg", NamedMatchClass<"Hwreg", 0>>;
1251
1252def exp_tgt : NamedOperandU32<"ExpTgt", NamedMatchClass<"ExpTgt", 0>> {
1253
1254}
1255
1256} // End OperandType = "OPERAND_IMMEDIATE"
1257
1258class KImmMatchClass<int size> : AsmOperandClass {
1259  let Name = "KImmFP"#size;
1260  let PredicateMethod = "isKImmFP"#size;
1261  let ParserMethod = "parseImm";
1262  let RenderMethod = "addKImmFP"#size#"Operands";
1263}
1264
1265class kimmOperand<ValueType vt> : Operand<vt> {
1266  let OperandNamespace = "AMDGPU";
1267  let OperandType = "OPERAND_KIMM"#vt.Size;
1268  let PrintMethod = "printU"#vt.Size#"ImmOperand";
1269  let ParserMatchClass = !cast<AsmOperandClass>("KImmFP"#vt.Size#"MatchClass");
1270  let DecoderMethod = "decodeOperand_f"#vt.Size#"kimm";
1271}
1272
1273// 32-bit VALU immediate operand that uses the constant bus.
1274def KImmFP32MatchClass : KImmMatchClass<32>;
1275def f32kimm : kimmOperand<i32>;
1276
1277// 32-bit VALU immediate operand with a 16-bit value that uses the
1278// constant bus.
1279def KImmFP16MatchClass : KImmMatchClass<16>;
1280def f16kimm : kimmOperand<i16>;
1281
1282class FPInputModsMatchClass <int opSize> : AsmOperandClass {
1283  let Name = "RegOrImmWithFP"#opSize#"InputMods";
1284  let ParserMethod = "parseRegOrImmWithFPInputMods";
1285  let PredicateMethod = "isRegOrImmWithFP"#opSize#"InputMods";
1286}
1287
1288def FP16InputModsMatchClass : FPInputModsMatchClass<16>;
1289def FP32InputModsMatchClass : FPInputModsMatchClass<32>;
1290def FP64InputModsMatchClass : FPInputModsMatchClass<64>;
1291
1292class InputMods <AsmOperandClass matchClass> : Operand <i32> {
1293  let OperandNamespace = "AMDGPU";
1294  let OperandType = "OPERAND_INPUT_MODS";
1295  let ParserMatchClass = matchClass;
1296}
1297
1298class FPInputMods <FPInputModsMatchClass matchClass> : InputMods <matchClass> {
1299  let PrintMethod = "printOperandAndFPInputMods";
1300}
1301
1302def FP16InputMods : FPInputMods<FP16InputModsMatchClass>;
1303def FP32InputMods : FPInputMods<FP32InputModsMatchClass>;
1304def FP64InputMods : FPInputMods<FP64InputModsMatchClass>;
1305
1306class IntInputModsMatchClass <int opSize> : AsmOperandClass {
1307  let Name = "RegOrImmWithInt"#opSize#"InputMods";
1308  let ParserMethod = "parseRegOrImmWithIntInputMods";
1309  let PredicateMethod = "isRegOrImmWithInt"#opSize#"InputMods";
1310}
1311def Int32InputModsMatchClass : IntInputModsMatchClass<32>;
1312def Int64InputModsMatchClass : IntInputModsMatchClass<64>;
1313
1314class IntInputMods <IntInputModsMatchClass matchClass> : InputMods <matchClass> {
1315  let PrintMethod = "printOperandAndIntInputMods";
1316}
1317def Int32InputMods : IntInputMods<Int32InputModsMatchClass>;
1318def Int64InputMods : IntInputMods<Int64InputModsMatchClass>;
1319
1320class OpSelModsMatchClass : AsmOperandClass {
1321  let Name = "OpSelMods";
1322  let ParserMethod = "parseRegOrImm";
1323  let PredicateMethod = "isRegOrImm";
1324}
1325
1326def IntOpSelModsMatchClass : OpSelModsMatchClass;
1327def IntOpSelMods : InputMods<IntOpSelModsMatchClass>;
1328
1329class FPSDWAInputModsMatchClass <int opSize> : AsmOperandClass {
1330  let Name = "SDWAWithFP"#opSize#"InputMods";
1331  let ParserMethod = "parseRegOrImmWithFPInputMods";
1332  let PredicateMethod = "isSDWAFP"#opSize#"Operand";
1333}
1334
1335def FP16SDWAInputModsMatchClass : FPSDWAInputModsMatchClass<16>;
1336def FP32SDWAInputModsMatchClass : FPSDWAInputModsMatchClass<32>;
1337
1338class FPSDWAInputMods <FPSDWAInputModsMatchClass matchClass> :
1339  InputMods <matchClass> {
1340  let PrintMethod = "printOperandAndFPInputMods";
1341}
1342
1343def FP16SDWAInputMods : FPSDWAInputMods<FP16SDWAInputModsMatchClass>;
1344def FP32SDWAInputMods : FPSDWAInputMods<FP32SDWAInputModsMatchClass>;
1345
1346def FPVRegInputModsMatchClass : AsmOperandClass {
1347  let Name = "VRegWithFPInputMods";
1348  let ParserMethod = "parseRegWithFPInputMods";
1349  let PredicateMethod = "isVRegWithInputMods";
1350}
1351
1352def FPVRegInputMods : InputMods <FPVRegInputModsMatchClass> {
1353  let PrintMethod = "printOperandAndFPInputMods";
1354}
1355
1356class IntSDWAInputModsMatchClass <int opSize> : AsmOperandClass {
1357  let Name = "SDWAWithInt"#opSize#"InputMods";
1358  let ParserMethod = "parseRegOrImmWithIntInputMods";
1359  let PredicateMethod = "isSDWAInt"#opSize#"Operand";
1360}
1361
1362def Int16SDWAInputModsMatchClass : IntSDWAInputModsMatchClass<16>;
1363def Int32SDWAInputModsMatchClass : IntSDWAInputModsMatchClass<32>;
1364
1365class IntSDWAInputMods <IntSDWAInputModsMatchClass matchClass> :
1366  InputMods <matchClass> {
1367  let PrintMethod = "printOperandAndIntInputMods";
1368}
1369
1370def Int16SDWAInputMods : IntSDWAInputMods<Int16SDWAInputModsMatchClass>;
1371def Int32SDWAInputMods : IntSDWAInputMods<Int32SDWAInputModsMatchClass>;
1372
1373def IntVRegInputModsMatchClass : AsmOperandClass {
1374  let Name = "VRegWithIntInputMods";
1375  let ParserMethod = "parseRegWithIntInputMods";
1376  let PredicateMethod = "isVRegWithInputMods";
1377}
1378
1379def IntVRegInputMods : InputMods <IntVRegInputModsMatchClass> {
1380  let PrintMethod = "printOperandAndIntInputMods";
1381}
1382
1383class PackedFPInputModsMatchClass <int opSize> : AsmOperandClass {
1384  let Name = "PackedFP"#opSize#"InputMods";
1385  let ParserMethod = "parseRegOrImm";
1386  let PredicateMethod = "isRegOrImm";
1387//  let PredicateMethod = "isPackedFP"#opSize#"InputMods";
1388}
1389
1390class PackedIntInputModsMatchClass <int opSize> : AsmOperandClass {
1391  let Name = "PackedInt"#opSize#"InputMods";
1392  let ParserMethod = "parseRegOrImm";
1393  let PredicateMethod = "isRegOrImm";
1394//  let PredicateMethod = "isPackedInt"#opSize#"InputMods";
1395}
1396
1397def PackedF16InputModsMatchClass : PackedFPInputModsMatchClass<16>;
1398def PackedI16InputModsMatchClass : PackedIntInputModsMatchClass<16>;
1399
1400class PackedFPInputMods <PackedFPInputModsMatchClass matchClass> : InputMods <matchClass> {
1401//  let PrintMethod = "printPackedFPInputMods";
1402}
1403
1404class PackedIntInputMods <PackedIntInputModsMatchClass matchClass> : InputMods <matchClass> {
1405  //let PrintMethod = "printPackedIntInputMods";
1406}
1407
1408def PackedF16InputMods : PackedFPInputMods<PackedF16InputModsMatchClass>;
1409def PackedI16InputMods : PackedIntInputMods<PackedI16InputModsMatchClass>;
1410
1411//===----------------------------------------------------------------------===//
1412// Complex patterns
1413//===----------------------------------------------------------------------===//
1414
1415def DS1Addr1Offset : ComplexPattern<iPTR, 2, "SelectDS1Addr1Offset">;
1416def DS64Bit4ByteAligned : ComplexPattern<iPTR, 3, "SelectDS64Bit4ByteAligned">;
1417def DS128Bit8ByteAligned : ComplexPattern<iPTR, 3, "SelectDS128Bit8ByteAligned">;
1418
1419def MOVRELOffset : ComplexPattern<iPTR, 2, "SelectMOVRELOffset">;
1420
1421def VOP3Mods0 : ComplexPattern<untyped, 4, "SelectVOP3Mods0">;
1422def VOP3Mods  : ComplexPattern<untyped, 2, "SelectVOP3Mods">;
1423def VOP3NoMods : ComplexPattern<untyped, 1, "SelectVOP3NoMods">;
1424// VOP3Mods, but the input source is known to never be NaN.
1425def VOP3Mods_nnan : ComplexPattern<fAny, 2, "SelectVOP3Mods_NNaN">;
1426
1427def VOP3OMods : ComplexPattern<untyped, 3, "SelectVOP3OMods">;
1428
1429def VOP3PMods  : ComplexPattern<untyped, 2, "SelectVOP3PMods">;
1430
1431def VOP3PModsDOT  : ComplexPattern<untyped, 2, "SelectVOP3PModsDOT">;
1432
1433def VOP3OpSel  : ComplexPattern<untyped, 2, "SelectVOP3OpSel">;
1434
1435def VOP3OpSelMods  : ComplexPattern<untyped, 2, "SelectVOP3OpSelMods">;
1436
1437def VOP3PMadMixMods  : ComplexPattern<untyped, 2, "SelectVOP3PMadMixMods">;
1438
1439//===----------------------------------------------------------------------===//
1440// SI assembler operands
1441//===----------------------------------------------------------------------===//
1442
1443def SIOperand {
1444  int ZERO = 0x80;
1445  int VCC = 0x6A;
1446  int FLAT_SCR = 0x68;
1447}
1448
1449// This should be kept in sync with SISrcMods enum
1450def SRCMODS {
1451  int NONE = 0;
1452  int NEG = 1;
1453  int ABS = 2;
1454  int NEG_ABS = 3;
1455
1456  int NEG_HI = ABS;
1457  int OP_SEL_0 = 4;
1458  int OP_SEL_1 = 8;
1459  int DST_OP_SEL = 8;
1460}
1461
1462def DSTCLAMP {
1463  int NONE = 0;
1464  int ENABLE = 1;
1465}
1466
1467def DSTOMOD {
1468  int NONE = 0;
1469}
1470
1471def HWREG {
1472  int MODE = 1;
1473  int STATUS = 2;
1474  int TRAPSTS = 3;
1475  int HW_ID = 4;
1476  int GPR_ALLOC = 5;
1477  int LDS_ALLOC = 6;
1478  int IB_STS = 7;
1479  int MEM_BASES = 15;
1480  int TBA_LO = 16;
1481  int TBA_HI = 17;
1482  int TMA_LO = 18;
1483  int TMA_HI = 19;
1484  int FLAT_SCR_LO = 20;
1485  int FLAT_SCR_HI = 21;
1486  int XNACK_MASK = 22;
1487  int POPS_PACKER = 25;
1488  int SHADER_CYCLES = 29;
1489}
1490
1491class getHwRegImm<int Reg, int Offset = 0, int Size = 32> {
1492  int ret = !and(!or(Reg,
1493                     !shl(Offset, 6),
1494                     !shl(!add(Size, -1), 11)), 65535);
1495}
1496
1497//===----------------------------------------------------------------------===//
1498//
1499// SI Instruction multiclass helpers.
1500//
1501// Instructions with _32 take 32-bit operands.
1502// Instructions with _64 take 64-bit operands.
1503//
1504// VOP_* instructions can use either a 32-bit or 64-bit encoding.  The 32-bit
1505// encoding is the standard encoding, but instruction that make use of
1506// any of the instruction modifiers must use the 64-bit encoding.
1507//
1508// Instructions with _e32 use the 32-bit encoding.
1509// Instructions with _e64 use the 64-bit encoding.
1510//
1511//===----------------------------------------------------------------------===//
1512
1513class SIMCInstr <string pseudo, int subtarget> {
1514  string PseudoInstr = pseudo;
1515  int Subtarget = subtarget;
1516}
1517
1518//===----------------------------------------------------------------------===//
1519// Vector ALU classes
1520//===----------------------------------------------------------------------===//
1521
1522class getNumSrcArgs<ValueType Src0, ValueType Src1, ValueType Src2> {
1523  int ret =
1524    !if (!eq(Src0.Value, untyped.Value),      0,
1525      !if (!eq(Src1.Value, untyped.Value),    1,   // VOP1
1526         !if (!eq(Src2.Value, untyped.Value), 2,   // VOP2
1527                                              3))); // VOP3
1528}
1529
1530// Returns the register class to use for the destination of VOP[123C]
1531// instructions for the given VT.
1532class getVALUDstForVT<ValueType VT> {
1533  RegisterOperand ret = !if(!eq(VT.Size, 32), VOPDstOperand<VGPR_32>,
1534                          !if(!eq(VT.Size, 128), VOPDstOperand<VReg_128>,
1535                            !if(!eq(VT.Size, 64), VOPDstOperand<VReg_64>,
1536                              !if(!eq(VT.Size, 16), VOPDstOperand<VGPR_32>,
1537                              VOPDstS64orS32)))); // else VT == i1
1538}
1539
1540// Returns the register class to use for the destination of VOP[12C]
1541// instructions with SDWA extension
1542class getSDWADstForVT<ValueType VT> {
1543  RegisterOperand ret = !if(!eq(VT.Size, 1),
1544                            SDWAVopcDst, // VOPC
1545                            VOPDstOperand<VGPR_32>); // VOP1/2 32-bit dst
1546}
1547
1548// Returns the register class to use for source 0 of VOP[12C]
1549// instructions for the given VT.
1550class getVOPSrc0ForVT<ValueType VT> {
1551  bit isFP = isFloatType<VT>.ret;
1552
1553  RegisterOperand ret =
1554    !if(isFP,
1555      !if(!eq(VT.Size, 64),
1556         VSrc_f64,
1557         !if(!eq(VT.Value, f16.Value),
1558            VSrc_f16,
1559            !if(!eq(VT.Value, v2f16.Value),
1560               VSrc_v2f16,
1561               !if(!eq(VT.Value, v4f16.Value),
1562                 AVSrc_64,
1563                 VSrc_f32
1564               )
1565            )
1566         )
1567       ),
1568       !if(!eq(VT.Size, 64),
1569          VSrc_b64,
1570          !if(!eq(VT.Value, i16.Value),
1571             VSrc_b16,
1572             !if(!eq(VT.Value, v2i16.Value),
1573                VSrc_v2b16,
1574                VSrc_b32
1575             )
1576          )
1577       )
1578    );
1579}
1580
1581class getSOPSrcForVT<ValueType VT> {
1582  RegisterOperand ret = !if(!eq(VT.Size, 64), SSrc_b64, SSrc_b32);
1583}
1584
1585// Returns the vreg register class to use for source operand given VT
1586class getVregSrcForVT<ValueType VT> {
1587  RegisterClass ret = !if(!eq(VT.Size, 128), VReg_128,
1588                        !if(!eq(VT.Size, 96), VReg_96,
1589                          !if(!eq(VT.Size, 64), VReg_64,
1590                            !if(!eq(VT.Size, 48), VReg_64,
1591                              VGPR_32))));
1592}
1593
1594class getSDWASrcForVT <ValueType VT> {
1595  bit isFP = isFloatType<VT>.ret;
1596  RegisterOperand retFlt = !if(!eq(VT.Size, 16), SDWASrc_f16, SDWASrc_f32);
1597  RegisterOperand retInt = !if(!eq(VT.Size, 16), SDWASrc_i16, SDWASrc_i32);
1598  RegisterOperand ret = !if(isFP, retFlt, retInt);
1599}
1600
1601// Returns the register class to use for sources of VOP3 instructions for the
1602// given VT.
1603class getVOP3SrcForVT<ValueType VT> {
1604  bit isFP = isFloatType<VT>.ret;
1605  RegisterOperand ret =
1606  !if(!eq(VT.Size, 128),
1607     VSrc_128,
1608     !if(!eq(VT.Size, 64),
1609        !if(isFP,
1610           !if(!eq(VT.Value, v2f32.Value),
1611               VSrc_v2f32,
1612               VSrc_f64),
1613           !if(!eq(VT.Value, v2i32.Value),
1614               VSrc_v2b32,
1615           VSrc_b64)),
1616        !if(!eq(VT.Value, i1.Value),
1617           SSrc_i1,
1618           !if(isFP,
1619              !if(!eq(VT.Value, f16.Value),
1620                 VSrc_f16,
1621                 !if(!eq(VT.Value, v2f16.Value),
1622                    VSrc_v2f16,
1623                    !if(!eq(VT.Value, v4f16.Value),
1624                      AVSrc_64,
1625                      VSrc_f32
1626                    )
1627                 )
1628              ),
1629              !if(!eq(VT.Value, i16.Value),
1630                 VSrc_b16,
1631                 !if(!eq(VT.Value, v2i16.Value),
1632                    VSrc_v2b16,
1633                    VSrc_b32
1634                 )
1635              )
1636           )
1637        )
1638     )
1639  );
1640}
1641
1642// Float or packed int
1643class isModifierType<ValueType SrcVT> {
1644  bit ret = !or(!eq(SrcVT.Value, f16.Value),
1645                !eq(SrcVT.Value, f32.Value),
1646                !eq(SrcVT.Value, f64.Value),
1647                !eq(SrcVT.Value, v2f16.Value),
1648                !eq(SrcVT.Value, v2i16.Value),
1649                !eq(SrcVT.Value, v2f32.Value),
1650                !eq(SrcVT.Value, v2i32.Value));
1651}
1652
1653// Return type of input modifiers operand for specified input operand
1654class getSrcMod <ValueType VT, bit EnableF32SrcMods> {
1655  bit isFP = isFloatType<VT>.ret;
1656  bit isPacked = isPackedType<VT>.ret;
1657  Operand ret =  !if(!eq(VT.Size, 64),
1658                     !if(isFP, FP64InputMods, Int64InputMods),
1659                       !if(isFP,
1660                         !if(!eq(VT.Value, f16.Value),
1661                            FP16InputMods,
1662                            FP32InputMods
1663                          ),
1664                         !if(EnableF32SrcMods, FP32InputMods, Int32InputMods))
1665                     );
1666}
1667
1668class getOpSelMod <ValueType VT> {
1669  Operand ret = !if(!eq(VT.Value, f16.Value), FP16InputMods, IntOpSelMods);
1670}
1671
1672// Return type of input modifiers operand specified input operand for DPP
1673class getSrcModDPP <ValueType VT> {
1674  bit isFP = isFloatType<VT>.ret;
1675  Operand ret = !if(isFP, FPVRegInputMods, IntVRegInputMods);
1676}
1677
1678// Return type of input modifiers operand specified input operand for SDWA
1679class getSrcModSDWA <ValueType VT> {
1680  Operand ret = !if(!eq(VT.Value, f16.Value), FP16SDWAInputMods,
1681                !if(!eq(VT.Value, f32.Value), FP32SDWAInputMods,
1682                !if(!eq(VT.Value, i16.Value), Int16SDWAInputMods,
1683                Int32SDWAInputMods)));
1684}
1685
1686// Returns the input arguments for VOP[12C] instructions for the given SrcVT.
1687class getIns32 <RegisterOperand Src0RC, RegisterClass Src1RC, int NumSrcArgs> {
1688  dag ret = !if(!eq(NumSrcArgs, 1), (ins Src0RC:$src0),               // VOP1
1689            !if(!eq(NumSrcArgs, 2), (ins Src0RC:$src0, Src1RC:$src1), // VOP2
1690                                    (ins)));
1691}
1692
1693// Returns the input arguments for VOP3 instructions for the given SrcVT.
1694class getIns64 <RegisterOperand Src0RC, RegisterOperand Src1RC,
1695                RegisterOperand Src2RC, int NumSrcArgs,
1696                bit HasClamp, bit HasModifiers, bit HasSrc2Mods, bit HasOMod,
1697                Operand Src0Mod, Operand Src1Mod, Operand Src2Mod> {
1698
1699  dag ret =
1700    !if (!eq(NumSrcArgs, 0),
1701      // VOP1 without input operands (V_NOP, V_CLREXCP)
1702      (ins),
1703      /* else */
1704    !if (!eq(NumSrcArgs, 1),
1705      !if (HasModifiers,
1706        // VOP1 with modifiers
1707        !if(HasOMod,
1708          (ins Src0Mod:$src0_modifiers, Src0RC:$src0,
1709               clampmod0:$clamp, omod0:$omod),
1710          (ins Src0Mod:$src0_modifiers, Src0RC:$src0,
1711               clampmod0:$clamp))
1712      /* else */,
1713        // VOP1 without modifiers
1714        !if (HasClamp,
1715          (ins Src0RC:$src0, clampmod0:$clamp),
1716          (ins Src0RC:$src0))
1717      /* endif */ ),
1718    !if (!eq(NumSrcArgs, 2),
1719      !if (HasModifiers,
1720        // VOP 2 with modifiers
1721        !if(HasOMod,
1722          (ins Src0Mod:$src0_modifiers, Src0RC:$src0,
1723               Src1Mod:$src1_modifiers, Src1RC:$src1,
1724               clampmod0:$clamp, omod0:$omod),
1725           (ins Src0Mod:$src0_modifiers, Src0RC:$src0,
1726               Src1Mod:$src1_modifiers, Src1RC:$src1,
1727               clampmod0:$clamp))
1728      /* else */,
1729        // VOP2 without modifiers
1730        !if (HasClamp,
1731          (ins Src0RC:$src0, Src1RC:$src1, clampmod0:$clamp),
1732          (ins Src0RC:$src0, Src1RC:$src1))
1733
1734      /* endif */ )
1735    /* NumSrcArgs == 3 */,
1736      !if (HasModifiers,
1737        !if (HasSrc2Mods,
1738          // VOP3 with modifiers
1739          !if (HasOMod,
1740            (ins Src0Mod:$src0_modifiers, Src0RC:$src0,
1741                 Src1Mod:$src1_modifiers, Src1RC:$src1,
1742                 Src2Mod:$src2_modifiers, Src2RC:$src2,
1743                 clampmod0:$clamp, omod0:$omod),
1744            !if (HasClamp,
1745              (ins Src0Mod:$src0_modifiers, Src0RC:$src0,
1746                   Src1Mod:$src1_modifiers, Src1RC:$src1,
1747                   Src2Mod:$src2_modifiers, Src2RC:$src2,
1748                   clampmod0:$clamp),
1749              (ins Src0Mod:$src0_modifiers, Src0RC:$src0,
1750                   Src1Mod:$src1_modifiers, Src1RC:$src1,
1751                   Src2Mod:$src2_modifiers, Src2RC:$src2))),
1752          // VOP3 with modifiers except src2
1753          !if (HasOMod,
1754            (ins Src0Mod:$src0_modifiers, Src0RC:$src0,
1755                 Src1Mod:$src1_modifiers, Src1RC:$src1,
1756                 Src2RC:$src2, clampmod0:$clamp, omod0:$omod),
1757            !if (HasClamp,
1758              (ins Src0Mod:$src0_modifiers, Src0RC:$src0,
1759                   Src1Mod:$src1_modifiers, Src1RC:$src1,
1760                   Src2RC:$src2, clampmod0:$clamp),
1761              (ins Src0Mod:$src0_modifiers, Src0RC:$src0,
1762                   Src1Mod:$src1_modifiers, Src1RC:$src1,
1763                   Src2RC:$src2))))
1764      /* else */,
1765        // VOP3 without modifiers
1766        !if (HasClamp,
1767          (ins Src0RC:$src0, Src1RC:$src1, Src2RC:$src2, clampmod0:$clamp),
1768          (ins Src0RC:$src0, Src1RC:$src1, Src2RC:$src2))
1769      /* endif */ ))));
1770}
1771
1772class getInsVOP3Base<RegisterOperand Src0RC, RegisterOperand Src1RC,
1773                RegisterOperand Src2RC, int NumSrcArgs,
1774                bit HasClamp, bit HasModifiers, bit HasSrc2Mods, bit HasOMod,
1775                Operand Src0Mod, Operand Src1Mod, Operand Src2Mod, bit HasOpSel,
1776                bit IsVOP3P> {
1777  // getInst64 handles clamp and omod. implicit mutex between vop3p and omod
1778  dag base = getIns64 <Src0RC, Src1RC, Src2RC, NumSrcArgs,
1779                HasClamp, HasModifiers, HasSrc2Mods, HasOMod,
1780                Src0Mod, Src1Mod, Src2Mod>.ret;
1781  dag opsel = (ins op_sel0:$op_sel);
1782  dag vop3pFields = (ins op_sel_hi0:$op_sel_hi, neg_lo0:$neg_lo, neg_hi0:$neg_hi);
1783  dag ret = !con(base,
1784                 !if(HasOpSel, opsel,(ins)),
1785                 !if(IsVOP3P, vop3pFields,(ins)));
1786}
1787
1788class getInsVOP3P <RegisterOperand Src0RC, RegisterOperand Src1RC,
1789                   RegisterOperand Src2RC, int NumSrcArgs, bit HasClamp,
1790                   Operand Src0Mod, Operand Src1Mod, Operand Src2Mod> {
1791  dag ret = getInsVOP3Base<Src0RC, Src1RC, Src2RC, NumSrcArgs,
1792                    HasClamp, 1/*HasModifiers*/, 1/*HasSrc2Mods*/,
1793                    0/*HasOMod*/, Src0Mod, Src1Mod, Src2Mod,
1794                    1/*HasOpSel*/, 1/*IsVOP3P*/>.ret;
1795}
1796
1797class getInsVOP3OpSel <RegisterOperand Src0RC, RegisterOperand Src1RC,
1798                       RegisterOperand Src2RC, int NumSrcArgs,
1799                       bit HasClamp, bit HasOMod,
1800                       Operand Src0Mod, Operand Src1Mod, Operand Src2Mod> {
1801  dag ret = getInsVOP3Base<Src0RC, Src1RC,
1802                    Src2RC, NumSrcArgs,
1803                    HasClamp, 1/*HasModifiers*/, 1/*HasSrc2Mods*/, HasOMod,
1804                    Src0Mod, Src1Mod, Src2Mod, 1/*HasOpSel*/, 0>.ret;
1805}
1806
1807class getInsDPPBase <RegisterOperand OldRC, RegisterClass Src0RC, RegisterClass Src1RC,
1808                 int NumSrcArgs, bit HasModifiers,
1809                 Operand Src0Mod, Operand Src1Mod> {
1810
1811  dag ret = !if (!eq(NumSrcArgs, 0),
1812                // VOP1 without input operands (V_NOP)
1813                (ins ),
1814            !if (!eq(NumSrcArgs, 1),
1815              !if (HasModifiers,
1816                // VOP1_DPP with modifiers
1817                (ins OldRC:$old, Src0Mod:$src0_modifiers,
1818                     Src0RC:$src0)
1819              /* else */,
1820                // VOP1_DPP without modifiers
1821                (ins OldRC:$old, Src0RC:$src0)
1822              /* endif */),
1823              !if (HasModifiers,
1824                // VOP2_DPP with modifiers
1825                (ins OldRC:$old,
1826                     Src0Mod:$src0_modifiers, Src0RC:$src0,
1827                     Src1Mod:$src1_modifiers, Src1RC:$src1)
1828              /* else */,
1829                // VOP2_DPP without modifiers
1830                (ins OldRC:$old,
1831                     Src0RC:$src0, Src1RC:$src1)
1832                )));
1833}
1834
1835class getInsDPP <RegisterOperand OldRC, RegisterClass Src0RC, RegisterClass Src1RC,
1836                 int NumSrcArgs, bit HasModifiers,
1837                 Operand Src0Mod, Operand Src1Mod> {
1838  dag ret = !con(getInsDPPBase<OldRC, Src0RC, Src1RC, NumSrcArgs,
1839                               HasModifiers, Src0Mod, Src1Mod>.ret,
1840                 (ins dpp_ctrl:$dpp_ctrl, row_mask:$row_mask,
1841                  bank_mask:$bank_mask, bound_ctrl:$bound_ctrl));
1842}
1843
1844class getInsDPP16 <RegisterOperand OldRC, RegisterClass Src0RC, RegisterClass Src1RC,
1845                 int NumSrcArgs, bit HasModifiers,
1846                 Operand Src0Mod, Operand Src1Mod> {
1847  dag ret = !con(getInsDPP<OldRC, Src0RC, Src1RC, NumSrcArgs,
1848                           HasModifiers, Src0Mod, Src1Mod>.ret,
1849                 (ins FI:$fi));
1850}
1851
1852class getInsDPP8 <RegisterOperand OldRC, RegisterClass Src0RC, RegisterClass Src1RC,
1853                 int NumSrcArgs, bit HasModifiers,
1854                 Operand Src0Mod, Operand Src1Mod> {
1855  dag ret = !con(getInsDPPBase<OldRC, Src0RC, Src1RC, NumSrcArgs,
1856                               HasModifiers, Src0Mod, Src1Mod>.ret,
1857                 (ins dpp8:$dpp8, FI:$fi));
1858}
1859
1860
1861// Ins for SDWA
1862class getInsSDWA <RegisterOperand Src0RC, RegisterOperand Src1RC, int NumSrcArgs,
1863                  bit HasSDWAOMod, Operand Src0Mod, Operand Src1Mod,
1864                  ValueType DstVT> {
1865
1866  dag ret = !if(!eq(NumSrcArgs, 0),
1867               // VOP1 without input operands (V_NOP)
1868               (ins),
1869            !if(!eq(NumSrcArgs, 1),
1870               // VOP1
1871               !if(!not(HasSDWAOMod),
1872                  // VOP1_SDWA without omod
1873                  (ins Src0Mod:$src0_modifiers, Src0RC:$src0,
1874                       clampmod:$clamp,
1875                       dst_sel:$dst_sel, dst_unused:$dst_unused,
1876                       src0_sel:$src0_sel),
1877                  // VOP1_SDWA with omod
1878                  (ins Src0Mod:$src0_modifiers, Src0RC:$src0,
1879                       clampmod:$clamp, omod:$omod,
1880                       dst_sel:$dst_sel, dst_unused:$dst_unused,
1881                       src0_sel:$src0_sel)),
1882            !if(!eq(NumSrcArgs, 2),
1883               !if(!eq(DstVT.Size, 1),
1884                  // VOPC_SDWA
1885                  (ins Src0Mod:$src0_modifiers, Src0RC:$src0,
1886                       Src1Mod:$src1_modifiers, Src1RC:$src1,
1887                       clampmod:$clamp, src0_sel:$src0_sel, src1_sel:$src1_sel),
1888                  // VOP2_SDWA
1889                  !if(!not(HasSDWAOMod),
1890                     // VOP2_SDWA without omod
1891                     (ins Src0Mod:$src0_modifiers, Src0RC:$src0,
1892                          Src1Mod:$src1_modifiers, Src1RC:$src1,
1893                          clampmod:$clamp,
1894                          dst_sel:$dst_sel, dst_unused:$dst_unused,
1895                          src0_sel:$src0_sel, src1_sel:$src1_sel),
1896                     // VOP2_SDWA with omod
1897                     (ins Src0Mod:$src0_modifiers, Src0RC:$src0,
1898                          Src1Mod:$src1_modifiers, Src1RC:$src1,
1899                          clampmod:$clamp, omod:$omod,
1900                          dst_sel:$dst_sel, dst_unused:$dst_unused,
1901                          src0_sel:$src0_sel, src1_sel:$src1_sel))),
1902            (ins)/* endif */)));
1903}
1904
1905// Outs for DPP
1906class getOutsDPP <bit HasDst, ValueType DstVT, RegisterOperand DstRCDPP> {
1907  dag ret = !if(HasDst,
1908                !if(!eq(DstVT.Size, 1),
1909                    (outs), // no dst for VOPC, we use "vcc"-token as dst in SDWA VOPC instructions
1910                    (outs DstRCDPP:$vdst)),
1911                (outs)); // V_NOP
1912}
1913
1914// Outs for SDWA
1915class getOutsSDWA <bit HasDst, ValueType DstVT, RegisterOperand DstRCSDWA> {
1916  dag ret = !if(HasDst,
1917                !if(!eq(DstVT.Size, 1),
1918                    (outs DstRCSDWA:$sdst),
1919                    (outs DstRCSDWA:$vdst)),
1920                (outs)); // V_NOP
1921}
1922
1923// Returns the assembly string for the inputs and outputs of a VOP[12C]
1924// instruction.  This does not add the _e32 suffix, so it can be reused
1925// by getAsm64.
1926class getAsm32 <bit HasDst, int NumSrcArgs, ValueType DstVT = i32> {
1927  string dst = !if(!eq(DstVT.Size, 1), "$sdst", "$vdst"); // use $sdst for VOPC
1928  string src0 = ", $src0";
1929  string src1 = ", $src1";
1930  string src2 = ", $src2";
1931  string ret = !if(HasDst, dst, "") #
1932               !if(!eq(NumSrcArgs, 1), src0, "") #
1933               !if(!eq(NumSrcArgs, 2), src0#src1, "") #
1934               !if(!eq(NumSrcArgs, 3), src0#src1#src2, "");
1935}
1936
1937// Returns the assembly string for the inputs and outputs of a VOP3
1938// instruction.
1939class getAsm64 <bit HasDst, int NumSrcArgs, bit HasIntClamp, bit HasModifiers,
1940                bit HasOMod, ValueType DstVT = i32> {
1941  string dst = !if(!eq(DstVT.Size, 1), "$sdst", "$vdst"); // use $sdst for VOPC
1942  string src0 = !if(!eq(NumSrcArgs, 1), "$src0_modifiers", "$src0_modifiers,");
1943  string src1 = !if(!eq(NumSrcArgs, 1), "",
1944                   !if(!eq(NumSrcArgs, 2), " $src1_modifiers",
1945                                           " $src1_modifiers,"));
1946  string src2 = !if(!eq(NumSrcArgs, 3), " $src2_modifiers", "");
1947  string iclamp = !if(HasIntClamp, "$clamp", "");
1948  string ret =
1949  !if(!not(HasModifiers),
1950      getAsm32<HasDst, NumSrcArgs, DstVT>.ret # iclamp,
1951      dst#", "#src0#src1#src2#"$clamp"#!if(HasOMod, "$omod", ""));
1952}
1953
1954// Returns the assembly string for the inputs and outputs of a VOP3P
1955// instruction.
1956class getAsmVOP3P <int NumSrcArgs, bit HasModifiers,
1957                   bit HasClamp> {
1958  string dst = "$vdst";
1959  string src0 = !if(!eq(NumSrcArgs, 1), "$src0", "$src0,");
1960  string src1 = !if(!eq(NumSrcArgs, 1), "",
1961                   !if(!eq(NumSrcArgs, 2), " $src1",
1962                                           " $src1,"));
1963  string src2 = !if(!eq(NumSrcArgs, 3), " $src2", "");
1964
1965  string mods = !if(HasModifiers, "$neg_lo$neg_hi", "");
1966  string clamp = !if(HasClamp, "$clamp", "");
1967
1968  // Each modifier is printed as an array of bits for each operand, so
1969  // all operands are printed as part of src0_modifiers.
1970  string ret = dst#", "#src0#src1#src2#"$op_sel$op_sel_hi"#mods#clamp;
1971}
1972
1973class getAsmVOP3OpSel <int NumSrcArgs,
1974                       bit HasClamp,
1975                       bit Src0HasMods,
1976                       bit Src1HasMods,
1977                       bit Src2HasMods> {
1978  string dst = "$vdst";
1979
1980  string isrc0 = !if(!eq(NumSrcArgs, 1), "$src0", "$src0,");
1981  string isrc1 = !if(!eq(NumSrcArgs, 1), "",
1982                     !if(!eq(NumSrcArgs, 2), " $src1",
1983                                             " $src1,"));
1984  string isrc2 = !if(!eq(NumSrcArgs, 3), " $src2", "");
1985
1986  string fsrc0 = !if(!eq(NumSrcArgs, 1), "$src0_modifiers", "$src0_modifiers,");
1987  string fsrc1 = !if(!eq(NumSrcArgs, 1), "",
1988                     !if(!eq(NumSrcArgs, 2), " $src1_modifiers",
1989                                             " $src1_modifiers,"));
1990  string fsrc2 = !if(!eq(NumSrcArgs, 3), " $src2_modifiers", "");
1991
1992  string src0 = !if(Src0HasMods, fsrc0, isrc0);
1993  string src1 = !if(Src1HasMods, fsrc1, isrc1);
1994  string src2 = !if(Src2HasMods, fsrc2, isrc2);
1995
1996  string clamp = !if(HasClamp, "$clamp", "");
1997
1998  string ret = dst#", "#src0#src1#src2#"$op_sel"#clamp;
1999}
2000
2001class getAsmDPP <bit HasDst, int NumSrcArgs, bit HasModifiers, ValueType DstVT = i32> {
2002  string dst = !if(HasDst,
2003                   !if(!eq(DstVT.Size, 1),
2004                       "$sdst",
2005                       "$vdst"),
2006                    ""); // use $sdst for VOPC
2007  string src0 = !if(!eq(NumSrcArgs, 1), "$src0_modifiers", "$src0_modifiers,");
2008  string src1 = !if(!eq(NumSrcArgs, 1), "",
2009                   !if(!eq(NumSrcArgs, 2), " $src1_modifiers",
2010                                           " $src1_modifiers,"));
2011  string args = !if(!not(HasModifiers),
2012                     getAsm32<0, NumSrcArgs, DstVT>.ret,
2013                     ", "#src0#src1);
2014  string ret = dst#args#" $dpp_ctrl$row_mask$bank_mask$bound_ctrl";
2015}
2016
2017class getAsmDPP16 <bit HasDst, int NumSrcArgs, bit HasModifiers, ValueType DstVT = i32> {
2018  string ret = getAsmDPP<HasDst, NumSrcArgs, HasModifiers, DstVT>.ret#"$fi";
2019}
2020
2021class getAsmDPP8 <bit HasDst, int NumSrcArgs, bit HasModifiers, ValueType DstVT = i32>
2022  : getAsmDPP<HasDst, NumSrcArgs, HasModifiers, DstVT> {
2023  let ret = dst#args#" $dpp8$fi";
2024}
2025
2026
2027class getAsmSDWA <bit HasDst, int NumSrcArgs, ValueType DstVT = i32> {
2028  string dst = !if(HasDst,
2029                   !if(!eq(DstVT.Size, 1),
2030                       " vcc", // use vcc token as dst for VOPC instructions
2031                       "$vdst"),
2032                    "");
2033  string src0 = "$src0_modifiers";
2034  string src1 = "$src1_modifiers";
2035  string args = !if(!eq(NumSrcArgs, 0),
2036                    "",
2037                    !if(!eq(NumSrcArgs, 1),
2038                        ", "#src0#"$clamp",
2039                        ", "#src0#", "#src1#"$clamp"
2040                     )
2041                );
2042  string sdwa = !if(!eq(NumSrcArgs, 0),
2043                    "",
2044                    !if(!eq(NumSrcArgs, 1),
2045                        " $dst_sel $dst_unused $src0_sel",
2046                        !if(!eq(DstVT.Size, 1),
2047                            " $src0_sel $src1_sel", // No dst_sel and dst_unused for VOPC
2048                            " $dst_sel $dst_unused $src0_sel $src1_sel"
2049                        )
2050                    )
2051                );
2052  string ret = dst#args#sdwa;
2053}
2054
2055class getAsmSDWA9 <bit HasDst, bit HasOMod, int NumSrcArgs,
2056                   ValueType DstVT = i32> {
2057  string dst = !if(HasDst,
2058                   !if(!eq(DstVT.Size, 1),
2059                       "$sdst", // VOPC
2060                       "$vdst"), // VOP1/2
2061                    "");
2062  string src0 = "$src0_modifiers";
2063  string src1 = "$src1_modifiers";
2064  string out_mods = !if(!not(HasOMod), "$clamp", "$clamp$omod");
2065  string args = !if(!eq(NumSrcArgs, 0), "",
2066                    !if(!eq(NumSrcArgs, 1),
2067                        ", "#src0,
2068                        ", "#src0#", "#src1
2069                     )
2070                );
2071  string sdwa = !if(!eq(NumSrcArgs, 0), "",
2072                    !if(!eq(NumSrcArgs, 1),
2073                        out_mods#" $dst_sel $dst_unused $src0_sel",
2074                        !if(!eq(DstVT.Size, 1),
2075                            " $src0_sel $src1_sel", // No dst_sel, dst_unused and output modifiers for VOPC
2076                            out_mods#" $dst_sel $dst_unused $src0_sel $src1_sel"
2077                        )
2078                    )
2079                );
2080  string ret = dst#args#sdwa;
2081}
2082
2083class getHas64BitOps <int NumSrcArgs, ValueType DstVT, ValueType Src0VT,
2084                      ValueType Src1VT> {
2085  bit ret = !if(!eq(NumSrcArgs, 3),
2086                0,
2087                !if(!eq(DstVT.Size, 64),
2088                    1,
2089                    !if(!eq(Src0VT.Size, 64),
2090                        1,
2091                        !if(!eq(Src1VT.Size, 64),
2092                            1,
2093                            0
2094                        )
2095                    )
2096                )
2097            );
2098}
2099
2100class getHasSDWA <int NumSrcArgs, ValueType DstVT = i32, ValueType Src0VT = i32,
2101                  ValueType Src1VT = i32> {
2102  bit ret = !if(!eq(NumSrcArgs, 3),
2103                0, // NumSrcArgs == 3 - No SDWA for VOP3
2104                !if(!eq(DstVT.Size, 64),
2105                    0, // 64-bit dst - No SDWA for 64-bit operands
2106                    !if(!eq(Src0VT.Size, 64),
2107                        0, // 64-bit src0
2108                        !if(!eq(Src1VT.Size, 64),
2109                            0, // 64-bit src2
2110                            1
2111                        )
2112                    )
2113                )
2114            );
2115}
2116
2117class getHasDPP <int NumSrcArgs> {
2118  bit ret = !if(!eq(NumSrcArgs, 3),
2119                0, // NumSrcArgs == 3 - No DPP for VOP3
2120                1);
2121}
2122
2123class getHasExt64BitDPP <int NumSrcArgs, ValueType DstVT = i32, ValueType Src0VT = i32,
2124                 ValueType Src1VT = i32> {
2125  bit ret = !and(getHasDPP<NumSrcArgs>.ret,
2126                 getHas64BitOps<NumSrcArgs, DstVT, Src0VT, Src1VT>.ret);
2127}
2128
2129// Function that checks if instruction supports DPP and SDWA
2130class getHasExt <int NumSrcArgs, ValueType DstVT = i32, ValueType Src0VT = i32,
2131                 ValueType Src1VT = i32> {
2132  bit ret = !or(getHasDPP<NumSrcArgs>.ret,
2133                getHasSDWA<NumSrcArgs, DstVT, Src0VT, Src1VT>.ret);
2134}
2135
2136// Return an AGPR+VGPR operand class for the given VGPR register class.
2137class getLdStRegisterOperand<RegisterClass RC> {
2138  RegisterOperand ret =
2139    !if(!eq(RC.Size, 32), AVLdSt_32,
2140      !if(!eq(RC.Size, 64), AVLdSt_64,
2141        !if(!eq(RC.Size, 96), AVLdSt_96,
2142          !if(!eq(RC.Size, 128), AVLdSt_128,
2143            !if(!eq(RC.Size, 160), AVLdSt_160,
2144              RegisterOperand<VReg_1> // invalid register
2145    )))));
2146}
2147
2148class BitOr<bit a, bit b> {
2149  bit ret = !if(a, 1, !if(b, 1, 0));
2150}
2151
2152class BitAnd<bit a, bit b> {
2153  bit ret = !if(a, !if(b, 1, 0), 0);
2154}
2155
2156def PatGenMode {
2157  int NoPattern = 0;
2158  int Pattern   = 1;
2159}
2160
2161class VOPProfile <list<ValueType> _ArgVT, bit _EnableF32SrcMods = 0,
2162                  bit _EnableClamp = 0> {
2163
2164  field list<ValueType> ArgVT = _ArgVT;
2165  field bit EnableF32SrcMods = _EnableF32SrcMods;
2166  field bit EnableClamp = _EnableClamp;
2167
2168  field ValueType DstVT = ArgVT[0];
2169  field ValueType Src0VT = ArgVT[1];
2170  field ValueType Src1VT = ArgVT[2];
2171  field ValueType Src2VT = ArgVT[3];
2172  field RegisterOperand DstRC = getVALUDstForVT<DstVT>.ret;
2173  field RegisterOperand DstRCDPP = getVALUDstForVT<DstVT>.ret;
2174  field RegisterOperand DstRCSDWA = getSDWADstForVT<DstVT>.ret;
2175  field RegisterOperand Src0RC32 = getVOPSrc0ForVT<Src0VT>.ret;
2176  field RegisterClass Src1RC32 = getVregSrcForVT<Src1VT>.ret;
2177  field RegisterOperand Src0RC64 = getVOP3SrcForVT<Src0VT>.ret;
2178  field RegisterOperand Src1RC64 = getVOP3SrcForVT<Src1VT>.ret;
2179  field RegisterOperand Src2RC64 = getVOP3SrcForVT<Src2VT>.ret;
2180  field RegisterClass Src0DPP = getVregSrcForVT<Src0VT>.ret;
2181  field RegisterClass Src1DPP = getVregSrcForVT<Src1VT>.ret;
2182  field RegisterOperand Src0SDWA = getSDWASrcForVT<Src0VT>.ret;
2183  field RegisterOperand Src1SDWA = getSDWASrcForVT<Src0VT>.ret;
2184  field Operand Src0Mod = getSrcMod<Src0VT, EnableF32SrcMods>.ret;
2185  field Operand Src1Mod = getSrcMod<Src1VT, EnableF32SrcMods>.ret;
2186  field Operand Src2Mod = getSrcMod<Src2VT, EnableF32SrcMods>.ret;
2187  field Operand Src0ModDPP = getSrcModDPP<Src0VT>.ret;
2188  field Operand Src1ModDPP = getSrcModDPP<Src1VT>.ret;
2189  field Operand Src0ModSDWA = getSrcModSDWA<Src0VT>.ret;
2190  field Operand Src1ModSDWA = getSrcModSDWA<Src1VT>.ret;
2191
2192
2193  field bit HasDst = !ne(DstVT.Value, untyped.Value);
2194  field bit HasDst32 = HasDst;
2195  field bit EmitDst = HasDst; // force dst encoding, see v_movreld_b32 special case
2196  field bit EmitDstSel = EmitDst;
2197  field int NumSrcArgs = getNumSrcArgs<Src0VT, Src1VT, Src2VT>.ret;
2198  field bit HasSrc0 = !ne(Src0VT.Value, untyped.Value);
2199  field bit HasSrc1 = !ne(Src1VT.Value, untyped.Value);
2200  field bit HasSrc2 = !ne(Src2VT.Value, untyped.Value);
2201
2202  // HasSrc*FloatMods affects the SDWA encoding. We ignore EnableF32SrcMods.
2203  field bit HasSrc0FloatMods = isFloatType<Src0VT>.ret;
2204  field bit HasSrc1FloatMods = isFloatType<Src1VT>.ret;
2205  field bit HasSrc2FloatMods = isFloatType<Src2VT>.ret;
2206
2207  // HasSrc*IntMods affects the SDWA encoding. We ignore EnableF32SrcMods.
2208  field bit HasSrc0IntMods = isIntType<Src0VT>.ret;
2209  field bit HasSrc1IntMods = isIntType<Src1VT>.ret;
2210  field bit HasSrc2IntMods = isIntType<Src2VT>.ret;
2211
2212  field bit HasClamp = !or(isModifierType<Src0VT>.ret, EnableClamp);
2213  field bit HasSDWAClamp = EmitDst;
2214  field bit HasFPClamp = !and(isFloatType<DstVT>.ret, HasClamp);
2215  field bit HasIntClamp = !if(isFloatType<DstVT>.ret, 0, HasClamp);
2216  field bit HasClampLo = HasClamp;
2217  field bit HasClampHi = !and(isPackedType<DstVT>.ret, HasClamp);
2218  field bit HasHigh = 0;
2219
2220  field bit IsPacked = isPackedType<Src0VT>.ret;
2221  field bit HasOpSel = IsPacked;
2222  field bit HasOMod = !if(HasOpSel, 0, isFloatType<DstVT>.ret);
2223  field bit HasSDWAOMod = isFloatType<DstVT>.ret;
2224
2225  field bit HasModifiers = !or(isModifierType<Src0VT>.ret,
2226                               isModifierType<Src1VT>.ret,
2227                               isModifierType<Src2VT>.ret,
2228                               HasOMod,
2229                               EnableF32SrcMods);
2230
2231  field bit HasSrc0Mods = HasModifiers;
2232  field bit HasSrc1Mods = !if(HasModifiers, !or(HasSrc1FloatMods, HasSrc1IntMods), 0);
2233  field bit HasSrc2Mods = !if(HasModifiers, !or(HasSrc2FloatMods, HasSrc2IntMods), 0);
2234
2235  field bit HasExt = getHasExt<NumSrcArgs, DstVT, Src0VT, Src1VT>.ret;
2236  field bit HasExtDPP = getHasDPP<NumSrcArgs>.ret;
2237  field bit HasExt64BitDPP = getHasExt64BitDPP<NumSrcArgs, DstVT, Src0VT, Src1VT>.ret;
2238  field bit HasExtSDWA = getHasSDWA<NumSrcArgs, DstVT, Src0VT, Src1VT>.ret;
2239  field bit HasExtSDWA9 = HasExtSDWA;
2240  field int NeedPatGen = PatGenMode.NoPattern;
2241
2242  field bit IsMAI = 0;
2243  field bit IsDOT = 0;
2244  field bit IsSingle = 0;
2245
2246  field Operand Src0PackedMod = !if(HasSrc0FloatMods, PackedF16InputMods, PackedI16InputMods);
2247  field Operand Src1PackedMod = !if(HasSrc1FloatMods, PackedF16InputMods, PackedI16InputMods);
2248  field Operand Src2PackedMod = !if(HasSrc2FloatMods, PackedF16InputMods, PackedI16InputMods);
2249
2250  field dag Outs = !if(HasDst,(outs DstRC:$vdst),(outs));
2251
2252  // VOP3b instructions are a special case with a second explicit
2253  // output. This is manually overridden for them.
2254  field dag Outs32 = Outs;
2255  field dag Outs64 = Outs;
2256  field dag OutsDPP = getOutsDPP<HasDst, DstVT, DstRCDPP>.ret;
2257  field dag OutsDPP8 = getOutsDPP<HasDst, DstVT, DstRCDPP>.ret;
2258  field dag OutsSDWA = getOutsSDWA<HasDst, DstVT, DstRCSDWA>.ret;
2259
2260  field dag Ins32 = getIns32<Src0RC32, Src1RC32, NumSrcArgs>.ret;
2261  field dag Ins64 = getIns64<Src0RC64, Src1RC64, Src2RC64, NumSrcArgs,
2262                             HasIntClamp, HasModifiers, HasSrc2Mods,
2263                             HasOMod, Src0Mod, Src1Mod, Src2Mod>.ret;
2264  field dag InsVOP3P = getInsVOP3P<Src0RC64, Src1RC64, Src2RC64,
2265                                   NumSrcArgs, HasClamp,
2266                                   Src0PackedMod, Src1PackedMod, Src2PackedMod>.ret;
2267  field dag InsVOP3OpSel = getInsVOP3OpSel<Src0RC64, Src1RC64, Src2RC64,
2268                                NumSrcArgs, HasClamp, HasOMod,
2269                                getOpSelMod<Src0VT>.ret,
2270                                getOpSelMod<Src1VT>.ret,
2271                                getOpSelMod<Src2VT>.ret>.ret;
2272  field dag InsDPP = !if(HasExtDPP,
2273                         getInsDPP<DstRCDPP, Src0DPP, Src1DPP, NumSrcArgs,
2274                                   HasModifiers, Src0ModDPP, Src1ModDPP>.ret,
2275                         (ins));
2276  field dag InsDPP16 = getInsDPP16<DstRCDPP, Src0DPP, Src1DPP, NumSrcArgs,
2277                                   HasModifiers, Src0ModDPP, Src1ModDPP>.ret;
2278  field dag InsDPP8 = getInsDPP8<DstRCDPP, Src0DPP, Src1DPP, NumSrcArgs, 0,
2279                                 Src0ModDPP, Src1ModDPP>.ret;
2280  field dag InsSDWA = getInsSDWA<Src0SDWA, Src1SDWA, NumSrcArgs,
2281                                 HasSDWAOMod, Src0ModSDWA, Src1ModSDWA,
2282                                 DstVT>.ret;
2283
2284
2285  field string Asm32 = getAsm32<HasDst, NumSrcArgs, DstVT>.ret;
2286  field string Asm64 = getAsm64<HasDst, NumSrcArgs, HasIntClamp, HasModifiers, HasOMod, DstVT>.ret;
2287  field string AsmVOP3P = getAsmVOP3P<NumSrcArgs, HasModifiers, HasClamp>.ret;
2288  field string AsmVOP3OpSel = getAsmVOP3OpSel<NumSrcArgs,
2289                                              HasClamp,
2290                                              HasSrc0FloatMods,
2291                                              HasSrc1FloatMods,
2292                                              HasSrc2FloatMods>.ret;
2293  field string AsmDPP = !if(HasExtDPP,
2294                            getAsmDPP<HasDst, NumSrcArgs, HasModifiers, DstVT>.ret, "");
2295  field string AsmDPP16 = getAsmDPP16<HasDst, NumSrcArgs, HasModifiers, DstVT>.ret;
2296  // DPP8 encoding has no fields for modifiers, and it is enforced by setting
2297  // the asm operand name via this HasModifiers flag
2298  field string AsmDPP8 = getAsmDPP8<HasDst, NumSrcArgs, 0 /*HasModifiers*/, DstVT>.ret;
2299  field string AsmSDWA = getAsmSDWA<HasDst, NumSrcArgs, DstVT>.ret;
2300  field string AsmSDWA9 = getAsmSDWA9<HasDst, HasSDWAOMod, NumSrcArgs, DstVT>.ret;
2301
2302  field string TieRegDPP = "$old";
2303}
2304
2305class VOP_NO_EXT <VOPProfile p> : VOPProfile <p.ArgVT> {
2306  let HasExt = 0;
2307  let HasExtDPP = 0;
2308  let HasExt64BitDPP = 0;
2309  let HasExtSDWA = 0;
2310  let HasExtSDWA9 = 0;
2311}
2312
2313class VOP_PAT_GEN <VOPProfile p, int mode=PatGenMode.NoPattern> : VOPProfile <p.ArgVT> {
2314  let NeedPatGen = mode;
2315}
2316
2317def VOP_F16_F16 : VOPProfile <[f16, f16, untyped, untyped]>;
2318def VOP_F16_I16 : VOPProfile <[f16, i16, untyped, untyped]>;
2319def VOP_I16_F16 : VOPProfile <[i16, f16, untyped, untyped]>;
2320
2321def VOP_F16_F16_F16 : VOPProfile <[f16, f16, f16, untyped]>;
2322def VOP_F16_F16_I16 : VOPProfile <[f16, f16, i16, untyped]>;
2323def VOP_F16_F16_I32 : VOPProfile <[f16, f16, i32, untyped]>;
2324def VOP_I16_I16_I16 : VOPProfile <[i16, i16, i16, untyped]>;
2325def VOP_I16_I16_I16_ARITH : VOPProfile <[i16, i16, i16, untyped], 0, /*EnableClamp=*/1>;
2326
2327def VOP_I16_I16_I16_I16 : VOPProfile <[i16, i16, i16, i16, untyped]>;
2328def VOP_F16_F16_F16_F16 : VOPProfile <[f16, f16, f16, f16, untyped]>;
2329
2330def VOP_I32_I16_I16_I32 : VOPProfile <[i32, i16, i16, i32, untyped]>;
2331
2332def VOP_V2F16_V2F16_V2F16 : VOPProfile <[v2f16, v2f16, v2f16, untyped]>;
2333def VOP_V2I16_V2I16_V2I16 : VOPProfile <[v2i16, v2i16, v2i16, untyped]>;
2334def VOP_B32_F16_F16 : VOPProfile <[i32, f16, f16, untyped]>;
2335
2336def VOP_V2F16_V2F16_V2F16_V2F16 : VOPProfile <[v2f16, v2f16, v2f16, v2f16]>;
2337def VOP_V2I16_V2I16_V2I16_V2I16 : VOPProfile <[v2i16, v2i16, v2i16, v2i16]>;
2338def VOP_V2I16_F32_F32 : VOPProfile <[v2i16, f32, f32, untyped]>;
2339def VOP_V2I16_I32_I32 : VOPProfile <[v2i16, i32, i32, untyped]>;
2340
2341def VOP_F32_V2F16_V2F16_V2F16 : VOPProfile <[f32, v2f16, v2f16, v2f16]>;
2342
2343def VOP_NONE : VOPProfile <[untyped, untyped, untyped, untyped]>;
2344
2345def VOP_F32_F32 : VOPProfile <[f32, f32, untyped, untyped]>;
2346def VOP_F32_F64 : VOPProfile <[f32, f64, untyped, untyped]>;
2347def VOP_F32_I32 : VOPProfile <[f32, i32, untyped, untyped]>;
2348def VOP_F64_F32 : VOPProfile <[f64, f32, untyped, untyped]>;
2349def VOP_F64_F64 : VOPProfile <[f64, f64, untyped, untyped]>;
2350def VOP_F64_I32 : VOPProfile <[f64, i32, untyped, untyped]>;
2351def VOP_I32_F32 : VOPProfile <[i32, f32, untyped, untyped]>;
2352def VOP_I32_F64 : VOPProfile <[i32, f64, untyped, untyped]>;
2353def VOP_I32_I32 : VOPProfile <[i32, i32, untyped, untyped]>;
2354def VOP_F16_F32 : VOPProfile <[f16, f32, untyped, untyped]>;
2355def VOP_F32_F16 : VOPProfile <[f32, f16, untyped, untyped]>;
2356def VOP_I64_I64 : VOPProfile <[i64, i64, untyped, untyped]>;
2357
2358def VOP_F32_F32_F16 : VOPProfile <[f32, f32, f16, untyped]>;
2359def VOP_F32_F32_F32 : VOPProfile <[f32, f32, f32, untyped]>;
2360def VOP_F32_F32_I32 : VOPProfile <[f32, f32, i32, untyped]>;
2361def VOP_F64_F64_F64 : VOPProfile <[f64, f64, f64, untyped]>;
2362def VOP_F64_F64_I32 : VOPProfile <[f64, f64, i32, untyped]>;
2363def VOP_I32_F32_F32 : VOPProfile <[i32, f32, f32, untyped]>;
2364def VOP_I32_F32_I32 : VOPProfile <[i32, f32, i32, untyped]>;
2365def VOP_I32_I32_I32 : VOPProfile <[i32, i32, i32, untyped]>;
2366def VOP_I32_I32_I32_ARITH : VOPProfile <[i32, i32, i32, untyped], 0, /*EnableClamp=*/1>;
2367def VOP_V2F16_F32_F32 : VOPProfile <[v2f16, f32, f32, untyped]>;
2368def VOP_F32_F16_F16_F16 : VOPProfile <[f32, f16, f16, f16]>;
2369
2370def VOP_I64_I64_I32 : VOPProfile <[i64, i64, i32, untyped]>;
2371def VOP_I64_I32_I64 : VOPProfile <[i64, i32, i64, untyped]>;
2372def VOP_I64_I64_I64 : VOPProfile <[i64, i64, i64, untyped]>;
2373
2374def VOP_F16_F32_F16_F32 : VOPProfile <[f16, f32, f16, f32]>;
2375def VOP_F32_F32_F16_F16 : VOPProfile <[f32, f32, f16, f16]>;
2376def VOP_F32_F32_F32_F32 : VOPProfile <[f32, f32, f32, f32]>;
2377def VOP_F64_F64_F64_F64 : VOPProfile <[f64, f64, f64, f64]>;
2378def VOP_I32_I32_I32_I32 : VOPProfile <[i32, i32, i32, i32]>;
2379def VOP_I64_I32_I32_I64 : VOPProfile <[i64, i32, i32, i64]>;
2380def VOP_I32_F32_I32_I32 : VOPProfile <[i32, f32, i32, i32]>;
2381def VOP_I64_I64_I32_I64 : VOPProfile <[i64, i64, i32, i64]>;
2382def VOP_V4I32_I64_I32_V4I32 : VOPProfile <[v4i32, i64, i32, v4i32]>;
2383
2384def VOP_F32_V2F16_V2F16_F32 : VOPProfile <[f32, v2f16, v2f16, f32]>;
2385def VOP_I32_V2I16_V2I16_I32 : VOPProfile <[i32, v2i16, v2i16, i32]>;
2386
2387def VOP_V4F32_F32_F32_V4F32       : VOPProfile <[v4f32,  f32,   f32,   v4f32]>;
2388def VOP_V16F32_F32_F32_V16F32     : VOPProfile <[v16f32, f32,   f32,   v16f32]>;
2389def VOP_V32F32_F32_F32_V32F32     : VOPProfile <[v32f32, f32,   f32,   v32f32]>;
2390def VOP_V4F32_V4F16_V4F16_V4F32   : VOPProfile <[v4f32,  v4f16, v4f16, v4f32]>;
2391def VOP_V16F32_V4F16_V4F16_V16F32 : VOPProfile <[v16f32, v4f16, v4f16, v16f32]>;
2392def VOP_V32F32_V4F16_V4F16_V32F32 : VOPProfile <[v32f32, v4f16, v4f16, v32f32]>;
2393def VOP_V4F32_V2I16_V2I16_V4F32   : VOPProfile <[v4f32,  v2i16, v2i16, v4f32]>;
2394def VOP_V16F32_V2I16_V2I16_V16F32 : VOPProfile <[v16f32, v2i16, v2i16, v16f32]>;
2395def VOP_V32F32_V2I16_V2I16_V32F32 : VOPProfile <[v32f32, v2i16, v2i16, v32f32]>;
2396def VOP_V4I32_I32_I32_V4I32       : VOPProfile <[v4i32,  i32,   i32,   v4i32]>;
2397def VOP_V16I32_I32_I32_V16I32     : VOPProfile <[v16i32, i32,   i32,   v16i32]>;
2398def VOP_V32I32_I32_I32_V32I32     : VOPProfile <[v32i32, i32,   i32,   v32i32]>;
2399
2400def VOP_V4F64_F64_F64_V4F64 : VOPProfile <[v4f64, f64, f64, v4f64]>;
2401def VOP_V1F64_F64_F64_V1F64 : VOPProfile <[v1f64, f64, f64, v1f64]>;
2402
2403def VOP_V2F32_V2F32_V2F32_V2F32   : VOPProfile <[v2f32,  v2f32, v2f32, v2f32]>;
2404def VOP_V2F32_V2F32_V2F32         : VOPProfile <[v2f32,  v2f32, v2f32, untyped]>;
2405def VOP_V2I32_V2I32_V2I32         : VOPProfile <[v2i32,  v2i32, v2i32, untyped]>;
2406def VOP_V4F32_V4I16_V4I16_V4F32   : VOPProfile <[v4f32,  v4i16, v4i16, v4f32]>;
2407def VOP_V16F32_V4I16_V4I16_V16F32 : VOPProfile <[v16f32, v4i16, v4i16, v16f32]>;
2408def VOP_V32F32_V4I16_V4I16_V32F32 : VOPProfile <[v32f32, v4i16, v4i16, v32f32]>;
2409
2410class Commutable_REV <string revOp, bit isOrig> {
2411  string RevOp = revOp;
2412  bit IsOrig = isOrig;
2413}
2414
2415class AtomicNoRet <string noRetOp, bit isRet> {
2416  string NoRetOp = noRetOp;
2417  bit IsRet = isRet;
2418}
2419
2420//===----------------------------------------------------------------------===//
2421// Interpolation opcodes
2422//===----------------------------------------------------------------------===//
2423
2424class VINTRPDstOperand <RegisterClass rc> : RegisterOperand <rc, "printVINTRPDst">;
2425
2426class VINTRP_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
2427  VINTRPCommon <outs, ins, "", pattern>,
2428  SIMCInstr<opName, SIEncodingFamily.NONE> {
2429  let isPseudo = 1;
2430  let isCodeGenOnly = 1;
2431}
2432
2433// FIXME-GFX10: WIP.
2434class VINTRP_Real_si <bits <2> op, string opName, dag outs, dag ins,
2435                      string asm, int encodingFamily> :
2436  VINTRPCommon <outs, ins, asm, []>,
2437  VINTRPe <op>,
2438  SIMCInstr<opName, encodingFamily> {
2439}
2440
2441class VINTRP_Real_vi <bits <2> op, string opName, dag outs, dag ins,
2442                      string asm> :
2443  VINTRPCommon <outs, ins, asm, []>,
2444  VINTRPe_vi <op>,
2445  SIMCInstr<opName, SIEncodingFamily.VI> {
2446  let AssemblerPredicate = VIAssemblerPredicate;
2447  let DecoderNamespace = "GFX8";
2448}
2449
2450// FIXME-GFX10: WIP.
2451multiclass VINTRP_m <bits <2> op, dag outs, dag ins, string asm,
2452                     list<dag> pattern = []> {
2453  def "" : VINTRP_Pseudo <NAME, outs, ins, pattern>;
2454
2455  let AssemblerPredicate = isGFX6GFX7, DecoderNamespace = "GFX6GFX7" in {
2456    def _si : VINTRP_Real_si <op, NAME, outs, ins, asm, SIEncodingFamily.SI>;
2457  } // End AssemblerPredicate = isGFX6GFX7, DecoderNamespace = "GFX6GFX7"
2458
2459  def _vi : VINTRP_Real_vi <op, NAME, outs, ins, asm>;
2460
2461  let AssemblerPredicate = isGFX10Plus, DecoderNamespace = "GFX10" in {
2462    def _gfx10 : VINTRP_Real_si<op, NAME, outs, ins, asm, SIEncodingFamily.GFX10>;
2463  } // End AssemblerPredicate = isGFX10Plus, DecoderNamespace = "GFX10"
2464}
2465//===----------------------------------------------------------------------===//
2466// Vector instruction mappings
2467//===----------------------------------------------------------------------===//
2468
2469// Maps an opcode in e32 form to its e64 equivalent
2470def getVOPe64 : InstrMapping {
2471  let FilterClass = "VOP";
2472  let RowFields = ["OpName"];
2473  let ColFields = ["Size", "VOP3"];
2474  let KeyCol = ["4", "0"];
2475  let ValueCols = [["8", "1"]];
2476}
2477
2478// Maps an opcode in e64 form to its e32 equivalent
2479def getVOPe32 : InstrMapping {
2480  let FilterClass = "VOP";
2481  let RowFields = ["OpName"];
2482  let ColFields = ["Size", "VOP3"];
2483  let KeyCol = ["8", "1"];
2484  let ValueCols = [["4", "0"]];
2485}
2486
2487// Maps ordinary instructions to their SDWA counterparts
2488def getSDWAOp : InstrMapping {
2489  let FilterClass = "VOP";
2490  let RowFields = ["OpName"];
2491  let ColFields = ["AsmVariantName"];
2492  let KeyCol = ["Default"];
2493  let ValueCols = [["SDWA"]];
2494}
2495
2496// Maps SDWA instructions to their ordinary counterparts
2497def getBasicFromSDWAOp : InstrMapping {
2498  let FilterClass = "VOP";
2499  let RowFields = ["OpName"];
2500  let ColFields = ["AsmVariantName"];
2501  let KeyCol = ["SDWA"];
2502  let ValueCols = [["Default"]];
2503}
2504
2505// Maps ordinary instructions to their DPP counterparts
2506def getDPPOp32 : InstrMapping {
2507  let FilterClass = "VOP";
2508  let RowFields = ["OpName"];
2509  let ColFields = ["AsmVariantName"];
2510  let KeyCol = ["Default"];
2511  let ValueCols = [["DPP"]];
2512}
2513
2514// Maps an commuted opcode to its original version
2515def getCommuteOrig : InstrMapping {
2516  let FilterClass = "Commutable_REV";
2517  let RowFields = ["RevOp"];
2518  let ColFields = ["IsOrig"];
2519  let KeyCol = ["0"];
2520  let ValueCols = [["1"]];
2521}
2522
2523// Maps an original opcode to its commuted version
2524def getCommuteRev : InstrMapping {
2525  let FilterClass = "Commutable_REV";
2526  let RowFields = ["RevOp"];
2527  let ColFields = ["IsOrig"];
2528  let KeyCol = ["1"];
2529  let ValueCols = [["0"]];
2530}
2531
2532def getMCOpcodeGen : InstrMapping {
2533  let FilterClass = "SIMCInstr";
2534  let RowFields = ["PseudoInstr"];
2535  let ColFields = ["Subtarget"];
2536  let KeyCol = [!cast<string>(SIEncodingFamily.NONE)];
2537  let ValueCols = [[!cast<string>(SIEncodingFamily.SI)],
2538                   [!cast<string>(SIEncodingFamily.VI)],
2539                   [!cast<string>(SIEncodingFamily.SDWA)],
2540                   [!cast<string>(SIEncodingFamily.SDWA9)],
2541                   // GFX80 encoding is added to work around a multiple matching
2542                   // issue for buffer instructions with unpacked d16 data. This
2543                   // does not actually change the encoding, and thus may be
2544                   // removed later.
2545                   [!cast<string>(SIEncodingFamily.GFX80)],
2546                   [!cast<string>(SIEncodingFamily.GFX9)],
2547                   [!cast<string>(SIEncodingFamily.GFX10)],
2548                   [!cast<string>(SIEncodingFamily.SDWA10)],
2549                   [!cast<string>(SIEncodingFamily.GFX90A)],
2550                   [!cast<string>(SIEncodingFamily.GFX940)]];
2551}
2552
2553// Get equivalent SOPK instruction.
2554def getSOPKOp : InstrMapping {
2555  let FilterClass = "SOPKInstTable";
2556  let RowFields = ["BaseCmpOp"];
2557  let ColFields = ["IsSOPK"];
2558  let KeyCol = ["0"];
2559  let ValueCols = [["1"]];
2560}
2561
2562def getAddr64Inst : InstrMapping {
2563  let FilterClass = "MUBUFAddr64Table";
2564  let RowFields = ["OpName"];
2565  let ColFields = ["IsAddr64"];
2566  let KeyCol = ["0"];
2567  let ValueCols = [["1"]];
2568}
2569
2570def getIfAddr64Inst : InstrMapping {
2571  let FilterClass = "MUBUFAddr64Table";
2572  let RowFields = ["OpName"];
2573  let ColFields = ["IsAddr64"];
2574  let KeyCol = ["1"];
2575  let ValueCols = [["1"]];
2576}
2577
2578def getMUBUFNoLdsInst : InstrMapping {
2579  let FilterClass = "MUBUFLdsTable";
2580  let RowFields = ["OpName"];
2581  let ColFields = ["IsLds"];
2582  let KeyCol = ["1"];
2583  let ValueCols = [["0"]];
2584}
2585
2586// Maps an atomic opcode to its returnless version.
2587def getAtomicNoRetOp : InstrMapping {
2588  let FilterClass = "AtomicNoRet";
2589  let RowFields = ["NoRetOp"];
2590  let ColFields = ["IsRet"];
2591  let KeyCol = ["1"];
2592  let ValueCols = [["0"]];
2593}
2594
2595// Maps a GLOBAL to its SADDR form.
2596def getGlobalSaddrOp : InstrMapping {
2597  let FilterClass = "GlobalSaddrTable";
2598  let RowFields = ["SaddrOp"];
2599  let ColFields = ["IsSaddr"];
2600  let KeyCol = ["0"];
2601  let ValueCols = [["1"]];
2602}
2603
2604// Maps a GLOBAL SADDR to its VADDR form.
2605def getGlobalVaddrOp : InstrMapping {
2606  let FilterClass = "GlobalSaddrTable";
2607  let RowFields = ["SaddrOp"];
2608  let ColFields = ["IsSaddr"];
2609  let KeyCol = ["1"];
2610  let ValueCols = [["0"]];
2611}
2612
2613// Maps a v_cmpx opcode with sdst to opcode without sdst.
2614def getVCMPXNoSDstOp : InstrMapping {
2615  let FilterClass = "VCMPXNoSDstTable";
2616  let RowFields = ["NoSDstOp"];
2617  let ColFields = ["HasSDst"];
2618  let KeyCol = ["1"];
2619  let ValueCols = [["0"]];
2620}
2621
2622// Maps a SOPP to a SOPP with S_NOP
2623def getSOPPWithRelaxation : InstrMapping {
2624  let FilterClass = "SOPPRelaxTable";
2625  let RowFields = ["KeyName"];
2626  let ColFields = ["IsRelaxed"];
2627  let KeyCol = ["0"];
2628  let ValueCols = [["1"]];
2629}
2630
2631// Maps flat scratch opcodes by addressing modes
2632def getFlatScratchInstSTfromSS : InstrMapping {
2633  let FilterClass = "FlatScratchInst";
2634  let RowFields = ["SVOp"];
2635  let ColFields = ["Mode"];
2636  let KeyCol = ["SS"];
2637  let ValueCols = [["ST"]];
2638}
2639
2640def getFlatScratchInstSSfromSV : InstrMapping {
2641  let FilterClass = "FlatScratchInst";
2642  let RowFields = ["SVOp"];
2643  let ColFields = ["Mode"];
2644  let KeyCol = ["SV"];
2645  let ValueCols = [["SS"]];
2646}
2647
2648def getFlatScratchInstSVfromSVS : InstrMapping {
2649  let FilterClass = "FlatScratchInst";
2650  let RowFields = ["SVOp"];
2651  let ColFields = ["Mode"];
2652  let KeyCol = ["SVS"];
2653  let ValueCols = [["SV"]];
2654}
2655
2656def getFlatScratchInstSVfromSS : InstrMapping {
2657  let FilterClass = "FlatScratchInst";
2658  let RowFields = ["SVOp"];
2659  let ColFields = ["Mode"];
2660  let KeyCol = ["SS"];
2661  let ValueCols = [["SV"]];
2662}
2663
2664def getMFMAEarlyClobberOp : InstrMapping {
2665  let FilterClass = "MFMATable";
2666  let RowFields = ["FMAOp"];
2667  let ColFields = ["IsMac"];
2668  let KeyCol = ["1"];
2669  let ValueCols = [["0"]];
2670}
2671
2672include "SIInstructions.td"
2673
2674include "DSInstructions.td"
2675include "MIMGInstructions.td"
2676