1 //===- SIInstrInfo.h - SI Instruction Info Interface ------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// Interface definition for SIInstrInfo.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_AMDGPU_SIINSTRINFO_H
15 #define LLVM_LIB_TARGET_AMDGPU_SIINSTRINFO_H
16 
17 #include "AMDGPUMIRFormatter.h"
18 #include "SIRegisterInfo.h"
19 #include "Utils/AMDGPUBaseInfo.h"
20 #include "llvm/ADT/SetVector.h"
21 #include "llvm/CodeGen/TargetInstrInfo.h"
22 #include "llvm/CodeGen/TargetSchedule.h"
23 
24 #define GET_INSTRINFO_HEADER
25 #include "AMDGPUGenInstrInfo.inc"
26 
27 namespace llvm {
28 
29 class APInt;
30 class GCNSubtarget;
31 class LiveVariables;
32 class MachineDominatorTree;
33 class MachineRegisterInfo;
34 class RegScavenger;
35 class TargetRegisterClass;
36 class ScheduleHazardRecognizer;
37 
38 class SIInstrInfo final : public AMDGPUGenInstrInfo {
39 private:
40   const SIRegisterInfo RI;
41   const GCNSubtarget &ST;
42   TargetSchedModel SchedModel;
43   mutable std::unique_ptr<AMDGPUMIRFormatter> Formatter;
44 
45   // The inverse predicate should have the negative value.
46   enum BranchPredicate {
47     INVALID_BR = 0,
48     SCC_TRUE = 1,
49     SCC_FALSE = -1,
50     VCCNZ = 2,
51     VCCZ = -2,
52     EXECNZ = -3,
53     EXECZ = 3
54   };
55 
56   using SetVectorType = SmallSetVector<MachineInstr *, 32>;
57 
58   static unsigned getBranchOpcode(BranchPredicate Cond);
59   static BranchPredicate getBranchPredicate(unsigned Opcode);
60 
61 public:
62   unsigned buildExtractSubReg(MachineBasicBlock::iterator MI,
63                               MachineRegisterInfo &MRI,
64                               MachineOperand &SuperReg,
65                               const TargetRegisterClass *SuperRC,
66                               unsigned SubIdx,
67                               const TargetRegisterClass *SubRC) const;
68   MachineOperand buildExtractSubRegOrImm(MachineBasicBlock::iterator MI,
69                                          MachineRegisterInfo &MRI,
70                                          MachineOperand &SuperReg,
71                                          const TargetRegisterClass *SuperRC,
72                                          unsigned SubIdx,
73                                          const TargetRegisterClass *SubRC) const;
74 private:
75   void swapOperands(MachineInstr &Inst) const;
76 
77   std::pair<bool, MachineBasicBlock *>
78   moveScalarAddSub(SetVectorType &Worklist, MachineInstr &Inst,
79                    MachineDominatorTree *MDT = nullptr) const;
80 
81   void lowerSelect(SetVectorType &Worklist, MachineInstr &Inst,
82                    MachineDominatorTree *MDT = nullptr) const;
83 
84   void lowerScalarAbs(SetVectorType &Worklist,
85                       MachineInstr &Inst) const;
86 
87   void lowerScalarXnor(SetVectorType &Worklist,
88                        MachineInstr &Inst) const;
89 
90   void splitScalarNotBinop(SetVectorType &Worklist,
91                            MachineInstr &Inst,
92                            unsigned Opcode) const;
93 
94   void splitScalarBinOpN2(SetVectorType &Worklist,
95                           MachineInstr &Inst,
96                           unsigned Opcode) const;
97 
98   void splitScalar64BitUnaryOp(SetVectorType &Worklist,
99                                MachineInstr &Inst, unsigned Opcode) const;
100 
101   void splitScalar64BitAddSub(SetVectorType &Worklist, MachineInstr &Inst,
102                               MachineDominatorTree *MDT = nullptr) const;
103 
104   void splitScalar64BitBinaryOp(SetVectorType &Worklist, MachineInstr &Inst,
105                                 unsigned Opcode,
106                                 MachineDominatorTree *MDT = nullptr) const;
107 
108   void splitScalar64BitXnor(SetVectorType &Worklist, MachineInstr &Inst,
109                                 MachineDominatorTree *MDT = nullptr) const;
110 
111   void splitScalar64BitBCNT(SetVectorType &Worklist,
112                             MachineInstr &Inst) const;
113   void splitScalar64BitBFE(SetVectorType &Worklist,
114                            MachineInstr &Inst) const;
115   void movePackToVALU(SetVectorType &Worklist,
116                       MachineRegisterInfo &MRI,
117                       MachineInstr &Inst) const;
118 
119   void addUsersToMoveToVALUWorklist(Register Reg, MachineRegisterInfo &MRI,
120                                     SetVectorType &Worklist) const;
121 
122   void addSCCDefUsersToVALUWorklist(MachineOperand &Op,
123                                     MachineInstr &SCCDefInst,
124                                     SetVectorType &Worklist) const;
125 
126   const TargetRegisterClass *
127   getDestEquivalentVGPRClass(const MachineInstr &Inst) const;
128 
129   bool checkInstOffsetsDoNotOverlap(const MachineInstr &MIa,
130                                     const MachineInstr &MIb) const;
131 
132   Register findUsedSGPR(const MachineInstr &MI, int OpIndices[3]) const;
133 
134 protected:
135   bool swapSourceModifiers(MachineInstr &MI,
136                            MachineOperand &Src0, unsigned Src0OpName,
137                            MachineOperand &Src1, unsigned Src1OpName) const;
138 
139   MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
140                                        unsigned OpIdx0,
141                                        unsigned OpIdx1) const override;
142 
143 public:
144   enum TargetOperandFlags {
145     MO_MASK = 0xf,
146 
147     MO_NONE = 0,
148     // MO_GOTPCREL -> symbol@GOTPCREL -> R_AMDGPU_GOTPCREL.
149     MO_GOTPCREL = 1,
150     // MO_GOTPCREL32_LO -> symbol@gotpcrel32@lo -> R_AMDGPU_GOTPCREL32_LO.
151     MO_GOTPCREL32 = 2,
152     MO_GOTPCREL32_LO = 2,
153     // MO_GOTPCREL32_HI -> symbol@gotpcrel32@hi -> R_AMDGPU_GOTPCREL32_HI.
154     MO_GOTPCREL32_HI = 3,
155     // MO_REL32_LO -> symbol@rel32@lo -> R_AMDGPU_REL32_LO.
156     MO_REL32 = 4,
157     MO_REL32_LO = 4,
158     // MO_REL32_HI -> symbol@rel32@hi -> R_AMDGPU_REL32_HI.
159     MO_REL32_HI = 5,
160 
161     MO_LONG_BRANCH_FORWARD = 6,
162     MO_LONG_BRANCH_BACKWARD = 7,
163 
164     MO_ABS32_LO = 8,
165     MO_ABS32_HI = 9,
166   };
167 
168   explicit SIInstrInfo(const GCNSubtarget &ST);
169 
170   const SIRegisterInfo &getRegisterInfo() const {
171     return RI;
172   }
173 
174   const GCNSubtarget &getSubtarget() const {
175     return ST;
176   }
177 
178   bool isReallyTriviallyReMaterializable(const MachineInstr &MI,
179                                          AAResults *AA) const override;
180 
181   bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
182                                int64_t &Offset1,
183                                int64_t &Offset2) const override;
184 
185   bool getMemOperandsWithOffsetWidth(
186       const MachineInstr &LdSt,
187       SmallVectorImpl<const MachineOperand *> &BaseOps, int64_t &Offset,
188       bool &OffsetIsScalable, unsigned &Width,
189       const TargetRegisterInfo *TRI) const final;
190 
191   bool shouldClusterMemOps(ArrayRef<const MachineOperand *> BaseOps1,
192                            ArrayRef<const MachineOperand *> BaseOps2,
193                            unsigned NumLoads, unsigned NumBytes) const override;
194 
195   bool shouldScheduleLoadsNear(SDNode *Load0, SDNode *Load1, int64_t Offset0,
196                                int64_t Offset1, unsigned NumLoads) const override;
197 
198   void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
199                    const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
200                    bool KillSrc) const override;
201 
202   void materializeImmediate(MachineBasicBlock &MBB,
203                             MachineBasicBlock::iterator MI,
204                             const DebugLoc &DL,
205                             unsigned DestReg,
206                             int64_t Value) const;
207 
208   const TargetRegisterClass *getPreferredSelectRegClass(
209                                unsigned Size) const;
210 
211   Register insertNE(MachineBasicBlock *MBB,
212                     MachineBasicBlock::iterator I, const DebugLoc &DL,
213                     Register SrcReg, int Value) const;
214 
215   Register insertEQ(MachineBasicBlock *MBB,
216                     MachineBasicBlock::iterator I, const DebugLoc &DL,
217                     Register SrcReg, int Value)  const;
218 
219   void storeRegToStackSlot(MachineBasicBlock &MBB,
220                            MachineBasicBlock::iterator MI, Register SrcReg,
221                            bool isKill, int FrameIndex,
222                            const TargetRegisterClass *RC,
223                            const TargetRegisterInfo *TRI) const override;
224 
225   void loadRegFromStackSlot(MachineBasicBlock &MBB,
226                             MachineBasicBlock::iterator MI, Register DestReg,
227                             int FrameIndex, const TargetRegisterClass *RC,
228                             const TargetRegisterInfo *TRI) const override;
229 
230   bool expandPostRAPseudo(MachineInstr &MI) const override;
231 
232   // Splits a V_MOV_B64_DPP_PSEUDO opcode into a pair of v_mov_b32_dpp
233   // instructions. Returns a pair of generated instructions.
234   // Can split either post-RA with physical registers or pre-RA with
235   // virtual registers. In latter case IR needs to be in SSA form and
236   // and a REG_SEQUENCE is produced to define original register.
237   std::pair<MachineInstr*, MachineInstr*>
238   expandMovDPP64(MachineInstr &MI) const;
239 
240   // Returns an opcode that can be used to move a value to a \p DstRC
241   // register.  If there is no hardware instruction that can store to \p
242   // DstRC, then AMDGPU::COPY is returned.
243   unsigned getMovOpcode(const TargetRegisterClass *DstRC) const;
244 
245   const MCInstrDesc &getIndirectRegWriteMovRelPseudo(unsigned VecSize,
246                                                      unsigned EltSize,
247                                                      bool IsSGPR) const;
248 
249   const MCInstrDesc &getIndirectGPRIDXPseudo(unsigned VecSize,
250                                              bool IsIndirectSrc) const;
251   LLVM_READONLY
252   int commuteOpcode(unsigned Opc) const;
253 
254   LLVM_READONLY
255   inline int commuteOpcode(const MachineInstr &MI) const {
256     return commuteOpcode(MI.getOpcode());
257   }
258 
259   bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1,
260                              unsigned &SrcOpIdx2) const override;
261 
262   bool findCommutedOpIndices(MCInstrDesc Desc, unsigned & SrcOpIdx0,
263    unsigned & SrcOpIdx1) const;
264 
265   bool isBranchOffsetInRange(unsigned BranchOpc,
266                              int64_t BrOffset) const override;
267 
268   MachineBasicBlock *getBranchDestBlock(const MachineInstr &MI) const override;
269 
270   unsigned insertIndirectBranch(MachineBasicBlock &MBB,
271                                 MachineBasicBlock &NewDestBB,
272                                 const DebugLoc &DL,
273                                 int64_t BrOffset,
274                                 RegScavenger *RS = nullptr) const override;
275 
276   bool analyzeBranchImpl(MachineBasicBlock &MBB,
277                          MachineBasicBlock::iterator I,
278                          MachineBasicBlock *&TBB,
279                          MachineBasicBlock *&FBB,
280                          SmallVectorImpl<MachineOperand> &Cond,
281                          bool AllowModify) const;
282 
283   bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
284                      MachineBasicBlock *&FBB,
285                      SmallVectorImpl<MachineOperand> &Cond,
286                      bool AllowModify = false) const override;
287 
288   unsigned removeBranch(MachineBasicBlock &MBB,
289                         int *BytesRemoved = nullptr) const override;
290 
291   unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
292                         MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
293                         const DebugLoc &DL,
294                         int *BytesAdded = nullptr) const override;
295 
296   bool reverseBranchCondition(
297     SmallVectorImpl<MachineOperand> &Cond) const override;
298 
299   bool canInsertSelect(const MachineBasicBlock &MBB,
300                        ArrayRef<MachineOperand> Cond, Register DstReg,
301                        Register TrueReg, Register FalseReg, int &CondCycles,
302                        int &TrueCycles, int &FalseCycles) const override;
303 
304   void insertSelect(MachineBasicBlock &MBB,
305                     MachineBasicBlock::iterator I, const DebugLoc &DL,
306                     Register DstReg, ArrayRef<MachineOperand> Cond,
307                     Register TrueReg, Register FalseReg) const override;
308 
309   void insertVectorSelect(MachineBasicBlock &MBB,
310                           MachineBasicBlock::iterator I, const DebugLoc &DL,
311                           Register DstReg, ArrayRef<MachineOperand> Cond,
312                           Register TrueReg, Register FalseReg) const;
313 
314   unsigned getAddressSpaceForPseudoSourceKind(
315              unsigned Kind) const override;
316 
317   bool
318   areMemAccessesTriviallyDisjoint(const MachineInstr &MIa,
319                                   const MachineInstr &MIb) const override;
320 
321   bool isFoldableCopy(const MachineInstr &MI) const;
322 
323   bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg,
324                      MachineRegisterInfo *MRI) const final;
325 
326   unsigned getMachineCSELookAheadLimit() const override { return 500; }
327 
328   MachineInstr *convertToThreeAddress(MachineFunction::iterator &MBB,
329                                       MachineInstr &MI,
330                                       LiveVariables *LV) const override;
331 
332   bool isSchedulingBoundary(const MachineInstr &MI,
333                             const MachineBasicBlock *MBB,
334                             const MachineFunction &MF) const override;
335 
336   static bool isSALU(const MachineInstr &MI) {
337     return MI.getDesc().TSFlags & SIInstrFlags::SALU;
338   }
339 
340   bool isSALU(uint16_t Opcode) const {
341     return get(Opcode).TSFlags & SIInstrFlags::SALU;
342   }
343 
344   static bool isVALU(const MachineInstr &MI) {
345     return MI.getDesc().TSFlags & SIInstrFlags::VALU;
346   }
347 
348   bool isVALU(uint16_t Opcode) const {
349     return get(Opcode).TSFlags & SIInstrFlags::VALU;
350   }
351 
352   static bool isVMEM(const MachineInstr &MI) {
353     return isMUBUF(MI) || isMTBUF(MI) || isMIMG(MI);
354   }
355 
356   bool isVMEM(uint16_t Opcode) const {
357     return isMUBUF(Opcode) || isMTBUF(Opcode) || isMIMG(Opcode);
358   }
359 
360   static bool isSOP1(const MachineInstr &MI) {
361     return MI.getDesc().TSFlags & SIInstrFlags::SOP1;
362   }
363 
364   bool isSOP1(uint16_t Opcode) const {
365     return get(Opcode).TSFlags & SIInstrFlags::SOP1;
366   }
367 
368   static bool isSOP2(const MachineInstr &MI) {
369     return MI.getDesc().TSFlags & SIInstrFlags::SOP2;
370   }
371 
372   bool isSOP2(uint16_t Opcode) const {
373     return get(Opcode).TSFlags & SIInstrFlags::SOP2;
374   }
375 
376   static bool isSOPC(const MachineInstr &MI) {
377     return MI.getDesc().TSFlags & SIInstrFlags::SOPC;
378   }
379 
380   bool isSOPC(uint16_t Opcode) const {
381     return get(Opcode).TSFlags & SIInstrFlags::SOPC;
382   }
383 
384   static bool isSOPK(const MachineInstr &MI) {
385     return MI.getDesc().TSFlags & SIInstrFlags::SOPK;
386   }
387 
388   bool isSOPK(uint16_t Opcode) const {
389     return get(Opcode).TSFlags & SIInstrFlags::SOPK;
390   }
391 
392   static bool isSOPP(const MachineInstr &MI) {
393     return MI.getDesc().TSFlags & SIInstrFlags::SOPP;
394   }
395 
396   bool isSOPP(uint16_t Opcode) const {
397     return get(Opcode).TSFlags & SIInstrFlags::SOPP;
398   }
399 
400   static bool isPacked(const MachineInstr &MI) {
401     return MI.getDesc().TSFlags & SIInstrFlags::IsPacked;
402   }
403 
404   bool isPacked(uint16_t Opcode) const {
405     return get(Opcode).TSFlags & SIInstrFlags::IsPacked;
406   }
407 
408   static bool isVOP1(const MachineInstr &MI) {
409     return MI.getDesc().TSFlags & SIInstrFlags::VOP1;
410   }
411 
412   bool isVOP1(uint16_t Opcode) const {
413     return get(Opcode).TSFlags & SIInstrFlags::VOP1;
414   }
415 
416   static bool isVOP2(const MachineInstr &MI) {
417     return MI.getDesc().TSFlags & SIInstrFlags::VOP2;
418   }
419 
420   bool isVOP2(uint16_t Opcode) const {
421     return get(Opcode).TSFlags & SIInstrFlags::VOP2;
422   }
423 
424   static bool isVOP3(const MachineInstr &MI) {
425     return MI.getDesc().TSFlags & SIInstrFlags::VOP3;
426   }
427 
428   bool isVOP3(uint16_t Opcode) const {
429     return get(Opcode).TSFlags & SIInstrFlags::VOP3;
430   }
431 
432   static bool isSDWA(const MachineInstr &MI) {
433     return MI.getDesc().TSFlags & SIInstrFlags::SDWA;
434   }
435 
436   bool isSDWA(uint16_t Opcode) const {
437     return get(Opcode).TSFlags & SIInstrFlags::SDWA;
438   }
439 
440   static bool isVOPC(const MachineInstr &MI) {
441     return MI.getDesc().TSFlags & SIInstrFlags::VOPC;
442   }
443 
444   bool isVOPC(uint16_t Opcode) const {
445     return get(Opcode).TSFlags & SIInstrFlags::VOPC;
446   }
447 
448   static bool isMUBUF(const MachineInstr &MI) {
449     return MI.getDesc().TSFlags & SIInstrFlags::MUBUF;
450   }
451 
452   bool isMUBUF(uint16_t Opcode) const {
453     return get(Opcode).TSFlags & SIInstrFlags::MUBUF;
454   }
455 
456   static bool isMTBUF(const MachineInstr &MI) {
457     return MI.getDesc().TSFlags & SIInstrFlags::MTBUF;
458   }
459 
460   bool isMTBUF(uint16_t Opcode) const {
461     return get(Opcode).TSFlags & SIInstrFlags::MTBUF;
462   }
463 
464   static bool isSMRD(const MachineInstr &MI) {
465     return MI.getDesc().TSFlags & SIInstrFlags::SMRD;
466   }
467 
468   bool isSMRD(uint16_t Opcode) const {
469     return get(Opcode).TSFlags & SIInstrFlags::SMRD;
470   }
471 
472   bool isBufferSMRD(const MachineInstr &MI) const;
473 
474   static bool isDS(const MachineInstr &MI) {
475     return MI.getDesc().TSFlags & SIInstrFlags::DS;
476   }
477 
478   bool isDS(uint16_t Opcode) const {
479     return get(Opcode).TSFlags & SIInstrFlags::DS;
480   }
481 
482   bool isAlwaysGDS(uint16_t Opcode) const;
483 
484   static bool isMIMG(const MachineInstr &MI) {
485     return MI.getDesc().TSFlags & SIInstrFlags::MIMG;
486   }
487 
488   bool isMIMG(uint16_t Opcode) const {
489     return get(Opcode).TSFlags & SIInstrFlags::MIMG;
490   }
491 
492   static bool isGather4(const MachineInstr &MI) {
493     return MI.getDesc().TSFlags & SIInstrFlags::Gather4;
494   }
495 
496   bool isGather4(uint16_t Opcode) const {
497     return get(Opcode).TSFlags & SIInstrFlags::Gather4;
498   }
499 
500   static bool isFLAT(const MachineInstr &MI) {
501     return MI.getDesc().TSFlags & SIInstrFlags::FLAT;
502   }
503 
504   // Is a FLAT encoded instruction which accesses a specific segment,
505   // i.e. global_* or scratch_*.
506   static bool isSegmentSpecificFLAT(const MachineInstr &MI) {
507     auto Flags = MI.getDesc().TSFlags;
508     return Flags & (SIInstrFlags::IsFlatGlobal | SIInstrFlags::IsFlatScratch);
509   }
510 
511   bool isSegmentSpecificFLAT(uint16_t Opcode) const {
512     auto Flags = get(Opcode).TSFlags;
513     return Flags & (SIInstrFlags::IsFlatGlobal | SIInstrFlags::IsFlatScratch);
514   }
515 
516   static bool isFLATGlobal(const MachineInstr &MI) {
517     return MI.getDesc().TSFlags & SIInstrFlags::IsFlatGlobal;
518   }
519 
520   bool isFLATGlobal(uint16_t Opcode) const {
521     return get(Opcode).TSFlags & SIInstrFlags::IsFlatGlobal;
522   }
523 
524   static bool isFLATScratch(const MachineInstr &MI) {
525     return MI.getDesc().TSFlags & SIInstrFlags::IsFlatScratch;
526   }
527 
528   bool isFLATScratch(uint16_t Opcode) const {
529     return get(Opcode).TSFlags & SIInstrFlags::IsFlatScratch;
530   }
531 
532   // Any FLAT encoded instruction, including global_* and scratch_*.
533   bool isFLAT(uint16_t Opcode) const {
534     return get(Opcode).TSFlags & SIInstrFlags::FLAT;
535   }
536 
537   static bool isEXP(const MachineInstr &MI) {
538     return MI.getDesc().TSFlags & SIInstrFlags::EXP;
539   }
540 
541   bool isEXP(uint16_t Opcode) const {
542     return get(Opcode).TSFlags & SIInstrFlags::EXP;
543   }
544 
545   static bool isAtomicNoRet(const MachineInstr &MI) {
546     return MI.getDesc().TSFlags & SIInstrFlags::IsAtomicNoRet;
547   }
548 
549   bool isAtomicNoRet(uint16_t Opcode) const {
550     return get(Opcode).TSFlags & SIInstrFlags::IsAtomicNoRet;
551   }
552 
553   static bool isAtomicRet(const MachineInstr &MI) {
554     return MI.getDesc().TSFlags & SIInstrFlags::IsAtomicRet;
555   }
556 
557   bool isAtomicRet(uint16_t Opcode) const {
558     return get(Opcode).TSFlags & SIInstrFlags::IsAtomicRet;
559   }
560 
561   static bool isAtomic(const MachineInstr &MI) {
562     return MI.getDesc().TSFlags & (SIInstrFlags::IsAtomicRet |
563                                    SIInstrFlags::IsAtomicNoRet);
564   }
565 
566   bool isAtomic(uint16_t Opcode) const {
567     return get(Opcode).TSFlags & (SIInstrFlags::IsAtomicRet |
568                                   SIInstrFlags::IsAtomicNoRet);
569   }
570 
571   static bool isWQM(const MachineInstr &MI) {
572     return MI.getDesc().TSFlags & SIInstrFlags::WQM;
573   }
574 
575   bool isWQM(uint16_t Opcode) const {
576     return get(Opcode).TSFlags & SIInstrFlags::WQM;
577   }
578 
579   static bool isDisableWQM(const MachineInstr &MI) {
580     return MI.getDesc().TSFlags & SIInstrFlags::DisableWQM;
581   }
582 
583   bool isDisableWQM(uint16_t Opcode) const {
584     return get(Opcode).TSFlags & SIInstrFlags::DisableWQM;
585   }
586 
587   static bool isVGPRSpill(const MachineInstr &MI) {
588     return MI.getDesc().TSFlags & SIInstrFlags::VGPRSpill;
589   }
590 
591   bool isVGPRSpill(uint16_t Opcode) const {
592     return get(Opcode).TSFlags & SIInstrFlags::VGPRSpill;
593   }
594 
595   static bool isSGPRSpill(const MachineInstr &MI) {
596     return MI.getDesc().TSFlags & SIInstrFlags::SGPRSpill;
597   }
598 
599   bool isSGPRSpill(uint16_t Opcode) const {
600     return get(Opcode).TSFlags & SIInstrFlags::SGPRSpill;
601   }
602 
603   static bool isDPP(const MachineInstr &MI) {
604     return MI.getDesc().TSFlags & SIInstrFlags::DPP;
605   }
606 
607   bool isDPP(uint16_t Opcode) const {
608     return get(Opcode).TSFlags & SIInstrFlags::DPP;
609   }
610 
611   static bool isTRANS(const MachineInstr &MI) {
612     return MI.getDesc().TSFlags & SIInstrFlags::TRANS;
613   }
614 
615   bool isTRANS(uint16_t Opcode) const {
616     return get(Opcode).TSFlags & SIInstrFlags::TRANS;
617   }
618 
619   static bool isVOP3P(const MachineInstr &MI) {
620     return MI.getDesc().TSFlags & SIInstrFlags::VOP3P;
621   }
622 
623   bool isVOP3P(uint16_t Opcode) const {
624     return get(Opcode).TSFlags & SIInstrFlags::VOP3P;
625   }
626 
627   static bool isVINTRP(const MachineInstr &MI) {
628     return MI.getDesc().TSFlags & SIInstrFlags::VINTRP;
629   }
630 
631   bool isVINTRP(uint16_t Opcode) const {
632     return get(Opcode).TSFlags & SIInstrFlags::VINTRP;
633   }
634 
635   static bool isMAI(const MachineInstr &MI) {
636     return MI.getDesc().TSFlags & SIInstrFlags::IsMAI;
637   }
638 
639   bool isMAI(uint16_t Opcode) const {
640     return get(Opcode).TSFlags & SIInstrFlags::IsMAI;
641   }
642 
643   static bool isDOT(const MachineInstr &MI) {
644     return MI.getDesc().TSFlags & SIInstrFlags::IsDOT;
645   }
646 
647   bool isDOT(uint16_t Opcode) const {
648     return get(Opcode).TSFlags & SIInstrFlags::IsDOT;
649   }
650 
651   static bool isScalarUnit(const MachineInstr &MI) {
652     return MI.getDesc().TSFlags & (SIInstrFlags::SALU | SIInstrFlags::SMRD);
653   }
654 
655   static bool usesVM_CNT(const MachineInstr &MI) {
656     return MI.getDesc().TSFlags & SIInstrFlags::VM_CNT;
657   }
658 
659   static bool usesLGKM_CNT(const MachineInstr &MI) {
660     return MI.getDesc().TSFlags & SIInstrFlags::LGKM_CNT;
661   }
662 
663   static bool sopkIsZext(const MachineInstr &MI) {
664     return MI.getDesc().TSFlags & SIInstrFlags::SOPK_ZEXT;
665   }
666 
667   bool sopkIsZext(uint16_t Opcode) const {
668     return get(Opcode).TSFlags & SIInstrFlags::SOPK_ZEXT;
669   }
670 
671   /// \returns true if this is an s_store_dword* instruction. This is more
672   /// specific than than isSMEM && mayStore.
673   static bool isScalarStore(const MachineInstr &MI) {
674     return MI.getDesc().TSFlags & SIInstrFlags::SCALAR_STORE;
675   }
676 
677   bool isScalarStore(uint16_t Opcode) const {
678     return get(Opcode).TSFlags & SIInstrFlags::SCALAR_STORE;
679   }
680 
681   static bool isFixedSize(const MachineInstr &MI) {
682     return MI.getDesc().TSFlags & SIInstrFlags::FIXED_SIZE;
683   }
684 
685   bool isFixedSize(uint16_t Opcode) const {
686     return get(Opcode).TSFlags & SIInstrFlags::FIXED_SIZE;
687   }
688 
689   static bool hasFPClamp(const MachineInstr &MI) {
690     return MI.getDesc().TSFlags & SIInstrFlags::FPClamp;
691   }
692 
693   bool hasFPClamp(uint16_t Opcode) const {
694     return get(Opcode).TSFlags & SIInstrFlags::FPClamp;
695   }
696 
697   static bool hasIntClamp(const MachineInstr &MI) {
698     return MI.getDesc().TSFlags & SIInstrFlags::IntClamp;
699   }
700 
701   uint64_t getClampMask(const MachineInstr &MI) const {
702     const uint64_t ClampFlags = SIInstrFlags::FPClamp |
703                                 SIInstrFlags::IntClamp |
704                                 SIInstrFlags::ClampLo |
705                                 SIInstrFlags::ClampHi;
706       return MI.getDesc().TSFlags & ClampFlags;
707   }
708 
709   static bool usesFPDPRounding(const MachineInstr &MI) {
710     return MI.getDesc().TSFlags & SIInstrFlags::FPDPRounding;
711   }
712 
713   bool usesFPDPRounding(uint16_t Opcode) const {
714     return get(Opcode).TSFlags & SIInstrFlags::FPDPRounding;
715   }
716 
717   static bool isFPAtomic(const MachineInstr &MI) {
718     return MI.getDesc().TSFlags & SIInstrFlags::FPAtomic;
719   }
720 
721   bool isFPAtomic(uint16_t Opcode) const {
722     return get(Opcode).TSFlags & SIInstrFlags::FPAtomic;
723   }
724 
725   bool isVGPRCopy(const MachineInstr &MI) const {
726     assert(MI.isCopy());
727     Register Dest = MI.getOperand(0).getReg();
728     const MachineFunction &MF = *MI.getParent()->getParent();
729     const MachineRegisterInfo &MRI = MF.getRegInfo();
730     return !RI.isSGPRReg(MRI, Dest);
731   }
732 
733   bool hasVGPRUses(const MachineInstr &MI) const {
734     const MachineFunction &MF = *MI.getParent()->getParent();
735     const MachineRegisterInfo &MRI = MF.getRegInfo();
736     return llvm::any_of(MI.explicit_uses(),
737                         [&MRI, this](const MachineOperand &MO) {
738       return MO.isReg() && RI.isVGPR(MRI, MO.getReg());});
739   }
740 
741   /// Return true if the instruction modifies the mode register.q
742   static bool modifiesModeRegister(const MachineInstr &MI);
743 
744   /// Whether we must prevent this instruction from executing with EXEC = 0.
745   bool hasUnwantedEffectsWhenEXECEmpty(const MachineInstr &MI) const;
746 
747   /// Returns true if the instruction could potentially depend on the value of
748   /// exec. If false, exec dependencies may safely be ignored.
749   bool mayReadEXEC(const MachineRegisterInfo &MRI, const MachineInstr &MI) const;
750 
751   bool isInlineConstant(const APInt &Imm) const;
752 
753   bool isInlineConstant(const APFloat &Imm) const {
754     return isInlineConstant(Imm.bitcastToAPInt());
755   }
756 
757   bool isInlineConstant(const MachineOperand &MO, uint8_t OperandType) const;
758 
759   bool isInlineConstant(const MachineOperand &MO,
760                         const MCOperandInfo &OpInfo) const {
761     return isInlineConstant(MO, OpInfo.OperandType);
762   }
763 
764   /// \p returns true if \p UseMO is substituted with \p DefMO in \p MI it would
765   /// be an inline immediate.
766   bool isInlineConstant(const MachineInstr &MI,
767                         const MachineOperand &UseMO,
768                         const MachineOperand &DefMO) const {
769     assert(UseMO.getParent() == &MI);
770     int OpIdx = MI.getOperandNo(&UseMO);
771     if (!MI.getDesc().OpInfo || OpIdx >= MI.getDesc().NumOperands) {
772       return false;
773     }
774 
775     return isInlineConstant(DefMO, MI.getDesc().OpInfo[OpIdx]);
776   }
777 
778   /// \p returns true if the operand \p OpIdx in \p MI is a valid inline
779   /// immediate.
780   bool isInlineConstant(const MachineInstr &MI, unsigned OpIdx) const {
781     const MachineOperand &MO = MI.getOperand(OpIdx);
782     return isInlineConstant(MO, MI.getDesc().OpInfo[OpIdx].OperandType);
783   }
784 
785   bool isInlineConstant(const MachineInstr &MI, unsigned OpIdx,
786                         const MachineOperand &MO) const {
787     if (!MI.getDesc().OpInfo || OpIdx >= MI.getDesc().NumOperands)
788       return false;
789 
790     if (MI.isCopy()) {
791       unsigned Size = getOpSize(MI, OpIdx);
792       assert(Size == 8 || Size == 4);
793 
794       uint8_t OpType = (Size == 8) ?
795         AMDGPU::OPERAND_REG_IMM_INT64 : AMDGPU::OPERAND_REG_IMM_INT32;
796       return isInlineConstant(MO, OpType);
797     }
798 
799     return isInlineConstant(MO, MI.getDesc().OpInfo[OpIdx].OperandType);
800   }
801 
802   bool isInlineConstant(const MachineOperand &MO) const {
803     const MachineInstr *Parent = MO.getParent();
804     return isInlineConstant(*Parent, Parent->getOperandNo(&MO));
805   }
806 
807   bool isLiteralConstant(const MachineOperand &MO,
808                          const MCOperandInfo &OpInfo) const {
809     return MO.isImm() && !isInlineConstant(MO, OpInfo.OperandType);
810   }
811 
812   bool isLiteralConstant(const MachineInstr &MI, int OpIdx) const {
813     const MachineOperand &MO = MI.getOperand(OpIdx);
814     return MO.isImm() && !isInlineConstant(MI, OpIdx);
815   }
816 
817   // Returns true if this operand could potentially require a 32-bit literal
818   // operand, but not necessarily. A FrameIndex for example could resolve to an
819   // inline immediate value that will not require an additional 4-bytes; this
820   // assumes that it will.
821   bool isLiteralConstantLike(const MachineOperand &MO,
822                              const MCOperandInfo &OpInfo) const;
823 
824   bool isImmOperandLegal(const MachineInstr &MI, unsigned OpNo,
825                          const MachineOperand &MO) const;
826 
827   /// Return true if this 64-bit VALU instruction has a 32-bit encoding.
828   /// This function will return false if you pass it a 32-bit instruction.
829   bool hasVALU32BitEncoding(unsigned Opcode) const;
830 
831   /// Returns true if this operand uses the constant bus.
832   bool usesConstantBus(const MachineRegisterInfo &MRI,
833                        const MachineOperand &MO,
834                        const MCOperandInfo &OpInfo) const;
835 
836   /// Return true if this instruction has any modifiers.
837   ///  e.g. src[012]_mod, omod, clamp.
838   bool hasModifiers(unsigned Opcode) const;
839 
840   bool hasModifiersSet(const MachineInstr &MI,
841                        unsigned OpName) const;
842   bool hasAnyModifiersSet(const MachineInstr &MI) const;
843 
844   bool canShrink(const MachineInstr &MI,
845                  const MachineRegisterInfo &MRI) const;
846 
847   MachineInstr *buildShrunkInst(MachineInstr &MI,
848                                 unsigned NewOpcode) const;
849 
850   bool verifyInstruction(const MachineInstr &MI,
851                          StringRef &ErrInfo) const override;
852 
853   unsigned getVALUOp(const MachineInstr &MI) const;
854 
855   /// Return the correct register class for \p OpNo.  For target-specific
856   /// instructions, this will return the register class that has been defined
857   /// in tablegen.  For generic instructions, like REG_SEQUENCE it will return
858   /// the register class of its machine operand.
859   /// to infer the correct register class base on the other operands.
860   const TargetRegisterClass *getOpRegClass(const MachineInstr &MI,
861                                            unsigned OpNo) const;
862 
863   /// Return the size in bytes of the operand OpNo on the given
864   // instruction opcode.
865   unsigned getOpSize(uint16_t Opcode, unsigned OpNo) const {
866     const MCOperandInfo &OpInfo = get(Opcode).OpInfo[OpNo];
867 
868     if (OpInfo.RegClass == -1) {
869       // If this is an immediate operand, this must be a 32-bit literal.
870       assert(OpInfo.OperandType == MCOI::OPERAND_IMMEDIATE);
871       return 4;
872     }
873 
874     return RI.getRegSizeInBits(*RI.getRegClass(OpInfo.RegClass)) / 8;
875   }
876 
877   /// This form should usually be preferred since it handles operands
878   /// with unknown register classes.
879   unsigned getOpSize(const MachineInstr &MI, unsigned OpNo) const {
880     const MachineOperand &MO = MI.getOperand(OpNo);
881     if (MO.isReg()) {
882       if (unsigned SubReg = MO.getSubReg()) {
883         return RI.getSubRegIdxSize(SubReg) / 8;
884       }
885     }
886     return RI.getRegSizeInBits(*getOpRegClass(MI, OpNo)) / 8;
887   }
888 
889   /// Legalize the \p OpIndex operand of this instruction by inserting
890   /// a MOV.  For example:
891   /// ADD_I32_e32 VGPR0, 15
892   /// to
893   /// MOV VGPR1, 15
894   /// ADD_I32_e32 VGPR0, VGPR1
895   ///
896   /// If the operand being legalized is a register, then a COPY will be used
897   /// instead of MOV.
898   void legalizeOpWithMove(MachineInstr &MI, unsigned OpIdx) const;
899 
900   /// Check if \p MO is a legal operand if it was the \p OpIdx Operand
901   /// for \p MI.
902   bool isOperandLegal(const MachineInstr &MI, unsigned OpIdx,
903                       const MachineOperand *MO = nullptr) const;
904 
905   /// Check if \p MO would be a valid operand for the given operand
906   /// definition \p OpInfo. Note this does not attempt to validate constant bus
907   /// restrictions (e.g. literal constant usage).
908   bool isLegalVSrcOperand(const MachineRegisterInfo &MRI,
909                           const MCOperandInfo &OpInfo,
910                           const MachineOperand &MO) const;
911 
912   /// Check if \p MO (a register operand) is a legal register for the
913   /// given operand description.
914   bool isLegalRegOperand(const MachineRegisterInfo &MRI,
915                          const MCOperandInfo &OpInfo,
916                          const MachineOperand &MO) const;
917 
918   /// Legalize operands in \p MI by either commuting it or inserting a
919   /// copy of src1.
920   void legalizeOperandsVOP2(MachineRegisterInfo &MRI, MachineInstr &MI) const;
921 
922   /// Fix operands in \p MI to satisfy constant bus requirements.
923   void legalizeOperandsVOP3(MachineRegisterInfo &MRI, MachineInstr &MI) const;
924 
925   /// Copy a value from a VGPR (\p SrcReg) to SGPR.  This function can only
926   /// be used when it is know that the value in SrcReg is same across all
927   /// threads in the wave.
928   /// \returns The SGPR register that \p SrcReg was copied to.
929   Register readlaneVGPRToSGPR(Register SrcReg, MachineInstr &UseMI,
930                               MachineRegisterInfo &MRI) const;
931 
932   void legalizeOperandsSMRD(MachineRegisterInfo &MRI, MachineInstr &MI) const;
933   void legalizeOperandsFLAT(MachineRegisterInfo &MRI, MachineInstr &MI) const;
934 
935   void legalizeGenericOperand(MachineBasicBlock &InsertMBB,
936                               MachineBasicBlock::iterator I,
937                               const TargetRegisterClass *DstRC,
938                               MachineOperand &Op, MachineRegisterInfo &MRI,
939                               const DebugLoc &DL) const;
940 
941   /// Legalize all operands in this instruction.  This function may create new
942   /// instructions and control-flow around \p MI.  If present, \p MDT is
943   /// updated.
944   /// \returns A new basic block that contains \p MI if new blocks were created.
945   MachineBasicBlock *
946   legalizeOperands(MachineInstr &MI, MachineDominatorTree *MDT = nullptr) const;
947 
948   /// Replace this instruction's opcode with the equivalent VALU
949   /// opcode.  This function will also move the users of \p MI to the
950   /// VALU if necessary. If present, \p MDT is updated.
951   MachineBasicBlock *moveToVALU(MachineInstr &MI,
952                                 MachineDominatorTree *MDT = nullptr) const;
953 
954   void insertNoop(MachineBasicBlock &MBB,
955                   MachineBasicBlock::iterator MI) const override;
956 
957   void insertNoops(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
958                    unsigned Quantity) const override;
959 
960   void insertReturn(MachineBasicBlock &MBB) const;
961   /// Return the number of wait states that result from executing this
962   /// instruction.
963   static unsigned getNumWaitStates(const MachineInstr &MI);
964 
965   /// Returns the operand named \p Op.  If \p MI does not have an
966   /// operand named \c Op, this function returns nullptr.
967   LLVM_READONLY
968   MachineOperand *getNamedOperand(MachineInstr &MI, unsigned OperandName) const;
969 
970   LLVM_READONLY
971   const MachineOperand *getNamedOperand(const MachineInstr &MI,
972                                         unsigned OpName) const {
973     return getNamedOperand(const_cast<MachineInstr &>(MI), OpName);
974   }
975 
976   /// Get required immediate operand
977   int64_t getNamedImmOperand(const MachineInstr &MI, unsigned OpName) const {
978     int Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), OpName);
979     return MI.getOperand(Idx).getImm();
980   }
981 
982   uint64_t getDefaultRsrcDataFormat() const;
983   uint64_t getScratchRsrcWords23() const;
984 
985   bool isLowLatencyInstruction(const MachineInstr &MI) const;
986   bool isHighLatencyDef(int Opc) const override;
987 
988   /// Return the descriptor of the target-specific machine instruction
989   /// that corresponds to the specified pseudo or native opcode.
990   const MCInstrDesc &getMCOpcodeFromPseudo(unsigned Opcode) const {
991     return get(pseudoToMCOpcode(Opcode));
992   }
993 
994   unsigned isStackAccess(const MachineInstr &MI, int &FrameIndex) const;
995   unsigned isSGPRStackAccess(const MachineInstr &MI, int &FrameIndex) const;
996 
997   unsigned isLoadFromStackSlot(const MachineInstr &MI,
998                                int &FrameIndex) const override;
999   unsigned isStoreToStackSlot(const MachineInstr &MI,
1000                               int &FrameIndex) const override;
1001 
1002   unsigned getInstBundleSize(const MachineInstr &MI) const;
1003   unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
1004 
1005   bool mayAccessFlatAddressSpace(const MachineInstr &MI) const;
1006 
1007   bool isNonUniformBranchInstr(MachineInstr &Instr) const;
1008 
1009   void convertNonUniformIfRegion(MachineBasicBlock *IfEntry,
1010                                  MachineBasicBlock *IfEnd) const;
1011 
1012   void convertNonUniformLoopRegion(MachineBasicBlock *LoopEntry,
1013                                    MachineBasicBlock *LoopEnd) const;
1014 
1015   std::pair<unsigned, unsigned>
1016   decomposeMachineOperandsTargetFlags(unsigned TF) const override;
1017 
1018   ArrayRef<std::pair<int, const char *>>
1019   getSerializableTargetIndices() const override;
1020 
1021   ArrayRef<std::pair<unsigned, const char *>>
1022   getSerializableDirectMachineOperandTargetFlags() const override;
1023 
1024   ScheduleHazardRecognizer *
1025   CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
1026                                  const ScheduleDAG *DAG) const override;
1027 
1028   ScheduleHazardRecognizer *
1029   CreateTargetPostRAHazardRecognizer(const MachineFunction &MF) const override;
1030 
1031   bool isBasicBlockPrologue(const MachineInstr &MI) const override;
1032 
1033   MachineInstr *createPHIDestinationCopy(MachineBasicBlock &MBB,
1034                                          MachineBasicBlock::iterator InsPt,
1035                                          const DebugLoc &DL, Register Src,
1036                                          Register Dst) const override;
1037 
1038   MachineInstr *createPHISourceCopy(MachineBasicBlock &MBB,
1039                                     MachineBasicBlock::iterator InsPt,
1040                                     const DebugLoc &DL, Register Src,
1041                                     unsigned SrcSubReg,
1042                                     Register Dst) const override;
1043 
1044   bool isWave32() const;
1045 
1046   /// Return a partially built integer add instruction without carry.
1047   /// Caller must add source operands.
1048   /// For pre-GFX9 it will generate unused carry destination operand.
1049   /// TODO: After GFX9 it should return a no-carry operation.
1050   MachineInstrBuilder getAddNoCarry(MachineBasicBlock &MBB,
1051                                     MachineBasicBlock::iterator I,
1052                                     const DebugLoc &DL,
1053                                     Register DestReg) const;
1054 
1055   MachineInstrBuilder getAddNoCarry(MachineBasicBlock &MBB,
1056                                     MachineBasicBlock::iterator I,
1057                                     const DebugLoc &DL,
1058                                     Register DestReg,
1059                                     RegScavenger &RS) const;
1060 
1061   static bool isKillTerminator(unsigned Opcode);
1062   const MCInstrDesc &getKillTerminatorFromPseudo(unsigned Opcode) const;
1063 
1064   static bool isLegalMUBUFImmOffset(unsigned Imm) {
1065     return isUInt<12>(Imm);
1066   }
1067 
1068   /// Returns if \p Offset is legal for the subtarget as the offset to a FLAT
1069   /// encoded instruction. If \p Signed, this is for an instruction that
1070   /// interprets the offset as signed.
1071   bool isLegalFLATOffset(int64_t Offset, unsigned AddrSpace,
1072                          bool Signed) const;
1073 
1074   /// Split \p COffsetVal into {immediate offset field, remainder offset}
1075   /// values.
1076   std::pair<int64_t, int64_t> splitFlatOffset(int64_t COffsetVal,
1077                                               unsigned AddrSpace,
1078                                               bool IsSigned) const;
1079 
1080   /// \brief Return a target-specific opcode if Opcode is a pseudo instruction.
1081   /// Return -1 if the target-specific opcode for the pseudo instruction does
1082   /// not exist. If Opcode is not a pseudo instruction, this is identity.
1083   int pseudoToMCOpcode(int Opcode) const;
1084 
1085   /// \brief Check if this instruction should only be used by assembler.
1086   /// Return true if this opcode should not be used by codegen.
1087   bool isAsmOnlyOpcode(int MCOp) const;
1088 
1089   const TargetRegisterClass *getRegClass(const MCInstrDesc &TID, unsigned OpNum,
1090                                          const TargetRegisterInfo *TRI,
1091                                          const MachineFunction &MF)
1092     const override;
1093 
1094   void fixImplicitOperands(MachineInstr &MI) const;
1095 
1096   MachineInstr *foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI,
1097                                       ArrayRef<unsigned> Ops,
1098                                       MachineBasicBlock::iterator InsertPt,
1099                                       int FrameIndex,
1100                                       LiveIntervals *LIS = nullptr,
1101                                       VirtRegMap *VRM = nullptr) const override;
1102 
1103   unsigned getInstrLatency(const InstrItineraryData *ItinData,
1104                            const MachineInstr &MI,
1105                            unsigned *PredCost = nullptr) const override;
1106 
1107   const MIRFormatter *getMIRFormatter() const override {
1108     if (!Formatter.get())
1109       Formatter = std::make_unique<AMDGPUMIRFormatter>();
1110     return Formatter.get();
1111   }
1112 
1113   static unsigned getDSShaderTypeValue(const MachineFunction &MF);
1114 };
1115 
1116 /// \brief Returns true if a reg:subreg pair P has a TRC class
1117 inline bool isOfRegClass(const TargetInstrInfo::RegSubRegPair &P,
1118                          const TargetRegisterClass &TRC,
1119                          MachineRegisterInfo &MRI) {
1120   auto *RC = MRI.getRegClass(P.Reg);
1121   if (!P.SubReg)
1122     return RC == &TRC;
1123   auto *TRI = MRI.getTargetRegisterInfo();
1124   return RC == TRI->getMatchingSuperRegClass(RC, &TRC, P.SubReg);
1125 }
1126 
1127 /// \brief Create RegSubRegPair from a register MachineOperand
1128 inline
1129 TargetInstrInfo::RegSubRegPair getRegSubRegPair(const MachineOperand &O) {
1130   assert(O.isReg());
1131   return TargetInstrInfo::RegSubRegPair(O.getReg(), O.getSubReg());
1132 }
1133 
1134 /// \brief Return the SubReg component from REG_SEQUENCE
1135 TargetInstrInfo::RegSubRegPair getRegSequenceSubReg(MachineInstr &MI,
1136                                                     unsigned SubReg);
1137 
1138 /// \brief Return the defining instruction for a given reg:subreg pair
1139 /// skipping copy like instructions and subreg-manipulation pseudos.
1140 /// Following another subreg of a reg:subreg isn't supported.
1141 MachineInstr *getVRegSubRegDef(const TargetInstrInfo::RegSubRegPair &P,
1142                                MachineRegisterInfo &MRI);
1143 
1144 /// \brief Return false if EXEC is not changed between the def of \p VReg at \p
1145 /// DefMI and the use at \p UseMI. Should be run on SSA. Currently does not
1146 /// attempt to track between blocks.
1147 bool execMayBeModifiedBeforeUse(const MachineRegisterInfo &MRI,
1148                                 Register VReg,
1149                                 const MachineInstr &DefMI,
1150                                 const MachineInstr &UseMI);
1151 
1152 /// \brief Return false if EXEC is not changed between the def of \p VReg at \p
1153 /// DefMI and all its uses. Should be run on SSA. Currently does not attempt to
1154 /// track between blocks.
1155 bool execMayBeModifiedBeforeAnyUse(const MachineRegisterInfo &MRI,
1156                                    Register VReg,
1157                                    const MachineInstr &DefMI);
1158 
1159 namespace AMDGPU {
1160 
1161   LLVM_READONLY
1162   int getVOPe64(uint16_t Opcode);
1163 
1164   LLVM_READONLY
1165   int getVOPe32(uint16_t Opcode);
1166 
1167   LLVM_READONLY
1168   int getSDWAOp(uint16_t Opcode);
1169 
1170   LLVM_READONLY
1171   int getDPPOp32(uint16_t Opcode);
1172 
1173   LLVM_READONLY
1174   int getBasicFromSDWAOp(uint16_t Opcode);
1175 
1176   LLVM_READONLY
1177   int getCommuteRev(uint16_t Opcode);
1178 
1179   LLVM_READONLY
1180   int getCommuteOrig(uint16_t Opcode);
1181 
1182   LLVM_READONLY
1183   int getAddr64Inst(uint16_t Opcode);
1184 
1185   /// Check if \p Opcode is an Addr64 opcode.
1186   ///
1187   /// \returns \p Opcode if it is an Addr64 opcode, otherwise -1.
1188   LLVM_READONLY
1189   int getIfAddr64Inst(uint16_t Opcode);
1190 
1191   LLVM_READONLY
1192   int getMUBUFNoLdsInst(uint16_t Opcode);
1193 
1194   LLVM_READONLY
1195   int getAtomicNoRetOp(uint16_t Opcode);
1196 
1197   LLVM_READONLY
1198   int getSOPKOp(uint16_t Opcode);
1199 
1200   LLVM_READONLY
1201   int getGlobalSaddrOp(uint16_t Opcode);
1202 
1203   LLVM_READONLY
1204   int getVCMPXNoSDstOp(uint16_t Opcode);
1205 
1206   LLVM_READONLY
1207   int getFlatScratchInstSTfromSS(uint16_t Opcode);
1208 
1209   LLVM_READONLY
1210   int getFlatScratchInstSSfromSV(uint16_t Opcode);
1211 
1212   const uint64_t RSRC_DATA_FORMAT = 0xf00000000000LL;
1213   const uint64_t RSRC_ELEMENT_SIZE_SHIFT = (32 + 19);
1214   const uint64_t RSRC_INDEX_STRIDE_SHIFT = (32 + 21);
1215   const uint64_t RSRC_TID_ENABLE = UINT64_C(1) << (32 + 23);
1216 
1217 } // end namespace AMDGPU
1218 
1219 namespace SI {
1220 namespace KernelInputOffsets {
1221 
1222 /// Offsets in bytes from the start of the input buffer
1223 enum Offsets {
1224   NGROUPS_X = 0,
1225   NGROUPS_Y = 4,
1226   NGROUPS_Z = 8,
1227   GLOBAL_SIZE_X = 12,
1228   GLOBAL_SIZE_Y = 16,
1229   GLOBAL_SIZE_Z = 20,
1230   LOCAL_SIZE_X = 24,
1231   LOCAL_SIZE_Y = 28,
1232   LOCAL_SIZE_Z = 32
1233 };
1234 
1235 } // end namespace KernelInputOffsets
1236 } // end namespace SI
1237 
1238 } // end namespace llvm
1239 
1240 #endif // LLVM_LIB_TARGET_AMDGPU_SIINSTRINFO_H
1241