1 //===- SIInstrInfo.h - SI Instruction Info Interface ------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// Interface definition for SIInstrInfo.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_AMDGPU_SIINSTRINFO_H
15 #define LLVM_LIB_TARGET_AMDGPU_SIINSTRINFO_H
16 
17 #include "AMDGPUMIRFormatter.h"
18 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
19 #include "SIRegisterInfo.h"
20 #include "Utils/AMDGPUBaseInfo.h"
21 #include "llvm/ADT/SetVector.h"
22 #include "llvm/CodeGen/TargetInstrInfo.h"
23 #include "llvm/CodeGen/TargetSchedule.h"
24 
25 #define GET_INSTRINFO_HEADER
26 #include "AMDGPUGenInstrInfo.inc"
27 
28 namespace llvm {
29 
30 class APInt;
31 class GCNSubtarget;
32 class LiveVariables;
33 class MachineDominatorTree;
34 class MachineRegisterInfo;
35 class RegScavenger;
36 class TargetRegisterClass;
37 class ScheduleHazardRecognizer;
38 
39 /// Mark the MMO of a uniform load if there are no potentially clobbering stores
40 /// on any path from the start of an entry function to this load.
41 static const MachineMemOperand::Flags MONoClobber =
42     MachineMemOperand::MOTargetFlag1;
43 
44 class SIInstrInfo final : public AMDGPUGenInstrInfo {
45 private:
46   const SIRegisterInfo RI;
47   const GCNSubtarget &ST;
48   TargetSchedModel SchedModel;
49   mutable std::unique_ptr<AMDGPUMIRFormatter> Formatter;
50 
51   // The inverse predicate should have the negative value.
52   enum BranchPredicate {
53     INVALID_BR = 0,
54     SCC_TRUE = 1,
55     SCC_FALSE = -1,
56     VCCNZ = 2,
57     VCCZ = -2,
58     EXECNZ = -3,
59     EXECZ = 3
60   };
61 
62   using SetVectorType = SmallSetVector<MachineInstr *, 32>;
63 
64   static unsigned getBranchOpcode(BranchPredicate Cond);
65   static BranchPredicate getBranchPredicate(unsigned Opcode);
66 
67 public:
68   unsigned buildExtractSubReg(MachineBasicBlock::iterator MI,
69                               MachineRegisterInfo &MRI,
70                               MachineOperand &SuperReg,
71                               const TargetRegisterClass *SuperRC,
72                               unsigned SubIdx,
73                               const TargetRegisterClass *SubRC) const;
74   MachineOperand buildExtractSubRegOrImm(MachineBasicBlock::iterator MI,
75                                          MachineRegisterInfo &MRI,
76                                          MachineOperand &SuperReg,
77                                          const TargetRegisterClass *SuperRC,
78                                          unsigned SubIdx,
79                                          const TargetRegisterClass *SubRC) const;
80 private:
81   void swapOperands(MachineInstr &Inst) const;
82 
83   std::pair<bool, MachineBasicBlock *>
84   moveScalarAddSub(SetVectorType &Worklist, MachineInstr &Inst,
85                    MachineDominatorTree *MDT = nullptr) const;
86 
87   void lowerSelect(SetVectorType &Worklist, MachineInstr &Inst,
88                    MachineDominatorTree *MDT = nullptr) const;
89 
90   void lowerScalarAbs(SetVectorType &Worklist,
91                       MachineInstr &Inst) const;
92 
93   void lowerScalarXnor(SetVectorType &Worklist,
94                        MachineInstr &Inst) const;
95 
96   void splitScalarNotBinop(SetVectorType &Worklist,
97                            MachineInstr &Inst,
98                            unsigned Opcode) const;
99 
100   void splitScalarBinOpN2(SetVectorType &Worklist,
101                           MachineInstr &Inst,
102                           unsigned Opcode) const;
103 
104   void splitScalar64BitUnaryOp(SetVectorType &Worklist,
105                                MachineInstr &Inst, unsigned Opcode,
106                                bool Swap = false) const;
107 
108   void splitScalar64BitAddSub(SetVectorType &Worklist, MachineInstr &Inst,
109                               MachineDominatorTree *MDT = nullptr) const;
110 
111   void splitScalar64BitBinaryOp(SetVectorType &Worklist, MachineInstr &Inst,
112                                 unsigned Opcode,
113                                 MachineDominatorTree *MDT = nullptr) const;
114 
115   void splitScalar64BitXnor(SetVectorType &Worklist, MachineInstr &Inst,
116                                 MachineDominatorTree *MDT = nullptr) const;
117 
118   void splitScalar64BitBCNT(SetVectorType &Worklist,
119                             MachineInstr &Inst) const;
120   void splitScalar64BitBFE(SetVectorType &Worklist,
121                            MachineInstr &Inst) const;
122   void movePackToVALU(SetVectorType &Worklist,
123                       MachineRegisterInfo &MRI,
124                       MachineInstr &Inst) const;
125 
126   void addUsersToMoveToVALUWorklist(Register Reg, MachineRegisterInfo &MRI,
127                                     SetVectorType &Worklist) const;
128 
129   void addSCCDefUsersToVALUWorklist(MachineOperand &Op,
130                                     MachineInstr &SCCDefInst,
131                                     SetVectorType &Worklist,
132                                     Register NewCond = Register()) const;
133   void addSCCDefsToVALUWorklist(MachineOperand &Op,
134                                 SetVectorType &Worklist) const;
135 
136   const TargetRegisterClass *
137   getDestEquivalentVGPRClass(const MachineInstr &Inst) const;
138 
139   bool checkInstOffsetsDoNotOverlap(const MachineInstr &MIa,
140                                     const MachineInstr &MIb) const;
141 
142   Register findUsedSGPR(const MachineInstr &MI, int OpIndices[3]) const;
143 
144 protected:
145   bool swapSourceModifiers(MachineInstr &MI,
146                            MachineOperand &Src0, unsigned Src0OpName,
147                            MachineOperand &Src1, unsigned Src1OpName) const;
148 
149   MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
150                                        unsigned OpIdx0,
151                                        unsigned OpIdx1) const override;
152 
153 public:
154   enum TargetOperandFlags {
155     MO_MASK = 0xf,
156 
157     MO_NONE = 0,
158     // MO_GOTPCREL -> symbol@GOTPCREL -> R_AMDGPU_GOTPCREL.
159     MO_GOTPCREL = 1,
160     // MO_GOTPCREL32_LO -> symbol@gotpcrel32@lo -> R_AMDGPU_GOTPCREL32_LO.
161     MO_GOTPCREL32 = 2,
162     MO_GOTPCREL32_LO = 2,
163     // MO_GOTPCREL32_HI -> symbol@gotpcrel32@hi -> R_AMDGPU_GOTPCREL32_HI.
164     MO_GOTPCREL32_HI = 3,
165     // MO_REL32_LO -> symbol@rel32@lo -> R_AMDGPU_REL32_LO.
166     MO_REL32 = 4,
167     MO_REL32_LO = 4,
168     // MO_REL32_HI -> symbol@rel32@hi -> R_AMDGPU_REL32_HI.
169     MO_REL32_HI = 5,
170 
171     MO_FAR_BRANCH_OFFSET = 6,
172 
173     MO_ABS32_LO = 8,
174     MO_ABS32_HI = 9,
175   };
176 
177   explicit SIInstrInfo(const GCNSubtarget &ST);
178 
179   const SIRegisterInfo &getRegisterInfo() const {
180     return RI;
181   }
182 
183   const GCNSubtarget &getSubtarget() const {
184     return ST;
185   }
186 
187   bool isReallyTriviallyReMaterializable(const MachineInstr &MI,
188                                          AAResults *AA) const override;
189 
190   bool isIgnorableUse(const MachineOperand &MO) const override;
191 
192   bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
193                                int64_t &Offset1,
194                                int64_t &Offset2) const override;
195 
196   bool getMemOperandsWithOffsetWidth(
197       const MachineInstr &LdSt,
198       SmallVectorImpl<const MachineOperand *> &BaseOps, int64_t &Offset,
199       bool &OffsetIsScalable, unsigned &Width,
200       const TargetRegisterInfo *TRI) const final;
201 
202   bool shouldClusterMemOps(ArrayRef<const MachineOperand *> BaseOps1,
203                            ArrayRef<const MachineOperand *> BaseOps2,
204                            unsigned NumLoads, unsigned NumBytes) const override;
205 
206   bool shouldScheduleLoadsNear(SDNode *Load0, SDNode *Load1, int64_t Offset0,
207                                int64_t Offset1, unsigned NumLoads) const override;
208 
209   void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
210                    const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
211                    bool KillSrc) const override;
212 
213   void materializeImmediate(MachineBasicBlock &MBB,
214                             MachineBasicBlock::iterator MI,
215                             const DebugLoc &DL,
216                             unsigned DestReg,
217                             int64_t Value) const;
218 
219   const TargetRegisterClass *getPreferredSelectRegClass(
220                                unsigned Size) const;
221 
222   Register insertNE(MachineBasicBlock *MBB,
223                     MachineBasicBlock::iterator I, const DebugLoc &DL,
224                     Register SrcReg, int Value) const;
225 
226   Register insertEQ(MachineBasicBlock *MBB,
227                     MachineBasicBlock::iterator I, const DebugLoc &DL,
228                     Register SrcReg, int Value)  const;
229 
230   void storeRegToStackSlot(MachineBasicBlock &MBB,
231                            MachineBasicBlock::iterator MI, Register SrcReg,
232                            bool isKill, int FrameIndex,
233                            const TargetRegisterClass *RC,
234                            const TargetRegisterInfo *TRI) const override;
235 
236   void loadRegFromStackSlot(MachineBasicBlock &MBB,
237                             MachineBasicBlock::iterator MI, Register DestReg,
238                             int FrameIndex, const TargetRegisterClass *RC,
239                             const TargetRegisterInfo *TRI) const override;
240 
241   bool expandPostRAPseudo(MachineInstr &MI) const override;
242 
243   // Splits a V_MOV_B64_DPP_PSEUDO opcode into a pair of v_mov_b32_dpp
244   // instructions. Returns a pair of generated instructions.
245   // Can split either post-RA with physical registers or pre-RA with
246   // virtual registers. In latter case IR needs to be in SSA form and
247   // and a REG_SEQUENCE is produced to define original register.
248   std::pair<MachineInstr*, MachineInstr*>
249   expandMovDPP64(MachineInstr &MI) const;
250 
251   // Returns an opcode that can be used to move a value to a \p DstRC
252   // register.  If there is no hardware instruction that can store to \p
253   // DstRC, then AMDGPU::COPY is returned.
254   unsigned getMovOpcode(const TargetRegisterClass *DstRC) const;
255 
256   const MCInstrDesc &getIndirectRegWriteMovRelPseudo(unsigned VecSize,
257                                                      unsigned EltSize,
258                                                      bool IsSGPR) const;
259 
260   const MCInstrDesc &getIndirectGPRIDXPseudo(unsigned VecSize,
261                                              bool IsIndirectSrc) const;
262   LLVM_READONLY
263   int commuteOpcode(unsigned Opc) const;
264 
265   LLVM_READONLY
266   inline int commuteOpcode(const MachineInstr &MI) const {
267     return commuteOpcode(MI.getOpcode());
268   }
269 
270   bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1,
271                              unsigned &SrcOpIdx2) const override;
272 
273   bool findCommutedOpIndices(MCInstrDesc Desc, unsigned & SrcOpIdx0,
274    unsigned & SrcOpIdx1) const;
275 
276   bool isBranchOffsetInRange(unsigned BranchOpc,
277                              int64_t BrOffset) const override;
278 
279   MachineBasicBlock *getBranchDestBlock(const MachineInstr &MI) const override;
280 
281   void insertIndirectBranch(MachineBasicBlock &MBB,
282                             MachineBasicBlock &NewDestBB,
283                             MachineBasicBlock &RestoreBB, const DebugLoc &DL,
284                             int64_t BrOffset, RegScavenger *RS) const override;
285 
286   bool analyzeBranchImpl(MachineBasicBlock &MBB,
287                          MachineBasicBlock::iterator I,
288                          MachineBasicBlock *&TBB,
289                          MachineBasicBlock *&FBB,
290                          SmallVectorImpl<MachineOperand> &Cond,
291                          bool AllowModify) const;
292 
293   bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
294                      MachineBasicBlock *&FBB,
295                      SmallVectorImpl<MachineOperand> &Cond,
296                      bool AllowModify = false) const override;
297 
298   unsigned removeBranch(MachineBasicBlock &MBB,
299                         int *BytesRemoved = nullptr) const override;
300 
301   unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
302                         MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
303                         const DebugLoc &DL,
304                         int *BytesAdded = nullptr) const override;
305 
306   bool reverseBranchCondition(
307     SmallVectorImpl<MachineOperand> &Cond) const override;
308 
309   bool canInsertSelect(const MachineBasicBlock &MBB,
310                        ArrayRef<MachineOperand> Cond, Register DstReg,
311                        Register TrueReg, Register FalseReg, int &CondCycles,
312                        int &TrueCycles, int &FalseCycles) const override;
313 
314   void insertSelect(MachineBasicBlock &MBB,
315                     MachineBasicBlock::iterator I, const DebugLoc &DL,
316                     Register DstReg, ArrayRef<MachineOperand> Cond,
317                     Register TrueReg, Register FalseReg) const override;
318 
319   void insertVectorSelect(MachineBasicBlock &MBB,
320                           MachineBasicBlock::iterator I, const DebugLoc &DL,
321                           Register DstReg, ArrayRef<MachineOperand> Cond,
322                           Register TrueReg, Register FalseReg) const;
323 
324   bool analyzeCompare(const MachineInstr &MI, Register &SrcReg,
325                       Register &SrcReg2, int64_t &CmpMask,
326                       int64_t &CmpValue) const override;
327 
328   bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
329                             Register SrcReg2, int64_t CmpMask, int64_t CmpValue,
330                             const MachineRegisterInfo *MRI) const override;
331 
332   bool
333   areMemAccessesTriviallyDisjoint(const MachineInstr &MIa,
334                                   const MachineInstr &MIb) const override;
335 
336   static bool isFoldableCopy(const MachineInstr &MI);
337 
338   void removeModOperands(MachineInstr &MI) const;
339 
340   bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg,
341                      MachineRegisterInfo *MRI) const final;
342 
343   unsigned getMachineCSELookAheadLimit() const override { return 500; }
344 
345   MachineInstr *convertToThreeAddress(MachineInstr &MI, LiveVariables *LV,
346                                       LiveIntervals *LIS) const override;
347 
348   bool isSchedulingBoundary(const MachineInstr &MI,
349                             const MachineBasicBlock *MBB,
350                             const MachineFunction &MF) const override;
351 
352   static bool isSALU(const MachineInstr &MI) {
353     return MI.getDesc().TSFlags & SIInstrFlags::SALU;
354   }
355 
356   bool isSALU(uint16_t Opcode) const {
357     return get(Opcode).TSFlags & SIInstrFlags::SALU;
358   }
359 
360   static bool isVALU(const MachineInstr &MI) {
361     return MI.getDesc().TSFlags & SIInstrFlags::VALU;
362   }
363 
364   bool isVALU(uint16_t Opcode) const {
365     return get(Opcode).TSFlags & SIInstrFlags::VALU;
366   }
367 
368   static bool isVMEM(const MachineInstr &MI) {
369     return isMUBUF(MI) || isMTBUF(MI) || isMIMG(MI);
370   }
371 
372   bool isVMEM(uint16_t Opcode) const {
373     return isMUBUF(Opcode) || isMTBUF(Opcode) || isMIMG(Opcode);
374   }
375 
376   static bool isSOP1(const MachineInstr &MI) {
377     return MI.getDesc().TSFlags & SIInstrFlags::SOP1;
378   }
379 
380   bool isSOP1(uint16_t Opcode) const {
381     return get(Opcode).TSFlags & SIInstrFlags::SOP1;
382   }
383 
384   static bool isSOP2(const MachineInstr &MI) {
385     return MI.getDesc().TSFlags & SIInstrFlags::SOP2;
386   }
387 
388   bool isSOP2(uint16_t Opcode) const {
389     return get(Opcode).TSFlags & SIInstrFlags::SOP2;
390   }
391 
392   static bool isSOPC(const MachineInstr &MI) {
393     return MI.getDesc().TSFlags & SIInstrFlags::SOPC;
394   }
395 
396   bool isSOPC(uint16_t Opcode) const {
397     return get(Opcode).TSFlags & SIInstrFlags::SOPC;
398   }
399 
400   static bool isSOPK(const MachineInstr &MI) {
401     return MI.getDesc().TSFlags & SIInstrFlags::SOPK;
402   }
403 
404   bool isSOPK(uint16_t Opcode) const {
405     return get(Opcode).TSFlags & SIInstrFlags::SOPK;
406   }
407 
408   static bool isSOPP(const MachineInstr &MI) {
409     return MI.getDesc().TSFlags & SIInstrFlags::SOPP;
410   }
411 
412   bool isSOPP(uint16_t Opcode) const {
413     return get(Opcode).TSFlags & SIInstrFlags::SOPP;
414   }
415 
416   static bool isPacked(const MachineInstr &MI) {
417     return MI.getDesc().TSFlags & SIInstrFlags::IsPacked;
418   }
419 
420   bool isPacked(uint16_t Opcode) const {
421     return get(Opcode).TSFlags & SIInstrFlags::IsPacked;
422   }
423 
424   static bool isVOP1(const MachineInstr &MI) {
425     return MI.getDesc().TSFlags & SIInstrFlags::VOP1;
426   }
427 
428   bool isVOP1(uint16_t Opcode) const {
429     return get(Opcode).TSFlags & SIInstrFlags::VOP1;
430   }
431 
432   static bool isVOP2(const MachineInstr &MI) {
433     return MI.getDesc().TSFlags & SIInstrFlags::VOP2;
434   }
435 
436   bool isVOP2(uint16_t Opcode) const {
437     return get(Opcode).TSFlags & SIInstrFlags::VOP2;
438   }
439 
440   static bool isVOP3(const MachineInstr &MI) {
441     return MI.getDesc().TSFlags & SIInstrFlags::VOP3;
442   }
443 
444   bool isVOP3(uint16_t Opcode) const {
445     return get(Opcode).TSFlags & SIInstrFlags::VOP3;
446   }
447 
448   static bool isSDWA(const MachineInstr &MI) {
449     return MI.getDesc().TSFlags & SIInstrFlags::SDWA;
450   }
451 
452   bool isSDWA(uint16_t Opcode) const {
453     return get(Opcode).TSFlags & SIInstrFlags::SDWA;
454   }
455 
456   static bool isVOPC(const MachineInstr &MI) {
457     return MI.getDesc().TSFlags & SIInstrFlags::VOPC;
458   }
459 
460   bool isVOPC(uint16_t Opcode) const {
461     return get(Opcode).TSFlags & SIInstrFlags::VOPC;
462   }
463 
464   static bool isMUBUF(const MachineInstr &MI) {
465     return MI.getDesc().TSFlags & SIInstrFlags::MUBUF;
466   }
467 
468   bool isMUBUF(uint16_t Opcode) const {
469     return get(Opcode).TSFlags & SIInstrFlags::MUBUF;
470   }
471 
472   static bool isMTBUF(const MachineInstr &MI) {
473     return MI.getDesc().TSFlags & SIInstrFlags::MTBUF;
474   }
475 
476   bool isMTBUF(uint16_t Opcode) const {
477     return get(Opcode).TSFlags & SIInstrFlags::MTBUF;
478   }
479 
480   static bool isSMRD(const MachineInstr &MI) {
481     return MI.getDesc().TSFlags & SIInstrFlags::SMRD;
482   }
483 
484   bool isSMRD(uint16_t Opcode) const {
485     return get(Opcode).TSFlags & SIInstrFlags::SMRD;
486   }
487 
488   bool isBufferSMRD(const MachineInstr &MI) const;
489 
490   static bool isDS(const MachineInstr &MI) {
491     return MI.getDesc().TSFlags & SIInstrFlags::DS;
492   }
493 
494   bool isDS(uint16_t Opcode) const {
495     return get(Opcode).TSFlags & SIInstrFlags::DS;
496   }
497 
498   bool isAlwaysGDS(uint16_t Opcode) const;
499 
500   static bool isMIMG(const MachineInstr &MI) {
501     return MI.getDesc().TSFlags & SIInstrFlags::MIMG;
502   }
503 
504   bool isMIMG(uint16_t Opcode) const {
505     return get(Opcode).TSFlags & SIInstrFlags::MIMG;
506   }
507 
508   static bool isGather4(const MachineInstr &MI) {
509     return MI.getDesc().TSFlags & SIInstrFlags::Gather4;
510   }
511 
512   bool isGather4(uint16_t Opcode) const {
513     return get(Opcode).TSFlags & SIInstrFlags::Gather4;
514   }
515 
516   static bool isFLAT(const MachineInstr &MI) {
517     return MI.getDesc().TSFlags & SIInstrFlags::FLAT;
518   }
519 
520   // Is a FLAT encoded instruction which accesses a specific segment,
521   // i.e. global_* or scratch_*.
522   static bool isSegmentSpecificFLAT(const MachineInstr &MI) {
523     auto Flags = MI.getDesc().TSFlags;
524     return Flags & (SIInstrFlags::FlatGlobal | SIInstrFlags::FlatScratch);
525   }
526 
527   bool isSegmentSpecificFLAT(uint16_t Opcode) const {
528     auto Flags = get(Opcode).TSFlags;
529     return Flags & (SIInstrFlags::FlatGlobal | SIInstrFlags::FlatScratch);
530   }
531 
532   static bool isFLATGlobal(const MachineInstr &MI) {
533     return MI.getDesc().TSFlags & SIInstrFlags::FlatGlobal;
534   }
535 
536   bool isFLATGlobal(uint16_t Opcode) const {
537     return get(Opcode).TSFlags & SIInstrFlags::FlatGlobal;
538   }
539 
540   static bool isFLATScratch(const MachineInstr &MI) {
541     return MI.getDesc().TSFlags & SIInstrFlags::FlatScratch;
542   }
543 
544   bool isFLATScratch(uint16_t Opcode) const {
545     return get(Opcode).TSFlags & SIInstrFlags::FlatScratch;
546   }
547 
548   // Any FLAT encoded instruction, including global_* and scratch_*.
549   bool isFLAT(uint16_t Opcode) const {
550     return get(Opcode).TSFlags & SIInstrFlags::FLAT;
551   }
552 
553   static bool isEXP(const MachineInstr &MI) {
554     return MI.getDesc().TSFlags & SIInstrFlags::EXP;
555   }
556 
557   static bool isDualSourceBlendEXP(const MachineInstr &MI) {
558     if (!isEXP(MI))
559       return false;
560     unsigned Target = MI.getOperand(0).getImm();
561     return Target == AMDGPU::Exp::ET_DUAL_SRC_BLEND0 ||
562            Target == AMDGPU::Exp::ET_DUAL_SRC_BLEND1;
563   }
564 
565   bool isEXP(uint16_t Opcode) const {
566     return get(Opcode).TSFlags & SIInstrFlags::EXP;
567   }
568 
569   static bool isAtomicNoRet(const MachineInstr &MI) {
570     return MI.getDesc().TSFlags & SIInstrFlags::IsAtomicNoRet;
571   }
572 
573   bool isAtomicNoRet(uint16_t Opcode) const {
574     return get(Opcode).TSFlags & SIInstrFlags::IsAtomicNoRet;
575   }
576 
577   static bool isAtomicRet(const MachineInstr &MI) {
578     return MI.getDesc().TSFlags & SIInstrFlags::IsAtomicRet;
579   }
580 
581   bool isAtomicRet(uint16_t Opcode) const {
582     return get(Opcode).TSFlags & SIInstrFlags::IsAtomicRet;
583   }
584 
585   static bool isAtomic(const MachineInstr &MI) {
586     return MI.getDesc().TSFlags & (SIInstrFlags::IsAtomicRet |
587                                    SIInstrFlags::IsAtomicNoRet);
588   }
589 
590   bool isAtomic(uint16_t Opcode) const {
591     return get(Opcode).TSFlags & (SIInstrFlags::IsAtomicRet |
592                                   SIInstrFlags::IsAtomicNoRet);
593   }
594 
595   static bool isWQM(const MachineInstr &MI) {
596     return MI.getDesc().TSFlags & SIInstrFlags::WQM;
597   }
598 
599   bool isWQM(uint16_t Opcode) const {
600     return get(Opcode).TSFlags & SIInstrFlags::WQM;
601   }
602 
603   static bool isDisableWQM(const MachineInstr &MI) {
604     return MI.getDesc().TSFlags & SIInstrFlags::DisableWQM;
605   }
606 
607   bool isDisableWQM(uint16_t Opcode) const {
608     return get(Opcode).TSFlags & SIInstrFlags::DisableWQM;
609   }
610 
611   static bool isVGPRSpill(const MachineInstr &MI) {
612     return MI.getDesc().TSFlags & SIInstrFlags::VGPRSpill;
613   }
614 
615   bool isVGPRSpill(uint16_t Opcode) const {
616     return get(Opcode).TSFlags & SIInstrFlags::VGPRSpill;
617   }
618 
619   static bool isSGPRSpill(const MachineInstr &MI) {
620     return MI.getDesc().TSFlags & SIInstrFlags::SGPRSpill;
621   }
622 
623   bool isSGPRSpill(uint16_t Opcode) const {
624     return get(Opcode).TSFlags & SIInstrFlags::SGPRSpill;
625   }
626 
627   static bool isDPP(const MachineInstr &MI) {
628     return MI.getDesc().TSFlags & SIInstrFlags::DPP;
629   }
630 
631   bool isDPP(uint16_t Opcode) const {
632     return get(Opcode).TSFlags & SIInstrFlags::DPP;
633   }
634 
635   static bool isTRANS(const MachineInstr &MI) {
636     return MI.getDesc().TSFlags & SIInstrFlags::TRANS;
637   }
638 
639   bool isTRANS(uint16_t Opcode) const {
640     return get(Opcode).TSFlags & SIInstrFlags::TRANS;
641   }
642 
643   static bool isVOP3P(const MachineInstr &MI) {
644     return MI.getDesc().TSFlags & SIInstrFlags::VOP3P;
645   }
646 
647   bool isVOP3P(uint16_t Opcode) const {
648     return get(Opcode).TSFlags & SIInstrFlags::VOP3P;
649   }
650 
651   static bool isVINTRP(const MachineInstr &MI) {
652     return MI.getDesc().TSFlags & SIInstrFlags::VINTRP;
653   }
654 
655   bool isVINTRP(uint16_t Opcode) const {
656     return get(Opcode).TSFlags & SIInstrFlags::VINTRP;
657   }
658 
659   static bool isMAI(const MachineInstr &MI) {
660     return MI.getDesc().TSFlags & SIInstrFlags::IsMAI;
661   }
662 
663   bool isMAI(uint16_t Opcode) const {
664     return get(Opcode).TSFlags & SIInstrFlags::IsMAI;
665   }
666 
667   static bool isMFMA(const MachineInstr &MI) {
668     return isMAI(MI) && MI.getOpcode() != AMDGPU::V_ACCVGPR_WRITE_B32_e64 &&
669            MI.getOpcode() != AMDGPU::V_ACCVGPR_READ_B32_e64;
670   }
671 
672   static bool isDOT(const MachineInstr &MI) {
673     return MI.getDesc().TSFlags & SIInstrFlags::IsDOT;
674   }
675 
676   bool isDOT(uint16_t Opcode) const {
677     return get(Opcode).TSFlags & SIInstrFlags::IsDOT;
678   }
679 
680   static bool isLDSDIR(const MachineInstr &MI) {
681     return MI.getDesc().TSFlags & SIInstrFlags::LDSDIR;
682   }
683 
684   bool isLDSDIR(uint16_t Opcode) const {
685     return get(Opcode).TSFlags & SIInstrFlags::LDSDIR;
686   }
687 
688   static bool isVINTERP(const MachineInstr &MI) {
689     return MI.getDesc().TSFlags & SIInstrFlags::VINTERP;
690   }
691 
692   bool isVINTERP(uint16_t Opcode) const {
693     return get(Opcode).TSFlags & SIInstrFlags::VINTERP;
694   }
695 
696   static bool isScalarUnit(const MachineInstr &MI) {
697     return MI.getDesc().TSFlags & (SIInstrFlags::SALU | SIInstrFlags::SMRD);
698   }
699 
700   static bool usesVM_CNT(const MachineInstr &MI) {
701     return MI.getDesc().TSFlags & SIInstrFlags::VM_CNT;
702   }
703 
704   static bool usesLGKM_CNT(const MachineInstr &MI) {
705     return MI.getDesc().TSFlags & SIInstrFlags::LGKM_CNT;
706   }
707 
708   static bool sopkIsZext(const MachineInstr &MI) {
709     return MI.getDesc().TSFlags & SIInstrFlags::SOPK_ZEXT;
710   }
711 
712   bool sopkIsZext(uint16_t Opcode) const {
713     return get(Opcode).TSFlags & SIInstrFlags::SOPK_ZEXT;
714   }
715 
716   /// \returns true if this is an s_store_dword* instruction. This is more
717   /// specific than than isSMEM && mayStore.
718   static bool isScalarStore(const MachineInstr &MI) {
719     return MI.getDesc().TSFlags & SIInstrFlags::SCALAR_STORE;
720   }
721 
722   bool isScalarStore(uint16_t Opcode) const {
723     return get(Opcode).TSFlags & SIInstrFlags::SCALAR_STORE;
724   }
725 
726   static bool isFixedSize(const MachineInstr &MI) {
727     return MI.getDesc().TSFlags & SIInstrFlags::FIXED_SIZE;
728   }
729 
730   bool isFixedSize(uint16_t Opcode) const {
731     return get(Opcode).TSFlags & SIInstrFlags::FIXED_SIZE;
732   }
733 
734   static bool hasFPClamp(const MachineInstr &MI) {
735     return MI.getDesc().TSFlags & SIInstrFlags::FPClamp;
736   }
737 
738   bool hasFPClamp(uint16_t Opcode) const {
739     return get(Opcode).TSFlags & SIInstrFlags::FPClamp;
740   }
741 
742   static bool hasIntClamp(const MachineInstr &MI) {
743     return MI.getDesc().TSFlags & SIInstrFlags::IntClamp;
744   }
745 
746   uint64_t getClampMask(const MachineInstr &MI) const {
747     const uint64_t ClampFlags = SIInstrFlags::FPClamp |
748                                 SIInstrFlags::IntClamp |
749                                 SIInstrFlags::ClampLo |
750                                 SIInstrFlags::ClampHi;
751       return MI.getDesc().TSFlags & ClampFlags;
752   }
753 
754   static bool usesFPDPRounding(const MachineInstr &MI) {
755     return MI.getDesc().TSFlags & SIInstrFlags::FPDPRounding;
756   }
757 
758   bool usesFPDPRounding(uint16_t Opcode) const {
759     return get(Opcode).TSFlags & SIInstrFlags::FPDPRounding;
760   }
761 
762   static bool isFPAtomic(const MachineInstr &MI) {
763     return MI.getDesc().TSFlags & SIInstrFlags::FPAtomic;
764   }
765 
766   bool isFPAtomic(uint16_t Opcode) const {
767     return get(Opcode).TSFlags & SIInstrFlags::FPAtomic;
768   }
769 
770   bool isVGPRCopy(const MachineInstr &MI) const {
771     assert(MI.isCopy());
772     Register Dest = MI.getOperand(0).getReg();
773     const MachineFunction &MF = *MI.getParent()->getParent();
774     const MachineRegisterInfo &MRI = MF.getRegInfo();
775     return !RI.isSGPRReg(MRI, Dest);
776   }
777 
778   bool hasVGPRUses(const MachineInstr &MI) const {
779     const MachineFunction &MF = *MI.getParent()->getParent();
780     const MachineRegisterInfo &MRI = MF.getRegInfo();
781     return llvm::any_of(MI.explicit_uses(),
782                         [&MRI, this](const MachineOperand &MO) {
783       return MO.isReg() && RI.isVGPR(MRI, MO.getReg());});
784   }
785 
786   /// Return true if the instruction modifies the mode register.q
787   static bool modifiesModeRegister(const MachineInstr &MI);
788 
789   /// Whether we must prevent this instruction from executing with EXEC = 0.
790   bool hasUnwantedEffectsWhenEXECEmpty(const MachineInstr &MI) const;
791 
792   /// Returns true if the instruction could potentially depend on the value of
793   /// exec. If false, exec dependencies may safely be ignored.
794   bool mayReadEXEC(const MachineRegisterInfo &MRI, const MachineInstr &MI) const;
795 
796   bool isInlineConstant(const APInt &Imm) const;
797 
798   bool isInlineConstant(const APFloat &Imm) const {
799     return isInlineConstant(Imm.bitcastToAPInt());
800   }
801 
802   bool isInlineConstant(const MachineOperand &MO, uint8_t OperandType) const;
803 
804   bool isInlineConstant(const MachineOperand &MO,
805                         const MCOperandInfo &OpInfo) const {
806     return isInlineConstant(MO, OpInfo.OperandType);
807   }
808 
809   /// \p returns true if \p UseMO is substituted with \p DefMO in \p MI it would
810   /// be an inline immediate.
811   bool isInlineConstant(const MachineInstr &MI,
812                         const MachineOperand &UseMO,
813                         const MachineOperand &DefMO) const {
814     assert(UseMO.getParent() == &MI);
815     int OpIdx = MI.getOperandNo(&UseMO);
816     if (!MI.getDesc().OpInfo || OpIdx >= MI.getDesc().NumOperands) {
817       return false;
818     }
819 
820     return isInlineConstant(DefMO, MI.getDesc().OpInfo[OpIdx]);
821   }
822 
823   /// \p returns true if the operand \p OpIdx in \p MI is a valid inline
824   /// immediate.
825   bool isInlineConstant(const MachineInstr &MI, unsigned OpIdx) const {
826     const MachineOperand &MO = MI.getOperand(OpIdx);
827     return isInlineConstant(MO, MI.getDesc().OpInfo[OpIdx].OperandType);
828   }
829 
830   bool isInlineConstant(const MachineInstr &MI, unsigned OpIdx,
831                         const MachineOperand &MO) const {
832     if (!MI.getDesc().OpInfo || OpIdx >= MI.getDesc().NumOperands)
833       return false;
834 
835     if (MI.isCopy()) {
836       unsigned Size = getOpSize(MI, OpIdx);
837       assert(Size == 8 || Size == 4);
838 
839       uint8_t OpType = (Size == 8) ?
840         AMDGPU::OPERAND_REG_IMM_INT64 : AMDGPU::OPERAND_REG_IMM_INT32;
841       return isInlineConstant(MO, OpType);
842     }
843 
844     return isInlineConstant(MO, MI.getDesc().OpInfo[OpIdx].OperandType);
845   }
846 
847   bool isInlineConstant(const MachineOperand &MO) const {
848     const MachineInstr *Parent = MO.getParent();
849     return isInlineConstant(*Parent, Parent->getOperandNo(&MO));
850   }
851 
852   bool isLiteralConstant(const MachineOperand &MO,
853                          const MCOperandInfo &OpInfo) const {
854     return MO.isImm() && !isInlineConstant(MO, OpInfo.OperandType);
855   }
856 
857   bool isLiteralConstant(const MachineInstr &MI, int OpIdx) const {
858     const MachineOperand &MO = MI.getOperand(OpIdx);
859     return MO.isImm() && !isInlineConstant(MI, OpIdx);
860   }
861 
862   // Returns true if this operand could potentially require a 32-bit literal
863   // operand, but not necessarily. A FrameIndex for example could resolve to an
864   // inline immediate value that will not require an additional 4-bytes; this
865   // assumes that it will.
866   bool isLiteralConstantLike(const MachineOperand &MO,
867                              const MCOperandInfo &OpInfo) const;
868 
869   bool isImmOperandLegal(const MachineInstr &MI, unsigned OpNo,
870                          const MachineOperand &MO) const;
871 
872   /// Return true if this 64-bit VALU instruction has a 32-bit encoding.
873   /// This function will return false if you pass it a 32-bit instruction.
874   bool hasVALU32BitEncoding(unsigned Opcode) const;
875 
876   /// Returns true if this operand uses the constant bus.
877   bool usesConstantBus(const MachineRegisterInfo &MRI,
878                        const MachineOperand &MO,
879                        const MCOperandInfo &OpInfo) const;
880 
881   /// Return true if this instruction has any modifiers.
882   ///  e.g. src[012]_mod, omod, clamp.
883   bool hasModifiers(unsigned Opcode) const;
884 
885   bool hasModifiersSet(const MachineInstr &MI,
886                        unsigned OpName) const;
887   bool hasAnyModifiersSet(const MachineInstr &MI) const;
888 
889   bool canShrink(const MachineInstr &MI,
890                  const MachineRegisterInfo &MRI) const;
891 
892   MachineInstr *buildShrunkInst(MachineInstr &MI,
893                                 unsigned NewOpcode) const;
894 
895   bool verifyInstruction(const MachineInstr &MI,
896                          StringRef &ErrInfo) const override;
897 
898   unsigned getVALUOp(const MachineInstr &MI) const;
899 
900   /// Return the correct register class for \p OpNo.  For target-specific
901   /// instructions, this will return the register class that has been defined
902   /// in tablegen.  For generic instructions, like REG_SEQUENCE it will return
903   /// the register class of its machine operand.
904   /// to infer the correct register class base on the other operands.
905   const TargetRegisterClass *getOpRegClass(const MachineInstr &MI,
906                                            unsigned OpNo) const;
907 
908   /// Return the size in bytes of the operand OpNo on the given
909   // instruction opcode.
910   unsigned getOpSize(uint16_t Opcode, unsigned OpNo) const {
911     const MCOperandInfo &OpInfo = get(Opcode).OpInfo[OpNo];
912 
913     if (OpInfo.RegClass == -1) {
914       // If this is an immediate operand, this must be a 32-bit literal.
915       assert(OpInfo.OperandType == MCOI::OPERAND_IMMEDIATE);
916       return 4;
917     }
918 
919     return RI.getRegSizeInBits(*RI.getRegClass(OpInfo.RegClass)) / 8;
920   }
921 
922   /// This form should usually be preferred since it handles operands
923   /// with unknown register classes.
924   unsigned getOpSize(const MachineInstr &MI, unsigned OpNo) const {
925     const MachineOperand &MO = MI.getOperand(OpNo);
926     if (MO.isReg()) {
927       if (unsigned SubReg = MO.getSubReg()) {
928         return RI.getSubRegIdxSize(SubReg) / 8;
929       }
930     }
931     return RI.getRegSizeInBits(*getOpRegClass(MI, OpNo)) / 8;
932   }
933 
934   /// Legalize the \p OpIndex operand of this instruction by inserting
935   /// a MOV.  For example:
936   /// ADD_I32_e32 VGPR0, 15
937   /// to
938   /// MOV VGPR1, 15
939   /// ADD_I32_e32 VGPR0, VGPR1
940   ///
941   /// If the operand being legalized is a register, then a COPY will be used
942   /// instead of MOV.
943   void legalizeOpWithMove(MachineInstr &MI, unsigned OpIdx) const;
944 
945   /// Check if \p MO is a legal operand if it was the \p OpIdx Operand
946   /// for \p MI.
947   bool isOperandLegal(const MachineInstr &MI, unsigned OpIdx,
948                       const MachineOperand *MO = nullptr) const;
949 
950   /// Check if \p MO would be a valid operand for the given operand
951   /// definition \p OpInfo. Note this does not attempt to validate constant bus
952   /// restrictions (e.g. literal constant usage).
953   bool isLegalVSrcOperand(const MachineRegisterInfo &MRI,
954                           const MCOperandInfo &OpInfo,
955                           const MachineOperand &MO) const;
956 
957   /// Check if \p MO (a register operand) is a legal register for the
958   /// given operand description.
959   bool isLegalRegOperand(const MachineRegisterInfo &MRI,
960                          const MCOperandInfo &OpInfo,
961                          const MachineOperand &MO) const;
962 
963   /// Legalize operands in \p MI by either commuting it or inserting a
964   /// copy of src1.
965   void legalizeOperandsVOP2(MachineRegisterInfo &MRI, MachineInstr &MI) const;
966 
967   /// Fix operands in \p MI to satisfy constant bus requirements.
968   void legalizeOperandsVOP3(MachineRegisterInfo &MRI, MachineInstr &MI) const;
969 
970   /// Copy a value from a VGPR (\p SrcReg) to SGPR.  This function can only
971   /// be used when it is know that the value in SrcReg is same across all
972   /// threads in the wave.
973   /// \returns The SGPR register that \p SrcReg was copied to.
974   Register readlaneVGPRToSGPR(Register SrcReg, MachineInstr &UseMI,
975                               MachineRegisterInfo &MRI) const;
976 
977   void legalizeOperandsSMRD(MachineRegisterInfo &MRI, MachineInstr &MI) const;
978   void legalizeOperandsFLAT(MachineRegisterInfo &MRI, MachineInstr &MI) const;
979 
980   void legalizeGenericOperand(MachineBasicBlock &InsertMBB,
981                               MachineBasicBlock::iterator I,
982                               const TargetRegisterClass *DstRC,
983                               MachineOperand &Op, MachineRegisterInfo &MRI,
984                               const DebugLoc &DL) const;
985 
986   /// Legalize all operands in this instruction.  This function may create new
987   /// instructions and control-flow around \p MI.  If present, \p MDT is
988   /// updated.
989   /// \returns A new basic block that contains \p MI if new blocks were created.
990   MachineBasicBlock *
991   legalizeOperands(MachineInstr &MI, MachineDominatorTree *MDT = nullptr) const;
992 
993   /// Change SADDR form of a FLAT \p Inst to its VADDR form if saddr operand
994   /// was moved to VGPR. \returns true if succeeded.
995   bool moveFlatAddrToVGPR(MachineInstr &Inst) const;
996 
997   /// Replace this instruction's opcode with the equivalent VALU
998   /// opcode.  This function will also move the users of \p MI to the
999   /// VALU if necessary. If present, \p MDT is updated.
1000   MachineBasicBlock *moveToVALU(MachineInstr &MI,
1001                                 MachineDominatorTree *MDT = nullptr) const;
1002 
1003   void insertNoop(MachineBasicBlock &MBB,
1004                   MachineBasicBlock::iterator MI) const override;
1005 
1006   void insertNoops(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
1007                    unsigned Quantity) const override;
1008 
1009   void insertReturn(MachineBasicBlock &MBB) const;
1010   /// Return the number of wait states that result from executing this
1011   /// instruction.
1012   static unsigned getNumWaitStates(const MachineInstr &MI);
1013 
1014   /// Returns the operand named \p Op.  If \p MI does not have an
1015   /// operand named \c Op, this function returns nullptr.
1016   LLVM_READONLY
1017   MachineOperand *getNamedOperand(MachineInstr &MI, unsigned OperandName) const;
1018 
1019   LLVM_READONLY
1020   const MachineOperand *getNamedOperand(const MachineInstr &MI,
1021                                         unsigned OpName) const {
1022     return getNamedOperand(const_cast<MachineInstr &>(MI), OpName);
1023   }
1024 
1025   /// Get required immediate operand
1026   int64_t getNamedImmOperand(const MachineInstr &MI, unsigned OpName) const {
1027     int Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), OpName);
1028     return MI.getOperand(Idx).getImm();
1029   }
1030 
1031   uint64_t getDefaultRsrcDataFormat() const;
1032   uint64_t getScratchRsrcWords23() const;
1033 
1034   bool isLowLatencyInstruction(const MachineInstr &MI) const;
1035   bool isHighLatencyDef(int Opc) const override;
1036 
1037   /// Return the descriptor of the target-specific machine instruction
1038   /// that corresponds to the specified pseudo or native opcode.
1039   const MCInstrDesc &getMCOpcodeFromPseudo(unsigned Opcode) const {
1040     return get(pseudoToMCOpcode(Opcode));
1041   }
1042 
1043   unsigned isStackAccess(const MachineInstr &MI, int &FrameIndex) const;
1044   unsigned isSGPRStackAccess(const MachineInstr &MI, int &FrameIndex) const;
1045 
1046   unsigned isLoadFromStackSlot(const MachineInstr &MI,
1047                                int &FrameIndex) const override;
1048   unsigned isStoreToStackSlot(const MachineInstr &MI,
1049                               int &FrameIndex) const override;
1050 
1051   unsigned getInstBundleSize(const MachineInstr &MI) const;
1052   unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
1053 
1054   bool mayAccessFlatAddressSpace(const MachineInstr &MI) const;
1055 
1056   bool isNonUniformBranchInstr(MachineInstr &Instr) const;
1057 
1058   void convertNonUniformIfRegion(MachineBasicBlock *IfEntry,
1059                                  MachineBasicBlock *IfEnd) const;
1060 
1061   void convertNonUniformLoopRegion(MachineBasicBlock *LoopEntry,
1062                                    MachineBasicBlock *LoopEnd) const;
1063 
1064   std::pair<unsigned, unsigned>
1065   decomposeMachineOperandsTargetFlags(unsigned TF) const override;
1066 
1067   ArrayRef<std::pair<int, const char *>>
1068   getSerializableTargetIndices() const override;
1069 
1070   ArrayRef<std::pair<unsigned, const char *>>
1071   getSerializableDirectMachineOperandTargetFlags() const override;
1072 
1073   ArrayRef<std::pair<MachineMemOperand::Flags, const char *>>
1074   getSerializableMachineMemOperandTargetFlags() const override;
1075 
1076   ScheduleHazardRecognizer *
1077   CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
1078                                  const ScheduleDAG *DAG) const override;
1079 
1080   ScheduleHazardRecognizer *
1081   CreateTargetPostRAHazardRecognizer(const MachineFunction &MF) const override;
1082 
1083   ScheduleHazardRecognizer *
1084   CreateTargetMIHazardRecognizer(const InstrItineraryData *II,
1085                                  const ScheduleDAGMI *DAG) const override;
1086 
1087   bool isBasicBlockPrologue(const MachineInstr &MI) const override;
1088 
1089   MachineInstr *createPHIDestinationCopy(MachineBasicBlock &MBB,
1090                                          MachineBasicBlock::iterator InsPt,
1091                                          const DebugLoc &DL, Register Src,
1092                                          Register Dst) const override;
1093 
1094   MachineInstr *createPHISourceCopy(MachineBasicBlock &MBB,
1095                                     MachineBasicBlock::iterator InsPt,
1096                                     const DebugLoc &DL, Register Src,
1097                                     unsigned SrcSubReg,
1098                                     Register Dst) const override;
1099 
1100   bool isWave32() const;
1101 
1102   /// Return a partially built integer add instruction without carry.
1103   /// Caller must add source operands.
1104   /// For pre-GFX9 it will generate unused carry destination operand.
1105   /// TODO: After GFX9 it should return a no-carry operation.
1106   MachineInstrBuilder getAddNoCarry(MachineBasicBlock &MBB,
1107                                     MachineBasicBlock::iterator I,
1108                                     const DebugLoc &DL,
1109                                     Register DestReg) const;
1110 
1111   MachineInstrBuilder getAddNoCarry(MachineBasicBlock &MBB,
1112                                     MachineBasicBlock::iterator I,
1113                                     const DebugLoc &DL,
1114                                     Register DestReg,
1115                                     RegScavenger &RS) const;
1116 
1117   static bool isKillTerminator(unsigned Opcode);
1118   const MCInstrDesc &getKillTerminatorFromPseudo(unsigned Opcode) const;
1119 
1120   static bool isLegalMUBUFImmOffset(unsigned Imm) {
1121     return isUInt<12>(Imm);
1122   }
1123 
1124   /// Returns if \p Offset is legal for the subtarget as the offset to a FLAT
1125   /// encoded instruction. If \p Signed, this is for an instruction that
1126   /// interprets the offset as signed.
1127   bool isLegalFLATOffset(int64_t Offset, unsigned AddrSpace,
1128                          uint64_t FlatVariant) const;
1129 
1130   /// Split \p COffsetVal into {immediate offset field, remainder offset}
1131   /// values.
1132   std::pair<int64_t, int64_t> splitFlatOffset(int64_t COffsetVal,
1133                                               unsigned AddrSpace,
1134                                               uint64_t FlatVariant) const;
1135 
1136   /// \brief Return a target-specific opcode if Opcode is a pseudo instruction.
1137   /// Return -1 if the target-specific opcode for the pseudo instruction does
1138   /// not exist. If Opcode is not a pseudo instruction, this is identity.
1139   int pseudoToMCOpcode(int Opcode) const;
1140 
1141   /// \brief Check if this instruction should only be used by assembler.
1142   /// Return true if this opcode should not be used by codegen.
1143   bool isAsmOnlyOpcode(int MCOp) const;
1144 
1145   const TargetRegisterClass *getRegClass(const MCInstrDesc &TID, unsigned OpNum,
1146                                          const TargetRegisterInfo *TRI,
1147                                          const MachineFunction &MF)
1148     const override;
1149 
1150   void fixImplicitOperands(MachineInstr &MI) const;
1151 
1152   MachineInstr *foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI,
1153                                       ArrayRef<unsigned> Ops,
1154                                       MachineBasicBlock::iterator InsertPt,
1155                                       int FrameIndex,
1156                                       LiveIntervals *LIS = nullptr,
1157                                       VirtRegMap *VRM = nullptr) const override;
1158 
1159   unsigned getInstrLatency(const InstrItineraryData *ItinData,
1160                            const MachineInstr &MI,
1161                            unsigned *PredCost = nullptr) const override;
1162 
1163   const MIRFormatter *getMIRFormatter() const override {
1164     if (!Formatter.get())
1165       Formatter = std::make_unique<AMDGPUMIRFormatter>();
1166     return Formatter.get();
1167   }
1168 
1169   static unsigned getDSShaderTypeValue(const MachineFunction &MF);
1170 
1171   const TargetSchedModel &getSchedModel() const { return SchedModel; }
1172 
1173   // Enforce operand's \p OpName even alignment if required by target.
1174   // This is used if an operand is a 32 bit register but needs to be aligned
1175   // regardless.
1176   void enforceOperandRCAlignment(MachineInstr &MI, unsigned OpName) const;
1177 };
1178 
1179 /// \brief Returns true if a reg:subreg pair P has a TRC class
1180 inline bool isOfRegClass(const TargetInstrInfo::RegSubRegPair &P,
1181                          const TargetRegisterClass &TRC,
1182                          MachineRegisterInfo &MRI) {
1183   auto *RC = MRI.getRegClass(P.Reg);
1184   if (!P.SubReg)
1185     return RC == &TRC;
1186   auto *TRI = MRI.getTargetRegisterInfo();
1187   return RC == TRI->getMatchingSuperRegClass(RC, &TRC, P.SubReg);
1188 }
1189 
1190 /// \brief Create RegSubRegPair from a register MachineOperand
1191 inline
1192 TargetInstrInfo::RegSubRegPair getRegSubRegPair(const MachineOperand &O) {
1193   assert(O.isReg());
1194   return TargetInstrInfo::RegSubRegPair(O.getReg(), O.getSubReg());
1195 }
1196 
1197 /// \brief Return the SubReg component from REG_SEQUENCE
1198 TargetInstrInfo::RegSubRegPair getRegSequenceSubReg(MachineInstr &MI,
1199                                                     unsigned SubReg);
1200 
1201 /// \brief Return the defining instruction for a given reg:subreg pair
1202 /// skipping copy like instructions and subreg-manipulation pseudos.
1203 /// Following another subreg of a reg:subreg isn't supported.
1204 MachineInstr *getVRegSubRegDef(const TargetInstrInfo::RegSubRegPair &P,
1205                                MachineRegisterInfo &MRI);
1206 
1207 /// \brief Return false if EXEC is not changed between the def of \p VReg at \p
1208 /// DefMI and the use at \p UseMI. Should be run on SSA. Currently does not
1209 /// attempt to track between blocks.
1210 bool execMayBeModifiedBeforeUse(const MachineRegisterInfo &MRI,
1211                                 Register VReg,
1212                                 const MachineInstr &DefMI,
1213                                 const MachineInstr &UseMI);
1214 
1215 /// \brief Return false if EXEC is not changed between the def of \p VReg at \p
1216 /// DefMI and all its uses. Should be run on SSA. Currently does not attempt to
1217 /// track between blocks.
1218 bool execMayBeModifiedBeforeAnyUse(const MachineRegisterInfo &MRI,
1219                                    Register VReg,
1220                                    const MachineInstr &DefMI);
1221 
1222 namespace AMDGPU {
1223 
1224   LLVM_READONLY
1225   int getVOPe64(uint16_t Opcode);
1226 
1227   LLVM_READONLY
1228   int getVOPe32(uint16_t Opcode);
1229 
1230   LLVM_READONLY
1231   int getSDWAOp(uint16_t Opcode);
1232 
1233   LLVM_READONLY
1234   int getDPPOp32(uint16_t Opcode);
1235 
1236   LLVM_READONLY
1237   int getBasicFromSDWAOp(uint16_t Opcode);
1238 
1239   LLVM_READONLY
1240   int getCommuteRev(uint16_t Opcode);
1241 
1242   LLVM_READONLY
1243   int getCommuteOrig(uint16_t Opcode);
1244 
1245   LLVM_READONLY
1246   int getAddr64Inst(uint16_t Opcode);
1247 
1248   /// Check if \p Opcode is an Addr64 opcode.
1249   ///
1250   /// \returns \p Opcode if it is an Addr64 opcode, otherwise -1.
1251   LLVM_READONLY
1252   int getIfAddr64Inst(uint16_t Opcode);
1253 
1254   LLVM_READONLY
1255   int getAtomicNoRetOp(uint16_t Opcode);
1256 
1257   LLVM_READONLY
1258   int getSOPKOp(uint16_t Opcode);
1259 
1260   /// \returns SADDR form of a FLAT Global instruction given an \p Opcode
1261   /// of a VADDR form.
1262   LLVM_READONLY
1263   int getGlobalSaddrOp(uint16_t Opcode);
1264 
1265   /// \returns VADDR form of a FLAT Global instruction given an \p Opcode
1266   /// of a SADDR form.
1267   LLVM_READONLY
1268   int getGlobalVaddrOp(uint16_t Opcode);
1269 
1270   LLVM_READONLY
1271   int getVCMPXNoSDstOp(uint16_t Opcode);
1272 
1273   /// \returns ST form with only immediate offset of a FLAT Scratch instruction
1274   /// given an \p Opcode of an SS (SADDR) form.
1275   LLVM_READONLY
1276   int getFlatScratchInstSTfromSS(uint16_t Opcode);
1277 
1278   /// \returns SV (VADDR) form of a FLAT Scratch instruction given an \p Opcode
1279   /// of an SVS (SADDR + VADDR) form.
1280   LLVM_READONLY
1281   int getFlatScratchInstSVfromSVS(uint16_t Opcode);
1282 
1283   /// \returns SS (SADDR) form of a FLAT Scratch instruction given an \p Opcode
1284   /// of an SV (VADDR) form.
1285   LLVM_READONLY
1286   int getFlatScratchInstSSfromSV(uint16_t Opcode);
1287 
1288   /// \returns SV (VADDR) form of a FLAT Scratch instruction given an \p Opcode
1289   /// of an SS (SADDR) form.
1290   LLVM_READONLY
1291   int getFlatScratchInstSVfromSS(uint16_t Opcode);
1292 
1293   /// \returns earlyclobber version of a MAC MFMA is exists.
1294   LLVM_READONLY
1295   int getMFMAEarlyClobberOp(uint16_t Opcode);
1296 
1297   /// \returns v_cmpx version of a v_cmp instruction.
1298   LLVM_READONLY
1299   int getVCMPXOpFromVCMP(uint16_t Opcode);
1300 
1301   const uint64_t RSRC_DATA_FORMAT = 0xf00000000000LL;
1302   const uint64_t RSRC_ELEMENT_SIZE_SHIFT = (32 + 19);
1303   const uint64_t RSRC_INDEX_STRIDE_SHIFT = (32 + 21);
1304   const uint64_t RSRC_TID_ENABLE = UINT64_C(1) << (32 + 23);
1305 
1306 } // end namespace AMDGPU
1307 
1308 namespace SI {
1309 namespace KernelInputOffsets {
1310 
1311 /// Offsets in bytes from the start of the input buffer
1312 enum Offsets {
1313   NGROUPS_X = 0,
1314   NGROUPS_Y = 4,
1315   NGROUPS_Z = 8,
1316   GLOBAL_SIZE_X = 12,
1317   GLOBAL_SIZE_Y = 16,
1318   GLOBAL_SIZE_Z = 20,
1319   LOCAL_SIZE_X = 24,
1320   LOCAL_SIZE_Y = 28,
1321   LOCAL_SIZE_Z = 32
1322 };
1323 
1324 } // end namespace KernelInputOffsets
1325 } // end namespace SI
1326 
1327 } // end namespace llvm
1328 
1329 #endif // LLVM_LIB_TARGET_AMDGPU_SIINSTRINFO_H
1330